git.gag.com Git - fw/openocd/blob - src/target/riscv/riscv.c

   1 #include <assert.h>
   2 #include <stdlib.h>
   3 #include <time.h>
   4
   5 #ifdef HAVE_CONFIG_H
   6 #include "config.h"
   7 #endif
   8
   9 #include "target/target.h"
  10 #include "target/algorithm.h"
  11 #include "target/target_type.h"
  12 #include "log.h"
  13 #include "jtag/jtag.h"
  14 #include "target/register.h"
  15 #include "target/breakpoints.h"
  16 #include "helper/time_support.h"
  17 #include "riscv.h"
  18 #include "gdb_regs.h"
  19 #include "rtos/rtos.h"
  20
  21 /**
  22  * Since almost everything can be accomplish by scanning the dbus register, all
  23  * functions here assume dbus is already selected. The exception are functions
  24  * called directly by OpenOCD, which can't assume anything about what's
  25  * currently in IR. They should set IR to dbus explicitly.
  26  */
  27
  28 /**
  29  * Code structure
  30  *
  31  * At the bottom of the stack are the OpenOCD JTAG functions:
  32  *              jtag_add_[id]r_scan
  33  *              jtag_execute_query
  34  *              jtag_add_runtest
  35  *
  36  * There are a few functions to just instantly shift a register and get its
  37  * value:
  38  *              dtmcontrol_scan
  39  *              idcode_scan
  40  *              dbus_scan
  41  *
  42  * Because doing one scan and waiting for the result is slow, most functions
  43  * batch up a bunch of dbus writes and then execute them all at once. They use
  44  * the scans "class" for this:
  45  *              scans_new
  46  *              scans_delete
  47  *              scans_execute
  48  *              scans_add_...
  49  * Usually you new(), call a bunch of add functions, then execute() and look
  50  * at the results by calling scans_get...()
  51  *
  52  * Optimized functions will directly use the scans class above, but slightly
  53  * lazier code will use the cache functions that in turn use the scans
  54  * functions:
  55  *              cache_get...
  56  *              cache_set...
  57  *              cache_write
  58  * cache_set... update a local structure, which is then synced to the target
  59  * with cache_write(). Only Debug RAM words that are actually changed are sent
  60  * to the target. Afterwards use cache_get... to read results.
  61  */
  62
  63 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
  64 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
  65
  66 #define DIM(x)          (sizeof(x)/sizeof(*x))
  67
  68 /* Constants for legacy SiFive hardware breakpoints. */
  69 #define CSR_BPCONTROL_X                 (1<<0)
  70 #define CSR_BPCONTROL_W                 (1<<1)
  71 #define CSR_BPCONTROL_R                 (1<<2)
  72 #define CSR_BPCONTROL_U                 (1<<3)
  73 #define CSR_BPCONTROL_S                 (1<<4)
  74 #define CSR_BPCONTROL_H                 (1<<5)
  75 #define CSR_BPCONTROL_M                 (1<<6)
  76 #define CSR_BPCONTROL_BPMATCH   (0xf<<7)
  77 #define CSR_BPCONTROL_BPACTION  (0xff<<11)
  78
  79 #define DEBUG_ROM_START         0x800
  80 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
  81 #define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
  82 #define DEBUG_RAM_START         0x400
  83
  84 #define SETHALTNOT                              0x10c
  85
  86 /*** JTAG registers. ***/
  87
  88 #define DTMCONTROL                                      0x10
  89 #define DTMCONTROL_DBUS_RESET           (1<<16)
  90 #define DTMCONTROL_IDLE                         (7<<10)
  91 #define DTMCONTROL_ADDRBITS                     (0xf<<4)
  92 #define DTMCONTROL_VERSION                      (0xf)
  93
  94 #define DBUS                                            0x11
  95 #define DBUS_OP_START                           0
  96 #define DBUS_OP_SIZE                            2
  97 typedef enum {
  98         DBUS_OP_NOP = 0,
  99         DBUS_OP_READ = 1,
 100         DBUS_OP_WRITE = 2
 101 } dbus_op_t;
 102 typedef enum {
 103         DBUS_STATUS_SUCCESS = 0,
 104         DBUS_STATUS_FAILED = 2,
 105         DBUS_STATUS_BUSY = 3
 106 } dbus_status_t;
 107 #define DBUS_DATA_START                         2
 108 #define DBUS_DATA_SIZE                          34
 109 #define DBUS_ADDRESS_START                      36
 110
 111 typedef enum {
 112         RE_OK,
 113         RE_FAIL,
 114         RE_AGAIN
 115 } riscv_error_t;
 116
 117 typedef enum slot {
 118         SLOT0,
 119         SLOT1,
 120         SLOT_LAST,
 121 } slot_t;
 122
 123 /*** Debug Bus registers. ***/
 124
 125 #define DMCONTROL                               0x10
 126 #define DMCONTROL_INTERRUPT             (((uint64_t)1)<<33)
 127 #define DMCONTROL_HALTNOT               (((uint64_t)1)<<32)
 128 #define DMCONTROL_BUSERROR              (7<<19)
 129 #define DMCONTROL_SERIAL                (3<<16)
 130 #define DMCONTROL_AUTOINCREMENT (1<<15)
 131 #define DMCONTROL_ACCESS                (7<<12)
 132 #define DMCONTROL_HARTID                (0x3ff<<2)
 133 #define DMCONTROL_NDRESET               (1<<1)
 134 #define DMCONTROL_FULLRESET             1
 135
 136 #define DMINFO                                  0x11
 137 #define DMINFO_ABUSSIZE                 (0x7fU<<25)
 138 #define DMINFO_SERIALCOUNT              (0xf<<21)
 139 #define DMINFO_ACCESS128                (1<<20)
 140 #define DMINFO_ACCESS64                 (1<<19)
 141 #define DMINFO_ACCESS32                 (1<<18)
 142 #define DMINFO_ACCESS16                 (1<<17)
 143 #define DMINFO_ACCESS8                  (1<<16)
 144 #define DMINFO_DRAMSIZE                 (0x3f<<10)
 145 #define DMINFO_AUTHENTICATED    (1<<5)
 146 #define DMINFO_AUTHBUSY                 (1<<4)
 147 #define DMINFO_AUTHTYPE                 (3<<2)
 148 #define DMINFO_VERSION                  3
 149
 150 /*** Info about the core being debugged. ***/
 151
 152 #define DBUS_ADDRESS_UNKNOWN    0xffff
 153
 154 #define MAX_HWBPS                       16
 155 #define DRAM_CACHE_SIZE         16
 156
 157 uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
 158 struct scan_field select_dtmcontrol = {
 159         .in_value = NULL,
 160         .out_value = ir_dtmcontrol
 161 };
 162 uint8_t ir_dbus[4] = {DBUS};
 163 struct scan_field select_dbus = {
 164         .in_value = NULL,
 165         .out_value = ir_dbus
 166 };
 167 uint8_t ir_idcode[4] = {0x1};
 168 struct scan_field select_idcode = {
 169         .in_value = NULL,
 170         .out_value = ir_idcode
 171 };
 172
 173 struct trigger {
 174         uint64_t address;
 175         uint32_t length;
 176         uint64_t mask;
 177         uint64_t value;
 178         bool read, write, execute;
 179         int unique_id;
 180 };
 181
 182 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 183 int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
 184
 185 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 186 int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
 187
 188 bool riscv_prefer_sba;
 189
 190 typedef struct {
 191         uint16_t low, high;
 192 } range_t;
 193
 194 /* In addition to the ones in the standard spec, we'll also expose additional
 195  * CSRs in this list.
 196  * The list is either NULL, or a series of ranges (inclusive), terminated with
 197  * 1,0. */
 198 range_t *expose_csr;
 199 /* Same, but for custom registers. */
 200 range_t *expose_custom;
 201
 202 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
 203 {
 204         struct scan_field field;
 205         uint8_t in_value[4];
 206         uint8_t out_value[4] = { 0 };
 207
 208         buf_set_u32(out_value, 0, 32, out);
 209
 210         jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
 211
 212         field.num_bits = 32;
 213         field.out_value = out_value;
 214         field.in_value = in_value;
 215         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 216
 217         /* Always return to dbus. */
 218         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 219
 220         int retval = jtag_execute_queue();
 221         if (retval != ERROR_OK) {
 222                 LOG_ERROR("failed jtag scan: %d", retval);
 223                 return retval;
 224         }
 225
 226         uint32_t in = buf_get_u32(field.in_value, 0, 32);
 227         LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
 228
 229         return in;
 230 }
 231
 232 static struct target_type *get_target_type(struct target *target)
 233 {
 234         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 235
 236         if (!info) {
 237                 LOG_ERROR("Target has not been initialized");
 238                 return NULL;
 239         }
 240
 241         switch (info->dtm_version) {
 242                 case 0:
 243                         return &riscv011_target;
 244                 case 1:
 245                         return &riscv013_target;
 246                 default:
 247                         LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
 248                         return NULL;
 249         }
 250 }
 251
 252 static int riscv_init_target(struct command_context *cmd_ctx,
 253                 struct target *target)
 254 {
 255         LOG_DEBUG("riscv_init_target()");
 256         target->arch_info = calloc(1, sizeof(riscv_info_t));
 257         if (!target->arch_info)
 258                 return ERROR_FAIL;
 259         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 260         riscv_info_init(target, info);
 261         info->cmd_ctx = cmd_ctx;
 262
 263         select_dtmcontrol.num_bits = target->tap->ir_length;
 264         select_dbus.num_bits = target->tap->ir_length;
 265         select_idcode.num_bits = target->tap->ir_length;
 266
 267         riscv_semihosting_init(target);
 268
 269         target->debug_reason = DBG_REASON_DBGRQ;
 270
 271         return ERROR_OK;
 272 }
 273
 274 static void riscv_free_registers(struct target *target)
 275 {
 276         /* Free the shared structure use for most registers. */
 277         if (target->reg_cache) {
 278                 if (target->reg_cache->reg_list) {
 279                         if (target->reg_cache->reg_list[0].arch_info)
 280                                 free(target->reg_cache->reg_list[0].arch_info);
 281                         /* Free the ones we allocated separately. */
 282                         for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
 283                                 free(target->reg_cache->reg_list[i].arch_info);
 284                         free(target->reg_cache->reg_list);
 285                 }
 286                 free(target->reg_cache);
 287         }
 288 }
 289
 290 static void riscv_deinit_target(struct target *target)
 291 {
 292         LOG_DEBUG("riscv_deinit_target()");
 293         struct target_type *tt = get_target_type(target);
 294         if (tt) {
 295                 tt->deinit_target(target);
 296                 riscv_info_t *info = (riscv_info_t *) target->arch_info;
 297                 free(info->reg_names);
 298                 free(info);
 299         }
 300
 301         riscv_free_registers(target);
 302
 303         target->arch_info = NULL;
 304 }
 305
 306 static int oldriscv_halt(struct target *target)
 307 {
 308         struct target_type *tt = get_target_type(target);
 309         return tt->halt(target);
 310 }
 311
 312 static void trigger_from_breakpoint(struct trigger *trigger,
 313                 const struct breakpoint *breakpoint)
 314 {
 315         trigger->address = breakpoint->address;
 316         trigger->length = breakpoint->length;
 317         trigger->mask = ~0LL;
 318         trigger->read = false;
 319         trigger->write = false;
 320         trigger->execute = true;
 321         /* unique_id is unique across both breakpoints and watchpoints. */
 322         trigger->unique_id = breakpoint->unique_id;
 323 }
 324
 325 static int maybe_add_trigger_t1(struct target *target, unsigned hartid,
 326                 struct trigger *trigger, uint64_t tdata1)
 327 {
 328         RISCV_INFO(r);
 329
 330         const uint32_t bpcontrol_x = 1<<0;
 331         const uint32_t bpcontrol_w = 1<<1;
 332         const uint32_t bpcontrol_r = 1<<2;
 333         const uint32_t bpcontrol_u = 1<<3;
 334         const uint32_t bpcontrol_s = 1<<4;
 335         const uint32_t bpcontrol_h = 1<<5;
 336         const uint32_t bpcontrol_m = 1<<6;
 337         const uint32_t bpcontrol_bpmatch = 0xf << 7;
 338         const uint32_t bpcontrol_bpaction = 0xff << 11;
 339
 340         if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
 341                 /* Trigger is already in use, presumably by user code. */
 342                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 343         }
 344
 345         tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
 346         tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
 347         tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
 348         tdata1 = set_field(tdata1, bpcontrol_u,
 349                         !!(r->misa[hartid] & (1 << ('U' - 'A'))));
 350         tdata1 = set_field(tdata1, bpcontrol_s,
 351                         !!(r->misa[hartid] & (1 << ('S' - 'A'))));
 352         tdata1 = set_field(tdata1, bpcontrol_h,
 353                         !!(r->misa[hartid] & (1 << ('H' - 'A'))));
 354         tdata1 |= bpcontrol_m;
 355         tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
 356         tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
 357
 358         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
 359
 360         riscv_reg_t tdata1_rb;
 361         if (riscv_get_register_on_hart(target, &tdata1_rb, hartid,
 362                                 GDB_REGNO_TDATA1) != ERROR_OK)
 363                 return ERROR_FAIL;
 364         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 365
 366         if (tdata1 != tdata1_rb) {
 367                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 368                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 369                                 tdata1, tdata1_rb);
 370                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
 371                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 372         }
 373
 374         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
 375
 376         return ERROR_OK;
 377 }
 378
 379 static int maybe_add_trigger_t2(struct target *target, unsigned hartid,
 380                 struct trigger *trigger, uint64_t tdata1)
 381 {
 382         RISCV_INFO(r);
 383
 384         /* tselect is already set */
 385         if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
 386                 /* Trigger is already in use, presumably by user code. */
 387                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 388         }
 389
 390         /* address/data match trigger */
 391         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 392         tdata1 = set_field(tdata1, MCONTROL_ACTION,
 393                         MCONTROL_ACTION_DEBUG_MODE);
 394         tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
 395         tdata1 |= MCONTROL_M;
 396         if (r->misa[hartid] & (1 << ('H' - 'A')))
 397                 tdata1 |= MCONTROL_H;
 398         if (r->misa[hartid] & (1 << ('S' - 'A')))
 399                 tdata1 |= MCONTROL_S;
 400         if (r->misa[hartid] & (1 << ('U' - 'A')))
 401                 tdata1 |= MCONTROL_U;
 402
 403         if (trigger->execute)
 404                 tdata1 |= MCONTROL_EXECUTE;
 405         if (trigger->read)
 406                 tdata1 |= MCONTROL_LOAD;
 407         if (trigger->write)
 408                 tdata1 |= MCONTROL_STORE;
 409
 410         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
 411
 412         uint64_t tdata1_rb;
 413         int result = riscv_get_register_on_hart(target, &tdata1_rb, hartid, GDB_REGNO_TDATA1);
 414         if (result != ERROR_OK)
 415                 return result;
 416         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 417
 418         if (tdata1 != tdata1_rb) {
 419                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 420                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 421                                 tdata1, tdata1_rb);
 422                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
 423                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 424         }
 425
 426         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
 427
 428         return ERROR_OK;
 429 }
 430
 431 static int add_trigger(struct target *target, struct trigger *trigger)
 432 {
 433         RISCV_INFO(r);
 434
 435         if (riscv_enumerate_triggers(target) != ERROR_OK)
 436                 return ERROR_FAIL;
 437
 438         /* In RTOS mode, we need to set the same trigger in the same slot on every
 439          * hart, to keep up the illusion that each hart is a thread running on the
 440          * same core. */
 441
 442         /* Otherwise, we just set the trigger on the one hart this target deals
 443          * with. */
 444
 445         riscv_reg_t tselect[RISCV_MAX_HARTS];
 446
 447         int first_hart = -1;
 448         for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
 449                 if (!riscv_hart_enabled(target, hartid))
 450                         continue;
 451                 if (first_hart < 0)
 452                         first_hart = hartid;
 453                 int result = riscv_get_register_on_hart(target, &tselect[hartid],
 454                                 hartid, GDB_REGNO_TSELECT);
 455                 if (result != ERROR_OK)
 456                         return result;
 457         }
 458         assert(first_hart >= 0);
 459
 460         unsigned int i;
 461         for (i = 0; i < r->trigger_count[first_hart]; i++) {
 462                 if (r->trigger_unique_id[i] != -1)
 463                         continue;
 464
 465                 riscv_set_register_on_hart(target, first_hart, GDB_REGNO_TSELECT, i);
 466
 467                 uint64_t tdata1;
 468                 int result = riscv_get_register_on_hart(target, &tdata1, first_hart,
 469                                 GDB_REGNO_TDATA1);
 470                 if (result != ERROR_OK)
 471                         return result;
 472                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
 473
 474                 result = ERROR_OK;
 475                 for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
 476                         if (!riscv_hart_enabled(target, hartid))
 477                                 continue;
 478                         if (hartid > first_hart)
 479                                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
 480                         switch (type) {
 481                                 case 1:
 482                                         result = maybe_add_trigger_t1(target, hartid, trigger, tdata1);
 483                                         break;
 484                                 case 2:
 485                                         result = maybe_add_trigger_t2(target, hartid, trigger, tdata1);
 486                                         break;
 487                                 default:
 488                                         LOG_DEBUG("trigger %d has unknown type %d", i, type);
 489                                         continue;
 490                         }
 491
 492                         if (result != ERROR_OK)
 493                                 continue;
 494                 }
 495
 496                 if (result != ERROR_OK)
 497                         continue;
 498
 499                 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
 500                                 i, type, trigger->unique_id);
 501                 r->trigger_unique_id[i] = trigger->unique_id;
 502                 break;
 503         }
 504
 505         for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
 506                 if (!riscv_hart_enabled(target, hartid))
 507                         continue;
 508                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT,
 509                                 tselect[hartid]);
 510         }
 511
 512         if (i >= r->trigger_count[first_hart]) {
 513                 LOG_ERROR("Couldn't find an available hardware trigger.");
 514                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 515         }
 516
 517         return ERROR_OK;
 518 }
 519
 520 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 521 {
 522         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
 523         assert(breakpoint);
 524         if (breakpoint->type == BKPT_SOFT) {
 525                 /** @todo check RVC for size/alignment */
 526                 if (!(breakpoint->length == 4 || breakpoint->length == 2)) {
 527                         LOG_ERROR("Invalid breakpoint length %d", breakpoint->length);
 528                         return ERROR_FAIL;
 529                 }
 530
 531                 if (0 != (breakpoint->address % 2)) {
 532                         LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR, breakpoint->address);
 533                         return ERROR_FAIL;
 534                 }
 535
 536                 if (target_read_memory(target, breakpoint->address, 2, breakpoint->length / 2,
 537                                         breakpoint->orig_instr) != ERROR_OK) {
 538                         LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
 539                                         breakpoint->address);
 540                         return ERROR_FAIL;
 541                 }
 542
 543                 uint8_t buff[4] = { 0 };
 544                 buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
 545                 int const retval = target_write_memory(target, breakpoint->address, 2, breakpoint->length / 2, buff);
 546
 547                 if (retval != ERROR_OK) {
 548                         LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
 549                                         TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 550                         return ERROR_FAIL;
 551                 }
 552
 553         } else if (breakpoint->type == BKPT_HARD) {
 554                 struct trigger trigger;
 555                 trigger_from_breakpoint(&trigger, breakpoint);
 556                 int const result = add_trigger(target, &trigger);
 557                 if (result != ERROR_OK)
 558                         return result;
 559         } else {
 560                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 561                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 562         }
 563
 564         breakpoint->set = true;
 565         return ERROR_OK;
 566 }
 567
 568 static int remove_trigger(struct target *target, struct trigger *trigger)
 569 {
 570         RISCV_INFO(r);
 571
 572         if (riscv_enumerate_triggers(target) != ERROR_OK)
 573                 return ERROR_FAIL;
 574
 575         int first_hart = -1;
 576         for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
 577                 if (!riscv_hart_enabled(target, hartid))
 578                         continue;
 579                 if (first_hart < 0) {
 580                         first_hart = hartid;
 581                         break;
 582                 }
 583         }
 584         assert(first_hart >= 0);
 585
 586         unsigned int i;
 587         for (i = 0; i < r->trigger_count[first_hart]; i++) {
 588                 if (r->trigger_unique_id[i] == trigger->unique_id)
 589                         break;
 590         }
 591         if (i >= r->trigger_count[first_hart]) {
 592                 LOG_ERROR("Couldn't find the hardware resources used by hardware "
 593                                 "trigger.");
 594                 return ERROR_FAIL;
 595         }
 596         LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
 597                         trigger->unique_id);
 598         for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
 599                 if (!riscv_hart_enabled(target, hartid))
 600                         continue;
 601                 riscv_reg_t tselect;
 602                 int result = riscv_get_register_on_hart(target, &tselect, hartid, GDB_REGNO_TSELECT);
 603                 if (result != ERROR_OK)
 604                         return result;
 605                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
 606                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
 607                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
 608         }
 609         r->trigger_unique_id[i] = -1;
 610
 611         return ERROR_OK;
 612 }
 613
 614 int riscv_remove_breakpoint(struct target *target,
 615                 struct breakpoint *breakpoint)
 616 {
 617         if (breakpoint->type == BKPT_SOFT) {
 618                 if (target_write_memory(target, breakpoint->address, 2, breakpoint->length / 2,
 619                                         breakpoint->orig_instr) != ERROR_OK) {
 620                         LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
 621                                         "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 622                         return ERROR_FAIL;
 623                 }
 624
 625         } else if (breakpoint->type == BKPT_HARD) {
 626                 struct trigger trigger;
 627                 trigger_from_breakpoint(&trigger, breakpoint);
 628                 int result = remove_trigger(target, &trigger);
 629                 if (result != ERROR_OK)
 630                         return result;
 631
 632         } else {
 633                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 634                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 635         }
 636
 637         breakpoint->set = false;
 638
 639         return ERROR_OK;
 640 }
 641
 642 static void trigger_from_watchpoint(struct trigger *trigger,
 643                 const struct watchpoint *watchpoint)
 644 {
 645         trigger->address = watchpoint->address;
 646         trigger->length = watchpoint->length;
 647         trigger->mask = watchpoint->mask;
 648         trigger->value = watchpoint->value;
 649         trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
 650         trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
 651         trigger->execute = false;
 652         /* unique_id is unique across both breakpoints and watchpoints. */
 653         trigger->unique_id = watchpoint->unique_id;
 654 }
 655
 656 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 657 {
 658         struct trigger trigger;
 659         trigger_from_watchpoint(&trigger, watchpoint);
 660
 661         int result = add_trigger(target, &trigger);
 662         if (result != ERROR_OK)
 663                 return result;
 664         watchpoint->set = true;
 665
 666         return ERROR_OK;
 667 }
 668
 669 int riscv_remove_watchpoint(struct target *target,
 670                 struct watchpoint *watchpoint)
 671 {
 672         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
 673
 674         struct trigger trigger;
 675         trigger_from_watchpoint(&trigger, watchpoint);
 676
 677         int result = remove_trigger(target, &trigger);
 678         if (result != ERROR_OK)
 679                 return result;
 680         watchpoint->set = false;
 681
 682         return ERROR_OK;
 683 }
 684
 685 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
 686  * current halt.
 687  *
 688  * The GDB server uses this information to tell GDB what data address has
 689  * been hit, which enables GDB to print the hit variable along with its old
 690  * and new value. */
 691 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
 692 {
 693         struct watchpoint *wp = target->watchpoints;
 694
 695         LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
 696
 697         /*TODO instead of disassembling the instruction that we think caused the
 698          * trigger, check the hit bit of each watchpoint first. The hit bit is
 699          * simpler and more reliable to check but as it is optional and relatively
 700          * new, not all hardware will implement it  */
 701         riscv_reg_t dpc;
 702         riscv_get_register(target, &dpc, GDB_REGNO_DPC);
 703         const uint8_t length = 4;
 704         LOG_DEBUG("dpc is 0x%" PRIx64, dpc);
 705
 706         /* fetch the instruction at dpc */
 707         uint8_t buffer[length];
 708         if (target_read_buffer(target, dpc, length, buffer) != ERROR_OK) {
 709                 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64, dpc);
 710                 return ERROR_FAIL;
 711         }
 712
 713         uint32_t instruction = 0;
 714
 715         for (int i = 0; i < length; i++) {
 716                 LOG_DEBUG("Next byte is %x", buffer[i]);
 717                 instruction += (buffer[i] << 8 * i);
 718         }
 719         LOG_DEBUG("Full instruction is %x", instruction);
 720
 721         /* find out which memory address is accessed by the instruction at dpc */
 722         /* opcode is first 7 bits of the instruction */
 723         uint8_t opcode = instruction & 0x7F;
 724         uint32_t rs1;
 725         int16_t imm;
 726         riscv_reg_t mem_addr;
 727
 728         if (opcode == MATCH_LB || opcode == MATCH_SB) {
 729                 rs1 = (instruction & 0xf8000) >> 15;
 730                 riscv_get_register(target, &mem_addr, rs1);
 731
 732                 if (opcode == MATCH_SB) {
 733                         LOG_DEBUG("%x is store instruction", instruction);
 734                         imm = ((instruction & 0xf80) >> 7) | ((instruction & 0xfe000000) >> 20);
 735                 } else {
 736                         LOG_DEBUG("%x is load instruction", instruction);
 737                         imm = (instruction & 0xfff00000) >> 20;
 738                 }
 739                 /* sign extend 12-bit imm to 16-bits */
 740                 if (imm & (1 << 11))
 741                         imm |= 0xf000;
 742                 mem_addr += imm;
 743                 LOG_DEBUG("memory address=0x%" PRIx64, mem_addr);
 744         } else {
 745                 LOG_DEBUG("%x is not a RV32I load or store", instruction);
 746                 return ERROR_FAIL;
 747         }
 748
 749         while (wp) {
 750                 /*TODO support length/mask */
 751                 if (wp->address == mem_addr) {
 752                         *hit_watchpoint = wp;
 753                         LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address);
 754                         return ERROR_OK;
 755                 }
 756                 wp = wp->next;
 757         }
 758
 759         /* No match found - either we hit a watchpoint caused by an instruction that
 760          * this function does not yet disassemble, or we hit a breakpoint.
 761          *
 762          * OpenOCD will behave as if this function had never been implemented i.e.
 763          * report the halt to GDB with no address information. */
 764         return ERROR_FAIL;
 765 }
 766
 767
 768 static int oldriscv_step(struct target *target, int current, uint32_t address,
 769                 int handle_breakpoints)
 770 {
 771         struct target_type *tt = get_target_type(target);
 772         return tt->step(target, current, address, handle_breakpoints);
 773 }
 774
 775 static int old_or_new_riscv_step(
 776                 struct target *target,
 777                 int current,
 778                 target_addr_t address,
 779                 int handle_breakpoints
 780 ){
 781         RISCV_INFO(r);
 782         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
 783         if (r->is_halted == NULL)
 784                 return oldriscv_step(target, current, address, handle_breakpoints);
 785         else
 786                 return riscv_openocd_step(target, current, address, handle_breakpoints);
 787 }
 788
 789
 790 static int riscv_examine(struct target *target)
 791 {
 792         LOG_DEBUG("riscv_examine()");
 793         if (target_was_examined(target)) {
 794                 LOG_DEBUG("Target was already examined.");
 795                 return ERROR_OK;
 796         }
 797
 798         /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
 799
 800         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 801         uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
 802         LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
 803         info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
 804         LOG_DEBUG("  version=0x%x", info->dtm_version);
 805
 806         struct target_type *tt = get_target_type(target);
 807         if (tt == NULL)
 808                 return ERROR_FAIL;
 809
 810         int result = tt->init_target(info->cmd_ctx, target);
 811         if (result != ERROR_OK)
 812                 return result;
 813
 814         return tt->examine(target);
 815 }
 816
 817 static int oldriscv_poll(struct target *target)
 818 {
 819         struct target_type *tt = get_target_type(target);
 820         return tt->poll(target);
 821 }
 822
 823 static int old_or_new_riscv_poll(struct target *target)
 824 {
 825         RISCV_INFO(r);
 826         if (r->is_halted == NULL)
 827                 return oldriscv_poll(target);
 828         else
 829                 return riscv_openocd_poll(target);
 830 }
 831
 832 static int old_or_new_riscv_halt(struct target *target)
 833 {
 834         RISCV_INFO(r);
 835         if (r->is_halted == NULL)
 836                 return oldriscv_halt(target);
 837         else
 838                 return riscv_openocd_halt(target);
 839 }
 840
 841 static int riscv_assert_reset(struct target *target)
 842 {
 843         LOG_DEBUG("[%d]", target->coreid);
 844         struct target_type *tt = get_target_type(target);
 845         riscv_invalidate_register_cache(target);
 846         return tt->assert_reset(target);
 847 }
 848
 849 static int riscv_deassert_reset(struct target *target)
 850 {
 851         LOG_DEBUG("[%d]", target->coreid);
 852         struct target_type *tt = get_target_type(target);
 853         return tt->deassert_reset(target);
 854 }
 855
 856
 857 static int oldriscv_resume(struct target *target, int current, uint32_t address,
 858                 int handle_breakpoints, int debug_execution)
 859 {
 860         struct target_type *tt = get_target_type(target);
 861         return tt->resume(target, current, address, handle_breakpoints,
 862                         debug_execution);
 863 }
 864
 865 static int old_or_new_riscv_resume(
 866                 struct target *target,
 867                 int current,
 868                 target_addr_t address,
 869                 int handle_breakpoints,
 870                 int debug_execution
 871 ){
 872         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
 873         if (target->smp) {
 874                 struct target_list *targets = target->head;
 875                 int result = ERROR_OK;
 876                 while (targets) {
 877                         struct target *t = targets->target;
 878                         riscv_info_t *r = riscv_info(t);
 879                         if (r->is_halted == NULL) {
 880                                 if (oldriscv_resume(t, current, address, handle_breakpoints,
 881                                                         debug_execution) != ERROR_OK)
 882                                         result = ERROR_FAIL;
 883                         } else {
 884                                 if (riscv_openocd_resume(t, current, address,
 885                                                         handle_breakpoints, debug_execution) != ERROR_OK)
 886                                         result = ERROR_FAIL;
 887                         }
 888                         targets = targets->next;
 889                 }
 890                 return result;
 891         }
 892
 893         RISCV_INFO(r);
 894         if (r->is_halted == NULL)
 895                 return oldriscv_resume(target, current, address, handle_breakpoints, debug_execution);
 896         else
 897                 return riscv_openocd_resume(target, current, address, handle_breakpoints, debug_execution);
 898 }
 899
 900 static int riscv_select_current_hart(struct target *target)
 901 {
 902         RISCV_INFO(r);
 903         if (riscv_rtos_enabled(target)) {
 904                 if (r->rtos_hartid == -1)
 905                         r->rtos_hartid = target->rtos->current_threadid - 1;
 906                 return riscv_set_current_hartid(target, r->rtos_hartid);
 907         } else
 908                 return riscv_set_current_hartid(target, target->coreid);
 909 }
 910
 911 static int riscv_read_memory(struct target *target, target_addr_t address,
 912                 uint32_t size, uint32_t count, uint8_t *buffer)
 913 {
 914         if (riscv_select_current_hart(target) != ERROR_OK)
 915                 return ERROR_FAIL;
 916         struct target_type *tt = get_target_type(target);
 917         return tt->read_memory(target, address, size, count, buffer);
 918 }
 919
 920 static int riscv_write_memory(struct target *target, target_addr_t address,
 921                 uint32_t size, uint32_t count, const uint8_t *buffer)
 922 {
 923         if (riscv_select_current_hart(target) != ERROR_OK)
 924                 return ERROR_FAIL;
 925         struct target_type *tt = get_target_type(target);
 926         return tt->write_memory(target, address, size, count, buffer);
 927 }
 928
 929 static int riscv_get_gdb_reg_list_internal(struct target *target,
 930                 struct reg **reg_list[], int *reg_list_size,
 931                 enum target_register_class reg_class, bool read)
 932 {
 933         RISCV_INFO(r);
 934         LOG_DEBUG("rtos_hartid=%d, current_hartid=%d, reg_class=%d, read=%d",
 935                         r->rtos_hartid, r->current_hartid, reg_class, read);
 936
 937         if (!target->reg_cache) {
 938                 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
 939                 return ERROR_FAIL;
 940         }
 941
 942         if (riscv_select_current_hart(target) != ERROR_OK)
 943                 return ERROR_FAIL;
 944
 945         switch (reg_class) {
 946                 case REG_CLASS_GENERAL:
 947                         *reg_list_size = 33;
 948                         break;
 949                 case REG_CLASS_ALL:
 950                         *reg_list_size = target->reg_cache->num_regs;
 951                         break;
 952                 default:
 953                         LOG_ERROR("Unsupported reg_class: %d", reg_class);
 954                         return ERROR_FAIL;
 955         }
 956
 957         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
 958         if (!*reg_list)
 959                 return ERROR_FAIL;
 960
 961         for (int i = 0; i < *reg_list_size; i++) {
 962                 assert(!target->reg_cache->reg_list[i].valid ||
 963                                 target->reg_cache->reg_list[i].size > 0);
 964                 (*reg_list)[i] = &target->reg_cache->reg_list[i];
 965                 if (read && !target->reg_cache->reg_list[i].valid) {
 966                         if (target->reg_cache->reg_list[i].type->get(
 967                                                 &target->reg_cache->reg_list[i]) != ERROR_OK)
 968                                 /* This function is called when first connecting to gdb,
 969                                  * resulting in an attempt to read all kinds of registers which
 970                                  * probably will fail. Ignore these failures, and when
 971                                  * encountered stop reading to save time. */
 972                                 read = false;
 973                 }
 974         }
 975
 976         return ERROR_OK;
 977 }
 978
 979 static int riscv_get_gdb_reg_list(struct target *target,
 980                 struct reg **reg_list[], int *reg_list_size,
 981                 enum target_register_class reg_class)
 982 {
 983         return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
 984                         reg_class, true);
 985 }
 986
 987 static int riscv_arch_state(struct target *target)
 988 {
 989         struct target_type *tt = get_target_type(target);
 990         return tt->arch_state(target);
 991 }
 992
 993 /* Algorithm must end with a software breakpoint instruction. */
 994 static int riscv_run_algorithm(struct target *target, int num_mem_params,
 995                 struct mem_param *mem_params, int num_reg_params,
 996                 struct reg_param *reg_params, target_addr_t entry_point,
 997                 target_addr_t exit_point, int timeout_ms, void *arch_info)
 998 {
 999         riscv_info_t *info = (riscv_info_t *) target->arch_info;
1000
1001         if (num_mem_params > 0) {
1002                 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1003                 return ERROR_FAIL;
1004         }
1005
1006         if (target->state != TARGET_HALTED) {
1007                 LOG_WARNING("target not halted");
1008                 return ERROR_TARGET_NOT_HALTED;
1009         }
1010
1011         /* Save registers */
1012         struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", 1);
1013         if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
1014                 return ERROR_FAIL;
1015         uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1016
1017         uint64_t saved_regs[32];
1018         for (int i = 0; i < num_reg_params; i++) {
1019                 if (reg_params[i].direction == PARAM_IN)
1020                         continue;
1021
1022                 LOG_DEBUG("save %s", reg_params[i].reg_name);
1023                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
1024                 if (!r) {
1025                         LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
1026                         return ERROR_FAIL;
1027                 }
1028
1029                 if (r->size != reg_params[i].size) {
1030                         LOG_ERROR("Register %s is %d bits instead of %d bits.",
1031                                         reg_params[i].reg_name, r->size, reg_params[i].size);
1032                         return ERROR_FAIL;
1033                 }
1034
1035                 if (r->number > GDB_REGNO_XPR31) {
1036                         LOG_ERROR("Only GPRs can be use as argument registers.");
1037                         return ERROR_FAIL;
1038                 }
1039
1040                 if (r->type->get(r) != ERROR_OK)
1041                         return ERROR_FAIL;
1042                 saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
1043                 if (r->type->set(r, reg_params[i].value) != ERROR_OK)
1044                         return ERROR_FAIL;
1045         }
1046
1047
1048         /* Disable Interrupts before attempting to run the algorithm. */
1049         uint64_t current_mstatus;
1050         uint8_t mstatus_bytes[8] = { 0 };
1051
1052         LOG_DEBUG("Disabling Interrupts");
1053         struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
1054                         "mstatus", 1);
1055         if (!reg_mstatus) {
1056                 LOG_ERROR("Couldn't find mstatus!");
1057                 return ERROR_FAIL;
1058         }
1059
1060         reg_mstatus->type->get(reg_mstatus);
1061         current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
1062         uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
1063         buf_set_u64(mstatus_bytes, 0, info->xlen[0], set_field(current_mstatus,
1064                                 ie_mask, 0));
1065
1066         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1067
1068         /* Run algorithm */
1069         LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
1070         if (oldriscv_resume(target, 0, entry_point, 0, 0) != ERROR_OK)
1071                 return ERROR_FAIL;
1072
1073         int64_t start = timeval_ms();
1074         while (target->state != TARGET_HALTED) {
1075                 LOG_DEBUG("poll()");
1076                 int64_t now = timeval_ms();
1077                 if (now - start > timeout_ms) {
1078                         LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms);
1079                         LOG_ERROR("  now   = 0x%08x", (uint32_t) now);
1080                         LOG_ERROR("  start = 0x%08x", (uint32_t) start);
1081                         oldriscv_halt(target);
1082                         old_or_new_riscv_poll(target);
1083                         return ERROR_TARGET_TIMEOUT;
1084                 }
1085
1086                 int result = old_or_new_riscv_poll(target);
1087                 if (result != ERROR_OK)
1088                         return result;
1089         }
1090
1091         if (reg_pc->type->get(reg_pc) != ERROR_OK)
1092                 return ERROR_FAIL;
1093         uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1094         if (final_pc != exit_point) {
1095                 LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
1096                                 TARGET_PRIxADDR, final_pc, exit_point);
1097                 return ERROR_FAIL;
1098         }
1099
1100         /* Restore Interrupts */
1101         LOG_DEBUG("Restoring Interrupts");
1102         buf_set_u64(mstatus_bytes, 0, info->xlen[0], current_mstatus);
1103         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1104
1105         /* Restore registers */
1106         uint8_t buf[8] = { 0 };
1107         buf_set_u64(buf, 0, info->xlen[0], saved_pc);
1108         if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
1109                 return ERROR_FAIL;
1110
1111         for (int i = 0; i < num_reg_params; i++) {
1112                 LOG_DEBUG("restore %s", reg_params[i].reg_name);
1113                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
1114                 buf_set_u64(buf, 0, info->xlen[0], saved_regs[r->number]);
1115                 if (r->type->set(r, buf) != ERROR_OK)
1116                         return ERROR_FAIL;
1117         }
1118
1119         return ERROR_OK;
1120 }
1121
1122 /* Should run code on the target to perform CRC of
1123 memory. Not yet implemented.
1124 */
1125
1126 static int riscv_checksum_memory(struct target *target,
1127                 target_addr_t address, uint32_t count,
1128                 uint32_t *checksum)
1129 {
1130         *checksum = 0xFFFFFFFF;
1131         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1132 }
1133
1134 /*** OpenOCD Helper Functions ***/
1135
1136 enum riscv_poll_hart {
1137         RPH_NO_CHANGE,
1138         RPH_DISCOVERED_HALTED,
1139         RPH_DISCOVERED_RUNNING,
1140         RPH_ERROR
1141 };
1142 static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
1143 {
1144         RISCV_INFO(r);
1145         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1146                 return RPH_ERROR;
1147
1148         LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
1149
1150         /* If OpenOCD thinks we're running but this hart is halted then it's time
1151          * to raise an event. */
1152         bool halted = riscv_is_halted(target);
1153         if (target->state != TARGET_HALTED && halted) {
1154                 LOG_DEBUG("  triggered a halt");
1155                 r->on_halt(target);
1156                 return RPH_DISCOVERED_HALTED;
1157         } else if (target->state != TARGET_RUNNING && !halted) {
1158                 LOG_DEBUG("  triggered running");
1159                 target->state = TARGET_RUNNING;
1160                 return RPH_DISCOVERED_RUNNING;
1161         }
1162
1163         return RPH_NO_CHANGE;
1164 }
1165
1166 int set_debug_reason(struct target *target, int hartid)
1167 {
1168         switch (riscv_halt_reason(target, hartid)) {
1169                 case RISCV_HALT_BREAKPOINT:
1170                         target->debug_reason = DBG_REASON_BREAKPOINT;
1171                         break;
1172                 case RISCV_HALT_TRIGGER:
1173                         target->debug_reason = DBG_REASON_WATCHPOINT;
1174                         break;
1175                 case RISCV_HALT_INTERRUPT:
1176                         target->debug_reason = DBG_REASON_DBGRQ;
1177                         break;
1178                 case RISCV_HALT_SINGLESTEP:
1179                         target->debug_reason = DBG_REASON_SINGLESTEP;
1180                         break;
1181                 case RISCV_HALT_UNKNOWN:
1182                         target->debug_reason = DBG_REASON_UNDEFINED;
1183                         break;
1184                 case RISCV_HALT_ERROR:
1185                         return ERROR_FAIL;
1186         }
1187         return ERROR_OK;
1188 }
1189
1190 /*** OpenOCD Interface ***/
1191 int riscv_openocd_poll(struct target *target)
1192 {
1193         LOG_DEBUG("polling all harts");
1194         int halted_hart = -1;
1195         if (riscv_rtos_enabled(target)) {
1196                 /* Check every hart for an event. */
1197                 for (int i = 0; i < riscv_count_harts(target); ++i) {
1198                         enum riscv_poll_hart out = riscv_poll_hart(target, i);
1199                         switch (out) {
1200                         case RPH_NO_CHANGE:
1201                         case RPH_DISCOVERED_RUNNING:
1202                                 continue;
1203                         case RPH_DISCOVERED_HALTED:
1204                                 halted_hart = i;
1205                                 break;
1206                         case RPH_ERROR:
1207                                 return ERROR_FAIL;
1208                         }
1209                 }
1210                 if (halted_hart == -1) {
1211                         LOG_DEBUG("  no harts just halted, target->state=%d", target->state);
1212                         return ERROR_OK;
1213                 }
1214                 LOG_DEBUG("  hart %d halted", halted_hart);
1215
1216                 /* If we're here then at least one hart triggered.  That means
1217                  * we want to go and halt _every_ hart in the system, as that's
1218                  * the invariant we hold here.  Some harts might have already
1219                  * halted (as we're either in single-step mode or they also
1220                  * triggered a breakpoint), so don't attempt to halt those
1221                  * harts. */
1222                 for (int i = 0; i < riscv_count_harts(target); ++i)
1223                         riscv_halt_one_hart(target, i);
1224
1225         } else if (target->smp) {
1226                 bool halt_discovered = false;
1227                 bool newly_halted[128] = {0};
1228                 unsigned i = 0;
1229                 for (struct target_list *list = target->head; list != NULL;
1230                                 list = list->next, i++) {
1231                         struct target *t = list->target;
1232                         riscv_info_t *r = riscv_info(t);
1233                         assert(i < DIM(newly_halted));
1234                         enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
1235                         switch (out) {
1236                                 case RPH_NO_CHANGE:
1237                                         break;
1238                                 case RPH_DISCOVERED_RUNNING:
1239                                         t->state = TARGET_RUNNING;
1240                                         break;
1241                                 case RPH_DISCOVERED_HALTED:
1242                                         halt_discovered = true;
1243                                         newly_halted[i] = true;
1244                                         t->state = TARGET_HALTED;
1245                                         if (set_debug_reason(t, r->current_hartid) != ERROR_OK)
1246                                                 return ERROR_FAIL;
1247                                         break;
1248                                 case RPH_ERROR:
1249                                         return ERROR_FAIL;
1250                         }
1251                 }
1252
1253                 if (halt_discovered) {
1254                         LOG_DEBUG("Halt other targets in this SMP group.");
1255                         i = 0;
1256                         for (struct target_list *list = target->head; list != NULL;
1257                                         list = list->next, i++) {
1258                                 struct target *t = list->target;
1259                                 riscv_info_t *r = riscv_info(t);
1260                                 if (t->state != TARGET_HALTED) {
1261                                         if (riscv_halt_one_hart(t, r->current_hartid) != ERROR_OK)
1262                                                 return ERROR_FAIL;
1263                                         t->state = TARGET_HALTED;
1264                                         if (set_debug_reason(t, r->current_hartid) != ERROR_OK)
1265                                                 return ERROR_FAIL;
1266                                         newly_halted[i] = true;
1267                                 }
1268                         }
1269
1270                         /* Now that we have all our ducks in a row, tell the higher layers
1271                          * what just happened. */
1272                         i = 0;
1273                         for (struct target_list *list = target->head; list != NULL;
1274                                         list = list->next, i++) {
1275                                 struct target *t = list->target;
1276                                 if (newly_halted[i])
1277                                         target_call_event_callbacks(t, TARGET_EVENT_HALTED);
1278                         }
1279                 }
1280                 return ERROR_OK;
1281
1282         } else {
1283                 enum riscv_poll_hart out = riscv_poll_hart(target,
1284                                 riscv_current_hartid(target));
1285                 if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING)
1286                         return ERROR_OK;
1287                 else if (out == RPH_ERROR)
1288                         return ERROR_FAIL;
1289
1290                 halted_hart = riscv_current_hartid(target);
1291                 LOG_DEBUG("  hart %d halted", halted_hart);
1292         }
1293
1294         target->state = TARGET_HALTED;
1295         if (set_debug_reason(target, halted_hart) != ERROR_OK)
1296                 return ERROR_FAIL;
1297
1298         if (riscv_rtos_enabled(target)) {
1299                 target->rtos->current_threadid = halted_hart + 1;
1300                 target->rtos->current_thread = halted_hart + 1;
1301                 riscv_set_rtos_hartid(target, halted_hart);
1302         }
1303
1304         target->state = TARGET_HALTED;
1305
1306         if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1307                 int retval;
1308                 if (riscv_semihosting(target, &retval) != 0)
1309                         return retval;
1310         }
1311
1312         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1313         return ERROR_OK;
1314 }
1315
1316 int riscv_openocd_halt(struct target *target)
1317 {
1318         RISCV_INFO(r);
1319         int result;
1320
1321         LOG_DEBUG("[%d] halting all harts", target->coreid);
1322
1323         if (target->smp) {
1324                 LOG_DEBUG("Halt other targets in this SMP group.");
1325                 struct target_list *targets = target->head;
1326                 result = ERROR_OK;
1327                 while (targets) {
1328                         struct target *t = targets->target;
1329                         targets = targets->next;
1330                         if (t->state != TARGET_HALTED) {
1331                                 if (riscv_halt_all_harts(t) != ERROR_OK)
1332                                         result = ERROR_FAIL;
1333                         }
1334                 }
1335         } else {
1336                 result = riscv_halt_all_harts(target);
1337         }
1338
1339         if (riscv_rtos_enabled(target)) {
1340                 if (r->rtos_hartid != -1) {
1341                         LOG_DEBUG("halt requested on RTOS hartid %d", r->rtos_hartid);
1342                         target->rtos->current_threadid = r->rtos_hartid + 1;
1343                         target->rtos->current_thread = r->rtos_hartid + 1;
1344                 } else
1345                         LOG_DEBUG("halt requested, but no known RTOS hartid");
1346         }
1347
1348         target->state = TARGET_HALTED;
1349         target->debug_reason = DBG_REASON_DBGRQ;
1350         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1351         return result;
1352 }
1353
1354 int riscv_openocd_resume(
1355                 struct target *target,
1356                 int current,
1357                 target_addr_t address,
1358                 int handle_breakpoints,
1359                 int debug_execution)
1360 {
1361         LOG_DEBUG("debug_reason=%d", target->debug_reason);
1362
1363         if (!current)
1364                 riscv_set_register(target, GDB_REGNO_PC, address);
1365
1366         if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1367                 /* To be able to run off a trigger, disable all the triggers, step, and
1368                  * then resume as usual. */
1369                 struct watchpoint *watchpoint = target->watchpoints;
1370                 bool trigger_temporarily_cleared[RISCV_MAX_HWBPS] = {0};
1371
1372                 int i = 0;
1373                 int result = ERROR_OK;
1374                 while (watchpoint && result == ERROR_OK) {
1375                         LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set);
1376                         trigger_temporarily_cleared[i] = watchpoint->set;
1377                         if (watchpoint->set)
1378                                 result = riscv_remove_watchpoint(target, watchpoint);
1379                         watchpoint = watchpoint->next;
1380                         i++;
1381                 }
1382
1383                 if (result == ERROR_OK)
1384                         result = riscv_step_rtos_hart(target);
1385
1386                 watchpoint = target->watchpoints;
1387                 i = 0;
1388                 while (watchpoint) {
1389                         LOG_DEBUG("watchpoint %d: cleared=%d", i, trigger_temporarily_cleared[i]);
1390                         if (trigger_temporarily_cleared[i]) {
1391                                 if (result == ERROR_OK)
1392                                         result = riscv_add_watchpoint(target, watchpoint);
1393                                 else
1394                                         riscv_add_watchpoint(target, watchpoint);
1395                         }
1396                         watchpoint = watchpoint->next;
1397                         i++;
1398                 }
1399
1400                 if (result != ERROR_OK)
1401                         return result;
1402         }
1403
1404         int out = riscv_resume_all_harts(target);
1405         if (out != ERROR_OK) {
1406                 LOG_ERROR("unable to resume all harts");
1407                 return out;
1408         }
1409
1410         register_cache_invalidate(target->reg_cache);
1411         target->state = TARGET_RUNNING;
1412         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1413         return out;
1414 }
1415
1416 int riscv_openocd_step(
1417                 struct target *target,
1418                 int current,
1419                 target_addr_t address,
1420                 int handle_breakpoints
1421 ) {
1422         LOG_DEBUG("stepping rtos hart");
1423
1424         if (!current)
1425                 riscv_set_register(target, GDB_REGNO_PC, address);
1426
1427         int out = riscv_step_rtos_hart(target);
1428         if (out != ERROR_OK) {
1429                 LOG_ERROR("unable to step rtos hart");
1430                 return out;
1431         }
1432
1433         register_cache_invalidate(target->reg_cache);
1434         target->state = TARGET_RUNNING;
1435         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1436         target->state = TARGET_HALTED;
1437         target->debug_reason = DBG_REASON_SINGLESTEP;
1438         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1439         return out;
1440 }
1441
1442 /* Command Handlers */
1443 COMMAND_HANDLER(riscv_set_command_timeout_sec)
1444 {
1445         if (CMD_ARGC != 1) {
1446                 LOG_ERROR("Command takes exactly 1 parameter");
1447                 return ERROR_COMMAND_SYNTAX_ERROR;
1448         }
1449         int timeout = atoi(CMD_ARGV[0]);
1450         if (timeout <= 0) {
1451                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
1452                 return ERROR_FAIL;
1453         }
1454
1455         riscv_command_timeout_sec = timeout;
1456
1457         return ERROR_OK;
1458 }
1459
1460 COMMAND_HANDLER(riscv_set_reset_timeout_sec)
1461 {
1462         if (CMD_ARGC != 1) {
1463                 LOG_ERROR("Command takes exactly 1 parameter");
1464                 return ERROR_COMMAND_SYNTAX_ERROR;
1465         }
1466         int timeout = atoi(CMD_ARGV[0]);
1467         if (timeout <= 0) {
1468                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
1469                 return ERROR_FAIL;
1470         }
1471
1472         riscv_reset_timeout_sec = timeout;
1473         return ERROR_OK;
1474 }
1475
1476 COMMAND_HANDLER(riscv_test_compliance) {
1477
1478         struct target *target = get_current_target(CMD_CTX);
1479
1480         RISCV_INFO(r);
1481
1482         if (CMD_ARGC > 0) {
1483                 LOG_ERROR("Command does not take any parameters.");
1484                 return ERROR_COMMAND_SYNTAX_ERROR;
1485         }
1486
1487         if (r->test_compliance) {
1488                 return r->test_compliance(target);
1489         } else {
1490                 LOG_ERROR("This target does not support this command (may implement an older version of the spec).");
1491                 return ERROR_FAIL;
1492         }
1493 }
1494
1495 COMMAND_HANDLER(riscv_set_prefer_sba)
1496 {
1497         if (CMD_ARGC != 1) {
1498                 LOG_ERROR("Command takes exactly 1 parameter");
1499                 return ERROR_COMMAND_SYNTAX_ERROR;
1500         }
1501         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_prefer_sba);
1502         return ERROR_OK;
1503 }
1504
1505 void parse_error(const char *string, char c, unsigned position)
1506 {
1507         char buf[position+2];
1508         for (unsigned i = 0; i < position; i++)
1509                 buf[i] = ' ';
1510         buf[position] = '^';
1511         buf[position + 1] = 0;
1512
1513         LOG_ERROR("Parse error at character %c in:", c);
1514         LOG_ERROR("%s", string);
1515         LOG_ERROR("%s", buf);
1516 }
1517
1518 int parse_ranges(range_t **ranges, const char **argv)
1519 {
1520         for (unsigned pass = 0; pass < 2; pass++) {
1521                 unsigned range = 0;
1522                 unsigned low = 0;
1523                 bool parse_low = true;
1524                 unsigned high = 0;
1525                 for (unsigned i = 0; i == 0 || argv[0][i-1]; i++) {
1526                         char c = argv[0][i];
1527                         if (isspace(c)) {
1528                                 /* Ignore whitespace. */
1529                                 continue;
1530                         }
1531
1532                         if (parse_low) {
1533                                 if (isdigit(c)) {
1534                                         low *= 10;
1535                                         low += c - '0';
1536                                 } else if (c == '-') {
1537                                         parse_low = false;
1538                                 } else if (c == ',' || c == 0) {
1539                                         if (pass == 1) {
1540                                                 (*ranges)[range].low = low;
1541                                                 (*ranges)[range].high = low;
1542                                         }
1543                                         low = 0;
1544                                         range++;
1545                                 } else {
1546                                         parse_error(argv[0], c, i);
1547                                         return ERROR_COMMAND_SYNTAX_ERROR;
1548                                 }
1549
1550                         } else {
1551                                 if (isdigit(c)) {
1552                                         high *= 10;
1553                                         high += c - '0';
1554                                 } else if (c == ',' || c == 0) {
1555                                         parse_low = true;
1556                                         if (pass == 1) {
1557                                                 (*ranges)[range].low = low;
1558                                                 (*ranges)[range].high = high;
1559                                         }
1560                                         low = 0;
1561                                         high = 0;
1562                                         range++;
1563                                 } else {
1564                                         parse_error(argv[0], c, i);
1565                                         return ERROR_COMMAND_SYNTAX_ERROR;
1566                                 }
1567                         }
1568                 }
1569
1570                 if (pass == 0) {
1571                         if (*ranges)
1572                                 free(*ranges);
1573                         *ranges = calloc(range + 2, sizeof(range_t));
1574                 } else {
1575                         (*ranges)[range].low = 1;
1576                         (*ranges)[range].high = 0;
1577                 }
1578         }
1579
1580         return ERROR_OK;
1581 }
1582
1583 COMMAND_HANDLER(riscv_set_expose_csrs)
1584 {
1585         if (CMD_ARGC != 1) {
1586                 LOG_ERROR("Command takes exactly 1 parameter");
1587                 return ERROR_COMMAND_SYNTAX_ERROR;
1588         }
1589
1590         return parse_ranges(&expose_csr, CMD_ARGV);
1591 }
1592
1593 COMMAND_HANDLER(riscv_set_expose_custom)
1594 {
1595         if (CMD_ARGC != 1) {
1596                 LOG_ERROR("Command takes exactly 1 parameter");
1597                 return ERROR_COMMAND_SYNTAX_ERROR;
1598         }
1599
1600         return parse_ranges(&expose_custom, CMD_ARGV);
1601 }
1602
1603 COMMAND_HANDLER(riscv_authdata_read)
1604 {
1605         if (CMD_ARGC != 0) {
1606                 LOG_ERROR("Command takes no parameters");
1607                 return ERROR_COMMAND_SYNTAX_ERROR;
1608         }
1609
1610         struct target *target = get_current_target(CMD_CTX);
1611         if (!target) {
1612                 LOG_ERROR("target is NULL!");
1613                 return ERROR_FAIL;
1614         }
1615
1616         RISCV_INFO(r);
1617         if (!r) {
1618                 LOG_ERROR("riscv_info is NULL!");
1619                 return ERROR_FAIL;
1620         }
1621
1622         if (r->authdata_read) {
1623                 uint32_t value;
1624                 if (r->authdata_read(target, &value) != ERROR_OK)
1625                         return ERROR_FAIL;
1626                 command_print(CMD, "0x%" PRIx32, value);
1627                 return ERROR_OK;
1628         } else {
1629                 LOG_ERROR("authdata_read is not implemented for this target.");
1630                 return ERROR_FAIL;
1631         }
1632 }
1633
1634 COMMAND_HANDLER(riscv_authdata_write)
1635 {
1636         if (CMD_ARGC != 1) {
1637                 LOG_ERROR("Command takes exactly 1 argument");
1638                 return ERROR_COMMAND_SYNTAX_ERROR;
1639         }
1640
1641         struct target *target = get_current_target(CMD_CTX);
1642         RISCV_INFO(r);
1643
1644         uint32_t value;
1645         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
1646
1647         if (r->authdata_write) {
1648                 return r->authdata_write(target, value);
1649         } else {
1650                 LOG_ERROR("authdata_write is not implemented for this target.");
1651                 return ERROR_FAIL;
1652         }
1653 }
1654
1655 COMMAND_HANDLER(riscv_dmi_read)
1656 {
1657         if (CMD_ARGC != 1) {
1658                 LOG_ERROR("Command takes 1 parameter");
1659                 return ERROR_COMMAND_SYNTAX_ERROR;
1660         }
1661
1662         struct target *target = get_current_target(CMD_CTX);
1663         if (!target) {
1664                 LOG_ERROR("target is NULL!");
1665                 return ERROR_FAIL;
1666         }
1667
1668         RISCV_INFO(r);
1669         if (!r) {
1670                 LOG_ERROR("riscv_info is NULL!");
1671                 return ERROR_FAIL;
1672         }
1673
1674         if (r->dmi_read) {
1675                 uint32_t address, value;
1676                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1677                 if (r->dmi_read(target, &value, address) != ERROR_OK)
1678                         return ERROR_FAIL;
1679                 command_print(CMD, "0x%" PRIx32, value);
1680                 return ERROR_OK;
1681         } else {
1682                 LOG_ERROR("dmi_read is not implemented for this target.");
1683                 return ERROR_FAIL;
1684         }
1685 }
1686
1687
1688 COMMAND_HANDLER(riscv_dmi_write)
1689 {
1690         if (CMD_ARGC != 2) {
1691                 LOG_ERROR("Command takes exactly 2 arguments");
1692                 return ERROR_COMMAND_SYNTAX_ERROR;
1693         }
1694
1695         struct target *target = get_current_target(CMD_CTX);
1696         RISCV_INFO(r);
1697
1698         uint32_t address, value;
1699         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1700         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1701
1702         if (r->dmi_write) {
1703                 return r->dmi_write(target, address, value);
1704         } else {
1705                 LOG_ERROR("dmi_write is not implemented for this target.");
1706                 return ERROR_FAIL;
1707         }
1708 }
1709
1710 COMMAND_HANDLER(riscv_test_sba_config_reg)
1711 {
1712         if (CMD_ARGC != 4) {
1713                 LOG_ERROR("Command takes exactly 4 arguments");
1714                 return ERROR_COMMAND_SYNTAX_ERROR;
1715         }
1716
1717         struct target *target = get_current_target(CMD_CTX);
1718         RISCV_INFO(r);
1719
1720         target_addr_t legal_address;
1721         uint32_t num_words;
1722         target_addr_t illegal_address;
1723         bool run_sbbusyerror_test;
1724
1725         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[0], legal_address);
1726         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words);
1727         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[2], illegal_address);
1728         COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test);
1729
1730         if (r->test_sba_config_reg) {
1731                 return r->test_sba_config_reg(target, legal_address, num_words,
1732                                 illegal_address, run_sbbusyerror_test);
1733         } else {
1734                 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
1735                 return ERROR_FAIL;
1736         }
1737 }
1738
1739 COMMAND_HANDLER(riscv_reset_delays)
1740 {
1741         int wait = 0;
1742
1743         if (CMD_ARGC > 1) {
1744                 LOG_ERROR("Command takes at most one argument");
1745                 return ERROR_COMMAND_SYNTAX_ERROR;
1746         }
1747
1748         if (CMD_ARGC == 1)
1749                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], wait);
1750
1751         struct target *target = get_current_target(CMD_CTX);
1752         RISCV_INFO(r);
1753         r->reset_delays_wait = wait;
1754         return ERROR_OK;
1755 }
1756
1757 COMMAND_HANDLER(riscv_set_ir)
1758 {
1759         if (CMD_ARGC != 2) {
1760                 LOG_ERROR("Command takes exactly 2 arguments");
1761                 return ERROR_COMMAND_SYNTAX_ERROR;
1762         }
1763
1764         uint32_t value;
1765         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1766
1767         if (!strcmp(CMD_ARGV[0], "idcode")) {
1768                 buf_set_u32(ir_idcode, 0, 32, value);
1769                 return ERROR_OK;
1770         } else if (!strcmp(CMD_ARGV[0], "dtmcs")) {
1771                 buf_set_u32(ir_dtmcontrol, 0, 32, value);
1772                 return ERROR_OK;
1773         } else if (!strcmp(CMD_ARGV[0], "dmi")) {
1774                 buf_set_u32(ir_dbus, 0, 32, value);
1775                 return ERROR_OK;
1776         } else {
1777                 return ERROR_FAIL;
1778         }
1779 }
1780
1781 static const struct command_registration riscv_exec_command_handlers[] = {
1782         {
1783                 .name = "test_compliance",
1784                 .handler = riscv_test_compliance,
1785                 .mode = COMMAND_EXEC,
1786                 .usage = "riscv test_compliance",
1787                 .help = "Runs a basic compliance test suite against the RISC-V Debug Spec."
1788         },
1789         {
1790                 .name = "set_command_timeout_sec",
1791                 .handler = riscv_set_command_timeout_sec,
1792                 .mode = COMMAND_ANY,
1793                 .usage = "riscv set_command_timeout_sec [sec]",
1794                 .help = "Set the wall-clock timeout (in seconds) for individual commands"
1795         },
1796         {
1797                 .name = "set_reset_timeout_sec",
1798                 .handler = riscv_set_reset_timeout_sec,
1799                 .mode = COMMAND_ANY,
1800                 .usage = "riscv set_reset_timeout_sec [sec]",
1801                 .help = "Set the wall-clock timeout (in seconds) after reset is deasserted"
1802         },
1803         {
1804                 .name = "set_prefer_sba",
1805                 .handler = riscv_set_prefer_sba,
1806                 .mode = COMMAND_ANY,
1807                 .usage = "riscv set_prefer_sba on|off",
1808                 .help = "When on, prefer to use System Bus Access to access memory. "
1809                         "When off, prefer to use the Program Buffer to access memory."
1810         },
1811         {
1812                 .name = "expose_csrs",
1813                 .handler = riscv_set_expose_csrs,
1814                 .mode = COMMAND_ANY,
1815                 .usage = "riscv expose_csrs n0[-m0][,n1[-m1]]...",
1816                 .help = "Configure a list of inclusive ranges for CSRs to expose in "
1817                                 "addition to the standard ones. This must be executed before "
1818                                 "`init`."
1819         },
1820         {
1821                 .name = "expose_custom",
1822                 .handler = riscv_set_expose_custom,
1823                 .mode = COMMAND_ANY,
1824                 .usage = "riscv expose_custom n0[-m0][,n1[-m1]]...",
1825                 .help = "Configure a list of inclusive ranges for custom registers to "
1826                         "expose. custom0 is accessed as abstract register number 0xc000, "
1827                         "etc. This must be executed before `init`."
1828         },
1829         {
1830                 .name = "authdata_read",
1831                 .handler = riscv_authdata_read,
1832                 .mode = COMMAND_ANY,
1833                 .usage = "riscv authdata_read",
1834                 .help = "Return the 32-bit value read from authdata."
1835         },
1836         {
1837                 .name = "authdata_write",
1838                 .handler = riscv_authdata_write,
1839                 .mode = COMMAND_ANY,
1840                 .usage = "riscv authdata_write value",
1841                 .help = "Write the 32-bit value to authdata."
1842         },
1843         {
1844                 .name = "dmi_read",
1845                 .handler = riscv_dmi_read,
1846                 .mode = COMMAND_ANY,
1847                 .usage = "riscv dmi_read address",
1848                 .help = "Perform a 32-bit DMI read at address, returning the value."
1849         },
1850         {
1851                 .name = "dmi_write",
1852                 .handler = riscv_dmi_write,
1853                 .mode = COMMAND_ANY,
1854                 .usage = "riscv dmi_write address value",
1855                 .help = "Perform a 32-bit DMI write of value at address."
1856         },
1857         {
1858                 .name = "test_sba_config_reg",
1859                 .handler = riscv_test_sba_config_reg,
1860                 .mode = COMMAND_ANY,
1861                 .usage = "riscv test_sba_config_reg legal_address num_words"
1862                         "illegal_address run_sbbusyerror_test[on/off]",
1863                 .help = "Perform a series of tests on the SBCS register."
1864                         "Inputs are a legal, 128-byte aligned address and a number of words to"
1865                         "read/write starting at that address (i.e., address range [legal address,"
1866                         "legal_address+word_size*num_words) must be legally readable/writable)"
1867                         ", an illegal, 128-byte aligned address for error flag/handling cases,"
1868                         "and whether sbbusyerror test should be run."
1869         },
1870         {
1871                 .name = "reset_delays",
1872                 .handler = riscv_reset_delays,
1873                 .mode = COMMAND_ANY,
1874                 .usage = "reset_delays [wait]",
1875                 .help = "OpenOCD learns how many Run-Test/Idle cycles are required "
1876                         "between scans to avoid encountering the target being busy. This "
1877                         "command resets those learned values after `wait` scans. It's only "
1878                         "useful for testing OpenOCD itself."
1879         },
1880         {
1881                 .name = "set_ir",
1882                 .handler = riscv_set_ir,
1883                 .mode = COMMAND_ANY,
1884                 .usage = "riscv set_ir_idcode [idcode|dtmcs|dmi] value",
1885                 .help = "Set IR value for specified JTAG register."
1886         },
1887         COMMAND_REGISTRATION_DONE
1888 };
1889
1890 extern __COMMAND_HANDLER(handle_common_semihosting_command);
1891 extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command);
1892 extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command);
1893 extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
1894
1895 /*
1896  * To be noted that RISC-V targets use the same semihosting commands as
1897  * ARM targets.
1898  *
1899  * The main reason is compatibility with existing tools. For example the
1900  * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
1901  * configure semihosting, which generate commands like `arm semihosting
1902  * enable`.
1903  * A secondary reason is the fact that the protocol used is exactly the
1904  * one specified by ARM. If RISC-V will ever define its own semihosting
1905  * protocol, then a command like `riscv semihosting enable` will make
1906  * sense, but for now all semihosting commands are prefixed with `arm`.
1907  */
1908 static const struct command_registration arm_exec_command_handlers[] = {
1909         {
1910                 .name = "semihosting",
1911                 .handler = handle_common_semihosting_command,
1912                 .mode = COMMAND_EXEC,
1913                 .usage = "['enable'|'disable']",
1914                 .help = "activate support for semihosting operations",
1915         },
1916         {
1917                 .name = "semihosting_cmdline",
1918                 .handler = handle_common_semihosting_cmdline,
1919                 .mode = COMMAND_EXEC,
1920                 .usage = "arguments",
1921                 .help = "command line arguments to be passed to program",
1922         },
1923         {
1924                 .name = "semihosting_fileio",
1925                 .handler = handle_common_semihosting_fileio_command,
1926                 .mode = COMMAND_EXEC,
1927                 .usage = "['enable'|'disable']",
1928                 .help = "activate support for semihosting fileio operations",
1929         },
1930         {
1931                 .name = "semihosting_resexit",
1932                 .handler = handle_common_semihosting_resumable_exit_command,
1933                 .mode = COMMAND_EXEC,
1934                 .usage = "['enable'|'disable']",
1935                 .help = "activate support for semihosting resumable exit",
1936         },
1937         COMMAND_REGISTRATION_DONE
1938 };
1939
1940 const struct command_registration riscv_command_handlers[] = {
1941         {
1942                 .name = "riscv",
1943                 .mode = COMMAND_ANY,
1944                 .help = "RISC-V Command Group",
1945                 .usage = "",
1946                 .chain = riscv_exec_command_handlers
1947         },
1948         {
1949                 .name = "arm",
1950                 .mode = COMMAND_ANY,
1951                 .help = "ARM Command Group",
1952                 .usage = "",
1953                 .chain = arm_exec_command_handlers
1954         },
1955         COMMAND_REGISTRATION_DONE
1956 };
1957
1958 unsigned riscv_address_bits(struct target *target)
1959 {
1960         return riscv_xlen(target);
1961 }
1962
1963 struct target_type riscv_target = {
1964         .name = "riscv",
1965
1966         .init_target = riscv_init_target,
1967         .deinit_target = riscv_deinit_target,
1968         .examine = riscv_examine,
1969
1970         /* poll current target status */
1971         .poll = old_or_new_riscv_poll,
1972
1973         .halt = old_or_new_riscv_halt,
1974         .resume = old_or_new_riscv_resume,
1975         .step = old_or_new_riscv_step,
1976
1977         .assert_reset = riscv_assert_reset,
1978         .deassert_reset = riscv_deassert_reset,
1979
1980         .read_memory = riscv_read_memory,
1981         .write_memory = riscv_write_memory,
1982
1983         .checksum_memory = riscv_checksum_memory,
1984
1985         .get_gdb_reg_list = riscv_get_gdb_reg_list,
1986
1987         .add_breakpoint = riscv_add_breakpoint,
1988         .remove_breakpoint = riscv_remove_breakpoint,
1989
1990         .add_watchpoint = riscv_add_watchpoint,
1991         .remove_watchpoint = riscv_remove_watchpoint,
1992         .hit_watchpoint = riscv_hit_watchpoint,
1993
1994         .arch_state = riscv_arch_state,
1995
1996         .run_algorithm = riscv_run_algorithm,
1997
1998         .commands = riscv_command_handlers,
1999
2000         .address_bits = riscv_address_bits
2001 };
2002
2003 /*** RISC-V Interface ***/
2004
2005 void riscv_info_init(struct target *target, riscv_info_t *r)
2006 {
2007         memset(r, 0, sizeof(*r));
2008         r->dtm_version = 1;
2009         r->registers_initialized = false;
2010         r->current_hartid = target->coreid;
2011
2012         memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
2013
2014         for (size_t h = 0; h < RISCV_MAX_HARTS; ++h) {
2015                 r->xlen[h] = -1;
2016
2017                 for (size_t e = 0; e < RISCV_MAX_REGISTERS; ++e)
2018                         r->valid_saved_registers[h][e] = false;
2019         }
2020 }
2021
2022 int riscv_halt_all_harts(struct target *target)
2023 {
2024         for (int i = 0; i < riscv_count_harts(target); ++i) {
2025                 if (!riscv_hart_enabled(target, i))
2026                         continue;
2027
2028                 riscv_halt_one_hart(target, i);
2029         }
2030
2031         riscv_invalidate_register_cache(target);
2032
2033         return ERROR_OK;
2034 }
2035
2036 int riscv_halt_one_hart(struct target *target, int hartid)
2037 {
2038         RISCV_INFO(r);
2039         LOG_DEBUG("halting hart %d", hartid);
2040         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2041                 return ERROR_FAIL;
2042         if (riscv_is_halted(target)) {
2043                 LOG_DEBUG("  hart %d requested halt, but was already halted", hartid);
2044                 return ERROR_OK;
2045         }
2046
2047         int result = r->halt_current_hart(target);
2048         register_cache_invalidate(target->reg_cache);
2049         return result;
2050 }
2051
2052 int riscv_resume_all_harts(struct target *target)
2053 {
2054         for (int i = 0; i < riscv_count_harts(target); ++i) {
2055                 if (!riscv_hart_enabled(target, i))
2056                         continue;
2057
2058                 riscv_resume_one_hart(target, i);
2059         }
2060
2061         riscv_invalidate_register_cache(target);
2062         return ERROR_OK;
2063 }
2064
2065 int riscv_resume_one_hart(struct target *target, int hartid)
2066 {
2067         RISCV_INFO(r);
2068         LOG_DEBUG("resuming hart %d", hartid);
2069         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2070                 return ERROR_FAIL;
2071         if (!riscv_is_halted(target)) {
2072                 LOG_DEBUG("  hart %d requested resume, but was already resumed", hartid);
2073                 return ERROR_OK;
2074         }
2075
2076         r->on_resume(target);
2077         return r->resume_current_hart(target);
2078 }
2079
2080 int riscv_step_rtos_hart(struct target *target)
2081 {
2082         RISCV_INFO(r);
2083         int hartid = r->current_hartid;
2084         if (riscv_rtos_enabled(target)) {
2085                 hartid = r->rtos_hartid;
2086                 if (hartid == -1) {
2087                         LOG_DEBUG("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
2088                         hartid = 0;
2089                 }
2090         }
2091         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2092                 return ERROR_FAIL;
2093         LOG_DEBUG("stepping hart %d", hartid);
2094
2095         if (!riscv_is_halted(target)) {
2096                 LOG_ERROR("Hart isn't halted before single step!");
2097                 return ERROR_FAIL;
2098         }
2099         riscv_invalidate_register_cache(target);
2100         r->on_step(target);
2101         if (r->step_current_hart(target) != ERROR_OK)
2102                 return ERROR_FAIL;
2103         riscv_invalidate_register_cache(target);
2104         r->on_halt(target);
2105         if (!riscv_is_halted(target)) {
2106                 LOG_ERROR("Hart was not halted after single step!");
2107                 return ERROR_FAIL;
2108         }
2109         return ERROR_OK;
2110 }
2111
2112 bool riscv_supports_extension(struct target *target, int hartid, char letter)
2113 {
2114         RISCV_INFO(r);
2115         unsigned num;
2116         if (letter >= 'a' && letter <= 'z')
2117                 num = letter - 'a';
2118         else if (letter >= 'A' && letter <= 'Z')
2119                 num = letter - 'A';
2120         else
2121                 return false;
2122         return r->misa[hartid] & (1 << num);
2123 }
2124
2125 int riscv_xlen(const struct target *target)
2126 {
2127         return riscv_xlen_of_hart(target, riscv_current_hartid(target));
2128 }
2129
2130 int riscv_xlen_of_hart(const struct target *target, int hartid)
2131 {
2132         RISCV_INFO(r);
2133         assert(r->xlen[hartid] != -1);
2134         return r->xlen[hartid];
2135 }
2136
2137 extern struct rtos_type riscv_rtos;
2138 bool riscv_rtos_enabled(const struct target *target)
2139 {
2140         return false;
2141 }
2142
2143 int riscv_set_current_hartid(struct target *target, int hartid)
2144 {
2145         RISCV_INFO(r);
2146         if (!r->select_current_hart)
2147                 return ERROR_OK;
2148
2149         int previous_hartid = riscv_current_hartid(target);
2150         r->current_hartid = hartid;
2151         assert(riscv_hart_enabled(target, hartid));
2152         LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
2153         if (r->select_current_hart(target) != ERROR_OK)
2154                 return ERROR_FAIL;
2155
2156         /* This might get called during init, in which case we shouldn't be
2157          * setting up the register cache. */
2158         if (target_was_examined(target) && riscv_rtos_enabled(target))
2159                 riscv_invalidate_register_cache(target);
2160
2161         return ERROR_OK;
2162 }
2163
2164 void riscv_invalidate_register_cache(struct target *target)
2165 {
2166         RISCV_INFO(r);
2167
2168         LOG_DEBUG("[%d]", target->coreid);
2169         register_cache_invalidate(target->reg_cache);
2170         for (size_t i = 0; i < target->reg_cache->num_regs; ++i) {
2171                 struct reg *reg = &target->reg_cache->reg_list[i];
2172                 reg->valid = false;
2173         }
2174
2175         r->registers_initialized = true;
2176 }
2177
2178 int riscv_current_hartid(const struct target *target)
2179 {
2180         RISCV_INFO(r);
2181         return r->current_hartid;
2182 }
2183
2184 void riscv_set_all_rtos_harts(struct target *target)
2185 {
2186         RISCV_INFO(r);
2187         r->rtos_hartid = -1;
2188 }
2189
2190 void riscv_set_rtos_hartid(struct target *target, int hartid)
2191 {
2192         LOG_DEBUG("setting RTOS hartid %d", hartid);
2193         RISCV_INFO(r);
2194         r->rtos_hartid = hartid;
2195 }
2196
2197 int riscv_count_harts(struct target *target)
2198 {
2199         if (target == NULL)
2200                 return 1;
2201         RISCV_INFO(r);
2202         if (r == NULL)
2203                 return 1;
2204         return r->hart_count;
2205 }
2206
2207 bool riscv_has_register(struct target *target, int hartid, int regid)
2208 {
2209         return 1;
2210 }
2211
2212 /**
2213  * This function is called when the debug user wants to change the value of a
2214  * register. The new value may be cached, and may not be written until the hart
2215  * is resumed. */
2216 int riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v)
2217 {
2218         return riscv_set_register_on_hart(target, riscv_current_hartid(target), r, v);
2219 }
2220
2221 int riscv_set_register_on_hart(struct target *target, int hartid,
2222                 enum gdb_regno regid, uint64_t value)
2223 {
2224         RISCV_INFO(r);
2225         LOG_DEBUG("{%d} %s <- %" PRIx64, hartid, gdb_regno_name(regid), value);
2226         assert(r->set_register);
2227         return r->set_register(target, hartid, regid, value);
2228 }
2229
2230 int riscv_get_register(struct target *target, riscv_reg_t *value,
2231                 enum gdb_regno r)
2232 {
2233         return riscv_get_register_on_hart(target, value,
2234                         riscv_current_hartid(target), r);
2235 }
2236
2237 int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
2238                 int hartid, enum gdb_regno regid)
2239 {
2240         RISCV_INFO(r);
2241
2242         struct reg *reg = &target->reg_cache->reg_list[regid];
2243
2244         if (reg && reg->valid && hartid == riscv_current_hartid(target)) {
2245                 *value = buf_get_u64(reg->value, 0, reg->size);
2246                 return ERROR_OK;
2247         }
2248
2249         int result = r->get_register(target, value, hartid, regid);
2250
2251         LOG_DEBUG("{%d} %s: %" PRIx64, hartid, gdb_regno_name(regid), *value);
2252         return result;
2253 }
2254
2255 bool riscv_is_halted(struct target *target)
2256 {
2257         RISCV_INFO(r);
2258         assert(r->is_halted);
2259         return r->is_halted(target);
2260 }
2261
2262 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
2263 {
2264         RISCV_INFO(r);
2265         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2266                 return RISCV_HALT_ERROR;
2267         if (!riscv_is_halted(target)) {
2268                 LOG_ERROR("Hart is not halted!");
2269                 return RISCV_HALT_UNKNOWN;
2270         }
2271         return r->halt_reason(target);
2272 }
2273
2274 size_t riscv_debug_buffer_size(struct target *target)
2275 {
2276         RISCV_INFO(r);
2277         return r->debug_buffer_size[riscv_current_hartid(target)];
2278 }
2279
2280 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
2281 {
2282         RISCV_INFO(r);
2283         r->write_debug_buffer(target, index, insn);
2284         return ERROR_OK;
2285 }
2286
2287 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
2288 {
2289         RISCV_INFO(r);
2290         return r->read_debug_buffer(target, index);
2291 }
2292
2293 int riscv_execute_debug_buffer(struct target *target)
2294 {
2295         RISCV_INFO(r);
2296         return r->execute_debug_buffer(target);
2297 }
2298
2299 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
2300 {
2301         RISCV_INFO(r);
2302         r->fill_dmi_write_u64(target, buf, a, d);
2303 }
2304
2305 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
2306 {
2307         RISCV_INFO(r);
2308         r->fill_dmi_read_u64(target, buf, a);
2309 }
2310
2311 void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
2312 {
2313         RISCV_INFO(r);
2314         r->fill_dmi_nop_u64(target, buf);
2315 }
2316
2317 int riscv_dmi_write_u64_bits(struct target *target)
2318 {
2319         RISCV_INFO(r);
2320         return r->dmi_write_u64_bits(target);
2321 }
2322
2323 bool riscv_hart_enabled(struct target *target, int hartid)
2324 {
2325         /* FIXME: Add a hart mask to the RTOS. */
2326         if (riscv_rtos_enabled(target))
2327                 return hartid < riscv_count_harts(target);
2328
2329         return hartid == target->coreid;
2330 }
2331
2332 /**
2333  * Count triggers, and initialize trigger_count for each hart.
2334  * trigger_count is initialized even if this function fails to discover
2335  * something.
2336  * Disable any hardware triggers that have dmode set. We can't have set them
2337  * ourselves. Maybe they're left over from some killed debug session.
2338  * */
2339 int riscv_enumerate_triggers(struct target *target)
2340 {
2341         RISCV_INFO(r);
2342
2343         if (r->triggers_enumerated)
2344                 return ERROR_OK;
2345
2346         r->triggers_enumerated = true;  /* At the very least we tried. */
2347
2348         for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
2349                 if (!riscv_hart_enabled(target, hartid))
2350                         continue;
2351
2352                 riscv_reg_t tselect;
2353                 int result = riscv_get_register_on_hart(target, &tselect, hartid,
2354                                 GDB_REGNO_TSELECT);
2355                 if (result != ERROR_OK)
2356                         return result;
2357
2358                 for (unsigned t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
2359                         r->trigger_count[hartid] = t;
2360
2361                         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, t);
2362                         uint64_t tselect_rb;
2363                         result = riscv_get_register_on_hart(target, &tselect_rb, hartid,
2364                                         GDB_REGNO_TSELECT);
2365                         if (result != ERROR_OK)
2366                                 return result;
2367                         /* Mask off the top bit, which is used as tdrmode in old
2368                          * implementations. */
2369                         tselect_rb &= ~(1ULL << (riscv_xlen(target)-1));
2370                         if (tselect_rb != t)
2371                                 break;
2372                         uint64_t tdata1;
2373                         result = riscv_get_register_on_hart(target, &tdata1, hartid,
2374                                         GDB_REGNO_TDATA1);
2375                         if (result != ERROR_OK)
2376                                 return result;
2377
2378                         int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
2379                         switch (type) {
2380                                 case 1:
2381                                         /* On these older cores we don't support software using
2382                                          * triggers. */
2383                                         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
2384                                         break;
2385                                 case 2:
2386                                         if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
2387                                                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
2388                                         break;
2389                         }
2390                 }
2391
2392                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
2393
2394                 LOG_INFO("[%d] Found %d triggers", hartid, r->trigger_count[hartid]);
2395         }
2396
2397         return ERROR_OK;
2398 }
2399
2400 const char *gdb_regno_name(enum gdb_regno regno)
2401 {
2402         static char buf[32];
2403
2404         switch (regno) {
2405                 case GDB_REGNO_ZERO:
2406                         return "zero";
2407                 case GDB_REGNO_S0:
2408                         return "s0";
2409                 case GDB_REGNO_S1:
2410                         return "s1";
2411                 case GDB_REGNO_PC:
2412                         return "pc";
2413                 case GDB_REGNO_FPR0:
2414                         return "fpr0";
2415                 case GDB_REGNO_FPR31:
2416                         return "fpr31";
2417                 case GDB_REGNO_CSR0:
2418                         return "csr0";
2419                 case GDB_REGNO_TSELECT:
2420                         return "tselect";
2421                 case GDB_REGNO_TDATA1:
2422                         return "tdata1";
2423                 case GDB_REGNO_TDATA2:
2424                         return "tdata2";
2425                 case GDB_REGNO_MISA:
2426                         return "misa";
2427                 case GDB_REGNO_DPC:
2428                         return "dpc";
2429                 case GDB_REGNO_DCSR:
2430                         return "dcsr";
2431                 case GDB_REGNO_DSCRATCH:
2432                         return "dscratch";
2433                 case GDB_REGNO_MSTATUS:
2434                         return "mstatus";
2435                 case GDB_REGNO_PRIV:
2436                         return "priv";
2437                 default:
2438                         if (regno <= GDB_REGNO_XPR31)
2439                                 sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
2440                         else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095)
2441                                 sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0);
2442                         else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31)
2443                                 sprintf(buf, "f%d", regno - GDB_REGNO_FPR0);
2444                         else
2445                                 sprintf(buf, "gdb_regno_%d", regno);
2446                         return buf;
2447         }
2448 }
2449
2450 static int register_get(struct reg *reg)
2451 {
2452         riscv_reg_info_t *reg_info = reg->arch_info;
2453         struct target *target = reg_info->target;
2454         uint64_t value;
2455         int result = riscv_get_register(target, &value, reg->number);
2456         if (result != ERROR_OK)
2457                 return result;
2458         buf_set_u64(reg->value, 0, reg->size, value);
2459         /* CSRs (and possibly other extension) registers may change value at any
2460          * time. */
2461         if (reg->number <= GDB_REGNO_XPR31 ||
2462                         (reg->number >= GDB_REGNO_FPR0 && reg->number <= GDB_REGNO_FPR31) ||
2463                         reg->number == GDB_REGNO_PC)
2464                 reg->valid = true;
2465         LOG_DEBUG("[%d]{%d} read 0x%" PRIx64 " from %s (valid=%d)",
2466                         target->coreid, riscv_current_hartid(target), value, reg->name,
2467                         reg->valid);
2468         return ERROR_OK;
2469 }
2470
2471 static int register_set(struct reg *reg, uint8_t *buf)
2472 {
2473         riscv_reg_info_t *reg_info = reg->arch_info;
2474         struct target *target = reg_info->target;
2475
2476         uint64_t value = buf_get_u64(buf, 0, reg->size);
2477
2478         LOG_DEBUG("[%d]{%d} write 0x%" PRIx64 " to %s (valid=%d)",
2479                         target->coreid, riscv_current_hartid(target), value, reg->name,
2480                         reg->valid);
2481         struct reg *r = &target->reg_cache->reg_list[reg->number];
2482         /* CSRs (and possibly other extension) registers may change value at any
2483          * time. */
2484         if (reg->number <= GDB_REGNO_XPR31 ||
2485                         (reg->number >= GDB_REGNO_FPR0 && reg->number <= GDB_REGNO_FPR31) ||
2486                         reg->number == GDB_REGNO_PC)
2487                 r->valid = true;
2488         memcpy(r->value, buf, (r->size + 7) / 8);
2489
2490         riscv_set_register(target, reg->number, value);
2491         return ERROR_OK;
2492 }
2493
2494 static struct reg_arch_type riscv_reg_arch_type = {
2495         .get = register_get,
2496         .set = register_set
2497 };
2498
2499 struct csr_info {
2500         unsigned number;
2501         const char *name;
2502 };
2503
2504 static int cmp_csr_info(const void *p1, const void *p2)
2505 {
2506         return (int) (((struct csr_info *)p1)->number) - (int) (((struct csr_info *)p2)->number);
2507 }
2508
2509 int riscv_init_registers(struct target *target)
2510 {
2511         RISCV_INFO(info);
2512
2513         riscv_free_registers(target);
2514
2515         target->reg_cache = calloc(1, sizeof(*target->reg_cache));
2516         target->reg_cache->name = "RISC-V Registers";
2517         target->reg_cache->num_regs = GDB_REGNO_COUNT;
2518
2519         if (expose_custom) {
2520                 for (unsigned i = 0; expose_custom[i].low <= expose_custom[i].high; i++) {
2521                         for (unsigned number = expose_custom[i].low;
2522                                         number <= expose_custom[i].high;
2523                                         number++)
2524                                 target->reg_cache->num_regs++;
2525                 }
2526         }
2527
2528         LOG_DEBUG("create register cache for %d registers",
2529                         target->reg_cache->num_regs);
2530
2531         target->reg_cache->reg_list =
2532                 calloc(target->reg_cache->num_regs, sizeof(struct reg));
2533
2534         const unsigned int max_reg_name_len = 12;
2535         if (info->reg_names)
2536                 free(info->reg_names);
2537         info->reg_names =
2538                 calloc(target->reg_cache->num_regs, max_reg_name_len);
2539         char *reg_name = info->reg_names;
2540
2541         static struct reg_feature feature_cpu = {
2542                 .name = "org.gnu.gdb.riscv.cpu"
2543         };
2544         static struct reg_feature feature_fpu = {
2545                 .name = "org.gnu.gdb.riscv.fpu"
2546         };
2547         static struct reg_feature feature_csr = {
2548                 .name = "org.gnu.gdb.riscv.csr"
2549         };
2550         static struct reg_feature feature_virtual = {
2551                 .name = "org.gnu.gdb.riscv.virtual"
2552         };
2553         static struct reg_feature feature_custom = {
2554                 .name = "org.gnu.gdb.riscv.custom"
2555         };
2556
2557         static struct reg_data_type type_ieee_single = {
2558                 .type = REG_TYPE_IEEE_SINGLE,
2559                 .id = "ieee_single"
2560         };
2561         static struct reg_data_type type_ieee_double = {
2562                 .type = REG_TYPE_IEEE_DOUBLE,
2563                 .id = "ieee_double"
2564         };
2565         struct csr_info csr_info[] = {
2566 #define DECLARE_CSR(name, number) { number, #name },
2567 #include "encoding.h"
2568 #undef DECLARE_CSR
2569         };
2570         /* encoding.h does not contain the registers in sorted order. */
2571         qsort(csr_info, DIM(csr_info), sizeof(*csr_info), cmp_csr_info);
2572         unsigned csr_info_index = 0;
2573
2574         unsigned custom_range_index = 0;
2575         int custom_within_range = 0;
2576
2577         riscv_reg_info_t *shared_reg_info = calloc(1, sizeof(riscv_reg_info_t));
2578         shared_reg_info->target = target;
2579
2580         /* When gdb requests register N, gdb_get_register_packet() assumes that this
2581          * is register at index N in reg_list. So if there are certain registers
2582          * that don't exist, we need to leave holes in the list (or renumber, but
2583          * it would be nice not to have yet another set of numbers to translate
2584          * between). */
2585         for (uint32_t number = 0; number < target->reg_cache->num_regs; number++) {
2586                 struct reg *r = &target->reg_cache->reg_list[number];
2587                 r->dirty = false;
2588                 r->valid = false;
2589                 r->exist = true;
2590                 r->type = &riscv_reg_arch_type;
2591                 r->arch_info = shared_reg_info;
2592                 r->number = number;
2593                 r->size = riscv_xlen(target);
2594                 /* r->size is set in riscv_invalidate_register_cache, maybe because the
2595                  * target is in theory allowed to change XLEN on us. But I expect a lot
2596                  * of other things to break in that case as well. */
2597                 if (number <= GDB_REGNO_XPR31) {
2598                         r->caller_save = true;
2599                         switch (number) {
2600                                 case GDB_REGNO_ZERO:
2601                                         r->name = "zero";
2602                                         break;
2603                                 case GDB_REGNO_RA:
2604                                         r->name = "ra";
2605                                         break;
2606                                 case GDB_REGNO_SP:
2607                                         r->name = "sp";
2608                                         break;
2609                                 case GDB_REGNO_GP:
2610                                         r->name = "gp";
2611                                         break;
2612                                 case GDB_REGNO_TP:
2613                                         r->name = "tp";
2614                                         break;
2615                                 case GDB_REGNO_T0:
2616                                         r->name = "t0";
2617                                         break;
2618                                 case GDB_REGNO_T1:
2619                                         r->name = "t1";
2620                                         break;
2621                                 case GDB_REGNO_T2:
2622                                         r->name = "t2";
2623                                         break;
2624                                 case GDB_REGNO_FP:
2625                                         r->name = "fp";
2626                                         break;
2627                                 case GDB_REGNO_S1:
2628                                         r->name = "s1";
2629                                         break;
2630                                 case GDB_REGNO_A0:
2631                                         r->name = "a0";
2632                                         break;
2633                                 case GDB_REGNO_A1:
2634                                         r->name = "a1";
2635                                         break;
2636                                 case GDB_REGNO_A2:
2637                                         r->name = "a2";
2638                                         break;
2639                                 case GDB_REGNO_A3:
2640                                         r->name = "a3";
2641                                         break;
2642                                 case GDB_REGNO_A4:
2643                                         r->name = "a4";
2644                                         break;
2645                                 case GDB_REGNO_A5:
2646                                         r->name = "a5";
2647                                         break;
2648                                 case GDB_REGNO_A6:
2649                                         r->name = "a6";
2650                                         break;
2651                                 case GDB_REGNO_A7:
2652                                         r->name = "a7";
2653                                         break;
2654                                 case GDB_REGNO_S2:
2655                                         r->name = "s2";
2656                                         break;
2657                                 case GDB_REGNO_S3:
2658                                         r->name = "s3";
2659                                         break;
2660                                 case GDB_REGNO_S4:
2661                                         r->name = "s4";
2662                                         break;
2663                                 case GDB_REGNO_S5:
2664                                         r->name = "s5";
2665                                         break;
2666                                 case GDB_REGNO_S6:
2667                                         r->name = "s6";
2668                                         break;
2669                                 case GDB_REGNO_S7:
2670                                         r->name = "s7";
2671                                         break;
2672                                 case GDB_REGNO_S8:
2673                                         r->name = "s8";
2674                                         break;
2675                                 case GDB_REGNO_S9:
2676                                         r->name = "s9";
2677                                         break;
2678                                 case GDB_REGNO_S10:
2679                                         r->name = "s10";
2680                                         break;
2681                                 case GDB_REGNO_S11:
2682                                         r->name = "s11";
2683                                         break;
2684                                 case GDB_REGNO_T3:
2685                                         r->name = "t3";
2686                                         break;
2687                                 case GDB_REGNO_T4:
2688                                         r->name = "t4";
2689                                         break;
2690                                 case GDB_REGNO_T5:
2691                                         r->name = "t5";
2692                                         break;
2693                                 case GDB_REGNO_T6:
2694                                         r->name = "t6";
2695                                         break;
2696                         }
2697                         r->group = "general";
2698                         r->feature = &feature_cpu;
2699                 } else if (number == GDB_REGNO_PC) {
2700                         r->caller_save = true;
2701                         sprintf(reg_name, "pc");
2702                         r->group = "general";
2703                         r->feature = &feature_cpu;
2704                 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
2705                         r->caller_save = true;
2706                         if (riscv_supports_extension(target, riscv_current_hartid(target),
2707                                                 'D')) {
2708                                 r->reg_data_type = &type_ieee_double;
2709                                 r->size = 64;
2710                         } else if (riscv_supports_extension(target,
2711                                                 riscv_current_hartid(target), 'F')) {
2712                                 r->reg_data_type = &type_ieee_single;
2713                                 r->size = 32;
2714                         } else {
2715                                 r->exist = false;
2716                         }
2717                         switch (number) {
2718                                 case GDB_REGNO_FT0:
2719                                         r->name = "ft0";
2720                                         break;
2721                                 case GDB_REGNO_FT1:
2722                                         r->name = "ft1";
2723                                         break;
2724                                 case GDB_REGNO_FT2:
2725                                         r->name = "ft2";
2726                                         break;
2727                                 case GDB_REGNO_FT3:
2728                                         r->name = "ft3";
2729                                         break;
2730                                 case GDB_REGNO_FT4:
2731                                         r->name = "ft4";
2732                                         break;
2733                                 case GDB_REGNO_FT5:
2734                                         r->name = "ft5";
2735                                         break;
2736                                 case GDB_REGNO_FT6:
2737                                         r->name = "ft6";
2738                                         break;
2739                                 case GDB_REGNO_FT7:
2740                                         r->name = "ft7";
2741                                         break;
2742                                 case GDB_REGNO_FS0:
2743                                         r->name = "fs0";
2744                                         break;
2745                                 case GDB_REGNO_FS1:
2746                                         r->name = "fs1";
2747                                         break;
2748                                 case GDB_REGNO_FA0:
2749                                         r->name = "fa0";
2750                                         break;
2751                                 case GDB_REGNO_FA1:
2752                                         r->name = "fa1";
2753                                         break;
2754                                 case GDB_REGNO_FA2:
2755                                         r->name = "fa2";
2756                                         break;
2757                                 case GDB_REGNO_FA3:
2758                                         r->name = "fa3";
2759                                         break;
2760                                 case GDB_REGNO_FA4:
2761                                         r->name = "fa4";
2762                                         break;
2763                                 case GDB_REGNO_FA5:
2764                                         r->name = "fa5";
2765                                         break;
2766                                 case GDB_REGNO_FA6:
2767                                         r->name = "fa6";
2768                                         break;
2769                                 case GDB_REGNO_FA7:
2770                                         r->name = "fa7";
2771                                         break;
2772                                 case GDB_REGNO_FS2:
2773                                         r->name = "fs2";
2774                                         break;
2775                                 case GDB_REGNO_FS3:
2776                                         r->name = "fs3";
2777                                         break;
2778                                 case GDB_REGNO_FS4:
2779                                         r->name = "fs4";
2780                                         break;
2781                                 case GDB_REGNO_FS5:
2782                                         r->name = "fs5";
2783                                         break;
2784                                 case GDB_REGNO_FS6:
2785                                         r->name = "fs6";
2786                                         break;
2787                                 case GDB_REGNO_FS7:
2788                                         r->name = "fs7";
2789                                         break;
2790                                 case GDB_REGNO_FS8:
2791                                         r->name = "fs8";
2792                                         break;
2793                                 case GDB_REGNO_FS9:
2794                                         r->name = "fs9";
2795                                         break;
2796                                 case GDB_REGNO_FS10:
2797                                         r->name = "fs10";
2798                                         break;
2799                                 case GDB_REGNO_FS11:
2800                                         r->name = "fs11";
2801                                         break;
2802                                 case GDB_REGNO_FT8:
2803                                         r->name = "ft8";
2804                                         break;
2805                                 case GDB_REGNO_FT9:
2806                                         r->name = "ft9";
2807                                         break;
2808                                 case GDB_REGNO_FT10:
2809                                         r->name = "ft10";
2810                                         break;
2811                                 case GDB_REGNO_FT11:
2812                                         r->name = "ft11";
2813                                         break;
2814                         }
2815                         r->group = "float";
2816                         r->feature = &feature_fpu;
2817                 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
2818                         r->group = "csr";
2819                         r->feature = &feature_csr;
2820                         unsigned csr_number = number - GDB_REGNO_CSR0;
2821
2822                         while (csr_info[csr_info_index].number < csr_number &&
2823                                         csr_info_index < DIM(csr_info) - 1) {
2824                                 csr_info_index++;
2825                         }
2826                         if (csr_info[csr_info_index].number == csr_number) {
2827                                 r->name = csr_info[csr_info_index].name;
2828                         } else {
2829                                 sprintf(reg_name, "csr%d", csr_number);
2830                                 /* Assume unnamed registers don't exist, unless we have some
2831                                  * configuration that tells us otherwise. That's important
2832                                  * because eg. Eclipse crashes if a target has too many
2833                                  * registers, and apparently has no way of only showing a
2834                                  * subset of registers in any case. */
2835                                 r->exist = false;
2836                         }
2837
2838                         switch (csr_number) {
2839                                 case CSR_FFLAGS:
2840                                 case CSR_FRM:
2841                                 case CSR_FCSR:
2842                                         r->exist = riscv_supports_extension(target,
2843                                                         riscv_current_hartid(target), 'F');
2844                                         r->group = "float";
2845                                         r->feature = &feature_fpu;
2846                                         break;
2847                                 case CSR_SSTATUS:
2848                                 case CSR_STVEC:
2849                                 case CSR_SIP:
2850                                 case CSR_SIE:
2851                                 case CSR_SCOUNTEREN:
2852                                 case CSR_SSCRATCH:
2853                                 case CSR_SEPC:
2854                                 case CSR_SCAUSE:
2855                                 case CSR_STVAL:
2856                                 case CSR_SATP:
2857                                         r->exist = riscv_supports_extension(target,
2858                                                         riscv_current_hartid(target), 'S');
2859                                         break;
2860                                 case CSR_MEDELEG:
2861                                 case CSR_MIDELEG:
2862                                         /* "In systems with only M-mode, or with both M-mode and
2863                                          * U-mode but without U-mode trap support, the medeleg and
2864                                          * mideleg registers should not exist." */
2865                                         r->exist = riscv_supports_extension(target, riscv_current_hartid(target), 'S') ||
2866                                                 riscv_supports_extension(target, riscv_current_hartid(target), 'N');
2867                                         break;
2868
2869                                 case CSR_CYCLEH:
2870                                 case CSR_TIMEH:
2871                                 case CSR_INSTRETH:
2872                                 case CSR_HPMCOUNTER3H:
2873                                 case CSR_HPMCOUNTER4H:
2874                                 case CSR_HPMCOUNTER5H:
2875                                 case CSR_HPMCOUNTER6H:
2876                                 case CSR_HPMCOUNTER7H:
2877                                 case CSR_HPMCOUNTER8H:
2878                                 case CSR_HPMCOUNTER9H:
2879                                 case CSR_HPMCOUNTER10H:
2880                                 case CSR_HPMCOUNTER11H:
2881                                 case CSR_HPMCOUNTER12H:
2882                                 case CSR_HPMCOUNTER13H:
2883                                 case CSR_HPMCOUNTER14H:
2884                                 case CSR_HPMCOUNTER15H:
2885                                 case CSR_HPMCOUNTER16H:
2886                                 case CSR_HPMCOUNTER17H:
2887                                 case CSR_HPMCOUNTER18H:
2888                                 case CSR_HPMCOUNTER19H:
2889                                 case CSR_HPMCOUNTER20H:
2890                                 case CSR_HPMCOUNTER21H:
2891                                 case CSR_HPMCOUNTER22H:
2892                                 case CSR_HPMCOUNTER23H:
2893                                 case CSR_HPMCOUNTER24H:
2894                                 case CSR_HPMCOUNTER25H:
2895                                 case CSR_HPMCOUNTER26H:
2896                                 case CSR_HPMCOUNTER27H:
2897                                 case CSR_HPMCOUNTER28H:
2898                                 case CSR_HPMCOUNTER29H:
2899                                 case CSR_HPMCOUNTER30H:
2900                                 case CSR_HPMCOUNTER31H:
2901                                 case CSR_MCYCLEH:
2902                                 case CSR_MINSTRETH:
2903                                 case CSR_MHPMCOUNTER3H:
2904                                 case CSR_MHPMCOUNTER4H:
2905                                 case CSR_MHPMCOUNTER5H:
2906                                 case CSR_MHPMCOUNTER6H:
2907                                 case CSR_MHPMCOUNTER7H:
2908                                 case CSR_MHPMCOUNTER8H:
2909                                 case CSR_MHPMCOUNTER9H:
2910                                 case CSR_MHPMCOUNTER10H:
2911                                 case CSR_MHPMCOUNTER11H:
2912                                 case CSR_MHPMCOUNTER12H:
2913                                 case CSR_MHPMCOUNTER13H:
2914                                 case CSR_MHPMCOUNTER14H:
2915                                 case CSR_MHPMCOUNTER15H:
2916                                 case CSR_MHPMCOUNTER16H:
2917                                 case CSR_MHPMCOUNTER17H:
2918                                 case CSR_MHPMCOUNTER18H:
2919                                 case CSR_MHPMCOUNTER19H:
2920                                 case CSR_MHPMCOUNTER20H:
2921                                 case CSR_MHPMCOUNTER21H:
2922                                 case CSR_MHPMCOUNTER22H:
2923                                 case CSR_MHPMCOUNTER23H:
2924                                 case CSR_MHPMCOUNTER24H:
2925                                 case CSR_MHPMCOUNTER25H:
2926                                 case CSR_MHPMCOUNTER26H:
2927                                 case CSR_MHPMCOUNTER27H:
2928                                 case CSR_MHPMCOUNTER28H:
2929                                 case CSR_MHPMCOUNTER29H:
2930                                 case CSR_MHPMCOUNTER30H:
2931                                 case CSR_MHPMCOUNTER31H:
2932                                         r->exist = riscv_xlen(target) == 32;
2933                                         break;
2934                         }
2935
2936                         if (!r->exist && expose_csr) {
2937                                 for (unsigned i = 0; expose_csr[i].low <= expose_csr[i].high; i++) {
2938                                         if (csr_number >= expose_csr[i].low && csr_number <= expose_csr[i].high) {
2939                                                 LOG_INFO("Exposing additional CSR %d", csr_number);
2940                                                 r->exist = true;
2941                                                 break;
2942                                         }
2943                                 }
2944                         }
2945
2946                 } else if (number == GDB_REGNO_PRIV) {
2947                         sprintf(reg_name, "priv");
2948                         r->group = "general";
2949                         r->feature = &feature_virtual;
2950                         r->size = 8;
2951
2952                 } else {
2953                         /* Custom registers. */
2954                         assert(expose_custom);
2955
2956                         range_t *range = &expose_custom[custom_range_index];
2957                         assert(range->low <= range->high);
2958                         unsigned custom_number = range->low + custom_within_range;
2959
2960                         r->group = "custom";
2961                         r->feature = &feature_custom;
2962                         r->arch_info = calloc(1, sizeof(riscv_reg_info_t));
2963                         assert(r->arch_info);
2964                         ((riscv_reg_info_t *) r->arch_info)->target = target;
2965                         ((riscv_reg_info_t *) r->arch_info)->custom_number = custom_number;
2966                         sprintf(reg_name, "custom%d", custom_number);
2967
2968                         custom_within_range++;
2969                         if (custom_within_range > range->high - range->low) {
2970                                 custom_within_range = 0;
2971                                 custom_range_index++;
2972                         }
2973                 }
2974
2975                 if (reg_name[0])
2976                         r->name = reg_name;
2977                 reg_name += strlen(reg_name) + 1;
2978                 assert(reg_name < info->reg_names + target->reg_cache->num_regs *
2979                                 max_reg_name_len);
2980                 r->value = &info->reg_cache_values[number];
2981         }
2982
2983         return ERROR_OK;
2984 }