9 #include "target/target.h"
10 #include "target/algorithm.h"
11 #include "target/target_type.h"
13 #include "jtag/jtag.h"
14 #include "target/register.h"
15 #include "target/breakpoints.h"
16 #include "helper/time_support.h"
19 #include "rtos/rtos.h"
22 * Since almost everything can be accomplish by scanning the dbus register, all
23 * functions here assume dbus is already selected. The exception are functions
24 * called directly by OpenOCD, which can't assume anything about what's
25 * currently in IR. They should set IR to dbus explicitly.
31 * At the bottom of the stack are the OpenOCD JTAG functions:
36 * There are a few functions to just instantly shift a register and get its
42 * Because doing one scan and waiting for the result is slow, most functions
43 * batch up a bunch of dbus writes and then execute them all at once. They use
44 * the scans "class" for this:
49 * Usually you new(), call a bunch of add functions, then execute() and look
50 * at the results by calling scans_get...()
52 * Optimized functions will directly use the scans class above, but slightly
53 * lazier code will use the cache functions that in turn use the scans
58 * cache_set... update a local structure, which is then synced to the target
59 * with cache_write(). Only Debug RAM words that are actually changed are sent
60 * to the target. Afterwards use cache_get... to read results.
63 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
64 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
66 #define DIM(x) (sizeof(x)/sizeof(*x))
68 /* Constants for legacy SiFive hardware breakpoints. */
69 #define CSR_BPCONTROL_X (1<<0)
70 #define CSR_BPCONTROL_W (1<<1)
71 #define CSR_BPCONTROL_R (1<<2)
72 #define CSR_BPCONTROL_U (1<<3)
73 #define CSR_BPCONTROL_S (1<<4)
74 #define CSR_BPCONTROL_H (1<<5)
75 #define CSR_BPCONTROL_M (1<<6)
76 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
77 #define CSR_BPCONTROL_BPACTION (0xff<<11)
79 #define DEBUG_ROM_START 0x800
80 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
81 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
82 #define DEBUG_RAM_START 0x400
84 #define SETHALTNOT 0x10c
86 /*** JTAG registers. ***/
88 #define DTMCONTROL 0x10
89 #define DTMCONTROL_DBUS_RESET (1<<16)
90 #define DTMCONTROL_IDLE (7<<10)
91 #define DTMCONTROL_ADDRBITS (0xf<<4)
92 #define DTMCONTROL_VERSION (0xf)
95 #define DBUS_OP_START 0
96 #define DBUS_OP_SIZE 2
103 DBUS_STATUS_SUCCESS = 0,
104 DBUS_STATUS_FAILED = 2,
107 #define DBUS_DATA_START 2
108 #define DBUS_DATA_SIZE 34
109 #define DBUS_ADDRESS_START 36
123 /*** Debug Bus registers. ***/
125 #define DMCONTROL 0x10
126 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
127 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
128 #define DMCONTROL_BUSERROR (7<<19)
129 #define DMCONTROL_SERIAL (3<<16)
130 #define DMCONTROL_AUTOINCREMENT (1<<15)
131 #define DMCONTROL_ACCESS (7<<12)
132 #define DMCONTROL_HARTID (0x3ff<<2)
133 #define DMCONTROL_NDRESET (1<<1)
134 #define DMCONTROL_FULLRESET 1
137 #define DMINFO_ABUSSIZE (0x7fU<<25)
138 #define DMINFO_SERIALCOUNT (0xf<<21)
139 #define DMINFO_ACCESS128 (1<<20)
140 #define DMINFO_ACCESS64 (1<<19)
141 #define DMINFO_ACCESS32 (1<<18)
142 #define DMINFO_ACCESS16 (1<<17)
143 #define DMINFO_ACCESS8 (1<<16)
144 #define DMINFO_DRAMSIZE (0x3f<<10)
145 #define DMINFO_AUTHENTICATED (1<<5)
146 #define DMINFO_AUTHBUSY (1<<4)
147 #define DMINFO_AUTHTYPE (3<<2)
148 #define DMINFO_VERSION 3
150 /*** Info about the core being debugged. ***/
152 #define DBUS_ADDRESS_UNKNOWN 0xffff
155 #define DRAM_CACHE_SIZE 16
157 uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
158 struct scan_field select_dtmcontrol = {
160 .out_value = ir_dtmcontrol
162 uint8_t ir_dbus[4] = {DBUS};
163 struct scan_field select_dbus = {
167 uint8_t ir_idcode[4] = {0x1};
168 struct scan_field select_idcode = {
170 .out_value = ir_idcode
178 bool read, write, execute;
182 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
183 int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
185 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
186 int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
188 bool riscv_prefer_sba;
194 /* In addition to the ones in the standard spec, we'll also expose additional
196 * The list is either NULL, or a series of ranges (inclusive), terminated with
199 /* Same, but for custom registers. */
200 range_t *expose_custom;
202 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
204 struct scan_field field;
206 uint8_t out_value[4] = { 0 };
208 buf_set_u32(out_value, 0, 32, out);
210 jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
213 field.out_value = out_value;
214 field.in_value = in_value;
215 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
217 /* Always return to dbus. */
218 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
220 int retval = jtag_execute_queue();
221 if (retval != ERROR_OK) {
222 LOG_ERROR("failed jtag scan: %d", retval);
226 uint32_t in = buf_get_u32(field.in_value, 0, 32);
227 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
232 static struct target_type *get_target_type(struct target *target)
234 riscv_info_t *info = (riscv_info_t *) target->arch_info;
237 LOG_ERROR("Target has not been initialized");
241 switch (info->dtm_version) {
243 return &riscv011_target;
245 return &riscv013_target;
247 LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
252 static int riscv_init_target(struct command_context *cmd_ctx,
253 struct target *target)
255 LOG_DEBUG("riscv_init_target()");
256 target->arch_info = calloc(1, sizeof(riscv_info_t));
257 if (!target->arch_info)
259 riscv_info_t *info = (riscv_info_t *) target->arch_info;
260 riscv_info_init(target, info);
261 info->cmd_ctx = cmd_ctx;
263 select_dtmcontrol.num_bits = target->tap->ir_length;
264 select_dbus.num_bits = target->tap->ir_length;
265 select_idcode.num_bits = target->tap->ir_length;
267 riscv_semihosting_init(target);
269 target->debug_reason = DBG_REASON_DBGRQ;
274 static void riscv_free_registers(struct target *target)
276 /* Free the shared structure use for most registers. */
277 if (target->reg_cache) {
278 if (target->reg_cache->reg_list) {
279 if (target->reg_cache->reg_list[0].arch_info)
280 free(target->reg_cache->reg_list[0].arch_info);
281 /* Free the ones we allocated separately. */
282 for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
283 free(target->reg_cache->reg_list[i].arch_info);
284 free(target->reg_cache->reg_list);
286 free(target->reg_cache);
290 static void riscv_deinit_target(struct target *target)
292 LOG_DEBUG("riscv_deinit_target()");
293 struct target_type *tt = get_target_type(target);
295 tt->deinit_target(target);
296 riscv_info_t *info = (riscv_info_t *) target->arch_info;
297 free(info->reg_names);
301 riscv_free_registers(target);
303 target->arch_info = NULL;
306 static int oldriscv_halt(struct target *target)
308 struct target_type *tt = get_target_type(target);
309 return tt->halt(target);
312 static void trigger_from_breakpoint(struct trigger *trigger,
313 const struct breakpoint *breakpoint)
315 trigger->address = breakpoint->address;
316 trigger->length = breakpoint->length;
317 trigger->mask = ~0LL;
318 trigger->read = false;
319 trigger->write = false;
320 trigger->execute = true;
321 /* unique_id is unique across both breakpoints and watchpoints. */
322 trigger->unique_id = breakpoint->unique_id;
325 static int maybe_add_trigger_t1(struct target *target, unsigned hartid,
326 struct trigger *trigger, uint64_t tdata1)
330 const uint32_t bpcontrol_x = 1<<0;
331 const uint32_t bpcontrol_w = 1<<1;
332 const uint32_t bpcontrol_r = 1<<2;
333 const uint32_t bpcontrol_u = 1<<3;
334 const uint32_t bpcontrol_s = 1<<4;
335 const uint32_t bpcontrol_h = 1<<5;
336 const uint32_t bpcontrol_m = 1<<6;
337 const uint32_t bpcontrol_bpmatch = 0xf << 7;
338 const uint32_t bpcontrol_bpaction = 0xff << 11;
340 if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
341 /* Trigger is already in use, presumably by user code. */
342 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
345 tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
346 tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
347 tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
348 tdata1 = set_field(tdata1, bpcontrol_u,
349 !!(r->misa[hartid] & (1 << ('U' - 'A'))));
350 tdata1 = set_field(tdata1, bpcontrol_s,
351 !!(r->misa[hartid] & (1 << ('S' - 'A'))));
352 tdata1 = set_field(tdata1, bpcontrol_h,
353 !!(r->misa[hartid] & (1 << ('H' - 'A'))));
354 tdata1 |= bpcontrol_m;
355 tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
356 tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
358 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
360 riscv_reg_t tdata1_rb;
361 if (riscv_get_register_on_hart(target, &tdata1_rb, hartid,
362 GDB_REGNO_TDATA1) != ERROR_OK)
364 LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
366 if (tdata1 != tdata1_rb) {
367 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
368 PRIx64 " to tdata1 it contains 0x%" PRIx64,
370 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
371 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
374 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
379 static int maybe_add_trigger_t2(struct target *target, unsigned hartid,
380 struct trigger *trigger, uint64_t tdata1)
384 /* tselect is already set */
385 if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
386 /* Trigger is already in use, presumably by user code. */
387 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
390 /* address/data match trigger */
391 tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
392 tdata1 = set_field(tdata1, MCONTROL_ACTION,
393 MCONTROL_ACTION_DEBUG_MODE);
394 tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
395 tdata1 |= MCONTROL_M;
396 if (r->misa[hartid] & (1 << ('H' - 'A')))
397 tdata1 |= MCONTROL_H;
398 if (r->misa[hartid] & (1 << ('S' - 'A')))
399 tdata1 |= MCONTROL_S;
400 if (r->misa[hartid] & (1 << ('U' - 'A')))
401 tdata1 |= MCONTROL_U;
403 if (trigger->execute)
404 tdata1 |= MCONTROL_EXECUTE;
406 tdata1 |= MCONTROL_LOAD;
408 tdata1 |= MCONTROL_STORE;
410 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
413 int result = riscv_get_register_on_hart(target, &tdata1_rb, hartid, GDB_REGNO_TDATA1);
414 if (result != ERROR_OK)
416 LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
418 if (tdata1 != tdata1_rb) {
419 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
420 PRIx64 " to tdata1 it contains 0x%" PRIx64,
422 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
423 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
426 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
431 static int add_trigger(struct target *target, struct trigger *trigger)
435 if (riscv_enumerate_triggers(target) != ERROR_OK)
438 /* In RTOS mode, we need to set the same trigger in the same slot on every
439 * hart, to keep up the illusion that each hart is a thread running on the
442 /* Otherwise, we just set the trigger on the one hart this target deals
445 riscv_reg_t tselect[RISCV_MAX_HARTS];
448 for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
449 if (!riscv_hart_enabled(target, hartid))
453 int result = riscv_get_register_on_hart(target, &tselect[hartid],
454 hartid, GDB_REGNO_TSELECT);
455 if (result != ERROR_OK)
458 assert(first_hart >= 0);
461 for (i = 0; i < r->trigger_count[first_hart]; i++) {
462 if (r->trigger_unique_id[i] != -1)
465 riscv_set_register_on_hart(target, first_hart, GDB_REGNO_TSELECT, i);
468 int result = riscv_get_register_on_hart(target, &tdata1, first_hart,
470 if (result != ERROR_OK)
472 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
475 for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
476 if (!riscv_hart_enabled(target, hartid))
478 if (hartid > first_hart)
479 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
482 result = maybe_add_trigger_t1(target, hartid, trigger, tdata1);
485 result = maybe_add_trigger_t2(target, hartid, trigger, tdata1);
488 LOG_DEBUG("trigger %d has unknown type %d", i, type);
492 if (result != ERROR_OK)
496 if (result != ERROR_OK)
499 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
500 i, type, trigger->unique_id);
501 r->trigger_unique_id[i] = trigger->unique_id;
505 for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
506 if (!riscv_hart_enabled(target, hartid))
508 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT,
512 if (i >= r->trigger_count[first_hart]) {
513 LOG_ERROR("Couldn't find an available hardware trigger.");
514 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
520 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
522 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
524 if (breakpoint->type == BKPT_SOFT) {
525 /** @todo check RVC for size/alignment */
526 if (!(breakpoint->length == 4 || breakpoint->length == 2)) {
527 LOG_ERROR("Invalid breakpoint length %d", breakpoint->length);
531 if (0 != (breakpoint->address % 2)) {
532 LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR, breakpoint->address);
536 if (target_read_memory(target, breakpoint->address, 2, breakpoint->length / 2,
537 breakpoint->orig_instr) != ERROR_OK) {
538 LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
539 breakpoint->address);
543 uint8_t buff[4] = { 0 };
544 buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
545 int const retval = target_write_memory(target, breakpoint->address, 2, breakpoint->length / 2, buff);
547 if (retval != ERROR_OK) {
548 LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
549 TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
553 } else if (breakpoint->type == BKPT_HARD) {
554 struct trigger trigger;
555 trigger_from_breakpoint(&trigger, breakpoint);
556 int const result = add_trigger(target, &trigger);
557 if (result != ERROR_OK)
560 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
561 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
564 breakpoint->set = true;
568 static int remove_trigger(struct target *target, struct trigger *trigger)
572 if (riscv_enumerate_triggers(target) != ERROR_OK)
576 for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
577 if (!riscv_hart_enabled(target, hartid))
579 if (first_hart < 0) {
584 assert(first_hart >= 0);
587 for (i = 0; i < r->trigger_count[first_hart]; i++) {
588 if (r->trigger_unique_id[i] == trigger->unique_id)
591 if (i >= r->trigger_count[first_hart]) {
592 LOG_ERROR("Couldn't find the hardware resources used by hardware "
596 LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
598 for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
599 if (!riscv_hart_enabled(target, hartid))
602 int result = riscv_get_register_on_hart(target, &tselect, hartid, GDB_REGNO_TSELECT);
603 if (result != ERROR_OK)
605 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
606 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
607 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
609 r->trigger_unique_id[i] = -1;
614 int riscv_remove_breakpoint(struct target *target,
615 struct breakpoint *breakpoint)
617 if (breakpoint->type == BKPT_SOFT) {
618 if (target_write_memory(target, breakpoint->address, 2, breakpoint->length / 2,
619 breakpoint->orig_instr) != ERROR_OK) {
620 LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
621 "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
625 } else if (breakpoint->type == BKPT_HARD) {
626 struct trigger trigger;
627 trigger_from_breakpoint(&trigger, breakpoint);
628 int result = remove_trigger(target, &trigger);
629 if (result != ERROR_OK)
633 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
634 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
637 breakpoint->set = false;
642 static void trigger_from_watchpoint(struct trigger *trigger,
643 const struct watchpoint *watchpoint)
645 trigger->address = watchpoint->address;
646 trigger->length = watchpoint->length;
647 trigger->mask = watchpoint->mask;
648 trigger->value = watchpoint->value;
649 trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
650 trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
651 trigger->execute = false;
652 /* unique_id is unique across both breakpoints and watchpoints. */
653 trigger->unique_id = watchpoint->unique_id;
656 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
658 struct trigger trigger;
659 trigger_from_watchpoint(&trigger, watchpoint);
661 int result = add_trigger(target, &trigger);
662 if (result != ERROR_OK)
664 watchpoint->set = true;
669 int riscv_remove_watchpoint(struct target *target,
670 struct watchpoint *watchpoint)
672 LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
674 struct trigger trigger;
675 trigger_from_watchpoint(&trigger, watchpoint);
677 int result = remove_trigger(target, &trigger);
678 if (result != ERROR_OK)
680 watchpoint->set = false;
685 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
688 * The GDB server uses this information to tell GDB what data address has
689 * been hit, which enables GDB to print the hit variable along with its old
691 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
693 struct watchpoint *wp = target->watchpoints;
695 LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
697 /*TODO instead of disassembling the instruction that we think caused the
698 * trigger, check the hit bit of each watchpoint first. The hit bit is
699 * simpler and more reliable to check but as it is optional and relatively
700 * new, not all hardware will implement it */
702 riscv_get_register(target, &dpc, GDB_REGNO_DPC);
703 const uint8_t length = 4;
704 LOG_DEBUG("dpc is 0x%" PRIx64, dpc);
706 /* fetch the instruction at dpc */
707 uint8_t buffer[length];
708 if (target_read_buffer(target, dpc, length, buffer) != ERROR_OK) {
709 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64, dpc);
713 uint32_t instruction = 0;
715 for (int i = 0; i < length; i++) {
716 LOG_DEBUG("Next byte is %x", buffer[i]);
717 instruction += (buffer[i] << 8 * i);
719 LOG_DEBUG("Full instruction is %x", instruction);
721 /* find out which memory address is accessed by the instruction at dpc */
722 /* opcode is first 7 bits of the instruction */
723 uint8_t opcode = instruction & 0x7F;
726 riscv_reg_t mem_addr;
728 if (opcode == MATCH_LB || opcode == MATCH_SB) {
729 rs1 = (instruction & 0xf8000) >> 15;
730 riscv_get_register(target, &mem_addr, rs1);
732 if (opcode == MATCH_SB) {
733 LOG_DEBUG("%x is store instruction", instruction);
734 imm = ((instruction & 0xf80) >> 7) | ((instruction & 0xfe000000) >> 20);
736 LOG_DEBUG("%x is load instruction", instruction);
737 imm = (instruction & 0xfff00000) >> 20;
739 /* sign extend 12-bit imm to 16-bits */
743 LOG_DEBUG("memory address=0x%" PRIx64, mem_addr);
745 LOG_DEBUG("%x is not a RV32I load or store", instruction);
750 /*TODO support length/mask */
751 if (wp->address == mem_addr) {
752 *hit_watchpoint = wp;
753 LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address);
759 /* No match found - either we hit a watchpoint caused by an instruction that
760 * this function does not yet disassemble, or we hit a breakpoint.
762 * OpenOCD will behave as if this function had never been implemented i.e.
763 * report the halt to GDB with no address information. */
768 static int oldriscv_step(struct target *target, int current, uint32_t address,
769 int handle_breakpoints)
771 struct target_type *tt = get_target_type(target);
772 return tt->step(target, current, address, handle_breakpoints);
775 static int old_or_new_riscv_step(struct target *target, int current,
776 target_addr_t address, int handle_breakpoints)
779 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
780 if (r->is_halted == NULL)
781 return oldriscv_step(target, current, address, handle_breakpoints);
783 return riscv_openocd_step(target, current, address, handle_breakpoints);
787 static int riscv_examine(struct target *target)
789 LOG_DEBUG("riscv_examine()");
790 if (target_was_examined(target)) {
791 LOG_DEBUG("Target was already examined.");
795 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
797 riscv_info_t *info = (riscv_info_t *) target->arch_info;
798 uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
799 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
800 info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
801 LOG_DEBUG(" version=0x%x", info->dtm_version);
803 struct target_type *tt = get_target_type(target);
807 int result = tt->init_target(info->cmd_ctx, target);
808 if (result != ERROR_OK)
811 return tt->examine(target);
814 static int oldriscv_poll(struct target *target)
816 struct target_type *tt = get_target_type(target);
817 return tt->poll(target);
820 static int old_or_new_riscv_poll(struct target *target)
823 if (r->is_halted == NULL)
824 return oldriscv_poll(target);
826 return riscv_openocd_poll(target);
829 static int old_or_new_riscv_halt(struct target *target)
832 if (r->is_halted == NULL)
833 return oldriscv_halt(target);
835 return riscv_openocd_halt(target);
838 static int riscv_assert_reset(struct target *target)
840 LOG_DEBUG("[%d]", target->coreid);
841 struct target_type *tt = get_target_type(target);
842 riscv_invalidate_register_cache(target);
843 return tt->assert_reset(target);
846 static int riscv_deassert_reset(struct target *target)
848 LOG_DEBUG("[%d]", target->coreid);
849 struct target_type *tt = get_target_type(target);
850 return tt->deassert_reset(target);
854 static int oldriscv_resume(struct target *target, int current, uint32_t address,
855 int handle_breakpoints, int debug_execution)
857 struct target_type *tt = get_target_type(target);
858 return tt->resume(target, current, address, handle_breakpoints,
862 static int old_or_new_riscv_resume(struct target *target, int current,
863 target_addr_t address, int handle_breakpoints, int debug_execution)
865 LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
867 struct target_list *targets = target->head;
868 int result = ERROR_OK;
870 struct target *t = targets->target;
871 riscv_info_t *r = riscv_info(t);
872 if (r->is_halted == NULL) {
873 if (oldriscv_resume(t, current, address, handle_breakpoints,
874 debug_execution) != ERROR_OK)
877 if (riscv_openocd_resume(t, current, address,
878 handle_breakpoints, debug_execution) != ERROR_OK)
881 targets = targets->next;
887 if (r->is_halted == NULL)
888 return oldriscv_resume(target, current, address, handle_breakpoints, debug_execution);
890 return riscv_openocd_resume(target, current, address, handle_breakpoints, debug_execution);
893 static int riscv_select_current_hart(struct target *target)
896 if (riscv_rtos_enabled(target)) {
897 if (r->rtos_hartid == -1)
898 r->rtos_hartid = target->rtos->current_threadid - 1;
899 return riscv_set_current_hartid(target, r->rtos_hartid);
901 return riscv_set_current_hartid(target, target->coreid);
904 static int riscv_read_memory(struct target *target, target_addr_t address,
905 uint32_t size, uint32_t count, uint8_t *buffer)
907 if (riscv_select_current_hart(target) != ERROR_OK)
909 struct target_type *tt = get_target_type(target);
910 return tt->read_memory(target, address, size, count, buffer);
913 static int riscv_write_memory(struct target *target, target_addr_t address,
914 uint32_t size, uint32_t count, const uint8_t *buffer)
916 if (riscv_select_current_hart(target) != ERROR_OK)
918 struct target_type *tt = get_target_type(target);
919 return tt->write_memory(target, address, size, count, buffer);
922 static int riscv_get_gdb_reg_list_internal(struct target *target,
923 struct reg **reg_list[], int *reg_list_size,
924 enum target_register_class reg_class, bool read)
927 LOG_DEBUG("rtos_hartid=%d, current_hartid=%d, reg_class=%d, read=%d",
928 r->rtos_hartid, r->current_hartid, reg_class, read);
930 if (!target->reg_cache) {
931 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
935 if (riscv_select_current_hart(target) != ERROR_OK)
939 case REG_CLASS_GENERAL:
943 *reg_list_size = target->reg_cache->num_regs;
946 LOG_ERROR("Unsupported reg_class: %d", reg_class);
950 *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
954 for (int i = 0; i < *reg_list_size; i++) {
955 assert(!target->reg_cache->reg_list[i].valid ||
956 target->reg_cache->reg_list[i].size > 0);
957 (*reg_list)[i] = &target->reg_cache->reg_list[i];
958 if (read && !target->reg_cache->reg_list[i].valid) {
959 if (target->reg_cache->reg_list[i].type->get(
960 &target->reg_cache->reg_list[i]) != ERROR_OK)
961 /* This function is called when first connecting to gdb,
962 * resulting in an attempt to read all kinds of registers which
963 * probably will fail. Ignore these failures, and when
964 * encountered stop reading to save time. */
972 static int riscv_get_gdb_reg_list(struct target *target,
973 struct reg **reg_list[], int *reg_list_size,
974 enum target_register_class reg_class)
976 return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
980 static int riscv_arch_state(struct target *target)
982 struct target_type *tt = get_target_type(target);
983 return tt->arch_state(target);
986 /* Algorithm must end with a software breakpoint instruction. */
987 static int riscv_run_algorithm(struct target *target, int num_mem_params,
988 struct mem_param *mem_params, int num_reg_params,
989 struct reg_param *reg_params, target_addr_t entry_point,
990 target_addr_t exit_point, int timeout_ms, void *arch_info)
992 riscv_info_t *info = (riscv_info_t *) target->arch_info;
994 if (num_mem_params > 0) {
995 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
999 if (target->state != TARGET_HALTED) {
1000 LOG_WARNING("target not halted");
1001 return ERROR_TARGET_NOT_HALTED;
1004 /* Save registers */
1005 struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", 1);
1006 if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
1008 uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1010 uint64_t saved_regs[32];
1011 for (int i = 0; i < num_reg_params; i++) {
1012 if (reg_params[i].direction == PARAM_IN)
1015 LOG_DEBUG("save %s", reg_params[i].reg_name);
1016 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
1018 LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
1022 if (r->size != reg_params[i].size) {
1023 LOG_ERROR("Register %s is %d bits instead of %d bits.",
1024 reg_params[i].reg_name, r->size, reg_params[i].size);
1028 if (r->number > GDB_REGNO_XPR31) {
1029 LOG_ERROR("Only GPRs can be use as argument registers.");
1033 if (r->type->get(r) != ERROR_OK)
1035 saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
1036 if (r->type->set(r, reg_params[i].value) != ERROR_OK)
1041 /* Disable Interrupts before attempting to run the algorithm. */
1042 uint64_t current_mstatus;
1043 uint8_t mstatus_bytes[8] = { 0 };
1045 LOG_DEBUG("Disabling Interrupts");
1046 struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
1049 LOG_ERROR("Couldn't find mstatus!");
1053 reg_mstatus->type->get(reg_mstatus);
1054 current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
1055 uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
1056 buf_set_u64(mstatus_bytes, 0, info->xlen[0], set_field(current_mstatus,
1059 reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1062 LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
1063 if (oldriscv_resume(target, 0, entry_point, 0, 0) != ERROR_OK)
1066 int64_t start = timeval_ms();
1067 while (target->state != TARGET_HALTED) {
1068 LOG_DEBUG("poll()");
1069 int64_t now = timeval_ms();
1070 if (now - start > timeout_ms) {
1071 LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms);
1072 LOG_ERROR(" now = 0x%08x", (uint32_t) now);
1073 LOG_ERROR(" start = 0x%08x", (uint32_t) start);
1074 oldriscv_halt(target);
1075 old_or_new_riscv_poll(target);
1076 return ERROR_TARGET_TIMEOUT;
1079 int result = old_or_new_riscv_poll(target);
1080 if (result != ERROR_OK)
1084 if (reg_pc->type->get(reg_pc) != ERROR_OK)
1086 uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1087 if (final_pc != exit_point) {
1088 LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
1089 TARGET_PRIxADDR, final_pc, exit_point);
1093 /* Restore Interrupts */
1094 LOG_DEBUG("Restoring Interrupts");
1095 buf_set_u64(mstatus_bytes, 0, info->xlen[0], current_mstatus);
1096 reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1098 /* Restore registers */
1099 uint8_t buf[8] = { 0 };
1100 buf_set_u64(buf, 0, info->xlen[0], saved_pc);
1101 if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
1104 for (int i = 0; i < num_reg_params; i++) {
1105 LOG_DEBUG("restore %s", reg_params[i].reg_name);
1106 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
1107 buf_set_u64(buf, 0, info->xlen[0], saved_regs[r->number]);
1108 if (r->type->set(r, buf) != ERROR_OK)
1115 /* Should run code on the target to perform CRC of
1116 memory. Not yet implemented.
1119 static int riscv_checksum_memory(struct target *target,
1120 target_addr_t address, uint32_t count,
1123 *checksum = 0xFFFFFFFF;
1124 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1127 /*** OpenOCD Helper Functions ***/
1129 enum riscv_poll_hart {
1131 RPH_DISCOVERED_HALTED,
1132 RPH_DISCOVERED_RUNNING,
1135 static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
1138 if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1141 LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
1143 /* If OpenOCD thinks we're running but this hart is halted then it's time
1144 * to raise an event. */
1145 bool halted = riscv_is_halted(target);
1146 if (target->state != TARGET_HALTED && halted) {
1147 LOG_DEBUG(" triggered a halt");
1149 return RPH_DISCOVERED_HALTED;
1150 } else if (target->state != TARGET_RUNNING && !halted) {
1151 LOG_DEBUG(" triggered running");
1152 target->state = TARGET_RUNNING;
1153 return RPH_DISCOVERED_RUNNING;
1156 return RPH_NO_CHANGE;
1159 int set_debug_reason(struct target *target, int hartid)
1161 switch (riscv_halt_reason(target, hartid)) {
1162 case RISCV_HALT_BREAKPOINT:
1163 target->debug_reason = DBG_REASON_BREAKPOINT;
1165 case RISCV_HALT_TRIGGER:
1166 target->debug_reason = DBG_REASON_WATCHPOINT;
1168 case RISCV_HALT_INTERRUPT:
1169 target->debug_reason = DBG_REASON_DBGRQ;
1171 case RISCV_HALT_SINGLESTEP:
1172 target->debug_reason = DBG_REASON_SINGLESTEP;
1174 case RISCV_HALT_UNKNOWN:
1175 target->debug_reason = DBG_REASON_UNDEFINED;
1177 case RISCV_HALT_ERROR:
1183 /*** OpenOCD Interface ***/
1184 int riscv_openocd_poll(struct target *target)
1186 LOG_DEBUG("polling all harts");
1187 int halted_hart = -1;
1188 if (riscv_rtos_enabled(target)) {
1189 /* Check every hart for an event. */
1190 for (int i = 0; i < riscv_count_harts(target); ++i) {
1191 enum riscv_poll_hart out = riscv_poll_hart(target, i);
1194 case RPH_DISCOVERED_RUNNING:
1196 case RPH_DISCOVERED_HALTED:
1203 if (halted_hart == -1) {
1204 LOG_DEBUG(" no harts just halted, target->state=%d", target->state);
1207 LOG_DEBUG(" hart %d halted", halted_hart);
1209 /* If we're here then at least one hart triggered. That means
1210 * we want to go and halt _every_ hart in the system, as that's
1211 * the invariant we hold here. Some harts might have already
1212 * halted (as we're either in single-step mode or they also
1213 * triggered a breakpoint), so don't attempt to halt those
1215 for (int i = 0; i < riscv_count_harts(target); ++i)
1216 riscv_halt_one_hart(target, i);
1218 } else if (target->smp) {
1219 bool halt_discovered = false;
1220 bool newly_halted[128] = {0};
1222 for (struct target_list *list = target->head; list != NULL;
1223 list = list->next, i++) {
1224 struct target *t = list->target;
1225 riscv_info_t *r = riscv_info(t);
1226 assert(i < DIM(newly_halted));
1227 enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
1231 case RPH_DISCOVERED_RUNNING:
1232 t->state = TARGET_RUNNING;
1234 case RPH_DISCOVERED_HALTED:
1235 halt_discovered = true;
1236 newly_halted[i] = true;
1237 t->state = TARGET_HALTED;
1238 if (set_debug_reason(t, r->current_hartid) != ERROR_OK)
1246 if (halt_discovered) {
1247 LOG_DEBUG("Halt other targets in this SMP group.");
1249 for (struct target_list *list = target->head; list != NULL;
1250 list = list->next, i++) {
1251 struct target *t = list->target;
1252 riscv_info_t *r = riscv_info(t);
1253 if (t->state != TARGET_HALTED) {
1254 if (riscv_halt_one_hart(t, r->current_hartid) != ERROR_OK)
1256 t->state = TARGET_HALTED;
1257 if (set_debug_reason(t, r->current_hartid) != ERROR_OK)
1259 newly_halted[i] = true;
1263 /* Now that we have all our ducks in a row, tell the higher layers
1264 * what just happened. */
1266 for (struct target_list *list = target->head; list != NULL;
1267 list = list->next, i++) {
1268 struct target *t = list->target;
1269 if (newly_halted[i])
1270 target_call_event_callbacks(t, TARGET_EVENT_HALTED);
1276 enum riscv_poll_hart out = riscv_poll_hart(target,
1277 riscv_current_hartid(target));
1278 if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING)
1280 else if (out == RPH_ERROR)
1283 halted_hart = riscv_current_hartid(target);
1284 LOG_DEBUG(" hart %d halted", halted_hart);
1287 target->state = TARGET_HALTED;
1288 if (set_debug_reason(target, halted_hart) != ERROR_OK)
1291 if (riscv_rtos_enabled(target)) {
1292 target->rtos->current_threadid = halted_hart + 1;
1293 target->rtos->current_thread = halted_hart + 1;
1294 riscv_set_rtos_hartid(target, halted_hart);
1297 target->state = TARGET_HALTED;
1299 if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1301 if (riscv_semihosting(target, &retval) != 0)
1305 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1309 int riscv_openocd_halt(struct target *target)
1314 LOG_DEBUG("[%d] halting all harts", target->coreid);
1317 LOG_DEBUG("Halt other targets in this SMP group.");
1318 struct target_list *targets = target->head;
1321 struct target *t = targets->target;
1322 targets = targets->next;
1323 if (t->state != TARGET_HALTED) {
1324 if (riscv_halt_all_harts(t) != ERROR_OK)
1325 result = ERROR_FAIL;
1329 result = riscv_halt_all_harts(target);
1332 if (riscv_rtos_enabled(target)) {
1333 if (r->rtos_hartid != -1) {
1334 LOG_DEBUG("halt requested on RTOS hartid %d", r->rtos_hartid);
1335 target->rtos->current_threadid = r->rtos_hartid + 1;
1336 target->rtos->current_thread = r->rtos_hartid + 1;
1338 LOG_DEBUG("halt requested, but no known RTOS hartid");
1341 target->state = TARGET_HALTED;
1342 target->debug_reason = DBG_REASON_DBGRQ;
1343 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1347 int riscv_openocd_resume(
1348 struct target *target,
1350 target_addr_t address,
1351 int handle_breakpoints,
1352 int debug_execution)
1354 LOG_DEBUG("debug_reason=%d", target->debug_reason);
1357 riscv_set_register(target, GDB_REGNO_PC, address);
1359 if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1360 /* To be able to run off a trigger, disable all the triggers, step, and
1361 * then resume as usual. */
1362 struct watchpoint *watchpoint = target->watchpoints;
1363 bool trigger_temporarily_cleared[RISCV_MAX_HWBPS] = {0};
1366 int result = ERROR_OK;
1367 while (watchpoint && result == ERROR_OK) {
1368 LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set);
1369 trigger_temporarily_cleared[i] = watchpoint->set;
1370 if (watchpoint->set)
1371 result = riscv_remove_watchpoint(target, watchpoint);
1372 watchpoint = watchpoint->next;
1376 if (result == ERROR_OK)
1377 result = riscv_step_rtos_hart(target);
1379 watchpoint = target->watchpoints;
1381 while (watchpoint) {
1382 LOG_DEBUG("watchpoint %d: cleared=%d", i, trigger_temporarily_cleared[i]);
1383 if (trigger_temporarily_cleared[i]) {
1384 if (result == ERROR_OK)
1385 result = riscv_add_watchpoint(target, watchpoint);
1387 riscv_add_watchpoint(target, watchpoint);
1389 watchpoint = watchpoint->next;
1393 if (result != ERROR_OK)
1397 int out = riscv_resume_all_harts(target);
1398 if (out != ERROR_OK) {
1399 LOG_ERROR("unable to resume all harts");
1403 register_cache_invalidate(target->reg_cache);
1404 target->state = TARGET_RUNNING;
1405 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1409 int riscv_openocd_step(struct target *target, int current,
1410 target_addr_t address, int handle_breakpoints)
1412 LOG_DEBUG("stepping rtos hart");
1415 riscv_set_register(target, GDB_REGNO_PC, address);
1417 int out = riscv_step_rtos_hart(target);
1418 if (out != ERROR_OK) {
1419 LOG_ERROR("unable to step rtos hart");
1423 register_cache_invalidate(target->reg_cache);
1424 target->state = TARGET_RUNNING;
1425 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1426 target->state = TARGET_HALTED;
1427 target->debug_reason = DBG_REASON_SINGLESTEP;
1428 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1432 /* Command Handlers */
1433 COMMAND_HANDLER(riscv_set_command_timeout_sec)
1435 if (CMD_ARGC != 1) {
1436 LOG_ERROR("Command takes exactly 1 parameter");
1437 return ERROR_COMMAND_SYNTAX_ERROR;
1439 int timeout = atoi(CMD_ARGV[0]);
1441 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
1445 riscv_command_timeout_sec = timeout;
1450 COMMAND_HANDLER(riscv_set_reset_timeout_sec)
1452 if (CMD_ARGC != 1) {
1453 LOG_ERROR("Command takes exactly 1 parameter");
1454 return ERROR_COMMAND_SYNTAX_ERROR;
1456 int timeout = atoi(CMD_ARGV[0]);
1458 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
1462 riscv_reset_timeout_sec = timeout;
1466 COMMAND_HANDLER(riscv_test_compliance) {
1468 struct target *target = get_current_target(CMD_CTX);
1473 LOG_ERROR("Command does not take any parameters.");
1474 return ERROR_COMMAND_SYNTAX_ERROR;
1477 if (r->test_compliance) {
1478 return r->test_compliance(target);
1480 LOG_ERROR("This target does not support this command (may implement an older version of the spec).");
1485 COMMAND_HANDLER(riscv_set_prefer_sba)
1487 if (CMD_ARGC != 1) {
1488 LOG_ERROR("Command takes exactly 1 parameter");
1489 return ERROR_COMMAND_SYNTAX_ERROR;
1491 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_prefer_sba);
1495 void parse_error(const char *string, char c, unsigned position)
1497 char buf[position+2];
1498 for (unsigned i = 0; i < position; i++)
1500 buf[position] = '^';
1501 buf[position + 1] = 0;
1503 LOG_ERROR("Parse error at character %c in:", c);
1504 LOG_ERROR("%s", string);
1505 LOG_ERROR("%s", buf);
1508 int parse_ranges(range_t **ranges, const char **argv)
1510 for (unsigned pass = 0; pass < 2; pass++) {
1513 bool parse_low = true;
1515 for (unsigned i = 0; i == 0 || argv[0][i-1]; i++) {
1516 char c = argv[0][i];
1518 /* Ignore whitespace. */
1526 } else if (c == '-') {
1528 } else if (c == ',' || c == 0) {
1530 (*ranges)[range].low = low;
1531 (*ranges)[range].high = low;
1536 parse_error(argv[0], c, i);
1537 return ERROR_COMMAND_SYNTAX_ERROR;
1544 } else if (c == ',' || c == 0) {
1547 (*ranges)[range].low = low;
1548 (*ranges)[range].high = high;
1554 parse_error(argv[0], c, i);
1555 return ERROR_COMMAND_SYNTAX_ERROR;
1563 *ranges = calloc(range + 2, sizeof(range_t));
1565 (*ranges)[range].low = 1;
1566 (*ranges)[range].high = 0;
1573 COMMAND_HANDLER(riscv_set_expose_csrs)
1575 if (CMD_ARGC != 1) {
1576 LOG_ERROR("Command takes exactly 1 parameter");
1577 return ERROR_COMMAND_SYNTAX_ERROR;
1580 return parse_ranges(&expose_csr, CMD_ARGV);
1583 COMMAND_HANDLER(riscv_set_expose_custom)
1585 if (CMD_ARGC != 1) {
1586 LOG_ERROR("Command takes exactly 1 parameter");
1587 return ERROR_COMMAND_SYNTAX_ERROR;
1590 return parse_ranges(&expose_custom, CMD_ARGV);
1593 COMMAND_HANDLER(riscv_authdata_read)
1595 if (CMD_ARGC != 0) {
1596 LOG_ERROR("Command takes no parameters");
1597 return ERROR_COMMAND_SYNTAX_ERROR;
1600 struct target *target = get_current_target(CMD_CTX);
1602 LOG_ERROR("target is NULL!");
1608 LOG_ERROR("riscv_info is NULL!");
1612 if (r->authdata_read) {
1614 if (r->authdata_read(target, &value) != ERROR_OK)
1616 command_print(CMD, "0x%" PRIx32, value);
1619 LOG_ERROR("authdata_read is not implemented for this target.");
1624 COMMAND_HANDLER(riscv_authdata_write)
1626 if (CMD_ARGC != 1) {
1627 LOG_ERROR("Command takes exactly 1 argument");
1628 return ERROR_COMMAND_SYNTAX_ERROR;
1631 struct target *target = get_current_target(CMD_CTX);
1635 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
1637 if (r->authdata_write) {
1638 return r->authdata_write(target, value);
1640 LOG_ERROR("authdata_write is not implemented for this target.");
1645 COMMAND_HANDLER(riscv_dmi_read)
1647 if (CMD_ARGC != 1) {
1648 LOG_ERROR("Command takes 1 parameter");
1649 return ERROR_COMMAND_SYNTAX_ERROR;
1652 struct target *target = get_current_target(CMD_CTX);
1654 LOG_ERROR("target is NULL!");
1660 LOG_ERROR("riscv_info is NULL!");
1665 uint32_t address, value;
1666 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1667 if (r->dmi_read(target, &value, address) != ERROR_OK)
1669 command_print(CMD, "0x%" PRIx32, value);
1672 LOG_ERROR("dmi_read is not implemented for this target.");
1678 COMMAND_HANDLER(riscv_dmi_write)
1680 if (CMD_ARGC != 2) {
1681 LOG_ERROR("Command takes exactly 2 arguments");
1682 return ERROR_COMMAND_SYNTAX_ERROR;
1685 struct target *target = get_current_target(CMD_CTX);
1688 uint32_t address, value;
1689 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1690 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1693 return r->dmi_write(target, address, value);
1695 LOG_ERROR("dmi_write is not implemented for this target.");
1700 COMMAND_HANDLER(riscv_test_sba_config_reg)
1702 if (CMD_ARGC != 4) {
1703 LOG_ERROR("Command takes exactly 4 arguments");
1704 return ERROR_COMMAND_SYNTAX_ERROR;
1707 struct target *target = get_current_target(CMD_CTX);
1710 target_addr_t legal_address;
1712 target_addr_t illegal_address;
1713 bool run_sbbusyerror_test;
1715 COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[0], legal_address);
1716 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words);
1717 COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[2], illegal_address);
1718 COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test);
1720 if (r->test_sba_config_reg) {
1721 return r->test_sba_config_reg(target, legal_address, num_words,
1722 illegal_address, run_sbbusyerror_test);
1724 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
1729 COMMAND_HANDLER(riscv_reset_delays)
1734 LOG_ERROR("Command takes at most one argument");
1735 return ERROR_COMMAND_SYNTAX_ERROR;
1739 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], wait);
1741 struct target *target = get_current_target(CMD_CTX);
1743 r->reset_delays_wait = wait;
1747 COMMAND_HANDLER(riscv_set_ir)
1749 if (CMD_ARGC != 2) {
1750 LOG_ERROR("Command takes exactly 2 arguments");
1751 return ERROR_COMMAND_SYNTAX_ERROR;
1755 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1757 if (!strcmp(CMD_ARGV[0], "idcode")) {
1758 buf_set_u32(ir_idcode, 0, 32, value);
1760 } else if (!strcmp(CMD_ARGV[0], "dtmcs")) {
1761 buf_set_u32(ir_dtmcontrol, 0, 32, value);
1763 } else if (!strcmp(CMD_ARGV[0], "dmi")) {
1764 buf_set_u32(ir_dbus, 0, 32, value);
1771 static const struct command_registration riscv_exec_command_handlers[] = {
1773 .name = "test_compliance",
1774 .handler = riscv_test_compliance,
1775 .mode = COMMAND_EXEC,
1776 .usage = "riscv test_compliance",
1777 .help = "Runs a basic compliance test suite against the RISC-V Debug Spec."
1780 .name = "set_command_timeout_sec",
1781 .handler = riscv_set_command_timeout_sec,
1782 .mode = COMMAND_ANY,
1783 .usage = "riscv set_command_timeout_sec [sec]",
1784 .help = "Set the wall-clock timeout (in seconds) for individual commands"
1787 .name = "set_reset_timeout_sec",
1788 .handler = riscv_set_reset_timeout_sec,
1789 .mode = COMMAND_ANY,
1790 .usage = "riscv set_reset_timeout_sec [sec]",
1791 .help = "Set the wall-clock timeout (in seconds) after reset is deasserted"
1794 .name = "set_prefer_sba",
1795 .handler = riscv_set_prefer_sba,
1796 .mode = COMMAND_ANY,
1797 .usage = "riscv set_prefer_sba on|off",
1798 .help = "When on, prefer to use System Bus Access to access memory. "
1799 "When off, prefer to use the Program Buffer to access memory."
1802 .name = "expose_csrs",
1803 .handler = riscv_set_expose_csrs,
1804 .mode = COMMAND_ANY,
1805 .usage = "riscv expose_csrs n0[-m0][,n1[-m1]]...",
1806 .help = "Configure a list of inclusive ranges for CSRs to expose in "
1807 "addition to the standard ones. This must be executed before "
1811 .name = "expose_custom",
1812 .handler = riscv_set_expose_custom,
1813 .mode = COMMAND_ANY,
1814 .usage = "riscv expose_custom n0[-m0][,n1[-m1]]...",
1815 .help = "Configure a list of inclusive ranges for custom registers to "
1816 "expose. custom0 is accessed as abstract register number 0xc000, "
1817 "etc. This must be executed before `init`."
1820 .name = "authdata_read",
1821 .handler = riscv_authdata_read,
1822 .mode = COMMAND_ANY,
1823 .usage = "riscv authdata_read",
1824 .help = "Return the 32-bit value read from authdata."
1827 .name = "authdata_write",
1828 .handler = riscv_authdata_write,
1829 .mode = COMMAND_ANY,
1830 .usage = "riscv authdata_write value",
1831 .help = "Write the 32-bit value to authdata."
1835 .handler = riscv_dmi_read,
1836 .mode = COMMAND_ANY,
1837 .usage = "riscv dmi_read address",
1838 .help = "Perform a 32-bit DMI read at address, returning the value."
1841 .name = "dmi_write",
1842 .handler = riscv_dmi_write,
1843 .mode = COMMAND_ANY,
1844 .usage = "riscv dmi_write address value",
1845 .help = "Perform a 32-bit DMI write of value at address."
1848 .name = "test_sba_config_reg",
1849 .handler = riscv_test_sba_config_reg,
1850 .mode = COMMAND_ANY,
1851 .usage = "riscv test_sba_config_reg legal_address num_words "
1852 "illegal_address run_sbbusyerror_test[on/off]",
1853 .help = "Perform a series of tests on the SBCS register. "
1854 "Inputs are a legal, 128-byte aligned address and a number of words to "
1855 "read/write starting at that address (i.e., address range [legal address, "
1856 "legal_address+word_size*num_words) must be legally readable/writable), "
1857 "an illegal, 128-byte aligned address for error flag/handling cases, "
1858 "and whether sbbusyerror test should be run."
1861 .name = "reset_delays",
1862 .handler = riscv_reset_delays,
1863 .mode = COMMAND_ANY,
1864 .usage = "reset_delays [wait]",
1865 .help = "OpenOCD learns how many Run-Test/Idle cycles are required "
1866 "between scans to avoid encountering the target being busy. This "
1867 "command resets those learned values after `wait` scans. It's only "
1868 "useful for testing OpenOCD itself."
1872 .handler = riscv_set_ir,
1873 .mode = COMMAND_ANY,
1874 .usage = "riscv set_ir_idcode [idcode|dtmcs|dmi] value",
1875 .help = "Set IR value for specified JTAG register."
1877 COMMAND_REGISTRATION_DONE
1881 * To be noted that RISC-V targets use the same semihosting commands as
1884 * The main reason is compatibility with existing tools. For example the
1885 * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
1886 * configure semihosting, which generate commands like `arm semihosting
1888 * A secondary reason is the fact that the protocol used is exactly the
1889 * one specified by ARM. If RISC-V will ever define its own semihosting
1890 * protocol, then a command like `riscv semihosting enable` will make
1891 * sense, but for now all semihosting commands are prefixed with `arm`.
1893 extern const struct command_registration semihosting_common_handlers[];
1895 const struct command_registration riscv_command_handlers[] = {
1898 .mode = COMMAND_ANY,
1899 .help = "RISC-V Command Group",
1901 .chain = riscv_exec_command_handlers
1905 .mode = COMMAND_ANY,
1906 .help = "ARM Command Group",
1908 .chain = semihosting_common_handlers
1910 COMMAND_REGISTRATION_DONE
1913 unsigned riscv_address_bits(struct target *target)
1915 return riscv_xlen(target);
1918 struct target_type riscv_target = {
1921 .init_target = riscv_init_target,
1922 .deinit_target = riscv_deinit_target,
1923 .examine = riscv_examine,
1925 /* poll current target status */
1926 .poll = old_or_new_riscv_poll,
1928 .halt = old_or_new_riscv_halt,
1929 .resume = old_or_new_riscv_resume,
1930 .step = old_or_new_riscv_step,
1932 .assert_reset = riscv_assert_reset,
1933 .deassert_reset = riscv_deassert_reset,
1935 .read_memory = riscv_read_memory,
1936 .write_memory = riscv_write_memory,
1938 .checksum_memory = riscv_checksum_memory,
1940 .get_gdb_reg_list = riscv_get_gdb_reg_list,
1942 .add_breakpoint = riscv_add_breakpoint,
1943 .remove_breakpoint = riscv_remove_breakpoint,
1945 .add_watchpoint = riscv_add_watchpoint,
1946 .remove_watchpoint = riscv_remove_watchpoint,
1947 .hit_watchpoint = riscv_hit_watchpoint,
1949 .arch_state = riscv_arch_state,
1951 .run_algorithm = riscv_run_algorithm,
1953 .commands = riscv_command_handlers,
1955 .address_bits = riscv_address_bits
1958 /*** RISC-V Interface ***/
1960 void riscv_info_init(struct target *target, riscv_info_t *r)
1962 memset(r, 0, sizeof(*r));
1964 r->registers_initialized = false;
1965 r->current_hartid = target->coreid;
1967 memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
1969 for (size_t h = 0; h < RISCV_MAX_HARTS; ++h) {
1972 for (size_t e = 0; e < RISCV_MAX_REGISTERS; ++e)
1973 r->valid_saved_registers[h][e] = false;
1977 int riscv_halt_all_harts(struct target *target)
1979 for (int i = 0; i < riscv_count_harts(target); ++i) {
1980 if (!riscv_hart_enabled(target, i))
1983 riscv_halt_one_hart(target, i);
1986 riscv_invalidate_register_cache(target);
1991 int riscv_halt_one_hart(struct target *target, int hartid)
1994 LOG_DEBUG("halting hart %d", hartid);
1995 if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1997 if (riscv_is_halted(target)) {
1998 LOG_DEBUG(" hart %d requested halt, but was already halted", hartid);
2002 int result = r->halt_current_hart(target);
2003 register_cache_invalidate(target->reg_cache);
2007 int riscv_resume_all_harts(struct target *target)
2009 for (int i = 0; i < riscv_count_harts(target); ++i) {
2010 if (!riscv_hart_enabled(target, i))
2013 riscv_resume_one_hart(target, i);
2016 riscv_invalidate_register_cache(target);
2020 int riscv_resume_one_hart(struct target *target, int hartid)
2023 LOG_DEBUG("resuming hart %d", hartid);
2024 if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2026 if (!riscv_is_halted(target)) {
2027 LOG_DEBUG(" hart %d requested resume, but was already resumed", hartid);
2031 r->on_resume(target);
2032 return r->resume_current_hart(target);
2035 int riscv_step_rtos_hart(struct target *target)
2038 int hartid = r->current_hartid;
2039 if (riscv_rtos_enabled(target)) {
2040 hartid = r->rtos_hartid;
2042 LOG_DEBUG("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
2046 if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2048 LOG_DEBUG("stepping hart %d", hartid);
2050 if (!riscv_is_halted(target)) {
2051 LOG_ERROR("Hart isn't halted before single step!");
2054 riscv_invalidate_register_cache(target);
2056 if (r->step_current_hart(target) != ERROR_OK)
2058 riscv_invalidate_register_cache(target);
2060 if (!riscv_is_halted(target)) {
2061 LOG_ERROR("Hart was not halted after single step!");
2067 bool riscv_supports_extension(struct target *target, int hartid, char letter)
2071 if (letter >= 'a' && letter <= 'z')
2073 else if (letter >= 'A' && letter <= 'Z')
2077 return r->misa[hartid] & (1 << num);
2080 int riscv_xlen(const struct target *target)
2082 return riscv_xlen_of_hart(target, riscv_current_hartid(target));
2085 int riscv_xlen_of_hart(const struct target *target, int hartid)
2088 assert(r->xlen[hartid] != -1);
2089 return r->xlen[hartid];
2092 extern struct rtos_type riscv_rtos;
2093 bool riscv_rtos_enabled(const struct target *target)
2098 int riscv_set_current_hartid(struct target *target, int hartid)
2101 if (!r->select_current_hart)
2104 int previous_hartid = riscv_current_hartid(target);
2105 r->current_hartid = hartid;
2106 assert(riscv_hart_enabled(target, hartid));
2107 LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
2108 if (r->select_current_hart(target) != ERROR_OK)
2111 /* This might get called during init, in which case we shouldn't be
2112 * setting up the register cache. */
2113 if (target_was_examined(target) && riscv_rtos_enabled(target))
2114 riscv_invalidate_register_cache(target);
2119 void riscv_invalidate_register_cache(struct target *target)
2123 LOG_DEBUG("[%d]", target->coreid);
2124 register_cache_invalidate(target->reg_cache);
2125 for (size_t i = 0; i < target->reg_cache->num_regs; ++i) {
2126 struct reg *reg = &target->reg_cache->reg_list[i];
2130 r->registers_initialized = true;
2133 int riscv_current_hartid(const struct target *target)
2136 return r->current_hartid;
2139 void riscv_set_all_rtos_harts(struct target *target)
2142 r->rtos_hartid = -1;
2145 void riscv_set_rtos_hartid(struct target *target, int hartid)
2147 LOG_DEBUG("setting RTOS hartid %d", hartid);
2149 r->rtos_hartid = hartid;
2152 int riscv_count_harts(struct target *target)
2159 return r->hart_count;
2162 bool riscv_has_register(struct target *target, int hartid, int regid)
2168 * This function is called when the debug user wants to change the value of a
2169 * register. The new value may be cached, and may not be written until the hart
2171 int riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v)
2173 return riscv_set_register_on_hart(target, riscv_current_hartid(target), r, v);
2176 int riscv_set_register_on_hart(struct target *target, int hartid,
2177 enum gdb_regno regid, uint64_t value)
2180 LOG_DEBUG("{%d} %s <- %" PRIx64, hartid, gdb_regno_name(regid), value);
2181 assert(r->set_register);
2182 return r->set_register(target, hartid, regid, value);
2185 int riscv_get_register(struct target *target, riscv_reg_t *value,
2188 return riscv_get_register_on_hart(target, value,
2189 riscv_current_hartid(target), r);
2192 int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
2193 int hartid, enum gdb_regno regid)
2197 struct reg *reg = &target->reg_cache->reg_list[regid];
2199 if (reg && reg->valid && hartid == riscv_current_hartid(target)) {
2200 *value = buf_get_u64(reg->value, 0, reg->size);
2204 int result = r->get_register(target, value, hartid, regid);
2206 LOG_DEBUG("{%d} %s: %" PRIx64, hartid, gdb_regno_name(regid), *value);
2210 bool riscv_is_halted(struct target *target)
2213 assert(r->is_halted);
2214 return r->is_halted(target);
2217 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
2220 if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2221 return RISCV_HALT_ERROR;
2222 if (!riscv_is_halted(target)) {
2223 LOG_ERROR("Hart is not halted!");
2224 return RISCV_HALT_UNKNOWN;
2226 return r->halt_reason(target);
2229 size_t riscv_debug_buffer_size(struct target *target)
2232 return r->debug_buffer_size[riscv_current_hartid(target)];
2235 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
2238 r->write_debug_buffer(target, index, insn);
2242 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
2245 return r->read_debug_buffer(target, index);
2248 int riscv_execute_debug_buffer(struct target *target)
2251 return r->execute_debug_buffer(target);
2254 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
2257 r->fill_dmi_write_u64(target, buf, a, d);
2260 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
2263 r->fill_dmi_read_u64(target, buf, a);
2266 void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
2269 r->fill_dmi_nop_u64(target, buf);
2272 int riscv_dmi_write_u64_bits(struct target *target)
2275 return r->dmi_write_u64_bits(target);
2278 bool riscv_hart_enabled(struct target *target, int hartid)
2280 /* FIXME: Add a hart mask to the RTOS. */
2281 if (riscv_rtos_enabled(target))
2282 return hartid < riscv_count_harts(target);
2284 return hartid == target->coreid;
2288 * Count triggers, and initialize trigger_count for each hart.
2289 * trigger_count is initialized even if this function fails to discover
2291 * Disable any hardware triggers that have dmode set. We can't have set them
2292 * ourselves. Maybe they're left over from some killed debug session.
2294 int riscv_enumerate_triggers(struct target *target)
2298 if (r->triggers_enumerated)
2301 r->triggers_enumerated = true; /* At the very least we tried. */
2303 for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
2304 if (!riscv_hart_enabled(target, hartid))
2307 riscv_reg_t tselect;
2308 int result = riscv_get_register_on_hart(target, &tselect, hartid,
2310 if (result != ERROR_OK)
2313 for (unsigned t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
2314 r->trigger_count[hartid] = t;
2316 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, t);
2317 uint64_t tselect_rb;
2318 result = riscv_get_register_on_hart(target, &tselect_rb, hartid,
2320 if (result != ERROR_OK)
2322 /* Mask off the top bit, which is used as tdrmode in old
2323 * implementations. */
2324 tselect_rb &= ~(1ULL << (riscv_xlen(target)-1));
2325 if (tselect_rb != t)
2328 result = riscv_get_register_on_hart(target, &tdata1, hartid,
2330 if (result != ERROR_OK)
2333 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
2336 /* On these older cores we don't support software using
2338 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
2341 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
2342 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
2347 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
2349 LOG_INFO("[%d] Found %d triggers", hartid, r->trigger_count[hartid]);
2355 const char *gdb_regno_name(enum gdb_regno regno)
2357 static char buf[32];
2360 case GDB_REGNO_ZERO:
2368 case GDB_REGNO_FPR0:
2370 case GDB_REGNO_FPR31:
2372 case GDB_REGNO_CSR0:
2374 case GDB_REGNO_TSELECT:
2376 case GDB_REGNO_TDATA1:
2378 case GDB_REGNO_TDATA2:
2380 case GDB_REGNO_MISA:
2384 case GDB_REGNO_DCSR:
2386 case GDB_REGNO_DSCRATCH:
2388 case GDB_REGNO_MSTATUS:
2390 case GDB_REGNO_PRIV:
2393 if (regno <= GDB_REGNO_XPR31)
2394 sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
2395 else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095)
2396 sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0);
2397 else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31)
2398 sprintf(buf, "f%d", regno - GDB_REGNO_FPR0);
2400 sprintf(buf, "gdb_regno_%d", regno);
2405 static int register_get(struct reg *reg)
2407 riscv_reg_info_t *reg_info = reg->arch_info;
2408 struct target *target = reg_info->target;
2410 int result = riscv_get_register(target, &value, reg->number);
2411 if (result != ERROR_OK)
2413 buf_set_u64(reg->value, 0, reg->size, value);
2414 /* CSRs (and possibly other extension) registers may change value at any
2416 if (reg->number <= GDB_REGNO_XPR31 ||
2417 (reg->number >= GDB_REGNO_FPR0 && reg->number <= GDB_REGNO_FPR31) ||
2418 reg->number == GDB_REGNO_PC)
2420 LOG_DEBUG("[%d]{%d} read 0x%" PRIx64 " from %s (valid=%d)",
2421 target->coreid, riscv_current_hartid(target), value, reg->name,
2426 static int register_set(struct reg *reg, uint8_t *buf)
2428 riscv_reg_info_t *reg_info = reg->arch_info;
2429 struct target *target = reg_info->target;
2431 uint64_t value = buf_get_u64(buf, 0, reg->size);
2433 LOG_DEBUG("[%d]{%d} write 0x%" PRIx64 " to %s (valid=%d)",
2434 target->coreid, riscv_current_hartid(target), value, reg->name,
2436 struct reg *r = &target->reg_cache->reg_list[reg->number];
2437 /* CSRs (and possibly other extension) registers may change value at any
2439 if (reg->number <= GDB_REGNO_XPR31 ||
2440 (reg->number >= GDB_REGNO_FPR0 && reg->number <= GDB_REGNO_FPR31) ||
2441 reg->number == GDB_REGNO_PC)
2443 memcpy(r->value, buf, (r->size + 7) / 8);
2445 riscv_set_register(target, reg->number, value);
2449 static struct reg_arch_type riscv_reg_arch_type = {
2450 .get = register_get,
2459 static int cmp_csr_info(const void *p1, const void *p2)
2461 return (int) (((struct csr_info *)p1)->number) - (int) (((struct csr_info *)p2)->number);
2464 int riscv_init_registers(struct target *target)
2468 riscv_free_registers(target);
2470 target->reg_cache = calloc(1, sizeof(*target->reg_cache));
2471 target->reg_cache->name = "RISC-V Registers";
2472 target->reg_cache->num_regs = GDB_REGNO_COUNT;
2474 if (expose_custom) {
2475 for (unsigned i = 0; expose_custom[i].low <= expose_custom[i].high; i++) {
2476 for (unsigned number = expose_custom[i].low;
2477 number <= expose_custom[i].high;
2479 target->reg_cache->num_regs++;
2483 LOG_DEBUG("create register cache for %d registers",
2484 target->reg_cache->num_regs);
2486 target->reg_cache->reg_list =
2487 calloc(target->reg_cache->num_regs, sizeof(struct reg));
2489 const unsigned int max_reg_name_len = 12;
2490 if (info->reg_names)
2491 free(info->reg_names);
2493 calloc(target->reg_cache->num_regs, max_reg_name_len);
2494 char *reg_name = info->reg_names;
2496 static struct reg_feature feature_cpu = {
2497 .name = "org.gnu.gdb.riscv.cpu"
2499 static struct reg_feature feature_fpu = {
2500 .name = "org.gnu.gdb.riscv.fpu"
2502 static struct reg_feature feature_csr = {
2503 .name = "org.gnu.gdb.riscv.csr"
2505 static struct reg_feature feature_virtual = {
2506 .name = "org.gnu.gdb.riscv.virtual"
2508 static struct reg_feature feature_custom = {
2509 .name = "org.gnu.gdb.riscv.custom"
2512 static struct reg_data_type type_ieee_single = {
2513 .type = REG_TYPE_IEEE_SINGLE,
2516 static struct reg_data_type type_ieee_double = {
2517 .type = REG_TYPE_IEEE_DOUBLE,
2520 struct csr_info csr_info[] = {
2521 #define DECLARE_CSR(name, number) { number, #name },
2522 #include "encoding.h"
2525 /* encoding.h does not contain the registers in sorted order. */
2526 qsort(csr_info, DIM(csr_info), sizeof(*csr_info), cmp_csr_info);
2527 unsigned csr_info_index = 0;
2529 unsigned custom_range_index = 0;
2530 int custom_within_range = 0;
2532 riscv_reg_info_t *shared_reg_info = calloc(1, sizeof(riscv_reg_info_t));
2533 shared_reg_info->target = target;
2535 /* When gdb requests register N, gdb_get_register_packet() assumes that this
2536 * is register at index N in reg_list. So if there are certain registers
2537 * that don't exist, we need to leave holes in the list (or renumber, but
2538 * it would be nice not to have yet another set of numbers to translate
2540 for (uint32_t number = 0; number < target->reg_cache->num_regs; number++) {
2541 struct reg *r = &target->reg_cache->reg_list[number];
2545 r->type = &riscv_reg_arch_type;
2546 r->arch_info = shared_reg_info;
2548 r->size = riscv_xlen(target);
2549 /* r->size is set in riscv_invalidate_register_cache, maybe because the
2550 * target is in theory allowed to change XLEN on us. But I expect a lot
2551 * of other things to break in that case as well. */
2552 if (number <= GDB_REGNO_XPR31) {
2553 r->caller_save = true;
2555 case GDB_REGNO_ZERO:
2652 r->group = "general";
2653 r->feature = &feature_cpu;
2654 } else if (number == GDB_REGNO_PC) {
2655 r->caller_save = true;
2656 sprintf(reg_name, "pc");
2657 r->group = "general";
2658 r->feature = &feature_cpu;
2659 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
2660 r->caller_save = true;
2661 if (riscv_supports_extension(target, riscv_current_hartid(target),
2663 r->reg_data_type = &type_ieee_double;
2665 } else if (riscv_supports_extension(target,
2666 riscv_current_hartid(target), 'F')) {
2667 r->reg_data_type = &type_ieee_single;
2751 case GDB_REGNO_FS10:
2754 case GDB_REGNO_FS11:
2763 case GDB_REGNO_FT10:
2766 case GDB_REGNO_FT11:
2771 r->feature = &feature_fpu;
2772 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
2774 r->feature = &feature_csr;
2775 unsigned csr_number = number - GDB_REGNO_CSR0;
2777 while (csr_info[csr_info_index].number < csr_number &&
2778 csr_info_index < DIM(csr_info) - 1) {
2781 if (csr_info[csr_info_index].number == csr_number) {
2782 r->name = csr_info[csr_info_index].name;
2784 sprintf(reg_name, "csr%d", csr_number);
2785 /* Assume unnamed registers don't exist, unless we have some
2786 * configuration that tells us otherwise. That's important
2787 * because eg. Eclipse crashes if a target has too many
2788 * registers, and apparently has no way of only showing a
2789 * subset of registers in any case. */
2793 switch (csr_number) {
2797 r->exist = riscv_supports_extension(target,
2798 riscv_current_hartid(target), 'F');
2800 r->feature = &feature_fpu;
2806 case CSR_SCOUNTEREN:
2812 r->exist = riscv_supports_extension(target,
2813 riscv_current_hartid(target), 'S');
2817 /* "In systems with only M-mode, or with both M-mode and
2818 * U-mode but without U-mode trap support, the medeleg and
2819 * mideleg registers should not exist." */
2820 r->exist = riscv_supports_extension(target, riscv_current_hartid(target), 'S') ||
2821 riscv_supports_extension(target, riscv_current_hartid(target), 'N');
2827 case CSR_HPMCOUNTER3H:
2828 case CSR_HPMCOUNTER4H:
2829 case CSR_HPMCOUNTER5H:
2830 case CSR_HPMCOUNTER6H:
2831 case CSR_HPMCOUNTER7H:
2832 case CSR_HPMCOUNTER8H:
2833 case CSR_HPMCOUNTER9H:
2834 case CSR_HPMCOUNTER10H:
2835 case CSR_HPMCOUNTER11H:
2836 case CSR_HPMCOUNTER12H:
2837 case CSR_HPMCOUNTER13H:
2838 case CSR_HPMCOUNTER14H:
2839 case CSR_HPMCOUNTER15H:
2840 case CSR_HPMCOUNTER16H:
2841 case CSR_HPMCOUNTER17H:
2842 case CSR_HPMCOUNTER18H:
2843 case CSR_HPMCOUNTER19H:
2844 case CSR_HPMCOUNTER20H:
2845 case CSR_HPMCOUNTER21H:
2846 case CSR_HPMCOUNTER22H:
2847 case CSR_HPMCOUNTER23H:
2848 case CSR_HPMCOUNTER24H:
2849 case CSR_HPMCOUNTER25H:
2850 case CSR_HPMCOUNTER26H:
2851 case CSR_HPMCOUNTER27H:
2852 case CSR_HPMCOUNTER28H:
2853 case CSR_HPMCOUNTER29H:
2854 case CSR_HPMCOUNTER30H:
2855 case CSR_HPMCOUNTER31H:
2858 case CSR_MHPMCOUNTER3H:
2859 case CSR_MHPMCOUNTER4H:
2860 case CSR_MHPMCOUNTER5H:
2861 case CSR_MHPMCOUNTER6H:
2862 case CSR_MHPMCOUNTER7H:
2863 case CSR_MHPMCOUNTER8H:
2864 case CSR_MHPMCOUNTER9H:
2865 case CSR_MHPMCOUNTER10H:
2866 case CSR_MHPMCOUNTER11H:
2867 case CSR_MHPMCOUNTER12H:
2868 case CSR_MHPMCOUNTER13H:
2869 case CSR_MHPMCOUNTER14H:
2870 case CSR_MHPMCOUNTER15H:
2871 case CSR_MHPMCOUNTER16H:
2872 case CSR_MHPMCOUNTER17H:
2873 case CSR_MHPMCOUNTER18H:
2874 case CSR_MHPMCOUNTER19H:
2875 case CSR_MHPMCOUNTER20H:
2876 case CSR_MHPMCOUNTER21H:
2877 case CSR_MHPMCOUNTER22H:
2878 case CSR_MHPMCOUNTER23H:
2879 case CSR_MHPMCOUNTER24H:
2880 case CSR_MHPMCOUNTER25H:
2881 case CSR_MHPMCOUNTER26H:
2882 case CSR_MHPMCOUNTER27H:
2883 case CSR_MHPMCOUNTER28H:
2884 case CSR_MHPMCOUNTER29H:
2885 case CSR_MHPMCOUNTER30H:
2886 case CSR_MHPMCOUNTER31H:
2887 r->exist = riscv_xlen(target) == 32;
2891 if (!r->exist && expose_csr) {
2892 for (unsigned i = 0; expose_csr[i].low <= expose_csr[i].high; i++) {
2893 if (csr_number >= expose_csr[i].low && csr_number <= expose_csr[i].high) {
2894 LOG_INFO("Exposing additional CSR %d", csr_number);
2901 } else if (number == GDB_REGNO_PRIV) {
2902 sprintf(reg_name, "priv");
2903 r->group = "general";
2904 r->feature = &feature_virtual;
2908 /* Custom registers. */
2909 assert(expose_custom);
2911 range_t *range = &expose_custom[custom_range_index];
2912 assert(range->low <= range->high);
2913 unsigned custom_number = range->low + custom_within_range;
2915 r->group = "custom";
2916 r->feature = &feature_custom;
2917 r->arch_info = calloc(1, sizeof(riscv_reg_info_t));
2918 assert(r->arch_info);
2919 ((riscv_reg_info_t *) r->arch_info)->target = target;
2920 ((riscv_reg_info_t *) r->arch_info)->custom_number = custom_number;
2921 sprintf(reg_name, "custom%d", custom_number);
2923 custom_within_range++;
2924 if (custom_within_range > range->high - range->low) {
2925 custom_within_range = 0;
2926 custom_range_index++;
2932 reg_name += strlen(reg_name) + 1;
2933 assert(reg_name < info->reg_names + target->reg_cache->num_regs *
2935 r->value = &info->reg_cache_values[number];