git.gag.com Git - fw/openocd/blob - src/target/riscv/riscv.c

   1 #include <assert.h>
   2 #include <stdlib.h>
   3 #include <time.h>
   4
   5 #ifdef HAVE_CONFIG_H
   6 #include "config.h"
   7 #endif
   8
   9 #include "target/target.h"
  10 #include "target/algorithm.h"
  11 #include "target/target_type.h"
  12 #include "log.h"
  13 #include "jtag/jtag.h"
  14 #include "target/register.h"
  15 #include "target/breakpoints.h"
  16 #include "helper/time_support.h"
  17 #include "riscv.h"
  18 #include "gdb_regs.h"
  19 #include "rtos/rtos.h"
  20
  21 /**
  22  * Since almost everything can be accomplish by scanning the dbus register, all
  23  * functions here assume dbus is already selected. The exception are functions
  24  * called directly by OpenOCD, which can't assume anything about what's
  25  * currently in IR. They should set IR to dbus explicitly.
  26  */
  27
  28 /**
  29  * Code structure
  30  *
  31  * At the bottom of the stack are the OpenOCD JTAG functions:
  32  *              jtag_add_[id]r_scan
  33  *              jtag_execute_query
  34  *              jtag_add_runtest
  35  *
  36  * There are a few functions to just instantly shift a register and get its
  37  * value:
  38  *              dtmcontrol_scan
  39  *              idcode_scan
  40  *              dbus_scan
  41  *
  42  * Because doing one scan and waiting for the result is slow, most functions
  43  * batch up a bunch of dbus writes and then execute them all at once. They use
  44  * the scans "class" for this:
  45  *              scans_new
  46  *              scans_delete
  47  *              scans_execute
  48  *              scans_add_...
  49  * Usually you new(), call a bunch of add functions, then execute() and look
  50  * at the results by calling scans_get...()
  51  *
  52  * Optimized functions will directly use the scans class above, but slightly
  53  * lazier code will use the cache functions that in turn use the scans
  54  * functions:
  55  *              cache_get...
  56  *              cache_set...
  57  *              cache_write
  58  * cache_set... update a local structure, which is then synced to the target
  59  * with cache_write(). Only Debug RAM words that are actually changed are sent
  60  * to the target. Afterwards use cache_get... to read results.
  61  */
  62
  63 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
  64 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
  65
  66 #define DIM(x)          (sizeof(x)/sizeof(*x))
  67
  68 /* Constants for legacy SiFive hardware breakpoints. */
  69 #define CSR_BPCONTROL_X                 (1<<0)
  70 #define CSR_BPCONTROL_W                 (1<<1)
  71 #define CSR_BPCONTROL_R                 (1<<2)
  72 #define CSR_BPCONTROL_U                 (1<<3)
  73 #define CSR_BPCONTROL_S                 (1<<4)
  74 #define CSR_BPCONTROL_H                 (1<<5)
  75 #define CSR_BPCONTROL_M                 (1<<6)
  76 #define CSR_BPCONTROL_BPMATCH   (0xf<<7)
  77 #define CSR_BPCONTROL_BPACTION  (0xff<<11)
  78
  79 #define DEBUG_ROM_START         0x800
  80 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
  81 #define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
  82 #define DEBUG_RAM_START         0x400
  83
  84 #define SETHALTNOT                              0x10c
  85
  86 /*** JTAG registers. ***/
  87
  88 #define DTMCONTROL                                      0x10
  89 #define DTMCONTROL_DBUS_RESET           (1<<16)
  90 #define DTMCONTROL_IDLE                         (7<<10)
  91 #define DTMCONTROL_ADDRBITS                     (0xf<<4)
  92 #define DTMCONTROL_VERSION                      (0xf)
  93
  94 #define DBUS                                            0x11
  95 #define DBUS_OP_START                           0
  96 #define DBUS_OP_SIZE                            2
  97 typedef enum {
  98         DBUS_OP_NOP = 0,
  99         DBUS_OP_READ = 1,
 100         DBUS_OP_WRITE = 2
 101 } dbus_op_t;
 102 typedef enum {
 103         DBUS_STATUS_SUCCESS = 0,
 104         DBUS_STATUS_FAILED = 2,
 105         DBUS_STATUS_BUSY = 3
 106 } dbus_status_t;
 107 #define DBUS_DATA_START                         2
 108 #define DBUS_DATA_SIZE                          34
 109 #define DBUS_ADDRESS_START                      36
 110
 111 typedef enum {
 112         RE_OK,
 113         RE_FAIL,
 114         RE_AGAIN
 115 } riscv_error_t;
 116
 117 typedef enum slot {
 118         SLOT0,
 119         SLOT1,
 120         SLOT_LAST,
 121 } slot_t;
 122
 123 /*** Debug Bus registers. ***/
 124
 125 #define DMCONTROL                               0x10
 126 #define DMCONTROL_INTERRUPT             (((uint64_t)1)<<33)
 127 #define DMCONTROL_HALTNOT               (((uint64_t)1)<<32)
 128 #define DMCONTROL_BUSERROR              (7<<19)
 129 #define DMCONTROL_SERIAL                (3<<16)
 130 #define DMCONTROL_AUTOINCREMENT (1<<15)
 131 #define DMCONTROL_ACCESS                (7<<12)
 132 #define DMCONTROL_HARTID                (0x3ff<<2)
 133 #define DMCONTROL_NDRESET               (1<<1)
 134 #define DMCONTROL_FULLRESET             1
 135
 136 #define DMINFO                                  0x11
 137 #define DMINFO_ABUSSIZE                 (0x7fU<<25)
 138 #define DMINFO_SERIALCOUNT              (0xf<<21)
 139 #define DMINFO_ACCESS128                (1<<20)
 140 #define DMINFO_ACCESS64                 (1<<19)
 141 #define DMINFO_ACCESS32                 (1<<18)
 142 #define DMINFO_ACCESS16                 (1<<17)
 143 #define DMINFO_ACCESS8                  (1<<16)
 144 #define DMINFO_DRAMSIZE                 (0x3f<<10)
 145 #define DMINFO_AUTHENTICATED    (1<<5)
 146 #define DMINFO_AUTHBUSY                 (1<<4)
 147 #define DMINFO_AUTHTYPE                 (3<<2)
 148 #define DMINFO_VERSION                  3
 149
 150 /*** Info about the core being debugged. ***/
 151
 152 #define DBUS_ADDRESS_UNKNOWN    0xffff
 153
 154 #define MAX_HWBPS                       16
 155 #define DRAM_CACHE_SIZE         16
 156
 157 uint8_t ir_dtmcontrol[1] = {DTMCONTROL};
 158 struct scan_field select_dtmcontrol = {
 159         .in_value = NULL,
 160         .out_value = ir_dtmcontrol
 161 };
 162 uint8_t ir_dbus[1] = {DBUS};
 163 struct scan_field select_dbus = {
 164         .in_value = NULL,
 165         .out_value = ir_dbus
 166 };
 167 uint8_t ir_idcode[1] = {0x1};
 168 struct scan_field select_idcode = {
 169         .in_value = NULL,
 170         .out_value = ir_idcode
 171 };
 172
 173 struct trigger {
 174         uint64_t address;
 175         uint32_t length;
 176         uint64_t mask;
 177         uint64_t value;
 178         bool read, write, execute;
 179         int unique_id;
 180 };
 181
 182 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 183 int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
 184
 185 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 186 int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
 187
 188 bool riscv_prefer_sba;
 189
 190 /* In addition to the ones in the standard spec, we'll also expose additional
 191  * CSRs in this list.
 192  * The list is either NULL, or a series of ranges (inclusive), terminated with
 193  * 1,0. */
 194 struct {
 195         uint16_t low, high;
 196 } *expose_csr;
 197
 198 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
 199 {
 200         struct scan_field field;
 201         uint8_t in_value[4];
 202         uint8_t out_value[4];
 203
 204         buf_set_u32(out_value, 0, 32, out);
 205
 206         jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
 207
 208         field.num_bits = 32;
 209         field.out_value = out_value;
 210         field.in_value = in_value;
 211         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 212
 213         /* Always return to dbus. */
 214         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 215
 216         int retval = jtag_execute_queue();
 217         if (retval != ERROR_OK) {
 218                 LOG_ERROR("failed jtag scan: %d", retval);
 219                 return retval;
 220         }
 221
 222         uint32_t in = buf_get_u32(field.in_value, 0, 32);
 223         LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
 224
 225         return in;
 226 }
 227
 228 static struct target_type *get_target_type(struct target *target)
 229 {
 230         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 231
 232         if (!info) {
 233                 LOG_ERROR("Target has not been initialized");
 234                 return NULL;
 235         }
 236
 237         switch (info->dtm_version) {
 238                 case 0:
 239                         return &riscv011_target;
 240                 case 1:
 241                         return &riscv013_target;
 242                 default:
 243                         LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
 244                         return NULL;
 245         }
 246 }
 247
 248 static int riscv_init_target(struct command_context *cmd_ctx,
 249                 struct target *target)
 250 {
 251         LOG_DEBUG("riscv_init_target()");
 252         target->arch_info = calloc(1, sizeof(riscv_info_t));
 253         if (!target->arch_info)
 254                 return ERROR_FAIL;
 255         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 256         riscv_info_init(target, info);
 257         info->cmd_ctx = cmd_ctx;
 258
 259         select_dtmcontrol.num_bits = target->tap->ir_length;
 260         select_dbus.num_bits = target->tap->ir_length;
 261         select_idcode.num_bits = target->tap->ir_length;
 262
 263         riscv_semihosting_init(target);
 264
 265         return ERROR_OK;
 266 }
 267
 268 static void riscv_deinit_target(struct target *target)
 269 {
 270         LOG_DEBUG("riscv_deinit_target()");
 271         struct target_type *tt = get_target_type(target);
 272         if (tt) {
 273                 tt->deinit_target(target);
 274                 riscv_info_t *info = (riscv_info_t *) target->arch_info;
 275                 free(info);
 276         }
 277         target->arch_info = NULL;
 278 }
 279
 280 static int oldriscv_halt(struct target *target)
 281 {
 282         struct target_type *tt = get_target_type(target);
 283         return tt->halt(target);
 284 }
 285
 286 static void trigger_from_breakpoint(struct trigger *trigger,
 287                 const struct breakpoint *breakpoint)
 288 {
 289         trigger->address = breakpoint->address;
 290         trigger->length = breakpoint->length;
 291         trigger->mask = ~0LL;
 292         trigger->read = false;
 293         trigger->write = false;
 294         trigger->execute = true;
 295         /* unique_id is unique across both breakpoints and watchpoints. */
 296         trigger->unique_id = breakpoint->unique_id;
 297 }
 298
 299 static int maybe_add_trigger_t1(struct target *target, unsigned hartid,
 300                 struct trigger *trigger, uint64_t tdata1)
 301 {
 302         RISCV_INFO(r);
 303
 304         const uint32_t bpcontrol_x = 1<<0;
 305         const uint32_t bpcontrol_w = 1<<1;
 306         const uint32_t bpcontrol_r = 1<<2;
 307         const uint32_t bpcontrol_u = 1<<3;
 308         const uint32_t bpcontrol_s = 1<<4;
 309         const uint32_t bpcontrol_h = 1<<5;
 310         const uint32_t bpcontrol_m = 1<<6;
 311         const uint32_t bpcontrol_bpmatch = 0xf << 7;
 312         const uint32_t bpcontrol_bpaction = 0xff << 11;
 313
 314         if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
 315                 /* Trigger is already in use, presumably by user code. */
 316                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 317         }
 318
 319         tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
 320         tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
 321         tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
 322         tdata1 = set_field(tdata1, bpcontrol_u,
 323                         !!(r->misa[hartid] & (1 << ('U' - 'A'))));
 324         tdata1 = set_field(tdata1, bpcontrol_s,
 325                         !!(r->misa[hartid] & (1 << ('S' - 'A'))));
 326         tdata1 = set_field(tdata1, bpcontrol_h,
 327                         !!(r->misa[hartid] & (1 << ('H' - 'A'))));
 328         tdata1 |= bpcontrol_m;
 329         tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
 330         tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
 331
 332         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
 333
 334         riscv_reg_t tdata1_rb;
 335         if (riscv_get_register_on_hart(target, &tdata1_rb, hartid,
 336                                 GDB_REGNO_TDATA1) != ERROR_OK)
 337                 return ERROR_FAIL;
 338         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 339
 340         if (tdata1 != tdata1_rb) {
 341                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 342                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 343                                 tdata1, tdata1_rb);
 344                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
 345                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 346         }
 347
 348         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
 349
 350         return ERROR_OK;
 351 }
 352
 353 static int maybe_add_trigger_t2(struct target *target, unsigned hartid,
 354                 struct trigger *trigger, uint64_t tdata1)
 355 {
 356         RISCV_INFO(r);
 357
 358         /* tselect is already set */
 359         if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
 360                 /* Trigger is already in use, presumably by user code. */
 361                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 362         }
 363
 364         /* address/data match trigger */
 365         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 366         tdata1 = set_field(tdata1, MCONTROL_ACTION,
 367                         MCONTROL_ACTION_DEBUG_MODE);
 368         tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
 369         tdata1 |= MCONTROL_M;
 370         if (r->misa[hartid] & (1 << ('H' - 'A')))
 371                 tdata1 |= MCONTROL_H;
 372         if (r->misa[hartid] & (1 << ('S' - 'A')))
 373                 tdata1 |= MCONTROL_S;
 374         if (r->misa[hartid] & (1 << ('U' - 'A')))
 375                 tdata1 |= MCONTROL_U;
 376
 377         if (trigger->execute)
 378                 tdata1 |= MCONTROL_EXECUTE;
 379         if (trigger->read)
 380                 tdata1 |= MCONTROL_LOAD;
 381         if (trigger->write)
 382                 tdata1 |= MCONTROL_STORE;
 383
 384         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
 385
 386         uint64_t tdata1_rb;
 387         int result = riscv_get_register_on_hart(target, &tdata1_rb, hartid, GDB_REGNO_TDATA1);
 388         if (result != ERROR_OK)
 389                 return result;
 390         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 391
 392         if (tdata1 != tdata1_rb) {
 393                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 394                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 395                                 tdata1, tdata1_rb);
 396                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
 397                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 398         }
 399
 400         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
 401
 402         return ERROR_OK;
 403 }
 404
 405 static int add_trigger(struct target *target, struct trigger *trigger)
 406 {
 407         RISCV_INFO(r);
 408
 409         if (riscv_enumerate_triggers(target) != ERROR_OK)
 410                 return ERROR_FAIL;
 411
 412         /* In RTOS mode, we need to set the same trigger in the same slot on every
 413          * hart, to keep up the illusion that each hart is a thread running on the
 414          * same core. */
 415
 416         /* Otherwise, we just set the trigger on the one hart this target deals
 417          * with. */
 418
 419         riscv_reg_t tselect[RISCV_MAX_HARTS];
 420
 421         int first_hart = -1;
 422         for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
 423                 if (!riscv_hart_enabled(target, hartid))
 424                         continue;
 425                 if (first_hart < 0)
 426                         first_hart = hartid;
 427                 int result = riscv_get_register_on_hart(target, &tselect[hartid],
 428                                 hartid, GDB_REGNO_TSELECT);
 429                 if (result != ERROR_OK)
 430                         return result;
 431         }
 432         assert(first_hart >= 0);
 433
 434         unsigned int i;
 435         for (i = 0; i < r->trigger_count[first_hart]; i++) {
 436                 if (r->trigger_unique_id[i] != -1)
 437                         continue;
 438
 439                 riscv_set_register_on_hart(target, first_hart, GDB_REGNO_TSELECT, i);
 440
 441                 uint64_t tdata1;
 442                 int result = riscv_get_register_on_hart(target, &tdata1, first_hart,
 443                                 GDB_REGNO_TDATA1);
 444                 if (result != ERROR_OK)
 445                         return result;
 446                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
 447
 448                 result = ERROR_OK;
 449                 for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
 450                         if (!riscv_hart_enabled(target, hartid))
 451                                 continue;
 452                         if (hartid > first_hart)
 453                                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
 454                         switch (type) {
 455                                 case 1:
 456                                         result = maybe_add_trigger_t1(target, hartid, trigger, tdata1);
 457                                         break;
 458                                 case 2:
 459                                         result = maybe_add_trigger_t2(target, hartid, trigger, tdata1);
 460                                         break;
 461                                 default:
 462                                         LOG_DEBUG("trigger %d has unknown type %d", i, type);
 463                                         continue;
 464                         }
 465
 466                         if (result != ERROR_OK)
 467                                 continue;
 468                 }
 469
 470                 if (result != ERROR_OK)
 471                         continue;
 472
 473                 LOG_DEBUG("Using trigger %d (type %d) for bp %d", i, type,
 474                                 trigger->unique_id);
 475                 r->trigger_unique_id[i] = trigger->unique_id;
 476                 break;
 477         }
 478
 479         for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
 480                 if (!riscv_hart_enabled(target, hartid))
 481                         continue;
 482                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT,
 483                                 tselect[hartid]);
 484         }
 485
 486         if (i >= r->trigger_count[first_hart]) {
 487                 LOG_ERROR("Couldn't find an available hardware trigger.");
 488                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 489         }
 490
 491         return ERROR_OK;
 492 }
 493
 494 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 495 {
 496         if (breakpoint->type == BKPT_SOFT) {
 497                 if (target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 498                                         breakpoint->orig_instr) != ERROR_OK) {
 499                         LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
 500                                         breakpoint->address);
 501                         return ERROR_FAIL;
 502                 }
 503
 504                 int retval;
 505                 if (breakpoint->length == 4)
 506                         retval = target_write_u32(target, breakpoint->address, ebreak());
 507                 else
 508                         retval = target_write_u16(target, breakpoint->address, ebreak_c());
 509                 if (retval != ERROR_OK) {
 510                         LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
 511                                         TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 512                         return ERROR_FAIL;
 513                 }
 514
 515         } else if (breakpoint->type == BKPT_HARD) {
 516                 struct trigger trigger;
 517                 trigger_from_breakpoint(&trigger, breakpoint);
 518                 int result = add_trigger(target, &trigger);
 519                 if (result != ERROR_OK)
 520                         return result;
 521
 522         } else {
 523                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 524                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 525         }
 526
 527         breakpoint->set = true;
 528
 529         return ERROR_OK;
 530 }
 531
 532 static int remove_trigger(struct target *target, struct trigger *trigger)
 533 {
 534         RISCV_INFO(r);
 535
 536         if (riscv_enumerate_triggers(target) != ERROR_OK)
 537                 return ERROR_FAIL;
 538
 539         int first_hart = -1;
 540         for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
 541                 if (!riscv_hart_enabled(target, hartid))
 542                         continue;
 543                 if (first_hart < 0) {
 544                         first_hart = hartid;
 545                         break;
 546                 }
 547         }
 548         assert(first_hart >= 0);
 549
 550         unsigned int i;
 551         for (i = 0; i < r->trigger_count[first_hart]; i++) {
 552                 if (r->trigger_unique_id[i] == trigger->unique_id)
 553                         break;
 554         }
 555         if (i >= r->trigger_count[first_hart]) {
 556                 LOG_ERROR("Couldn't find the hardware resources used by hardware "
 557                                 "trigger.");
 558                 return ERROR_FAIL;
 559         }
 560         LOG_DEBUG("Stop using resource %d for bp %d", i, trigger->unique_id);
 561         for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
 562                 if (!riscv_hart_enabled(target, hartid))
 563                         continue;
 564                 riscv_reg_t tselect;
 565                 int result = riscv_get_register_on_hart(target, &tselect, hartid, GDB_REGNO_TSELECT);
 566                 if (result != ERROR_OK)
 567                         return result;
 568                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
 569                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
 570                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
 571         }
 572         r->trigger_unique_id[i] = -1;
 573
 574         return ERROR_OK;
 575 }
 576
 577 int riscv_remove_breakpoint(struct target *target,
 578                 struct breakpoint *breakpoint)
 579 {
 580         if (breakpoint->type == BKPT_SOFT) {
 581                 if (target_write_memory(target, breakpoint->address, breakpoint->length, 1,
 582                                         breakpoint->orig_instr) != ERROR_OK) {
 583                         LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
 584                                         "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 585                         return ERROR_FAIL;
 586                 }
 587
 588         } else if (breakpoint->type == BKPT_HARD) {
 589                 struct trigger trigger;
 590                 trigger_from_breakpoint(&trigger, breakpoint);
 591                 int result = remove_trigger(target, &trigger);
 592                 if (result != ERROR_OK)
 593                         return result;
 594
 595         } else {
 596                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 597                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 598         }
 599
 600         breakpoint->set = false;
 601
 602         return ERROR_OK;
 603 }
 604
 605 static void trigger_from_watchpoint(struct trigger *trigger,
 606                 const struct watchpoint *watchpoint)
 607 {
 608         trigger->address = watchpoint->address;
 609         trigger->length = watchpoint->length;
 610         trigger->mask = watchpoint->mask;
 611         trigger->value = watchpoint->value;
 612         trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
 613         trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
 614         trigger->execute = false;
 615         /* unique_id is unique across both breakpoints and watchpoints. */
 616         trigger->unique_id = watchpoint->unique_id;
 617 }
 618
 619 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 620 {
 621         struct trigger trigger;
 622         trigger_from_watchpoint(&trigger, watchpoint);
 623
 624         int result = add_trigger(target, &trigger);
 625         if (result != ERROR_OK)
 626                 return result;
 627         watchpoint->set = true;
 628
 629         return ERROR_OK;
 630 }
 631
 632 int riscv_remove_watchpoint(struct target *target,
 633                 struct watchpoint *watchpoint)
 634 {
 635         struct trigger trigger;
 636         trigger_from_watchpoint(&trigger, watchpoint);
 637
 638         int result = remove_trigger(target, &trigger);
 639         if (result != ERROR_OK)
 640                 return result;
 641         watchpoint->set = false;
 642
 643         return ERROR_OK;
 644 }
 645
 646 static int oldriscv_step(struct target *target, int current, uint32_t address,
 647                 int handle_breakpoints)
 648 {
 649         struct target_type *tt = get_target_type(target);
 650         return tt->step(target, current, address, handle_breakpoints);
 651 }
 652
 653 static int old_or_new_riscv_step(
 654                 struct target *target,
 655                 int current,
 656                 target_addr_t address,
 657                 int handle_breakpoints
 658 ){
 659         RISCV_INFO(r);
 660         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
 661         if (r->is_halted == NULL)
 662                 return oldriscv_step(target, current, address, handle_breakpoints);
 663         else
 664                 return riscv_openocd_step(target, current, address, handle_breakpoints);
 665 }
 666
 667
 668 static int riscv_examine(struct target *target)
 669 {
 670         LOG_DEBUG("riscv_examine()");
 671         if (target_was_examined(target)) {
 672                 LOG_DEBUG("Target was already examined.");
 673                 return ERROR_OK;
 674         }
 675
 676         /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
 677
 678         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 679         uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
 680         LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
 681         info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
 682         LOG_DEBUG("  version=0x%x", info->dtm_version);
 683
 684         struct target_type *tt = get_target_type(target);
 685         if (tt == NULL)
 686                 return ERROR_FAIL;
 687
 688         int result = tt->init_target(info->cmd_ctx, target);
 689         if (result != ERROR_OK)
 690                 return result;
 691
 692         return tt->examine(target);
 693 }
 694
 695 static int oldriscv_poll(struct target *target)
 696 {
 697         struct target_type *tt = get_target_type(target);
 698         return tt->poll(target);
 699 }
 700
 701 static int old_or_new_riscv_poll(struct target *target)
 702 {
 703         RISCV_INFO(r);
 704         if (r->is_halted == NULL)
 705                 return oldriscv_poll(target);
 706         else
 707                 return riscv_openocd_poll(target);
 708 }
 709
 710 static int old_or_new_riscv_halt(struct target *target)
 711 {
 712         RISCV_INFO(r);
 713         if (r->is_halted == NULL)
 714                 return oldriscv_halt(target);
 715         else
 716                 return riscv_openocd_halt(target);
 717 }
 718
 719 static int riscv_assert_reset(struct target *target)
 720 {
 721         struct target_type *tt = get_target_type(target);
 722         return tt->assert_reset(target);
 723 }
 724
 725 static int riscv_deassert_reset(struct target *target)
 726 {
 727         LOG_DEBUG("RISCV DEASSERT RESET");
 728         struct target_type *tt = get_target_type(target);
 729         return tt->deassert_reset(target);
 730 }
 731
 732
 733 static int oldriscv_resume(struct target *target, int current, uint32_t address,
 734                 int handle_breakpoints, int debug_execution)
 735 {
 736         struct target_type *tt = get_target_type(target);
 737         return tt->resume(target, current, address, handle_breakpoints,
 738                         debug_execution);
 739 }
 740
 741 static int old_or_new_riscv_resume(
 742                 struct target *target,
 743                 int current,
 744                 target_addr_t address,
 745                 int handle_breakpoints,
 746                 int debug_execution
 747 ){
 748         RISCV_INFO(r);
 749         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
 750         if (r->is_halted == NULL)
 751                 return oldriscv_resume(target, current, address, handle_breakpoints, debug_execution);
 752         else
 753                 return riscv_openocd_resume(target, current, address, handle_breakpoints, debug_execution);
 754 }
 755
 756 static int riscv_select_current_hart(struct target *target)
 757 {
 758         RISCV_INFO(r);
 759         if (r->rtos_hartid != -1 && riscv_rtos_enabled(target))
 760                 return riscv_set_current_hartid(target, r->rtos_hartid);
 761         else
 762                 return riscv_set_current_hartid(target, target->coreid);
 763 }
 764
 765 static int riscv_read_memory(struct target *target, target_addr_t address,
 766                 uint32_t size, uint32_t count, uint8_t *buffer)
 767 {
 768         if (riscv_select_current_hart(target) != ERROR_OK)
 769                 return ERROR_FAIL;
 770         struct target_type *tt = get_target_type(target);
 771         return tt->read_memory(target, address, size, count, buffer);
 772 }
 773
 774 static int riscv_write_memory(struct target *target, target_addr_t address,
 775                 uint32_t size, uint32_t count, const uint8_t *buffer)
 776 {
 777         if (riscv_select_current_hart(target) != ERROR_OK)
 778                 return ERROR_FAIL;
 779         struct target_type *tt = get_target_type(target);
 780         return tt->write_memory(target, address, size, count, buffer);
 781 }
 782
 783 static int riscv_get_gdb_reg_list(struct target *target,
 784                 struct reg **reg_list[], int *reg_list_size,
 785                 enum target_register_class reg_class)
 786 {
 787         RISCV_INFO(r);
 788         LOG_DEBUG("reg_class=%d", reg_class);
 789         LOG_DEBUG("rtos_hartid=%d current_hartid=%d", r->rtos_hartid, r->current_hartid);
 790
 791         if (!target->reg_cache) {
 792                 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
 793                 return ERROR_FAIL;
 794         }
 795
 796         if (riscv_select_current_hart(target) != ERROR_OK)
 797                 return ERROR_FAIL;
 798
 799         switch (reg_class) {
 800                 case REG_CLASS_GENERAL:
 801                         *reg_list_size = 32;
 802                         break;
 803                 case REG_CLASS_ALL:
 804                         *reg_list_size = GDB_REGNO_COUNT;
 805                         break;
 806                 default:
 807                         LOG_ERROR("Unsupported reg_class: %d", reg_class);
 808                         return ERROR_FAIL;
 809         }
 810
 811         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
 812         if (!*reg_list)
 813                 return ERROR_FAIL;
 814
 815         for (int i = 0; i < *reg_list_size; i++) {
 816                 assert(!target->reg_cache->reg_list[i].valid ||
 817                                 target->reg_cache->reg_list[i].size > 0);
 818                 (*reg_list)[i] = &target->reg_cache->reg_list[i];
 819         }
 820
 821         return ERROR_OK;
 822 }
 823
 824 static int riscv_arch_state(struct target *target)
 825 {
 826         struct target_type *tt = get_target_type(target);
 827         return tt->arch_state(target);
 828 }
 829
 830 /* Algorithm must end with a software breakpoint instruction. */
 831 static int riscv_run_algorithm(struct target *target, int num_mem_params,
 832                 struct mem_param *mem_params, int num_reg_params,
 833                 struct reg_param *reg_params, target_addr_t entry_point,
 834                 target_addr_t exit_point, int timeout_ms, void *arch_info)
 835 {
 836         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 837
 838         if (num_mem_params > 0) {
 839                 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
 840                 return ERROR_FAIL;
 841         }
 842
 843         if (target->state != TARGET_HALTED) {
 844                 LOG_WARNING("target not halted");
 845                 return ERROR_TARGET_NOT_HALTED;
 846         }
 847
 848         /* Save registers */
 849         struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", 1);
 850         if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
 851                 return ERROR_FAIL;
 852         uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
 853
 854         uint64_t saved_regs[32];
 855         for (int i = 0; i < num_reg_params; i++) {
 856                 if (mem_params[i].direction == PARAM_IN)
 857                         continue;
 858
 859                 LOG_DEBUG("save %s", reg_params[i].reg_name);
 860                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
 861                 if (!r) {
 862                         LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
 863                         return ERROR_FAIL;
 864                 }
 865
 866                 if (r->size != reg_params[i].size) {
 867                         LOG_ERROR("Register %s is %d bits instead of %d bits.",
 868                                         reg_params[i].reg_name, r->size, reg_params[i].size);
 869                         return ERROR_FAIL;
 870                 }
 871
 872                 if (r->number > GDB_REGNO_XPR31) {
 873                         LOG_ERROR("Only GPRs can be use as argument registers.");
 874                         return ERROR_FAIL;
 875                 }
 876
 877                 if (r->type->get(r) != ERROR_OK)
 878                         return ERROR_FAIL;
 879                 saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
 880                 if (r->type->set(r, reg_params[i].value) != ERROR_OK)
 881                         return ERROR_FAIL;
 882         }
 883
 884
 885         /* Disable Interrupts before attempting to run the algorithm. */
 886         uint64_t current_mstatus;
 887         uint8_t mstatus_bytes[8];
 888
 889         LOG_DEBUG("Disabling Interrupts");
 890         struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
 891                         "mstatus", 1);
 892         if (!reg_mstatus) {
 893                 LOG_ERROR("Couldn't find mstatus!");
 894                 return ERROR_FAIL;
 895         }
 896
 897         reg_mstatus->type->get(reg_mstatus);
 898         current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
 899         uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
 900         buf_set_u64(mstatus_bytes, 0, info->xlen[0], set_field(current_mstatus,
 901                                 ie_mask, 0));
 902
 903         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
 904
 905         /* Run algorithm */
 906         LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
 907         if (oldriscv_resume(target, 0, entry_point, 0, 0) != ERROR_OK)
 908                 return ERROR_FAIL;
 909
 910         int64_t start = timeval_ms();
 911         while (target->state != TARGET_HALTED) {
 912                 LOG_DEBUG("poll()");
 913                 int64_t now = timeval_ms();
 914                 if (now - start > timeout_ms) {
 915                         LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms);
 916                         LOG_ERROR("  now   = 0x%08x", (uint32_t) now);
 917                         LOG_ERROR("  start = 0x%08x", (uint32_t) start);
 918                         oldriscv_halt(target);
 919                         old_or_new_riscv_poll(target);
 920                         return ERROR_TARGET_TIMEOUT;
 921                 }
 922
 923                 int result = old_or_new_riscv_poll(target);
 924                 if (result != ERROR_OK)
 925                         return result;
 926         }
 927
 928         if (reg_pc->type->get(reg_pc) != ERROR_OK)
 929                 return ERROR_FAIL;
 930         uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
 931         if (final_pc != exit_point) {
 932                 LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
 933                                 TARGET_PRIxADDR, final_pc, exit_point);
 934                 return ERROR_FAIL;
 935         }
 936
 937         /* Restore Interrupts */
 938         LOG_DEBUG("Restoring Interrupts");
 939         buf_set_u64(mstatus_bytes, 0, info->xlen[0], current_mstatus);
 940         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
 941
 942         /* Restore registers */
 943         uint8_t buf[8];
 944         buf_set_u64(buf, 0, info->xlen[0], saved_pc);
 945         if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
 946                 return ERROR_FAIL;
 947
 948         for (int i = 0; i < num_reg_params; i++) {
 949                 LOG_DEBUG("restore %s", reg_params[i].reg_name);
 950                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
 951                 buf_set_u64(buf, 0, info->xlen[0], saved_regs[r->number]);
 952                 if (r->type->set(r, buf) != ERROR_OK)
 953                         return ERROR_FAIL;
 954         }
 955
 956         return ERROR_OK;
 957 }
 958
 959 /* Should run code on the target to perform CRC of
 960 memory. Not yet implemented.
 961 */
 962
 963 static int riscv_checksum_memory(struct target *target,
 964                 target_addr_t address, uint32_t count,
 965                 uint32_t *checksum)
 966 {
 967         *checksum = 0xFFFFFFFF;
 968         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 969 }
 970
 971 /*** OpenOCD Helper Functions ***/
 972
 973 enum riscv_poll_hart {
 974         RPH_NO_CHANGE,
 975         RPH_DISCOVERED_HALTED,
 976         RPH_DISCOVERED_RUNNING,
 977         RPH_ERROR
 978 };
 979 static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
 980 {
 981         RISCV_INFO(r);
 982         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
 983                 return RPH_ERROR;
 984
 985         LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
 986
 987         /* If OpenOCD thinks we're running but this hart is halted then it's time
 988          * to raise an event. */
 989         bool halted = riscv_is_halted(target);
 990         if (target->state != TARGET_HALTED && halted) {
 991                 LOG_DEBUG("  triggered a halt");
 992                 r->on_halt(target);
 993                 return RPH_DISCOVERED_HALTED;
 994         } else if (target->state != TARGET_RUNNING && !halted) {
 995                 LOG_DEBUG("  triggered running");
 996                 target->state = TARGET_RUNNING;
 997                 return RPH_DISCOVERED_RUNNING;
 998         }
 999
1000         return RPH_NO_CHANGE;
1001 }
1002
1003 /*** OpenOCD Interface ***/
1004 int riscv_openocd_poll(struct target *target)
1005 {
1006         LOG_DEBUG("polling all harts");
1007         int halted_hart = -1;
1008         if (riscv_rtos_enabled(target)) {
1009                 /* Check every hart for an event. */
1010                 for (int i = 0; i < riscv_count_harts(target); ++i) {
1011                         enum riscv_poll_hart out = riscv_poll_hart(target, i);
1012                         switch (out) {
1013                         case RPH_NO_CHANGE:
1014                         case RPH_DISCOVERED_RUNNING:
1015                                 continue;
1016                         case RPH_DISCOVERED_HALTED:
1017                                 halted_hart = i;
1018                                 break;
1019                         case RPH_ERROR:
1020                                 return ERROR_FAIL;
1021                         }
1022                 }
1023                 if (halted_hart == -1) {
1024                         LOG_DEBUG("  no harts just halted, target->state=%d", target->state);
1025                         return ERROR_OK;
1026                 }
1027                 LOG_DEBUG("  hart %d halted", halted_hart);
1028
1029                 /* If we're here then at least one hart triggered.  That means
1030                  * we want to go and halt _every_ hart in the system, as that's
1031                  * the invariant we hold here.  Some harts might have already
1032                  * halted (as we're either in single-step mode or they also
1033                  * triggered a breakpoint), so don't attempt to halt those
1034                  * harts. */
1035                 for (int i = 0; i < riscv_count_harts(target); ++i)
1036                         riscv_halt_one_hart(target, i);
1037         } else {
1038                 enum riscv_poll_hart out = riscv_poll_hart(target,
1039                                 riscv_current_hartid(target));
1040                 if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING)
1041                         return ERROR_OK;
1042                 else if (out == RPH_ERROR)
1043                         return ERROR_FAIL;
1044
1045                 halted_hart = riscv_current_hartid(target);
1046                 LOG_DEBUG("  hart %d halted", halted_hart);
1047         }
1048
1049         target->state = TARGET_HALTED;
1050         switch (riscv_halt_reason(target, halted_hart)) {
1051         case RISCV_HALT_BREAKPOINT:
1052                 target->debug_reason = DBG_REASON_BREAKPOINT;
1053                 break;
1054         case RISCV_HALT_TRIGGER:
1055                 target->debug_reason = DBG_REASON_WATCHPOINT;
1056                 break;
1057         case RISCV_HALT_INTERRUPT:
1058                 target->debug_reason = DBG_REASON_DBGRQ;
1059                 break;
1060         case RISCV_HALT_SINGLESTEP:
1061                 target->debug_reason = DBG_REASON_SINGLESTEP;
1062                 break;
1063         case RISCV_HALT_UNKNOWN:
1064                 target->debug_reason = DBG_REASON_UNDEFINED;
1065                 break;
1066         case RISCV_HALT_ERROR:
1067                 return ERROR_FAIL;
1068         }
1069
1070         if (riscv_rtos_enabled(target)) {
1071                 target->rtos->current_threadid = halted_hart + 1;
1072                 target->rtos->current_thread = halted_hart + 1;
1073         }
1074
1075         target->state = TARGET_HALTED;
1076
1077         if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1078                 int retval;
1079                 if (riscv_semihosting(target, &retval) != 0)
1080                         return retval;
1081         }
1082
1083         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1084         return ERROR_OK;
1085 }
1086
1087 int riscv_openocd_halt(struct target *target)
1088 {
1089         RISCV_INFO(r);
1090
1091         LOG_DEBUG("halting all harts");
1092
1093         int out = riscv_halt_all_harts(target);
1094         if (out != ERROR_OK) {
1095                 LOG_ERROR("Unable to halt all harts");
1096                 return out;
1097         }
1098
1099         register_cache_invalidate(target->reg_cache);
1100         if (riscv_rtos_enabled(target)) {
1101                 target->rtos->current_threadid = r->rtos_hartid + 1;
1102                 target->rtos->current_thread = r->rtos_hartid + 1;
1103         }
1104
1105         target->state = TARGET_HALTED;
1106         target->debug_reason = DBG_REASON_DBGRQ;
1107         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1108         return out;
1109 }
1110
1111 int riscv_openocd_resume(
1112                 struct target *target,
1113                 int current,
1114                 target_addr_t address,
1115                 int handle_breakpoints,
1116                 int debug_execution)
1117 {
1118         LOG_DEBUG("debug_reason=%d", target->debug_reason);
1119
1120         if (!current)
1121                 riscv_set_register(target, GDB_REGNO_PC, address);
1122
1123         if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1124                 /* To be able to run off a trigger, disable all the triggers, step, and
1125                  * then resume as usual. */
1126                 struct watchpoint *watchpoint = target->watchpoints;
1127                 bool trigger_temporarily_cleared[RISCV_MAX_HWBPS] = {0};
1128
1129                 int i = 0;
1130                 int result = ERROR_OK;
1131                 while (watchpoint && result == ERROR_OK) {
1132                         LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set);
1133                         trigger_temporarily_cleared[i] = watchpoint->set;
1134                         if (watchpoint->set)
1135                                 result = riscv_remove_watchpoint(target, watchpoint);
1136                         watchpoint = watchpoint->next;
1137                         i++;
1138                 }
1139
1140                 if (result == ERROR_OK)
1141                         result = riscv_step_rtos_hart(target);
1142
1143                 watchpoint = target->watchpoints;
1144                 i = 0;
1145                 while (watchpoint) {
1146                         LOG_DEBUG("watchpoint %d: cleared=%d", i, trigger_temporarily_cleared[i]);
1147                         if (trigger_temporarily_cleared[i]) {
1148                                 if (result == ERROR_OK)
1149                                         result = riscv_add_watchpoint(target, watchpoint);
1150                                 else
1151                                         riscv_add_watchpoint(target, watchpoint);
1152                         }
1153                         watchpoint = watchpoint->next;
1154                         i++;
1155                 }
1156
1157                 if (result != ERROR_OK)
1158                         return result;
1159         }
1160
1161         int out = riscv_resume_all_harts(target);
1162         if (out != ERROR_OK) {
1163                 LOG_ERROR("unable to resume all harts");
1164                 return out;
1165         }
1166
1167         register_cache_invalidate(target->reg_cache);
1168         target->state = TARGET_RUNNING;
1169         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1170         return out;
1171 }
1172
1173 int riscv_openocd_step(
1174                 struct target *target,
1175                 int current,
1176                 target_addr_t address,
1177                 int handle_breakpoints
1178 ) {
1179         LOG_DEBUG("stepping rtos hart");
1180
1181         if (!current)
1182                 riscv_set_register(target, GDB_REGNO_PC, address);
1183
1184         int out = riscv_step_rtos_hart(target);
1185         if (out != ERROR_OK) {
1186                 LOG_ERROR("unable to step rtos hart");
1187                 return out;
1188         }
1189
1190         register_cache_invalidate(target->reg_cache);
1191         target->state = TARGET_RUNNING;
1192         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1193         target->state = TARGET_HALTED;
1194         target->debug_reason = DBG_REASON_SINGLESTEP;
1195         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1196         return out;
1197 }
1198
1199 /* Command Handlers */
1200 COMMAND_HANDLER(riscv_set_command_timeout_sec)
1201 {
1202         if (CMD_ARGC != 1) {
1203                 LOG_ERROR("Command takes exactly 1 parameter");
1204                 return ERROR_COMMAND_SYNTAX_ERROR;
1205         }
1206         int timeout = atoi(CMD_ARGV[0]);
1207         if (timeout <= 0) {
1208                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
1209                 return ERROR_FAIL;
1210         }
1211
1212         riscv_command_timeout_sec = timeout;
1213
1214         return ERROR_OK;
1215 }
1216
1217 COMMAND_HANDLER(riscv_set_reset_timeout_sec)
1218 {
1219         if (CMD_ARGC != 1) {
1220                 LOG_ERROR("Command takes exactly 1 parameter");
1221                 return ERROR_COMMAND_SYNTAX_ERROR;
1222         }
1223         int timeout = atoi(CMD_ARGV[0]);
1224         if (timeout <= 0) {
1225                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
1226                 return ERROR_FAIL;
1227         }
1228
1229         riscv_reset_timeout_sec = timeout;
1230         return ERROR_OK;
1231 }
1232
1233 COMMAND_HANDLER(riscv_set_prefer_sba)
1234 {
1235         if (CMD_ARGC != 1) {
1236                 LOG_ERROR("Command takes exactly 1 parameter");
1237                 return ERROR_COMMAND_SYNTAX_ERROR;
1238         }
1239         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_prefer_sba);
1240         return ERROR_OK;
1241 }
1242
1243 void parse_error(const char *string, char c, unsigned position)
1244 {
1245         char buf[position+2];
1246         for (unsigned i = 0; i < position; i++)
1247                 buf[i] = ' ';
1248         buf[position] = '^';
1249         buf[position + 1] = 0;
1250
1251         LOG_ERROR("Parse error at character %c in:", c);
1252         LOG_ERROR("%s", string);
1253         LOG_ERROR("%s", buf);
1254 }
1255
1256 COMMAND_HANDLER(riscv_set_expose_csrs)
1257 {
1258         if (CMD_ARGC != 1) {
1259                 LOG_ERROR("Command takes exactly 1 parameter");
1260                 return ERROR_COMMAND_SYNTAX_ERROR;
1261         }
1262
1263         for (unsigned pass = 0; pass < 2; pass++) {
1264                 unsigned range = 0;
1265                 unsigned low = 0;
1266                 bool parse_low = true;
1267                 unsigned high = 0;
1268                 for (unsigned i = 0; i == 0 || CMD_ARGV[0][i-1]; i++) {
1269                         char c = CMD_ARGV[0][i];
1270                         if (isspace(c)) {
1271                                 /* Ignore whitespace. */
1272                                 continue;
1273                         }
1274
1275                         if (parse_low) {
1276                                 if (isdigit(c)) {
1277                                         low *= 10;
1278                                         low += c - '0';
1279                                 } else if (c == '-') {
1280                                         parse_low = false;
1281                                 } else if (c == ',' || c == 0) {
1282                                         if (pass == 1) {
1283                                                 expose_csr[range].low = low;
1284                                                 expose_csr[range].high = low;
1285                                         }
1286                                         low = 0;
1287                                         range++;
1288                                 } else {
1289                                         parse_error(CMD_ARGV[0], c, i);
1290                                         return ERROR_COMMAND_SYNTAX_ERROR;
1291                                 }
1292
1293                         } else {
1294                                 if (isdigit(c)) {
1295                                         high *= 10;
1296                                         high += c - '0';
1297                                 } else if (c == ',' || c == 0) {
1298                                         parse_low = true;
1299                                         if (pass == 1) {
1300                                                 expose_csr[range].low = low;
1301                                                 expose_csr[range].high = high;
1302                                         }
1303                                         low = 0;
1304                                         high = 0;
1305                                         range++;
1306                                 } else {
1307                                         parse_error(CMD_ARGV[0], c, i);
1308                                         return ERROR_COMMAND_SYNTAX_ERROR;
1309                                 }
1310                         }
1311                 }
1312
1313                 if (pass == 0) {
1314                         if (expose_csr)
1315                                 free(expose_csr);
1316                         expose_csr = calloc(range + 2, sizeof(*expose_csr));
1317                 } else {
1318                         expose_csr[range].low = 1;
1319                         expose_csr[range].high = 0;
1320                 }
1321         }
1322         return ERROR_OK;
1323 }
1324
1325 COMMAND_HANDLER(riscv_authdata_read)
1326 {
1327         if (CMD_ARGC != 0) {
1328                 LOG_ERROR("Command takes no parameters");
1329                 return ERROR_COMMAND_SYNTAX_ERROR;
1330         }
1331
1332         struct target *target = get_current_target(CMD_CTX);
1333         if (!target) {
1334                 LOG_ERROR("target is NULL!");
1335                 return ERROR_FAIL;
1336         }
1337
1338         RISCV_INFO(r);
1339         if (!r) {
1340                 LOG_ERROR("riscv_info is NULL!");
1341                 return ERROR_FAIL;
1342         }
1343
1344         if (r->authdata_read) {
1345                 uint32_t value;
1346                 if (r->authdata_read(target, &value) != ERROR_OK)
1347                         return ERROR_FAIL;
1348                 command_print(CMD_CTX, "0x%" PRIx32, value);
1349                 return ERROR_OK;
1350         } else {
1351                 LOG_ERROR("authdata_read is not implemented for this target.");
1352                 return ERROR_FAIL;
1353         }
1354 }
1355
1356 COMMAND_HANDLER(riscv_authdata_write)
1357 {
1358         if (CMD_ARGC != 1) {
1359                 LOG_ERROR("Command takes exactly 1 argument");
1360                 return ERROR_COMMAND_SYNTAX_ERROR;
1361         }
1362
1363         struct target *target = get_current_target(CMD_CTX);
1364         RISCV_INFO(r);
1365
1366         uint32_t value;
1367         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
1368
1369         if (r->authdata_write) {
1370                 return r->authdata_write(target, value);
1371         } else {
1372                 LOG_ERROR("authdata_write is not implemented for this target.");
1373                 return ERROR_FAIL;
1374         }
1375 }
1376
1377 COMMAND_HANDLER(riscv_dmi_read)
1378 {
1379         if (CMD_ARGC != 1) {
1380                 LOG_ERROR("Command takes 1 parameter");
1381                 return ERROR_COMMAND_SYNTAX_ERROR;
1382         }
1383
1384         struct target *target = get_current_target(CMD_CTX);
1385         if (!target) {
1386                 LOG_ERROR("target is NULL!");
1387                 return ERROR_FAIL;
1388         }
1389
1390         RISCV_INFO(r);
1391         if (!r) {
1392                 LOG_ERROR("riscv_info is NULL!");
1393                 return ERROR_FAIL;
1394         }
1395
1396         if (r->dmi_read) {
1397                 uint32_t address, value;
1398                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1399                 if (r->dmi_read(target, &value, address) != ERROR_OK)
1400                         return ERROR_FAIL;
1401                 command_print(CMD_CTX, "0x%" PRIx32, value);
1402                 return ERROR_OK;
1403         } else {
1404                 LOG_ERROR("dmi_read is not implemented for this target.");
1405                 return ERROR_FAIL;
1406         }
1407 }
1408
1409
1410 COMMAND_HANDLER(riscv_dmi_write)
1411 {
1412         if (CMD_ARGC != 2) {
1413                 LOG_ERROR("Command takes exactly 2 arguments");
1414                 return ERROR_COMMAND_SYNTAX_ERROR;
1415         }
1416
1417         struct target *target = get_current_target(CMD_CTX);
1418         RISCV_INFO(r);
1419
1420         uint32_t address, value;
1421         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1422         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1423
1424         if (r->dmi_write) {
1425                 return r->dmi_write(target, address, value);
1426         } else {
1427                 LOG_ERROR("dmi_write is not implemented for this target.");
1428                 return ERROR_FAIL;
1429         }
1430 }
1431
1432 static const struct command_registration riscv_exec_command_handlers[] = {
1433         {
1434                 .name = "set_command_timeout_sec",
1435                 .handler = riscv_set_command_timeout_sec,
1436                 .mode = COMMAND_ANY,
1437                 .usage = "riscv set_command_timeout_sec [sec]",
1438                 .help = "Set the wall-clock timeout (in seconds) for individual commands"
1439         },
1440         {
1441                 .name = "set_reset_timeout_sec",
1442                 .handler = riscv_set_reset_timeout_sec,
1443                 .mode = COMMAND_ANY,
1444                 .usage = "riscv set_reset_timeout_sec [sec]",
1445                 .help = "Set the wall-clock timeout (in seconds) after reset is deasserted"
1446         },
1447         {
1448                 .name = "set_prefer_sba",
1449                 .handler = riscv_set_prefer_sba,
1450                 .mode = COMMAND_ANY,
1451                 .usage = "riscv set_prefer_sba on|off",
1452                 .help = "When on, prefer to use System Bus Access to access memory. "
1453                         "When off, prefer to use the Program Buffer to access memory."
1454         },
1455         {
1456                 .name = "expose_csrs",
1457                 .handler = riscv_set_expose_csrs,
1458                 .mode = COMMAND_ANY,
1459                 .usage = "riscv expose_csrs n0[-m0][,n1[-m1]]...",
1460                 .help = "Configure a list of inclusive ranges for CSRs to expose in "
1461                                 "addition to the standard ones. This must be executed before "
1462                                 "`init`."
1463         },
1464         {
1465                 .name = "authdata_read",
1466                 .handler = riscv_authdata_read,
1467                 .mode = COMMAND_ANY,
1468                 .usage = "riscv authdata_read",
1469                 .help = "Return the 32-bit value read from authdata."
1470         },
1471         {
1472                 .name = "authdata_write",
1473                 .handler = riscv_authdata_write,
1474                 .mode = COMMAND_ANY,
1475                 .usage = "riscv authdata_write value",
1476                 .help = "Write the 32-bit value to authdata."
1477         },
1478         {
1479                 .name = "dmi_read",
1480                 .handler = riscv_dmi_read,
1481                 .mode = COMMAND_ANY,
1482                 .usage = "riscv dmi_read address",
1483                 .help = "Perform a 32-bit DMI read at address, returning the value."
1484         },
1485         {
1486                 .name = "dmi_write",
1487                 .handler = riscv_dmi_write,
1488                 .mode = COMMAND_ANY,
1489                 .usage = "riscv dmi_write address value",
1490                 .help = "Perform a 32-bit DMI write of value at address."
1491         },
1492         COMMAND_REGISTRATION_DONE
1493 };
1494
1495 extern __COMMAND_HANDLER(handle_common_semihosting_command);
1496 extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command);
1497 extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command);
1498 extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
1499
1500 /*
1501  * To be noted that RISC-V targets use the same semihosting commands as
1502  * ARM targets.
1503  *
1504  * The main reason is compatibility with existing tools. For example the
1505  * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
1506  * configure semihosting, which generate commands like `arm semihosting
1507  * enable`.
1508  * A secondary reason is the fact that the protocol used is exactly the
1509  * one specified by ARM. If RISC-V will ever define its own semihosting
1510  * protocol, then a command like `riscv semihosting enable` will make
1511  * sense, but for now all semihosting commands are prefixed with `arm`.
1512  */
1513 static const struct command_registration arm_exec_command_handlers[] = {
1514         {
1515                 "semihosting",
1516                 .handler = handle_common_semihosting_command,
1517                 .mode = COMMAND_EXEC,
1518                 .usage = "['enable'|'disable']",
1519                 .help = "activate support for semihosting operations",
1520         },
1521         {
1522                 "semihosting_cmdline",
1523                 .handler = handle_common_semihosting_cmdline,
1524                 .mode = COMMAND_EXEC,
1525                 .usage = "arguments",
1526                 .help = "command line arguments to be passed to program",
1527         },
1528         {
1529                 "semihosting_fileio",
1530                 .handler = handle_common_semihosting_fileio_command,
1531                 .mode = COMMAND_EXEC,
1532                 .usage = "['enable'|'disable']",
1533                 .help = "activate support for semihosting fileio operations",
1534         },
1535         {
1536                 "semihosting_resexit",
1537                 .handler = handle_common_semihosting_resumable_exit_command,
1538                 .mode = COMMAND_EXEC,
1539                 .usage = "['enable'|'disable']",
1540                 .help = "activate support for semihosting resumable exit",
1541         },
1542         COMMAND_REGISTRATION_DONE
1543 };
1544
1545 const struct command_registration riscv_command_handlers[] = {
1546         {
1547                 .name = "riscv",
1548                 .mode = COMMAND_ANY,
1549                 .help = "RISC-V Command Group",
1550                 .usage = "",
1551                 .chain = riscv_exec_command_handlers
1552         },
1553         {
1554                 .name = "arm",
1555                 .mode = COMMAND_ANY,
1556                 .help = "ARM Command Group",
1557                 .usage = "",
1558                 .chain = arm_exec_command_handlers
1559         },
1560         COMMAND_REGISTRATION_DONE
1561 };
1562
1563 unsigned riscv_address_bits(struct target *target)
1564 {
1565         return riscv_xlen(target);
1566 }
1567
1568 struct target_type riscv_target = {
1569         .name = "riscv",
1570
1571         .init_target = riscv_init_target,
1572         .deinit_target = riscv_deinit_target,
1573         .examine = riscv_examine,
1574
1575         /* poll current target status */
1576         .poll = old_or_new_riscv_poll,
1577
1578         .halt = old_or_new_riscv_halt,
1579         .resume = old_or_new_riscv_resume,
1580         .step = old_or_new_riscv_step,
1581
1582         .assert_reset = riscv_assert_reset,
1583         .deassert_reset = riscv_deassert_reset,
1584
1585         .read_memory = riscv_read_memory,
1586         .write_memory = riscv_write_memory,
1587
1588         .checksum_memory = riscv_checksum_memory,
1589
1590         .get_gdb_reg_list = riscv_get_gdb_reg_list,
1591
1592         .add_breakpoint = riscv_add_breakpoint,
1593         .remove_breakpoint = riscv_remove_breakpoint,
1594
1595         .add_watchpoint = riscv_add_watchpoint,
1596         .remove_watchpoint = riscv_remove_watchpoint,
1597
1598         .arch_state = riscv_arch_state,
1599
1600         .run_algorithm = riscv_run_algorithm,
1601
1602         .commands = riscv_command_handlers,
1603
1604         .address_bits = riscv_address_bits
1605 };
1606
1607 /*** RISC-V Interface ***/
1608
1609 void riscv_info_init(struct target *target, riscv_info_t *r)
1610 {
1611         memset(r, 0, sizeof(*r));
1612         r->dtm_version = 1;
1613         r->registers_initialized = false;
1614         r->current_hartid = target->coreid;
1615
1616         memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
1617
1618         for (size_t h = 0; h < RISCV_MAX_HARTS; ++h) {
1619                 r->xlen[h] = -1;
1620
1621                 for (size_t e = 0; e < RISCV_MAX_REGISTERS; ++e)
1622                         r->valid_saved_registers[h][e] = false;
1623         }
1624 }
1625
1626 int riscv_halt_all_harts(struct target *target)
1627 {
1628         for (int i = 0; i < riscv_count_harts(target); ++i) {
1629                 if (!riscv_hart_enabled(target, i))
1630                         continue;
1631
1632                 riscv_halt_one_hart(target, i);
1633         }
1634
1635         return ERROR_OK;
1636 }
1637
1638 int riscv_halt_one_hart(struct target *target, int hartid)
1639 {
1640         RISCV_INFO(r);
1641         LOG_DEBUG("halting hart %d", hartid);
1642         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1643                 return ERROR_FAIL;
1644         if (riscv_is_halted(target)) {
1645                 LOG_DEBUG("  hart %d requested halt, but was already halted", hartid);
1646                 return ERROR_OK;
1647         }
1648
1649         return r->halt_current_hart(target);
1650 }
1651
1652 int riscv_resume_all_harts(struct target *target)
1653 {
1654         for (int i = 0; i < riscv_count_harts(target); ++i) {
1655                 if (!riscv_hart_enabled(target, i))
1656                         continue;
1657
1658                 riscv_resume_one_hart(target, i);
1659         }
1660
1661         riscv_invalidate_register_cache(target);
1662         return ERROR_OK;
1663 }
1664
1665 int riscv_resume_one_hart(struct target *target, int hartid)
1666 {
1667         RISCV_INFO(r);
1668         LOG_DEBUG("resuming hart %d", hartid);
1669         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1670                 return ERROR_FAIL;
1671         if (!riscv_is_halted(target)) {
1672                 LOG_DEBUG("  hart %d requested resume, but was already resumed", hartid);
1673                 return ERROR_OK;
1674         }
1675
1676         r->on_resume(target);
1677         return r->resume_current_hart(target);
1678 }
1679
1680 int riscv_step_rtos_hart(struct target *target)
1681 {
1682         RISCV_INFO(r);
1683         int hartid = r->current_hartid;
1684         if (riscv_rtos_enabled(target)) {
1685                 hartid = r->rtos_hartid;
1686                 if (hartid == -1) {
1687                         LOG_USER("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
1688                         hartid = 0;
1689                 }
1690         }
1691         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1692                 return ERROR_FAIL;
1693         LOG_DEBUG("stepping hart %d", hartid);
1694
1695         if (!riscv_is_halted(target)) {
1696                 LOG_ERROR("Hart isn't halted before single step!");
1697                 return ERROR_FAIL;
1698         }
1699         riscv_invalidate_register_cache(target);
1700         r->on_step(target);
1701         if (r->step_current_hart(target) != ERROR_OK)
1702                 return ERROR_FAIL;
1703         riscv_invalidate_register_cache(target);
1704         r->on_halt(target);
1705         if (!riscv_is_halted(target)) {
1706                 LOG_ERROR("Hart was not halted after single step!");
1707                 return ERROR_FAIL;
1708         }
1709         return ERROR_OK;
1710 }
1711
1712 bool riscv_supports_extension(struct target *target, int hartid, char letter)
1713 {
1714         RISCV_INFO(r);
1715         unsigned num;
1716         if (letter >= 'a' && letter <= 'z')
1717                 num = letter - 'a';
1718         else if (letter >= 'A' && letter <= 'Z')
1719                 num = letter - 'A';
1720         else
1721                 return false;
1722         return r->misa[hartid] & (1 << num);
1723 }
1724
1725 int riscv_xlen(const struct target *target)
1726 {
1727         return riscv_xlen_of_hart(target, riscv_current_hartid(target));
1728 }
1729
1730 int riscv_xlen_of_hart(const struct target *target, int hartid)
1731 {
1732         RISCV_INFO(r);
1733         assert(r->xlen[hartid] != -1);
1734         return r->xlen[hartid];
1735 }
1736
1737 bool riscv_rtos_enabled(const struct target *target)
1738 {
1739         return target->rtos != NULL;
1740 }
1741
1742 int riscv_set_current_hartid(struct target *target, int hartid)
1743 {
1744         RISCV_INFO(r);
1745         if (!r->select_current_hart)
1746                 return ERROR_OK;
1747
1748         int previous_hartid = riscv_current_hartid(target);
1749         r->current_hartid = hartid;
1750         assert(riscv_hart_enabled(target, hartid));
1751         LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
1752         if (r->select_current_hart(target) != ERROR_OK)
1753                 return ERROR_FAIL;
1754
1755         /* This might get called during init, in which case we shouldn't be
1756          * setting up the register cache. */
1757         if (!target_was_examined(target))
1758                 return ERROR_OK;
1759
1760         /* Avoid invalidating the register cache all the time. */
1761         if (r->registers_initialized
1762                         && (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
1763                         && target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target)
1764                         && (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
1765                 return ERROR_OK;
1766         } else
1767                 LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target));
1768
1769         riscv_invalidate_register_cache(target);
1770         return ERROR_OK;
1771 }
1772
1773 void riscv_invalidate_register_cache(struct target *target)
1774 {
1775         RISCV_INFO(r);
1776
1777         register_cache_invalidate(target->reg_cache);
1778         for (size_t i = 0; i < GDB_REGNO_COUNT; ++i) {
1779                 struct reg *reg = &target->reg_cache->reg_list[i];
1780                 reg->valid = false;
1781         }
1782
1783         r->registers_initialized = true;
1784 }
1785
1786 int riscv_current_hartid(const struct target *target)
1787 {
1788         RISCV_INFO(r);
1789         return r->current_hartid;
1790 }
1791
1792 void riscv_set_all_rtos_harts(struct target *target)
1793 {
1794         RISCV_INFO(r);
1795         r->rtos_hartid = -1;
1796 }
1797
1798 void riscv_set_rtos_hartid(struct target *target, int hartid)
1799 {
1800         LOG_DEBUG("setting RTOS hartid %d", hartid);
1801         RISCV_INFO(r);
1802         r->rtos_hartid = hartid;
1803 }
1804
1805 int riscv_count_harts(struct target *target)
1806 {
1807         if (target == NULL)
1808                 return 1;
1809         RISCV_INFO(r);
1810         if (r == NULL)
1811                 return 1;
1812         return r->hart_count;
1813 }
1814
1815 bool riscv_has_register(struct target *target, int hartid, int regid)
1816 {
1817         return 1;
1818 }
1819
1820 /**
1821  * This function is called when the debug user wants to change the value of a
1822  * register. The new value may be cached, and may not be written until the hart
1823  * is resumed. */
1824 int riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v)
1825 {
1826         return riscv_set_register_on_hart(target, riscv_current_hartid(target), r, v);
1827 }
1828
1829 int riscv_set_register_on_hart(struct target *target, int hartid,
1830                 enum gdb_regno regid, uint64_t value)
1831 {
1832         RISCV_INFO(r);
1833         LOG_DEBUG("[%d] %s <- %" PRIx64, hartid, gdb_regno_name(regid), value);
1834         assert(r->set_register);
1835         return r->set_register(target, hartid, regid, value);
1836 }
1837
1838 int riscv_get_register(struct target *target, riscv_reg_t *value,
1839                 enum gdb_regno r)
1840 {
1841         return riscv_get_register_on_hart(target, value,
1842                         riscv_current_hartid(target), r);
1843 }
1844
1845 int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
1846                 int hartid, enum gdb_regno regid)
1847 {
1848         RISCV_INFO(r);
1849         int result = r->get_register(target, value, hartid, regid);
1850         LOG_DEBUG("[%d] %s: %" PRIx64, hartid, gdb_regno_name(regid), *value);
1851         return result;
1852 }
1853
1854 bool riscv_is_halted(struct target *target)
1855 {
1856         RISCV_INFO(r);
1857         assert(r->is_halted);
1858         return r->is_halted(target);
1859 }
1860
1861 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
1862 {
1863         RISCV_INFO(r);
1864         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1865                 return RISCV_HALT_ERROR;
1866         if (!riscv_is_halted(target)) {
1867                 LOG_ERROR("Hart is not halted!");
1868                 return RISCV_HALT_UNKNOWN;
1869         }
1870         return r->halt_reason(target);
1871 }
1872
1873 size_t riscv_debug_buffer_size(struct target *target)
1874 {
1875         RISCV_INFO(r);
1876         return r->debug_buffer_size[riscv_current_hartid(target)];
1877 }
1878
1879 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
1880 {
1881         RISCV_INFO(r);
1882         r->write_debug_buffer(target, index, insn);
1883         return ERROR_OK;
1884 }
1885
1886 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
1887 {
1888         RISCV_INFO(r);
1889         return r->read_debug_buffer(target, index);
1890 }
1891
1892 int riscv_execute_debug_buffer(struct target *target)
1893 {
1894         RISCV_INFO(r);
1895         return r->execute_debug_buffer(target);
1896 }
1897
1898 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
1899 {
1900         RISCV_INFO(r);
1901         r->fill_dmi_write_u64(target, buf, a, d);
1902 }
1903
1904 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
1905 {
1906         RISCV_INFO(r);
1907         r->fill_dmi_read_u64(target, buf, a);
1908 }
1909
1910 void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
1911 {
1912         RISCV_INFO(r);
1913         r->fill_dmi_nop_u64(target, buf);
1914 }
1915
1916 int riscv_dmi_write_u64_bits(struct target *target)
1917 {
1918         RISCV_INFO(r);
1919         return r->dmi_write_u64_bits(target);
1920 }
1921
1922 bool riscv_hart_enabled(struct target *target, int hartid)
1923 {
1924         /* FIXME: Add a hart mask to the RTOS. */
1925         if (riscv_rtos_enabled(target))
1926                 return hartid < riscv_count_harts(target);
1927
1928         return hartid == target->coreid;
1929 }
1930
1931 /**
1932  * Count triggers, and initialize trigger_count for each hart.
1933  * trigger_count is initialized even if this function fails to discover
1934  * something.
1935  * Disable any hardware triggers that have dmode set. We can't have set them
1936  * ourselves. Maybe they're left over from some killed debug session.
1937  * */
1938 int riscv_enumerate_triggers(struct target *target)
1939 {
1940         RISCV_INFO(r);
1941
1942         if (r->triggers_enumerated)
1943                 return ERROR_OK;
1944
1945         r->triggers_enumerated = true;  /* At the very least we tried. */
1946
1947         for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
1948                 if (!riscv_hart_enabled(target, hartid))
1949                         continue;
1950
1951                 riscv_reg_t tselect;
1952                 int result = riscv_get_register_on_hart(target, &tselect, hartid,
1953                                 GDB_REGNO_TSELECT);
1954                 if (result != ERROR_OK)
1955                         return result;
1956
1957                 for (unsigned t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
1958                         r->trigger_count[hartid] = t;
1959
1960                         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, t);
1961                         uint64_t tselect_rb;
1962                         result = riscv_get_register_on_hart(target, &tselect_rb, hartid,
1963                                         GDB_REGNO_TSELECT);
1964                         if (result != ERROR_OK)
1965                                 return result;
1966                         /* Mask off the top bit, which is used as tdrmode in old
1967                          * implementations. */
1968                         tselect_rb &= ~(1ULL << (riscv_xlen(target)-1));
1969                         if (tselect_rb != t)
1970                                 break;
1971                         uint64_t tdata1;
1972                         result = riscv_get_register_on_hart(target, &tdata1, hartid,
1973                                         GDB_REGNO_TDATA1);
1974                         if (result != ERROR_OK)
1975                                 return result;
1976
1977                         int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
1978                         switch (type) {
1979                                 case 1:
1980                                         /* On these older cores we don't support software using
1981                                          * triggers. */
1982                                         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
1983                                         break;
1984                                 case 2:
1985                                         if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
1986                                                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
1987                                         break;
1988                         }
1989                 }
1990
1991                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
1992
1993                 LOG_INFO("[%d] Found %d triggers", hartid, r->trigger_count[hartid]);
1994         }
1995
1996         return ERROR_OK;
1997 }
1998
1999 const char *gdb_regno_name(enum gdb_regno regno)
2000 {
2001         static char buf[32];
2002
2003         switch (regno) {
2004                 case GDB_REGNO_ZERO:
2005                         return "zero";
2006                 case GDB_REGNO_S0:
2007                         return "s0";
2008                 case GDB_REGNO_S1:
2009                         return "s1";
2010                 case GDB_REGNO_PC:
2011                         return "pc";
2012                 case GDB_REGNO_FPR0:
2013                         return "fpr0";
2014                 case GDB_REGNO_FPR31:
2015                         return "fpr31";
2016                 case GDB_REGNO_CSR0:
2017                         return "csr0";
2018                 case GDB_REGNO_TSELECT:
2019                         return "tselect";
2020                 case GDB_REGNO_TDATA1:
2021                         return "tdata1";
2022                 case GDB_REGNO_TDATA2:
2023                         return "tdata2";
2024                 case GDB_REGNO_MISA:
2025                         return "misa";
2026                 case GDB_REGNO_DPC:
2027                         return "dpc";
2028                 case GDB_REGNO_DCSR:
2029                         return "dcsr";
2030                 case GDB_REGNO_DSCRATCH:
2031                         return "dscratch";
2032                 case GDB_REGNO_MSTATUS:
2033                         return "mstatus";
2034                 case GDB_REGNO_PRIV:
2035                         return "priv";
2036                 default:
2037                         if (regno <= GDB_REGNO_XPR31)
2038                                 sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
2039                         else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095)
2040                                 sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0);
2041                         else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31)
2042                                 sprintf(buf, "f%d", regno - GDB_REGNO_FPR0);
2043                         else
2044                                 sprintf(buf, "gdb_regno_%d", regno);
2045                         return buf;
2046         }
2047 }
2048
2049 static int register_get(struct reg *reg)
2050 {
2051         struct target *target = (struct target *) reg->arch_info;
2052         uint64_t value;
2053         int result = riscv_get_register(target, &value, reg->number);
2054         if (result != ERROR_OK)
2055                 return result;
2056         buf_set_u64(reg->value, 0, reg->size, value);
2057         return ERROR_OK;
2058 }
2059
2060 static int register_set(struct reg *reg, uint8_t *buf)
2061 {
2062         struct target *target = (struct target *) reg->arch_info;
2063
2064         uint64_t value = buf_get_u64(buf, 0, reg->size);
2065
2066         LOG_DEBUG("write 0x%" PRIx64 " to %s", value, reg->name);
2067         struct reg *r = &target->reg_cache->reg_list[reg->number];
2068         r->valid = true;
2069         memcpy(r->value, buf, (r->size + 7) / 8);
2070
2071         riscv_set_register(target, reg->number, value);
2072         return ERROR_OK;
2073 }
2074
2075 static struct reg_arch_type riscv_reg_arch_type = {
2076         .get = register_get,
2077         .set = register_set
2078 };
2079
2080 struct csr_info {
2081         unsigned number;
2082         const char *name;
2083 };
2084
2085 static int cmp_csr_info(const void *p1, const void *p2)
2086 {
2087         return (int) (((struct csr_info *)p1)->number) - (int) (((struct csr_info *)p2)->number);
2088 }
2089
2090 int riscv_init_registers(struct target *target)
2091 {
2092         RISCV_INFO(info);
2093
2094         if (target->reg_cache) {
2095                 if (target->reg_cache->reg_list)
2096                         free(target->reg_cache->reg_list);
2097                 free(target->reg_cache);
2098         }
2099
2100         target->reg_cache = calloc(1, sizeof(*target->reg_cache));
2101         target->reg_cache->name = "RISC-V Registers";
2102         target->reg_cache->num_regs = GDB_REGNO_COUNT;
2103
2104         target->reg_cache->reg_list = calloc(GDB_REGNO_COUNT, sizeof(struct reg));
2105
2106         const unsigned int max_reg_name_len = 12;
2107         if (info->reg_names)
2108                 free(info->reg_names);
2109         info->reg_names = calloc(1, GDB_REGNO_COUNT * max_reg_name_len);
2110         char *reg_name = info->reg_names;
2111
2112         static struct reg_feature feature_cpu = {
2113                 .name = "org.gnu.gdb.riscv.cpu"
2114         };
2115         static struct reg_feature feature_fpu = {
2116                 .name = "org.gnu.gdb.riscv.fpu"
2117         };
2118         static struct reg_feature feature_csr = {
2119                 .name = "org.gnu.gdb.riscv.csr"
2120         };
2121         static struct reg_feature feature_virtual = {
2122                 .name = "org.gnu.gdb.riscv.virtual"
2123         };
2124
2125         static struct reg_data_type type_ieee_single = {
2126                 .type = REG_TYPE_IEEE_SINGLE,
2127                 .id = "ieee_single"
2128         };
2129         static struct reg_data_type type_ieee_double = {
2130                 .type = REG_TYPE_IEEE_DOUBLE,
2131                 .id = "ieee_double"
2132         };
2133         struct csr_info csr_info[] = {
2134 #define DECLARE_CSR(name, number) { number, #name },
2135 #include "encoding.h"
2136 #undef DECLARE_CSR
2137         };
2138         /* encoding.h does not contain the registers in sorted order. */
2139         qsort(csr_info, DIM(csr_info), sizeof(*csr_info), cmp_csr_info);
2140         unsigned csr_info_index = 0;
2141
2142         /* When gdb request register N, gdb_get_register_packet() assumes that this
2143          * is register at index N in reg_list. So if there are certain registers
2144          * that don't exist, we need to leave holes in the list (or renumber, but
2145          * it would be nice not to have yet another set of numbers to translate
2146          * between). */
2147         for (uint32_t number = 0; number < GDB_REGNO_COUNT; number++) {
2148                 struct reg *r = &target->reg_cache->reg_list[number];
2149                 r->dirty = false;
2150                 r->valid = false;
2151                 r->exist = true;
2152                 r->type = &riscv_reg_arch_type;
2153                 r->arch_info = target;
2154                 r->number = number;
2155                 r->size = riscv_xlen(target);
2156                 /* r->size is set in riscv_invalidate_register_cache, maybe because the
2157                  * target is in theory allowed to change XLEN on us. But I expect a lot
2158                  * of other things to break in that case as well. */
2159                 if (number <= GDB_REGNO_XPR31) {
2160                         r->caller_save = true;
2161                         switch (number) {
2162                                 case GDB_REGNO_ZERO:
2163                                         r->name = "zero";
2164                                         break;
2165                                 case GDB_REGNO_RA:
2166                                         r->name = "ra";
2167                                         break;
2168                                 case GDB_REGNO_SP:
2169                                         r->name = "sp";
2170                                         break;
2171                                 case GDB_REGNO_GP:
2172                                         r->name = "gp";
2173                                         break;
2174                                 case GDB_REGNO_TP:
2175                                         r->name = "tp";
2176                                         break;
2177                                 case GDB_REGNO_T0:
2178                                         r->name = "t0";
2179                                         break;
2180                                 case GDB_REGNO_T1:
2181                                         r->name = "t1";
2182                                         break;
2183                                 case GDB_REGNO_T2:
2184                                         r->name = "t2";
2185                                         break;
2186                                 case GDB_REGNO_FP:
2187                                         r->name = "fp";
2188                                         break;
2189                                 case GDB_REGNO_S1:
2190                                         r->name = "s1";
2191                                         break;
2192                                 case GDB_REGNO_A0:
2193                                         r->name = "a0";
2194                                         break;
2195                                 case GDB_REGNO_A1:
2196                                         r->name = "a1";
2197                                         break;
2198                                 case GDB_REGNO_A2:
2199                                         r->name = "a2";
2200                                         break;
2201                                 case GDB_REGNO_A3:
2202                                         r->name = "a3";
2203                                         break;
2204                                 case GDB_REGNO_A4:
2205                                         r->name = "a4";
2206                                         break;
2207                                 case GDB_REGNO_A5:
2208                                         r->name = "a5";
2209                                         break;
2210                                 case GDB_REGNO_A6:
2211                                         r->name = "a6";
2212                                         break;
2213                                 case GDB_REGNO_A7:
2214                                         r->name = "a7";
2215                                         break;
2216                                 case GDB_REGNO_S2:
2217                                         r->name = "s2";
2218                                         break;
2219                                 case GDB_REGNO_S3:
2220                                         r->name = "s3";
2221                                         break;
2222                                 case GDB_REGNO_S4:
2223                                         r->name = "s4";
2224                                         break;
2225                                 case GDB_REGNO_S5:
2226                                         r->name = "s5";
2227                                         break;
2228                                 case GDB_REGNO_S6:
2229                                         r->name = "s6";
2230                                         break;
2231                                 case GDB_REGNO_S7:
2232                                         r->name = "s7";
2233                                         break;
2234                                 case GDB_REGNO_S8:
2235                                         r->name = "s8";
2236                                         break;
2237                                 case GDB_REGNO_S9:
2238                                         r->name = "s9";
2239                                         break;
2240                                 case GDB_REGNO_S10:
2241                                         r->name = "s10";
2242                                         break;
2243                                 case GDB_REGNO_S11:
2244                                         r->name = "s11";
2245                                         break;
2246                                 case GDB_REGNO_T3:
2247                                         r->name = "t3";
2248                                         break;
2249                                 case GDB_REGNO_T4:
2250                                         r->name = "t4";
2251                                         break;
2252                                 case GDB_REGNO_T5:
2253                                         r->name = "t5";
2254                                         break;
2255                                 case GDB_REGNO_T6:
2256                                         r->name = "t6";
2257                                         break;
2258                         }
2259                         r->group = "general";
2260                         r->feature = &feature_cpu;
2261                 } else if (number == GDB_REGNO_PC) {
2262                         r->caller_save = true;
2263                         sprintf(reg_name, "pc");
2264                         r->group = "general";
2265                         r->feature = &feature_cpu;
2266                 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
2267                         r->caller_save = true;
2268                         if (riscv_supports_extension(target, riscv_current_hartid(target),
2269                                                 'D')) {
2270                                 r->reg_data_type = &type_ieee_double;
2271                                 r->size = 64;
2272                         } else if (riscv_supports_extension(target,
2273                                                 riscv_current_hartid(target), 'F')) {
2274                                 r->reg_data_type = &type_ieee_single;
2275                                 r->size = 32;
2276                         } else {
2277                                 r->exist = false;
2278                         }
2279                         switch (number) {
2280                                 case GDB_REGNO_FT0:
2281                                         r->name = "ft0";
2282                                         break;
2283                                 case GDB_REGNO_FT1:
2284                                         r->name = "ft1";
2285                                         break;
2286                                 case GDB_REGNO_FT2:
2287                                         r->name = "ft2";
2288                                         break;
2289                                 case GDB_REGNO_FT3:
2290                                         r->name = "ft3";
2291                                         break;
2292                                 case GDB_REGNO_FT4:
2293                                         r->name = "ft4";
2294                                         break;
2295                                 case GDB_REGNO_FT5:
2296                                         r->name = "ft5";
2297                                         break;
2298                                 case GDB_REGNO_FT6:
2299                                         r->name = "ft6";
2300                                         break;
2301                                 case GDB_REGNO_FT7:
2302                                         r->name = "ft7";
2303                                         break;
2304                                 case GDB_REGNO_FS0:
2305                                         r->name = "fs0";
2306                                         break;
2307                                 case GDB_REGNO_FS1:
2308                                         r->name = "fs1";
2309                                         break;
2310                                 case GDB_REGNO_FA0:
2311                                         r->name = "fa0";
2312                                         break;
2313                                 case GDB_REGNO_FA1:
2314                                         r->name = "fa1";
2315                                         break;
2316                                 case GDB_REGNO_FA2:
2317                                         r->name = "fa2";
2318                                         break;
2319                                 case GDB_REGNO_FA3:
2320                                         r->name = "fa3";
2321                                         break;
2322                                 case GDB_REGNO_FA4:
2323                                         r->name = "fa4";
2324                                         break;
2325                                 case GDB_REGNO_FA5:
2326                                         r->name = "fa5";
2327                                         break;
2328                                 case GDB_REGNO_FA6:
2329                                         r->name = "fa6";
2330                                         break;
2331                                 case GDB_REGNO_FA7:
2332                                         r->name = "fa7";
2333                                         break;
2334                                 case GDB_REGNO_FS2:
2335                                         r->name = "fs2";
2336                                         break;
2337                                 case GDB_REGNO_FS3:
2338                                         r->name = "fs3";
2339                                         break;
2340                                 case GDB_REGNO_FS4:
2341                                         r->name = "fs4";
2342                                         break;
2343                                 case GDB_REGNO_FS5:
2344                                         r->name = "fs5";
2345                                         break;
2346                                 case GDB_REGNO_FS6:
2347                                         r->name = "fs6";
2348                                         break;
2349                                 case GDB_REGNO_FS7:
2350                                         r->name = "fs7";
2351                                         break;
2352                                 case GDB_REGNO_FS8:
2353                                         r->name = "fs8";
2354                                         break;
2355                                 case GDB_REGNO_FS9:
2356                                         r->name = "fs9";
2357                                         break;
2358                                 case GDB_REGNO_FS10:
2359                                         r->name = "fs10";
2360                                         break;
2361                                 case GDB_REGNO_FS11:
2362                                         r->name = "fs11";
2363                                         break;
2364                                 case GDB_REGNO_FT8:
2365                                         r->name = "ft8";
2366                                         break;
2367                                 case GDB_REGNO_FT9:
2368                                         r->name = "ft9";
2369                                         break;
2370                                 case GDB_REGNO_FT10:
2371                                         r->name = "ft10";
2372                                         break;
2373                                 case GDB_REGNO_FT11:
2374                                         r->name = "ft11";
2375                                         break;
2376                         }
2377                         r->group = "float";
2378                         r->feature = &feature_fpu;
2379                 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
2380                         r->group = "csr";
2381                         r->feature = &feature_csr;
2382                         unsigned csr_number = number - GDB_REGNO_CSR0;
2383
2384                         while (csr_info[csr_info_index].number < csr_number &&
2385                                         csr_info_index < DIM(csr_info) - 1) {
2386                                 csr_info_index++;
2387                         }
2388                         if (csr_info[csr_info_index].number == csr_number) {
2389                                 r->name = csr_info[csr_info_index].name;
2390                         } else {
2391                                 sprintf(reg_name, "csr%d", csr_number);
2392                                 /* Assume unnamed registers don't exist, unless we have some
2393                                  * configuration that tells us otherwise. That's important
2394                                  * because eg. Eclipse crashes if a target has too many
2395                                  * registers, and apparently has no way of only showing a
2396                                  * subset of registers in any case. */
2397                                 r->exist = false;
2398                         }
2399
2400                         switch (csr_number) {
2401                                 case CSR_FFLAGS:
2402                                 case CSR_FRM:
2403                                 case CSR_FCSR:
2404                                         r->exist = riscv_supports_extension(target,
2405                                                         riscv_current_hartid(target), 'F');
2406                                         r->group = "float";
2407                                         r->feature = &feature_fpu;
2408                                         break;
2409                                 case CSR_SSTATUS:
2410                                 case CSR_STVEC:
2411                                 case CSR_SIP:
2412                                 case CSR_SIE:
2413                                 case CSR_SCOUNTEREN:
2414                                 case CSR_SSCRATCH:
2415                                 case CSR_SEPC:
2416                                 case CSR_SCAUSE:
2417                                 case CSR_STVAL:
2418                                 case CSR_SATP:
2419                                         r->exist = riscv_supports_extension(target,
2420                                                         riscv_current_hartid(target), 'S');
2421                                         break;
2422                                 case CSR_MEDELEG:
2423                                 case CSR_MIDELEG:
2424                                         /* "In systems with only M-mode, or with both M-mode and
2425                                          * U-mode but without U-mode trap support, the medeleg and
2426                                          * mideleg registers should not exist." */
2427                                         r->exist = riscv_supports_extension(target, riscv_current_hartid(target), 'S') ||
2428                                                 riscv_supports_extension(target, riscv_current_hartid(target), 'N');
2429                                         break;
2430
2431                                 case CSR_CYCLEH:
2432                                 case CSR_TIMEH:
2433                                 case CSR_INSTRETH:
2434                                 case CSR_HPMCOUNTER3H:
2435                                 case CSR_HPMCOUNTER4H:
2436                                 case CSR_HPMCOUNTER5H:
2437                                 case CSR_HPMCOUNTER6H:
2438                                 case CSR_HPMCOUNTER7H:
2439                                 case CSR_HPMCOUNTER8H:
2440                                 case CSR_HPMCOUNTER9H:
2441                                 case CSR_HPMCOUNTER10H:
2442                                 case CSR_HPMCOUNTER11H:
2443                                 case CSR_HPMCOUNTER12H:
2444                                 case CSR_HPMCOUNTER13H:
2445                                 case CSR_HPMCOUNTER14H:
2446                                 case CSR_HPMCOUNTER15H:
2447                                 case CSR_HPMCOUNTER16H:
2448                                 case CSR_HPMCOUNTER17H:
2449                                 case CSR_HPMCOUNTER18H:
2450                                 case CSR_HPMCOUNTER19H:
2451                                 case CSR_HPMCOUNTER20H:
2452                                 case CSR_HPMCOUNTER21H:
2453                                 case CSR_HPMCOUNTER22H:
2454                                 case CSR_HPMCOUNTER23H:
2455                                 case CSR_HPMCOUNTER24H:
2456                                 case CSR_HPMCOUNTER25H:
2457                                 case CSR_HPMCOUNTER26H:
2458                                 case CSR_HPMCOUNTER27H:
2459                                 case CSR_HPMCOUNTER28H:
2460                                 case CSR_HPMCOUNTER29H:
2461                                 case CSR_HPMCOUNTER30H:
2462                                 case CSR_HPMCOUNTER31H:
2463                                 case CSR_MCYCLEH:
2464                                 case CSR_MINSTRETH:
2465                                 case CSR_MHPMCOUNTER3H:
2466                                 case CSR_MHPMCOUNTER4H:
2467                                 case CSR_MHPMCOUNTER5H:
2468                                 case CSR_MHPMCOUNTER6H:
2469                                 case CSR_MHPMCOUNTER7H:
2470                                 case CSR_MHPMCOUNTER8H:
2471                                 case CSR_MHPMCOUNTER9H:
2472                                 case CSR_MHPMCOUNTER10H:
2473                                 case CSR_MHPMCOUNTER11H:
2474                                 case CSR_MHPMCOUNTER12H:
2475                                 case CSR_MHPMCOUNTER13H:
2476                                 case CSR_MHPMCOUNTER14H:
2477                                 case CSR_MHPMCOUNTER15H:
2478                                 case CSR_MHPMCOUNTER16H:
2479                                 case CSR_MHPMCOUNTER17H:
2480                                 case CSR_MHPMCOUNTER18H:
2481                                 case CSR_MHPMCOUNTER19H:
2482                                 case CSR_MHPMCOUNTER20H:
2483                                 case CSR_MHPMCOUNTER21H:
2484                                 case CSR_MHPMCOUNTER22H:
2485                                 case CSR_MHPMCOUNTER23H:
2486                                 case CSR_MHPMCOUNTER24H:
2487                                 case CSR_MHPMCOUNTER25H:
2488                                 case CSR_MHPMCOUNTER26H:
2489                                 case CSR_MHPMCOUNTER27H:
2490                                 case CSR_MHPMCOUNTER28H:
2491                                 case CSR_MHPMCOUNTER29H:
2492                                 case CSR_MHPMCOUNTER30H:
2493                                 case CSR_MHPMCOUNTER31H:
2494                                         r->exist = riscv_xlen(target) == 32;
2495                                         break;
2496                         }
2497
2498                         if (!r->exist && expose_csr) {
2499                                 for (unsigned i = 0; expose_csr[i].low <= expose_csr[i].high; i++) {
2500                                         if (csr_number >= expose_csr[i].low && csr_number <= expose_csr[i].high) {
2501                                                 LOG_INFO("Exposing additional CSR %d", csr_number);
2502                                                 r->exist = true;
2503                                                 break;
2504                                         }
2505                                 }
2506                         }
2507
2508                 } else if (number == GDB_REGNO_PRIV) {
2509                         sprintf(reg_name, "priv");
2510                         r->group = "general";
2511                         r->feature = &feature_virtual;
2512                         r->size = 8;
2513                 }
2514                 if (reg_name[0])
2515                         r->name = reg_name;
2516                 reg_name += strlen(reg_name) + 1;
2517                 assert(reg_name < info->reg_names + GDB_REGNO_COUNT * max_reg_name_len);
2518                 r->value = &info->reg_cache_values[number];
2519         }
2520
2521         return ERROR_OK;
2522 }