git.gag.com Git - fw/openocd/blob - src/target/riscv/riscv.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <assert.h>
   4 #include <stdlib.h>
   5 #include <time.h>
   6
   7 #ifdef HAVE_CONFIG_H
   8 #include "config.h"
   9 #endif
  10
  11 #include <helper/log.h>
  12 #include <helper/time_support.h>
  13 #include "target/target.h"
  14 #include "target/algorithm.h"
  15 #include "target/target_type.h"
  16 #include "jtag/jtag.h"
  17 #include "target/register.h"
  18 #include "target/breakpoints.h"
  19 #include "riscv.h"
  20 #include "gdb_regs.h"
  21 #include "rtos/rtos.h"
  22 #include "debug_defines.h"
  23 #include <helper/bits.h>
  24
  25 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
  26 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
  27
  28 /* Constants for legacy SiFive hardware breakpoints. */
  29 #define CSR_BPCONTROL_X                 (1<<0)
  30 #define CSR_BPCONTROL_W                 (1<<1)
  31 #define CSR_BPCONTROL_R                 (1<<2)
  32 #define CSR_BPCONTROL_U                 (1<<3)
  33 #define CSR_BPCONTROL_S                 (1<<4)
  34 #define CSR_BPCONTROL_H                 (1<<5)
  35 #define CSR_BPCONTROL_M                 (1<<6)
  36 #define CSR_BPCONTROL_BPMATCH   (0xf<<7)
  37 #define CSR_BPCONTROL_BPACTION  (0xff<<11)
  38
  39 #define DEBUG_ROM_START         0x800
  40 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
  41 #define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
  42 #define DEBUG_RAM_START         0x400
  43
  44 #define SETHALTNOT                              0x10c
  45
  46 /*** JTAG registers. ***/
  47
  48 #define DTMCONTROL                                      0x10
  49 #define DTMCONTROL_DBUS_RESET           (1<<16)
  50 #define DTMCONTROL_IDLE                         (7<<10)
  51 #define DTMCONTROL_ADDRBITS                     (0xf<<4)
  52 #define DTMCONTROL_VERSION                      (0xf)
  53
  54 #define DBUS                                            0x11
  55 #define DBUS_OP_START                           0
  56 #define DBUS_OP_SIZE                            2
  57 typedef enum {
  58         DBUS_OP_NOP = 0,
  59         DBUS_OP_READ = 1,
  60         DBUS_OP_WRITE = 2
  61 } dbus_op_t;
  62 typedef enum {
  63         DBUS_STATUS_SUCCESS = 0,
  64         DBUS_STATUS_FAILED = 2,
  65         DBUS_STATUS_BUSY = 3
  66 } dbus_status_t;
  67 #define DBUS_DATA_START                         2
  68 #define DBUS_DATA_SIZE                          34
  69 #define DBUS_ADDRESS_START                      36
  70
  71 typedef enum slot {
  72         SLOT0,
  73         SLOT1,
  74         SLOT_LAST,
  75 } slot_t;
  76
  77 /*** Debug Bus registers. ***/
  78
  79 #define DMCONTROL                               0x10
  80 #define DMCONTROL_INTERRUPT             (((uint64_t)1)<<33)
  81 #define DMCONTROL_HALTNOT               (((uint64_t)1)<<32)
  82 #define DMCONTROL_BUSERROR              (7<<19)
  83 #define DMCONTROL_SERIAL                (3<<16)
  84 #define DMCONTROL_AUTOINCREMENT (1<<15)
  85 #define DMCONTROL_ACCESS                (7<<12)
  86 #define DMCONTROL_HARTID                (0x3ff<<2)
  87 #define DMCONTROL_NDRESET               (1<<1)
  88 #define DMCONTROL_FULLRESET             1
  89
  90 #define DMINFO                                  0x11
  91 #define DMINFO_ABUSSIZE                 (0x7fU<<25)
  92 #define DMINFO_SERIALCOUNT              (0xf<<21)
  93 #define DMINFO_ACCESS128                (1<<20)
  94 #define DMINFO_ACCESS64                 (1<<19)
  95 #define DMINFO_ACCESS32                 (1<<18)
  96 #define DMINFO_ACCESS16                 (1<<17)
  97 #define DMINFO_ACCESS8                  (1<<16)
  98 #define DMINFO_DRAMSIZE                 (0x3f<<10)
  99 #define DMINFO_AUTHENTICATED    (1<<5)
 100 #define DMINFO_AUTHBUSY                 (1<<4)
 101 #define DMINFO_AUTHTYPE                 (3<<2)
 102 #define DMINFO_VERSION                  3
 103
 104 /*** Info about the core being debugged. ***/
 105
 106 #define DBUS_ADDRESS_UNKNOWN    0xffff
 107
 108 #define MAX_HWBPS                       16
 109 #define DRAM_CACHE_SIZE         16
 110
 111 uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
 112 struct scan_field select_dtmcontrol = {
 113         .in_value = NULL,
 114         .out_value = ir_dtmcontrol
 115 };
 116 uint8_t ir_dbus[4] = {DBUS};
 117 struct scan_field select_dbus = {
 118         .in_value = NULL,
 119         .out_value = ir_dbus
 120 };
 121 uint8_t ir_idcode[4] = {0x1};
 122 struct scan_field select_idcode = {
 123         .in_value = NULL,
 124         .out_value = ir_idcode
 125 };
 126
 127 bscan_tunnel_type_t bscan_tunnel_type;
 128 int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
 129
 130 static const uint8_t bscan_zero[4] = {0};
 131 static const uint8_t bscan_one[4] = {1};
 132
 133 uint8_t ir_user4[4];
 134 struct scan_field select_user4 = {
 135         .in_value = NULL,
 136         .out_value = ir_user4
 137 };
 138
 139
 140 uint8_t bscan_tunneled_ir_width[4] = {5};  /* overridden by assignment in riscv_init_target */
 141 struct scan_field _bscan_tunnel_data_register_select_dmi[] = {
 142                 {
 143                         .num_bits = 3,
 144                         .out_value = bscan_zero,
 145                         .in_value = NULL,
 146                 },
 147                 {
 148                         .num_bits = 5, /* initialized in riscv_init_target to ir width of DM */
 149                         .out_value = ir_dbus,
 150                         .in_value = NULL,
 151                 },
 152                 {
 153                         .num_bits = 7,
 154                         .out_value = bscan_tunneled_ir_width,
 155                         .in_value = NULL,
 156                 },
 157                 {
 158                         .num_bits = 1,
 159                         .out_value = bscan_zero,
 160                         .in_value = NULL,
 161                 }
 162 };
 163
 164 struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = {
 165                 {
 166                         .num_bits = 1,
 167                         .out_value = bscan_zero,
 168                         .in_value = NULL,
 169                 },
 170                 {
 171                         .num_bits = 7,
 172                         .out_value = bscan_tunneled_ir_width,
 173                         .in_value = NULL,
 174                 },
 175                 {
 176                         .num_bits = 0, /* initialized in riscv_init_target to ir width of DM */
 177                         .out_value = ir_dbus,
 178                         .in_value = NULL,
 179                 },
 180                 {
 181                         .num_bits = 3,
 182                         .out_value = bscan_zero,
 183                         .in_value = NULL,
 184                 }
 185 };
 186 struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi;
 187 uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi);
 188
 189 struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi;
 190 uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi);
 191
 192 struct trigger {
 193         uint64_t address;
 194         uint32_t length;
 195         uint64_t mask;
 196         uint64_t value;
 197         bool read, write, execute;
 198         int unique_id;
 199 };
 200
 201 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 202 int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
 203
 204 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 205 int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
 206
 207 bool riscv_enable_virt2phys = true;
 208 bool riscv_ebreakm = true;
 209 bool riscv_ebreaks = true;
 210 bool riscv_ebreaku = true;
 211
 212 bool riscv_enable_virtual;
 213
 214 static enum {
 215         RO_NORMAL,
 216         RO_REVERSED
 217 } resume_order;
 218
 219 const virt2phys_info_t sv32 = {
 220         .name = "Sv32",
 221         .va_bits = 32,
 222         .level = 2,
 223         .pte_shift = 2,
 224         .vpn_shift = {12, 22},
 225         .vpn_mask = {0x3ff, 0x3ff},
 226         .pte_ppn_shift = {10, 20},
 227         .pte_ppn_mask = {0x3ff, 0xfff},
 228         .pa_ppn_shift = {12, 22},
 229         .pa_ppn_mask = {0x3ff, 0xfff},
 230 };
 231
 232 const virt2phys_info_t sv39 = {
 233         .name = "Sv39",
 234         .va_bits = 39,
 235         .level = 3,
 236         .pte_shift = 3,
 237         .vpn_shift = {12, 21, 30},
 238         .vpn_mask = {0x1ff, 0x1ff, 0x1ff},
 239         .pte_ppn_shift = {10, 19, 28},
 240         .pte_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
 241         .pa_ppn_shift = {12, 21, 30},
 242         .pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
 243 };
 244
 245 const virt2phys_info_t sv48 = {
 246         .name = "Sv48",
 247         .va_bits = 48,
 248         .level = 4,
 249         .pte_shift = 3,
 250         .vpn_shift = {12, 21, 30, 39},
 251         .vpn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff},
 252         .pte_ppn_shift = {10, 19, 28, 37},
 253         .pte_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
 254         .pa_ppn_shift = {12, 21, 30, 39},
 255         .pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
 256 };
 257
 258 void riscv_sample_buf_maybe_add_timestamp(struct target *target, bool before)
 259 {
 260         RISCV_INFO(r);
 261         uint32_t now = timeval_ms() & 0xffffffff;
 262         if (r->sample_buf.used + 5 < r->sample_buf.size) {
 263                 if (before)
 264                         r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE;
 265                 else
 266                         r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_AFTER;
 267                 r->sample_buf.buf[r->sample_buf.used++] = now & 0xff;
 268                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 8) & 0xff;
 269                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 16) & 0xff;
 270                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 24) & 0xff;
 271         }
 272 }
 273
 274 static int riscv_resume_go_all_harts(struct target *target);
 275
 276 void select_dmi_via_bscan(struct target *target)
 277 {
 278         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
 279         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
 280                 jtag_add_dr_scan(target->tap, bscan_tunnel_data_register_select_dmi_num_fields,
 281                                                                                 bscan_tunnel_data_register_select_dmi, TAP_IDLE);
 282         else /* BSCAN_TUNNEL_NESTED_TAP */
 283                 jtag_add_dr_scan(target->tap, bscan_tunnel_nested_tap_select_dmi_num_fields,
 284                                                                                 bscan_tunnel_nested_tap_select_dmi, TAP_IDLE);
 285 }
 286
 287 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
 288 {
 289         /* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
 290         uint8_t tunneled_ir_width[4] = {bscan_tunnel_ir_width};
 291         uint8_t tunneled_dr_width[4] = {32};
 292         uint8_t out_value[5] = {0};
 293         uint8_t in_value[5] = {0};
 294
 295         buf_set_u32(out_value, 0, 32, out);
 296         struct scan_field tunneled_ir[4] = {};
 297         struct scan_field tunneled_dr[4] = {};
 298
 299         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
 300                 tunneled_ir[0].num_bits = 3;
 301                 tunneled_ir[0].out_value = bscan_zero;
 302                 tunneled_ir[0].in_value = NULL;
 303                 tunneled_ir[1].num_bits = bscan_tunnel_ir_width;
 304                 tunneled_ir[1].out_value = ir_dtmcontrol;
 305                 tunneled_ir[1].in_value = NULL;
 306                 tunneled_ir[2].num_bits = 7;
 307                 tunneled_ir[2].out_value = tunneled_ir_width;
 308                 tunneled_ir[2].in_value = NULL;
 309                 tunneled_ir[3].num_bits = 1;
 310                 tunneled_ir[3].out_value = bscan_zero;
 311                 tunneled_ir[3].in_value = NULL;
 312
 313                 tunneled_dr[0].num_bits = 3;
 314                 tunneled_dr[0].out_value = bscan_zero;
 315                 tunneled_dr[0].in_value = NULL;
 316                 tunneled_dr[1].num_bits = 32 + 1;
 317                 tunneled_dr[1].out_value = out_value;
 318                 tunneled_dr[1].in_value = in_value;
 319                 tunneled_dr[2].num_bits = 7;
 320                 tunneled_dr[2].out_value = tunneled_dr_width;
 321                 tunneled_dr[2].in_value = NULL;
 322                 tunneled_dr[3].num_bits = 1;
 323                 tunneled_dr[3].out_value = bscan_one;
 324                 tunneled_dr[3].in_value = NULL;
 325         } else {
 326                 /* BSCAN_TUNNEL_NESTED_TAP */
 327                 tunneled_ir[3].num_bits = 3;
 328                 tunneled_ir[3].out_value = bscan_zero;
 329                 tunneled_ir[3].in_value = NULL;
 330                 tunneled_ir[2].num_bits = bscan_tunnel_ir_width;
 331                 tunneled_ir[2].out_value = ir_dtmcontrol;
 332                 tunneled_ir[1].in_value = NULL;
 333                 tunneled_ir[1].num_bits = 7;
 334                 tunneled_ir[1].out_value = tunneled_ir_width;
 335                 tunneled_ir[2].in_value = NULL;
 336                 tunneled_ir[0].num_bits = 1;
 337                 tunneled_ir[0].out_value = bscan_zero;
 338                 tunneled_ir[0].in_value = NULL;
 339
 340                 tunneled_dr[3].num_bits = 3;
 341                 tunneled_dr[3].out_value = bscan_zero;
 342                 tunneled_dr[3].in_value = NULL;
 343                 tunneled_dr[2].num_bits = 32 + 1;
 344                 tunneled_dr[2].out_value = out_value;
 345                 tunneled_dr[2].in_value = in_value;
 346                 tunneled_dr[1].num_bits = 7;
 347                 tunneled_dr[1].out_value = tunneled_dr_width;
 348                 tunneled_dr[1].in_value = NULL;
 349                 tunneled_dr[0].num_bits = 1;
 350                 tunneled_dr[0].out_value = bscan_one;
 351                 tunneled_dr[0].in_value = NULL;
 352         }
 353         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
 354         jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_ir), tunneled_ir, TAP_IDLE);
 355         jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_dr), tunneled_dr, TAP_IDLE);
 356         select_dmi_via_bscan(target);
 357
 358         int retval = jtag_execute_queue();
 359         if (retval != ERROR_OK) {
 360                 LOG_ERROR("failed jtag scan: %d", retval);
 361                 return retval;
 362         }
 363         /* Note the starting offset is bit 1, not bit 0.  In BSCAN tunnel, there is a one-bit TCK skew between
 364            output and input */
 365         uint32_t in = buf_get_u32(in_value, 1, 32);
 366         LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
 367
 368         return in;
 369 }
 370
 371 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
 372 {
 373         struct scan_field field;
 374         uint8_t in_value[4];
 375         uint8_t out_value[4] = { 0 };
 376
 377         if (bscan_tunnel_ir_width != 0)
 378                 return dtmcontrol_scan_via_bscan(target, out);
 379
 380
 381         buf_set_u32(out_value, 0, 32, out);
 382
 383         jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
 384
 385         field.num_bits = 32;
 386         field.out_value = out_value;
 387         field.in_value = in_value;
 388         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 389
 390         /* Always return to dbus. */
 391         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 392
 393         int retval = jtag_execute_queue();
 394         if (retval != ERROR_OK) {
 395                 LOG_ERROR("failed jtag scan: %d", retval);
 396                 return retval;
 397         }
 398
 399         uint32_t in = buf_get_u32(field.in_value, 0, 32);
 400         LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
 401
 402         return in;
 403 }
 404
 405 static struct target_type *get_target_type(struct target *target)
 406 {
 407         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 408
 409         if (!info) {
 410                 LOG_ERROR("Target has not been initialized");
 411                 return NULL;
 412         }
 413
 414         switch (info->dtm_version) {
 415                 case 0:
 416                         return &riscv011_target;
 417                 case 1:
 418                         return &riscv013_target;
 419                 default:
 420                         LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
 421                         return NULL;
 422         }
 423 }
 424
 425 static int riscv_create_target(struct target *target, Jim_Interp *interp)
 426 {
 427         LOG_DEBUG("riscv_create_target()");
 428         target->arch_info = calloc(1, sizeof(riscv_info_t));
 429         if (!target->arch_info) {
 430                 LOG_ERROR("Failed to allocate RISC-V target structure.");
 431                 return ERROR_FAIL;
 432         }
 433         riscv_info_init(target, target->arch_info);
 434         return ERROR_OK;
 435 }
 436
 437 static int riscv_init_target(struct command_context *cmd_ctx,
 438                 struct target *target)
 439 {
 440         LOG_DEBUG("riscv_init_target()");
 441         RISCV_INFO(info);
 442         info->cmd_ctx = cmd_ctx;
 443
 444         select_dtmcontrol.num_bits = target->tap->ir_length;
 445         select_dbus.num_bits = target->tap->ir_length;
 446         select_idcode.num_bits = target->tap->ir_length;
 447
 448         if (bscan_tunnel_ir_width != 0) {
 449                 assert(target->tap->ir_length >= 6);
 450                 uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
 451                 ir_user4[0] = (uint8_t)ir_user4_raw;
 452                 ir_user4[1] = (uint8_t)(ir_user4_raw >>= 8);
 453                 ir_user4[2] = (uint8_t)(ir_user4_raw >>= 8);
 454                 ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8);
 455                 select_user4.num_bits = target->tap->ir_length;
 456                 bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width;
 457                 if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
 458                         bscan_tunnel_data_register_select_dmi[1].num_bits = bscan_tunnel_ir_width;
 459                 else /* BSCAN_TUNNEL_NESTED_TAP */
 460                         bscan_tunnel_nested_tap_select_dmi[2].num_bits = bscan_tunnel_ir_width;
 461         }
 462
 463         riscv_semihosting_init(target);
 464
 465         target->debug_reason = DBG_REASON_DBGRQ;
 466
 467         return ERROR_OK;
 468 }
 469
 470 static void riscv_free_registers(struct target *target)
 471 {
 472         /* Free the shared structure use for most registers. */
 473         if (target->reg_cache) {
 474                 if (target->reg_cache->reg_list) {
 475                         free(target->reg_cache->reg_list[0].arch_info);
 476                         /* Free the ones we allocated separately. */
 477                         for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
 478                                 free(target->reg_cache->reg_list[i].arch_info);
 479                         for (unsigned int i = 0; i < target->reg_cache->num_regs; i++)
 480                                 free(target->reg_cache->reg_list[i].value);
 481                         free(target->reg_cache->reg_list);
 482                 }
 483                 free(target->reg_cache);
 484         }
 485 }
 486
 487 static void riscv_deinit_target(struct target *target)
 488 {
 489         LOG_DEBUG("riscv_deinit_target()");
 490
 491         riscv_info_t *info = target->arch_info;
 492         struct target_type *tt = get_target_type(target);
 493
 494         if (tt && info->version_specific)
 495                 tt->deinit_target(target);
 496
 497         riscv_free_registers(target);
 498
 499         range_list_t *entry, *tmp;
 500         list_for_each_entry_safe(entry, tmp, &info->expose_csr, list) {
 501                 free(entry->name);
 502                 free(entry);
 503         }
 504
 505         list_for_each_entry_safe(entry, tmp, &info->expose_custom, list) {
 506                 free(entry->name);
 507                 free(entry);
 508         }
 509
 510         free(info->reg_names);
 511         free(target->arch_info);
 512
 513         target->arch_info = NULL;
 514 }
 515
 516 static void trigger_from_breakpoint(struct trigger *trigger,
 517                 const struct breakpoint *breakpoint)
 518 {
 519         trigger->address = breakpoint->address;
 520         trigger->length = breakpoint->length;
 521         trigger->mask = ~0LL;
 522         trigger->read = false;
 523         trigger->write = false;
 524         trigger->execute = true;
 525         /* unique_id is unique across both breakpoints and watchpoints. */
 526         trigger->unique_id = breakpoint->unique_id;
 527 }
 528
 529 static int maybe_add_trigger_t1(struct target *target,
 530                 struct trigger *trigger, uint64_t tdata1)
 531 {
 532         RISCV_INFO(r);
 533
 534         const uint32_t bpcontrol_x = 1<<0;
 535         const uint32_t bpcontrol_w = 1<<1;
 536         const uint32_t bpcontrol_r = 1<<2;
 537         const uint32_t bpcontrol_u = 1<<3;
 538         const uint32_t bpcontrol_s = 1<<4;
 539         const uint32_t bpcontrol_h = 1<<5;
 540         const uint32_t bpcontrol_m = 1<<6;
 541         const uint32_t bpcontrol_bpmatch = 0xf << 7;
 542         const uint32_t bpcontrol_bpaction = 0xff << 11;
 543
 544         if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
 545                 /* Trigger is already in use, presumably by user code. */
 546                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 547         }
 548
 549         tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
 550         tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
 551         tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
 552         tdata1 = set_field(tdata1, bpcontrol_u,
 553                         !!(r->misa & BIT('U' - 'A')));
 554         tdata1 = set_field(tdata1, bpcontrol_s,
 555                         !!(r->misa & BIT('S' - 'A')));
 556         tdata1 = set_field(tdata1, bpcontrol_h,
 557                         !!(r->misa & BIT('H' - 'A')));
 558         tdata1 |= bpcontrol_m;
 559         tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
 560         tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
 561
 562         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 563
 564         riscv_reg_t tdata1_rb;
 565         if (riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1) != ERROR_OK)
 566                 return ERROR_FAIL;
 567         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 568
 569         if (tdata1 != tdata1_rb) {
 570                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 571                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 572                                 tdata1, tdata1_rb);
 573                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 574                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 575         }
 576
 577         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 578
 579         return ERROR_OK;
 580 }
 581
 582 static int maybe_add_trigger_t2(struct target *target,
 583                 struct trigger *trigger, uint64_t tdata1)
 584 {
 585         RISCV_INFO(r);
 586
 587         /* tselect is already set */
 588         if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
 589                 /* Trigger is already in use, presumably by user code. */
 590                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 591         }
 592
 593         /* address/data match trigger */
 594         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 595         tdata1 = set_field(tdata1, MCONTROL_ACTION,
 596                         MCONTROL_ACTION_DEBUG_MODE);
 597         tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
 598         tdata1 |= MCONTROL_M;
 599         if (r->misa & (1 << ('S' - 'A')))
 600                 tdata1 |= MCONTROL_S;
 601         if (r->misa & (1 << ('U' - 'A')))
 602                 tdata1 |= MCONTROL_U;
 603
 604         if (trigger->execute)
 605                 tdata1 |= MCONTROL_EXECUTE;
 606         if (trigger->read)
 607                 tdata1 |= MCONTROL_LOAD;
 608         if (trigger->write)
 609                 tdata1 |= MCONTROL_STORE;
 610
 611         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 612
 613         uint64_t tdata1_rb;
 614         int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
 615         if (result != ERROR_OK)
 616                 return result;
 617         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 618
 619         if (tdata1 != tdata1_rb) {
 620                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 621                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 622                                 tdata1, tdata1_rb);
 623                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 624                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 625         }
 626
 627         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 628
 629         return ERROR_OK;
 630 }
 631
 632 static int maybe_add_trigger_t6(struct target *target,
 633                 struct trigger *trigger, uint64_t tdata1)
 634 {
 635         RISCV_INFO(r);
 636
 637         /* tselect is already set */
 638         if (tdata1 & (CSR_MCONTROL6_EXECUTE | CSR_MCONTROL6_STORE | CSR_MCONTROL6_LOAD)) {
 639                 /* Trigger is already in use, presumably by user code. */
 640                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 641         }
 642
 643         /* address/data match trigger */
 644         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 645         tdata1 = set_field(tdata1, CSR_MCONTROL6_ACTION,
 646                         MCONTROL_ACTION_DEBUG_MODE);
 647         tdata1 = set_field(tdata1, CSR_MCONTROL6_MATCH, MCONTROL_MATCH_EQUAL);
 648         tdata1 |= CSR_MCONTROL6_M;
 649         if (r->misa & (1 << ('H' - 'A')))
 650                 tdata1 |= CSR_MCONTROL6_VS | CSR_MCONTROL6_VU;
 651         if (r->misa & (1 << ('S' - 'A')))
 652                 tdata1 |= CSR_MCONTROL6_S;
 653         if (r->misa & (1 << ('U' - 'A')))
 654                 tdata1 |= CSR_MCONTROL6_U;
 655
 656         if (trigger->execute)
 657                 tdata1 |= CSR_MCONTROL6_EXECUTE;
 658         if (trigger->read)
 659                 tdata1 |= CSR_MCONTROL6_LOAD;
 660         if (trigger->write)
 661                 tdata1 |= CSR_MCONTROL6_STORE;
 662
 663         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 664
 665         uint64_t tdata1_rb;
 666         int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
 667         if (result != ERROR_OK)
 668                 return result;
 669         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 670
 671         if (tdata1 != tdata1_rb) {
 672                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 673                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 674                                 tdata1, tdata1_rb);
 675                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 676                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 677         }
 678
 679         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 680
 681         return ERROR_OK;
 682 }
 683
 684 static int add_trigger(struct target *target, struct trigger *trigger)
 685 {
 686         RISCV_INFO(r);
 687
 688         if (riscv_enumerate_triggers(target) != ERROR_OK)
 689                 return ERROR_FAIL;
 690
 691         riscv_reg_t tselect;
 692         if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
 693                 return ERROR_FAIL;
 694
 695         unsigned int i;
 696         for (i = 0; i < r->trigger_count; i++) {
 697                 if (r->trigger_unique_id[i] != -1)
 698                         continue;
 699
 700                 riscv_set_register(target, GDB_REGNO_TSELECT, i);
 701
 702                 uint64_t tdata1;
 703                 int result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
 704                 if (result != ERROR_OK)
 705                         return result;
 706                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
 707
 708                 result = ERROR_OK;
 709                 switch (type) {
 710                         case 1:
 711                                 result = maybe_add_trigger_t1(target, trigger, tdata1);
 712                                 break;
 713                         case 2:
 714                                 result = maybe_add_trigger_t2(target, trigger, tdata1);
 715                                 break;
 716                         case 6:
 717                                 result = maybe_add_trigger_t6(target, trigger, tdata1);
 718                                 break;
 719                         default:
 720                                 LOG_DEBUG("trigger %d has unknown type %d", i, type);
 721                                 continue;
 722                 }
 723
 724                 if (result != ERROR_OK)
 725                         continue;
 726
 727                 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
 728                                 i, type, trigger->unique_id);
 729                 r->trigger_unique_id[i] = trigger->unique_id;
 730                 break;
 731         }
 732
 733         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
 734
 735         if (i >= r->trigger_count) {
 736                 LOG_ERROR("Couldn't find an available hardware trigger.");
 737                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 738         }
 739
 740         return ERROR_OK;
 741 }
 742
 743 /**
 744  * Write one memory item of given "size". Use memory access of given "access_size".
 745  * Utilize read-modify-write, if needed.
 746  * */
 747 static int write_by_given_size(struct target *target, target_addr_t address,
 748                 uint32_t size, uint8_t *buffer, uint32_t access_size)
 749 {
 750         assert(size == 1 || size == 2 || size == 4 || size == 8);
 751         assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
 752
 753         if (access_size <= size && address % access_size == 0)
 754                 /* Can do the memory access directly without a helper buffer. */
 755                 return target_write_memory(target, address, access_size, size / access_size, buffer);
 756
 757         unsigned int offset_head = address % access_size;
 758         unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 759         uint8_t helper_buf[n_blocks * access_size];
 760
 761         /* Read from memory */
 762         if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
 763                 return ERROR_FAIL;
 764
 765         /* Modify and write back */
 766         memcpy(helper_buf + offset_head, buffer, size);
 767         return target_write_memory(target, address - offset_head, access_size, n_blocks, helper_buf);
 768 }
 769
 770 /**
 771  * Read one memory item of given "size". Use memory access of given "access_size".
 772  * Read larger section of memory and pick out the required portion, if needed.
 773  * */
 774 static int read_by_given_size(struct target *target, target_addr_t address,
 775         uint32_t size, uint8_t *buffer, uint32_t access_size)
 776 {
 777         assert(size == 1 || size == 2 || size == 4 || size == 8);
 778         assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
 779
 780         if (access_size <= size && address % access_size == 0)
 781                 /* Can do the memory access directly without a helper buffer. */
 782                 return target_read_memory(target, address, access_size, size / access_size, buffer);
 783
 784         unsigned int offset_head = address % access_size;
 785         unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 786         uint8_t helper_buf[n_blocks * access_size];
 787
 788         /* Read from memory */
 789         if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
 790                 return ERROR_FAIL;
 791
 792         /* Pick the requested portion from the buffer */
 793         memcpy(buffer, helper_buf + offset_head, size);
 794         return ERROR_OK;
 795 }
 796
 797 /**
 798  * Write one memory item using any memory access size that will work.
 799  * Utilize read-modify-write, if needed.
 800  * */
 801 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 802 {
 803         assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 804
 805         /* Find access size that correspond to data size and the alignment. */
 806         unsigned int preferred_size = size;
 807         while (address % preferred_size != 0)
 808                 preferred_size /= 2;
 809
 810         /* First try the preferred (most natural) access size. */
 811         if (write_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
 812                 return ERROR_OK;
 813
 814         /* On failure, try other access sizes.
 815            Minimize the number of accesses by trying first the largest size. */
 816         for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 817                 if (access_size == preferred_size)
 818                         /* Already tried this size. */
 819                         continue;
 820
 821                 if (write_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
 822                         return ERROR_OK;
 823         }
 824
 825         /* No access attempt succeeded. */
 826         return ERROR_FAIL;
 827 }
 828
 829 /**
 830  * Read one memory item using any memory access size that will work.
 831  * Read larger section of memory and pick out the required portion, if needed.
 832  * */
 833 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 834 {
 835         assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 836
 837         /* Find access size that correspond to data size and the alignment. */
 838         unsigned int preferred_size = size;
 839         while (address % preferred_size != 0)
 840                 preferred_size /= 2;
 841
 842         /* First try the preferred (most natural) access size. */
 843         if (read_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
 844                 return ERROR_OK;
 845
 846         /* On failure, try other access sizes.
 847            Minimize the number of accesses by trying first the largest size. */
 848         for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 849                 if (access_size == preferred_size)
 850                         /* Already tried this size. */
 851                         continue;
 852
 853                 if (read_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
 854                         return ERROR_OK;
 855         }
 856
 857         /* No access attempt succeeded. */
 858         return ERROR_FAIL;
 859 }
 860
 861 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 862 {
 863         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
 864         assert(breakpoint);
 865         if (breakpoint->type == BKPT_SOFT) {
 866                 /** @todo check RVC for size/alignment */
 867                 if (!(breakpoint->length == 4 || breakpoint->length == 2)) {
 868                         LOG_ERROR("Invalid breakpoint length %d", breakpoint->length);
 869                         return ERROR_FAIL;
 870                 }
 871
 872                 if (0 != (breakpoint->address % 2)) {
 873                         LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR, breakpoint->address);
 874                         return ERROR_FAIL;
 875                 }
 876
 877                 /* Read the original instruction. */
 878                 if (riscv_read_by_any_size(
 879                                 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
 880                         LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
 881                                         breakpoint->address);
 882                         return ERROR_FAIL;
 883                 }
 884
 885                 uint8_t buff[4] = { 0 };
 886                 buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
 887                 /* Write the ebreak instruction. */
 888                 if (riscv_write_by_any_size(target, breakpoint->address, breakpoint->length, buff) != ERROR_OK) {
 889                         LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
 890                                         TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 891                         return ERROR_FAIL;
 892                 }
 893
 894         } else if (breakpoint->type == BKPT_HARD) {
 895                 struct trigger trigger;
 896                 trigger_from_breakpoint(&trigger, breakpoint);
 897                 int const result = add_trigger(target, &trigger);
 898                 if (result != ERROR_OK)
 899                         return result;
 900         } else {
 901                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 902                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 903         }
 904
 905         breakpoint->set = true;
 906         return ERROR_OK;
 907 }
 908
 909 static int remove_trigger(struct target *target, struct trigger *trigger)
 910 {
 911         RISCV_INFO(r);
 912
 913         if (riscv_enumerate_triggers(target) != ERROR_OK)
 914                 return ERROR_FAIL;
 915
 916         unsigned int i;
 917         for (i = 0; i < r->trigger_count; i++) {
 918                 if (r->trigger_unique_id[i] == trigger->unique_id)
 919                         break;
 920         }
 921         if (i >= r->trigger_count) {
 922                 LOG_ERROR("Couldn't find the hardware resources used by hardware "
 923                                 "trigger.");
 924                 return ERROR_FAIL;
 925         }
 926         LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
 927                         trigger->unique_id);
 928
 929         riscv_reg_t tselect;
 930         int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
 931         if (result != ERROR_OK)
 932                 return result;
 933         riscv_set_register(target, GDB_REGNO_TSELECT, i);
 934         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 935         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
 936         r->trigger_unique_id[i] = -1;
 937
 938         return ERROR_OK;
 939 }
 940
 941 int riscv_remove_breakpoint(struct target *target,
 942                 struct breakpoint *breakpoint)
 943 {
 944         if (breakpoint->type == BKPT_SOFT) {
 945                 /* Write the original instruction. */
 946                 if (riscv_write_by_any_size(
 947                                 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
 948                         LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
 949                                         "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 950                         return ERROR_FAIL;
 951                 }
 952
 953         } else if (breakpoint->type == BKPT_HARD) {
 954                 struct trigger trigger;
 955                 trigger_from_breakpoint(&trigger, breakpoint);
 956                 int result = remove_trigger(target, &trigger);
 957                 if (result != ERROR_OK)
 958                         return result;
 959
 960         } else {
 961                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 962                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 963         }
 964
 965         breakpoint->set = false;
 966
 967         return ERROR_OK;
 968 }
 969
 970 static void trigger_from_watchpoint(struct trigger *trigger,
 971                 const struct watchpoint *watchpoint)
 972 {
 973         trigger->address = watchpoint->address;
 974         trigger->length = watchpoint->length;
 975         trigger->mask = watchpoint->mask;
 976         trigger->value = watchpoint->value;
 977         trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
 978         trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
 979         trigger->execute = false;
 980         /* unique_id is unique across both breakpoints and watchpoints. */
 981         trigger->unique_id = watchpoint->unique_id;
 982 }
 983
 984 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 985 {
 986         struct trigger trigger;
 987         trigger_from_watchpoint(&trigger, watchpoint);
 988
 989         int result = add_trigger(target, &trigger);
 990         if (result != ERROR_OK)
 991                 return result;
 992         watchpoint->set = true;
 993
 994         return ERROR_OK;
 995 }
 996
 997 int riscv_remove_watchpoint(struct target *target,
 998                 struct watchpoint *watchpoint)
 999 {
1000         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
1001
1002         struct trigger trigger;
1003         trigger_from_watchpoint(&trigger, watchpoint);
1004
1005         int result = remove_trigger(target, &trigger);
1006         if (result != ERROR_OK)
1007                 return result;
1008         watchpoint->set = false;
1009
1010         return ERROR_OK;
1011 }
1012
1013 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
1014  * current halt.
1015  *
1016  * The GDB server uses this information to tell GDB what data address has
1017  * been hit, which enables GDB to print the hit variable along with its old
1018  * and new value. */
1019 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1020 {
1021         struct watchpoint *wp = target->watchpoints;
1022
1023         LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
1024
1025         /*TODO instead of disassembling the instruction that we think caused the
1026          * trigger, check the hit bit of each watchpoint first. The hit bit is
1027          * simpler and more reliable to check but as it is optional and relatively
1028          * new, not all hardware will implement it  */
1029         riscv_reg_t dpc;
1030         riscv_get_register(target, &dpc, GDB_REGNO_DPC);
1031         const uint8_t length = 4;
1032         LOG_DEBUG("dpc is 0x%" PRIx64, dpc);
1033
1034         /* fetch the instruction at dpc */
1035         uint8_t buffer[length];
1036         if (target_read_buffer(target, dpc, length, buffer) != ERROR_OK) {
1037                 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64, dpc);
1038                 return ERROR_FAIL;
1039         }
1040
1041         uint32_t instruction = 0;
1042
1043         for (int i = 0; i < length; i++) {
1044                 LOG_DEBUG("Next byte is %x", buffer[i]);
1045                 instruction += (buffer[i] << 8 * i);
1046         }
1047         LOG_DEBUG("Full instruction is %x", instruction);
1048
1049         /* find out which memory address is accessed by the instruction at dpc */
1050         /* opcode is first 7 bits of the instruction */
1051         uint8_t opcode = instruction & 0x7F;
1052         uint32_t rs1;
1053         int16_t imm;
1054         riscv_reg_t mem_addr;
1055
1056         if (opcode == MATCH_LB || opcode == MATCH_SB) {
1057                 rs1 = (instruction & 0xf8000) >> 15;
1058                 riscv_get_register(target, &mem_addr, rs1);
1059
1060                 if (opcode == MATCH_SB) {
1061                         LOG_DEBUG("%x is store instruction", instruction);
1062                         imm = ((instruction & 0xf80) >> 7) | ((instruction & 0xfe000000) >> 20);
1063                 } else {
1064                         LOG_DEBUG("%x is load instruction", instruction);
1065                         imm = (instruction & 0xfff00000) >> 20;
1066                 }
1067                 /* sign extend 12-bit imm to 16-bits */
1068                 if (imm & (1 << 11))
1069                         imm |= 0xf000;
1070                 mem_addr += imm;
1071                 LOG_DEBUG("memory address=0x%" PRIx64, mem_addr);
1072         } else {
1073                 LOG_DEBUG("%x is not a RV32I load or store", instruction);
1074                 return ERROR_FAIL;
1075         }
1076
1077         while (wp) {
1078                 /*TODO support length/mask */
1079                 if (wp->address == mem_addr) {
1080                         *hit_watchpoint = wp;
1081                         LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address);
1082                         return ERROR_OK;
1083                 }
1084                 wp = wp->next;
1085         }
1086
1087         /* No match found - either we hit a watchpoint caused by an instruction that
1088          * this function does not yet disassemble, or we hit a breakpoint.
1089          *
1090          * OpenOCD will behave as if this function had never been implemented i.e.
1091          * report the halt to GDB with no address information. */
1092         return ERROR_FAIL;
1093 }
1094
1095
1096 static int oldriscv_step(struct target *target, int current, uint32_t address,
1097                 int handle_breakpoints)
1098 {
1099         struct target_type *tt = get_target_type(target);
1100         return tt->step(target, current, address, handle_breakpoints);
1101 }
1102
1103 static int old_or_new_riscv_step(struct target *target, int current,
1104                 target_addr_t address, int handle_breakpoints)
1105 {
1106         RISCV_INFO(r);
1107         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1108         if (!r->is_halted)
1109                 return oldriscv_step(target, current, address, handle_breakpoints);
1110         else
1111                 return riscv_openocd_step(target, current, address, handle_breakpoints);
1112 }
1113
1114
1115 static int riscv_examine(struct target *target)
1116 {
1117         LOG_DEBUG("riscv_examine()");
1118         if (target_was_examined(target)) {
1119                 LOG_DEBUG("Target was already examined.");
1120                 return ERROR_OK;
1121         }
1122
1123         /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1124
1125         RISCV_INFO(info);
1126         uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1127         LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1128         info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
1129         LOG_DEBUG("  version=0x%x", info->dtm_version);
1130
1131         struct target_type *tt = get_target_type(target);
1132         if (!tt)
1133                 return ERROR_FAIL;
1134
1135         int result = tt->init_target(info->cmd_ctx, target);
1136         if (result != ERROR_OK)
1137                 return result;
1138
1139         return tt->examine(target);
1140 }
1141
1142 static int oldriscv_poll(struct target *target)
1143 {
1144         struct target_type *tt = get_target_type(target);
1145         return tt->poll(target);
1146 }
1147
1148 static int old_or_new_riscv_poll(struct target *target)
1149 {
1150         RISCV_INFO(r);
1151         if (!r->is_halted)
1152                 return oldriscv_poll(target);
1153         else
1154                 return riscv_openocd_poll(target);
1155 }
1156
1157 int riscv_select_current_hart(struct target *target)
1158 {
1159         return riscv_set_current_hartid(target, target->coreid);
1160 }
1161
1162 int halt_prep(struct target *target)
1163 {
1164         RISCV_INFO(r);
1165
1166         LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target),
1167                                 target->debug_reason);
1168         if (riscv_select_current_hart(target) != ERROR_OK)
1169                 return ERROR_FAIL;
1170         if (riscv_is_halted(target)) {
1171                 LOG_DEBUG("[%s] Hart is already halted (reason=%d).",
1172                                 target_name(target), target->debug_reason);
1173         } else {
1174                 if (r->halt_prep(target) != ERROR_OK)
1175                         return ERROR_FAIL;
1176                 r->prepped = true;
1177         }
1178
1179         return ERROR_OK;
1180 }
1181
1182 int riscv_halt_go_all_harts(struct target *target)
1183 {
1184         RISCV_INFO(r);
1185
1186         if (riscv_select_current_hart(target) != ERROR_OK)
1187                 return ERROR_FAIL;
1188         if (riscv_is_halted(target)) {
1189                 LOG_DEBUG("[%s] Hart is already halted.", target_name(target));
1190         } else {
1191                 if (r->halt_go(target) != ERROR_OK)
1192                         return ERROR_FAIL;
1193         }
1194
1195         riscv_invalidate_register_cache(target);
1196
1197         return ERROR_OK;
1198 }
1199
1200 int halt_go(struct target *target)
1201 {
1202         riscv_info_t *r = riscv_info(target);
1203         int result;
1204         if (!r->is_halted) {
1205                 struct target_type *tt = get_target_type(target);
1206                 result = tt->halt(target);
1207         } else {
1208                 result = riscv_halt_go_all_harts(target);
1209         }
1210         target->state = TARGET_HALTED;
1211         if (target->debug_reason == DBG_REASON_NOTHALTED)
1212                 target->debug_reason = DBG_REASON_DBGRQ;
1213
1214         return result;
1215 }
1216
1217 static int halt_finish(struct target *target)
1218 {
1219         return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1220 }
1221
1222 int riscv_halt(struct target *target)
1223 {
1224         RISCV_INFO(r);
1225
1226         if (!r->is_halted) {
1227                 struct target_type *tt = get_target_type(target);
1228                 return tt->halt(target);
1229         }
1230
1231         LOG_DEBUG("[%d] halting all harts", target->coreid);
1232
1233         int result = ERROR_OK;
1234         if (target->smp) {
1235                 for (struct target_list *tlist = target->head; tlist; tlist = tlist->next) {
1236                         struct target *t = tlist->target;
1237                         if (halt_prep(t) != ERROR_OK)
1238                                 result = ERROR_FAIL;
1239                 }
1240
1241                 for (struct target_list *tlist = target->head; tlist; tlist = tlist->next) {
1242                         struct target *t = tlist->target;
1243                         riscv_info_t *i = riscv_info(t);
1244                         if (i->prepped) {
1245                                 if (halt_go(t) != ERROR_OK)
1246                                         result = ERROR_FAIL;
1247                         }
1248                 }
1249
1250                 for (struct target_list *tlist = target->head; tlist; tlist = tlist->next) {
1251                         struct target *t = tlist->target;
1252                         if (halt_finish(t) != ERROR_OK)
1253                                 return ERROR_FAIL;
1254                 }
1255
1256         } else {
1257                 if (halt_prep(target) != ERROR_OK)
1258                         result = ERROR_FAIL;
1259                 if (halt_go(target) != ERROR_OK)
1260                         result = ERROR_FAIL;
1261                 if (halt_finish(target) != ERROR_OK)
1262                         return ERROR_FAIL;
1263         }
1264
1265         return result;
1266 }
1267
1268 static int riscv_assert_reset(struct target *target)
1269 {
1270         LOG_DEBUG("[%d]", target->coreid);
1271         struct target_type *tt = get_target_type(target);
1272         riscv_invalidate_register_cache(target);
1273         return tt->assert_reset(target);
1274 }
1275
1276 static int riscv_deassert_reset(struct target *target)
1277 {
1278         LOG_DEBUG("[%d]", target->coreid);
1279         struct target_type *tt = get_target_type(target);
1280         return tt->deassert_reset(target);
1281 }
1282
1283 int riscv_resume_prep_all_harts(struct target *target)
1284 {
1285         RISCV_INFO(r);
1286
1287         LOG_DEBUG("[%s] prep hart", target_name(target));
1288         if (riscv_select_current_hart(target) != ERROR_OK)
1289                 return ERROR_FAIL;
1290         if (riscv_is_halted(target)) {
1291                 if (r->resume_prep(target) != ERROR_OK)
1292                         return ERROR_FAIL;
1293         } else {
1294                 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
1295                                 target_name(target));
1296         }
1297
1298         LOG_DEBUG("[%s] mark as prepped", target_name(target));
1299         r->prepped = true;
1300
1301         return ERROR_OK;
1302 }
1303
1304 /* state must be riscv_reg_t state[RISCV_MAX_HWBPS] = {0}; */
1305 static int disable_triggers(struct target *target, riscv_reg_t *state)
1306 {
1307         RISCV_INFO(r);
1308
1309         LOG_DEBUG("deal with triggers");
1310
1311         if (riscv_enumerate_triggers(target) != ERROR_OK)
1312                 return ERROR_FAIL;
1313
1314         if (r->manual_hwbp_set) {
1315                 /* Look at every trigger that may have been set. */
1316                 riscv_reg_t tselect;
1317                 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1318                         return ERROR_FAIL;
1319                 for (unsigned int t = 0; t < r->trigger_count; t++) {
1320                         if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1321                                 return ERROR_FAIL;
1322                         riscv_reg_t tdata1;
1323                         if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK)
1324                                 return ERROR_FAIL;
1325                         if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) {
1326                                 state[t] = tdata1;
1327                                 if (riscv_set_register(target, GDB_REGNO_TDATA1, 0) != ERROR_OK)
1328                                         return ERROR_FAIL;
1329                         }
1330                 }
1331                 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1332                         return ERROR_FAIL;
1333
1334         } else {
1335                 /* Just go through the triggers we manage. */
1336                 struct watchpoint *watchpoint = target->watchpoints;
1337                 int i = 0;
1338                 while (watchpoint) {
1339                         LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set);
1340                         state[i] = watchpoint->set;
1341                         if (watchpoint->set) {
1342                                 if (riscv_remove_watchpoint(target, watchpoint) != ERROR_OK)
1343                                         return ERROR_FAIL;
1344                         }
1345                         watchpoint = watchpoint->next;
1346                         i++;
1347                 }
1348         }
1349
1350         return ERROR_OK;
1351 }
1352
1353 static int enable_triggers(struct target *target, riscv_reg_t *state)
1354 {
1355         RISCV_INFO(r);
1356
1357         if (r->manual_hwbp_set) {
1358                 /* Look at every trigger that may have been set. */
1359                 riscv_reg_t tselect;
1360                 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1361                         return ERROR_FAIL;
1362                 for (unsigned int t = 0; t < r->trigger_count; t++) {
1363                         if (state[t] != 0) {
1364                                 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1365                                         return ERROR_FAIL;
1366                                 if (riscv_set_register(target, GDB_REGNO_TDATA1, state[t]) != ERROR_OK)
1367                                         return ERROR_FAIL;
1368                         }
1369                 }
1370                 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1371                         return ERROR_FAIL;
1372
1373         } else {
1374                 struct watchpoint *watchpoint = target->watchpoints;
1375                 int i = 0;
1376                 while (watchpoint) {
1377                         LOG_DEBUG("watchpoint %d: cleared=%" PRId64, i, state[i]);
1378                         if (state[i]) {
1379                                 if (riscv_add_watchpoint(target, watchpoint) != ERROR_OK)
1380                                         return ERROR_FAIL;
1381                         }
1382                         watchpoint = watchpoint->next;
1383                         i++;
1384                 }
1385         }
1386
1387         return ERROR_OK;
1388 }
1389
1390 /**
1391  * Get everything ready to resume.
1392  */
1393 static int resume_prep(struct target *target, int current,
1394                 target_addr_t address, int handle_breakpoints, int debug_execution)
1395 {
1396         RISCV_INFO(r);
1397         LOG_DEBUG("[%d]", target->coreid);
1398
1399         if (!current)
1400                 riscv_set_register(target, GDB_REGNO_PC, address);
1401
1402         if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1403                 /* To be able to run off a trigger, disable all the triggers, step, and
1404                  * then resume as usual. */
1405                 riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
1406
1407                 if (disable_triggers(target, trigger_state) != ERROR_OK)
1408                         return ERROR_FAIL;
1409
1410                 if (old_or_new_riscv_step(target, true, 0, false) != ERROR_OK)
1411                         return ERROR_FAIL;
1412
1413                 if (enable_triggers(target, trigger_state) != ERROR_OK)
1414                         return ERROR_FAIL;
1415         }
1416
1417         if (r->is_halted) {
1418                 if (riscv_resume_prep_all_harts(target) != ERROR_OK)
1419                         return ERROR_FAIL;
1420         }
1421
1422         LOG_DEBUG("[%d] mark as prepped", target->coreid);
1423         r->prepped = true;
1424
1425         return ERROR_OK;
1426 }
1427
1428 /**
1429  * Resume all the harts that have been prepped, as close to instantaneous as
1430  * possible.
1431  */
1432 static int resume_go(struct target *target, int current,
1433                 target_addr_t address, int handle_breakpoints, int debug_execution)
1434 {
1435         riscv_info_t *r = riscv_info(target);
1436         int result;
1437         if (!r->is_halted) {
1438                 struct target_type *tt = get_target_type(target);
1439                 result = tt->resume(target, current, address, handle_breakpoints,
1440                                 debug_execution);
1441         } else {
1442                 result = riscv_resume_go_all_harts(target);
1443         }
1444
1445         return result;
1446 }
1447
1448 static int resume_finish(struct target *target)
1449 {
1450         register_cache_invalidate(target->reg_cache);
1451
1452         target->state = TARGET_RUNNING;
1453         target->debug_reason = DBG_REASON_NOTHALTED;
1454         return target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1455 }
1456
1457 /**
1458  * @par single_hart When true, only resume a single hart even if SMP is
1459  * configured.  This is used to run algorithms on just one hart.
1460  */
1461 int riscv_resume(
1462                 struct target *target,
1463                 int current,
1464                 target_addr_t address,
1465                 int handle_breakpoints,
1466                 int debug_execution,
1467                 bool single_hart)
1468 {
1469         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1470         int result = ERROR_OK;
1471         if (target->smp && !single_hart) {
1472                 for (struct target_list *tlist = target->head; tlist; tlist = tlist->next) {
1473                         struct target *t = tlist->target;
1474                         if (resume_prep(t, current, address, handle_breakpoints,
1475                                                 debug_execution) != ERROR_OK)
1476                                 result = ERROR_FAIL;
1477                 }
1478
1479                 for (struct target_list *tlist = target->head; tlist; tlist = tlist->next) {
1480                         struct target *t = tlist->target;
1481                         riscv_info_t *i = riscv_info(t);
1482                         if (i->prepped) {
1483                                 if (resume_go(t, current, address, handle_breakpoints,
1484                                                         debug_execution) != ERROR_OK)
1485                                         result = ERROR_FAIL;
1486                         }
1487                 }
1488
1489                 for (struct target_list *tlist = target->head; tlist; tlist = tlist->next) {
1490                         struct target *t = tlist->target;
1491                         if (resume_finish(t) != ERROR_OK)
1492                                 return ERROR_FAIL;
1493                 }
1494
1495         } else {
1496                 if (resume_prep(target, current, address, handle_breakpoints,
1497                                         debug_execution) != ERROR_OK)
1498                         result = ERROR_FAIL;
1499                 if (resume_go(target, current, address, handle_breakpoints,
1500                                         debug_execution) != ERROR_OK)
1501                         result = ERROR_FAIL;
1502                 if (resume_finish(target) != ERROR_OK)
1503                         return ERROR_FAIL;
1504         }
1505
1506         return result;
1507 }
1508
1509 static int riscv_target_resume(struct target *target, int current, target_addr_t address,
1510                 int handle_breakpoints, int debug_execution)
1511 {
1512         return riscv_resume(target, current, address, handle_breakpoints,
1513                         debug_execution, false);
1514 }
1515
1516 static int riscv_mmu(struct target *target, int *enabled)
1517 {
1518         if (!riscv_enable_virt2phys) {
1519                 *enabled = 0;
1520                 return ERROR_OK;
1521         }
1522
1523         /* Don't use MMU in explicit or effective M (machine) mode */
1524         riscv_reg_t priv;
1525         if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) {
1526                 LOG_ERROR("Failed to read priv register.");
1527                 return ERROR_FAIL;
1528         }
1529
1530         riscv_reg_t mstatus;
1531         if (riscv_get_register(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK) {
1532                 LOG_ERROR("Failed to read mstatus register.");
1533                 return ERROR_FAIL;
1534         }
1535
1536         if ((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP) : priv) == PRV_M) {
1537                 LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
1538                 *enabled = 0;
1539                 return ERROR_OK;
1540         }
1541
1542         riscv_reg_t satp;
1543         if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) {
1544                 LOG_DEBUG("Couldn't read SATP.");
1545                 /* If we can't read SATP, then there must not be an MMU. */
1546                 *enabled = 0;
1547                 return ERROR_OK;
1548         }
1549
1550         if (get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF) {
1551                 LOG_DEBUG("MMU is disabled.");
1552                 *enabled = 0;
1553         } else {
1554                 LOG_DEBUG("MMU is enabled.");
1555                 *enabled = 1;
1556         }
1557
1558         return ERROR_OK;
1559 }
1560
1561 static int riscv_address_translate(struct target *target,
1562                 target_addr_t virtual, target_addr_t *physical)
1563 {
1564         RISCV_INFO(r);
1565         riscv_reg_t satp_value;
1566         int mode;
1567         uint64_t ppn_value;
1568         target_addr_t table_address;
1569         const virt2phys_info_t *info;
1570         uint64_t pte = 0;
1571         int i;
1572
1573         int result = riscv_get_register(target, &satp_value, GDB_REGNO_SATP);
1574         if (result != ERROR_OK)
1575                 return result;
1576
1577         unsigned xlen = riscv_xlen(target);
1578         mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
1579         switch (mode) {
1580                 case SATP_MODE_SV32:
1581                         info = &sv32;
1582                         break;
1583                 case SATP_MODE_SV39:
1584                         info = &sv39;
1585                         break;
1586                 case SATP_MODE_SV48:
1587                         info = &sv48;
1588                         break;
1589                 case SATP_MODE_OFF:
1590                         LOG_ERROR("No translation or protection." \
1591                                       " (satp: 0x%" PRIx64 ")", satp_value);
1592                         return ERROR_FAIL;
1593                 default:
1594                         LOG_ERROR("The translation mode is not supported." \
1595                                       " (satp: 0x%" PRIx64 ")", satp_value);
1596                         return ERROR_FAIL;
1597         }
1598         LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
1599
1600         /* verify bits xlen-1:va_bits-1 are all equal */
1601         target_addr_t mask = ((target_addr_t)1 << (xlen - (info->va_bits - 1))) - 1;
1602         target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask;
1603         if (masked_msbs != 0 && masked_msbs != mask) {
1604                 LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR " is not sign-extended "
1605                                 "for %s mode.", virtual, info->name);
1606                 return ERROR_FAIL;
1607         }
1608
1609         ppn_value = get_field(satp_value, RISCV_SATP_PPN(xlen));
1610         table_address = ppn_value << RISCV_PGSHIFT;
1611         i = info->level - 1;
1612         while (i >= 0) {
1613                 uint64_t vpn = virtual >> info->vpn_shift[i];
1614                 vpn &= info->vpn_mask[i];
1615                 target_addr_t pte_address = table_address +
1616                                                                         (vpn << info->pte_shift);
1617                 uint8_t buffer[8];
1618                 assert(info->pte_shift <= 3);
1619                 int retval = r->read_memory(target, pte_address,
1620                                 4, (1 << info->pte_shift) / 4, buffer, 4);
1621                 if (retval != ERROR_OK)
1622                         return ERROR_FAIL;
1623
1624                 if (info->pte_shift == 2)
1625                         pte = buf_get_u32(buffer, 0, 32);
1626                 else
1627                         pte = buf_get_u64(buffer, 0, 64);
1628
1629                 LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
1630                                 pte_address, pte);
1631
1632                 if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W)))
1633                         return ERROR_FAIL;
1634
1635                 if ((pte & PTE_R) || (pte & PTE_X)) /* Found leaf PTE. */
1636                         break;
1637
1638                 i--;
1639                 if (i < 0)
1640                         break;
1641                 ppn_value = pte >> PTE_PPN_SHIFT;
1642                 table_address = ppn_value << RISCV_PGSHIFT;
1643         }
1644
1645         if (i < 0) {
1646                 LOG_ERROR("Couldn't find the PTE.");
1647                 return ERROR_FAIL;
1648         }
1649
1650         /* Make sure to clear out the high bits that may be set. */
1651         *physical = virtual & (((target_addr_t)1 << info->va_bits) - 1);
1652
1653         while (i < info->level) {
1654                 ppn_value = pte >> info->pte_ppn_shift[i];
1655                 ppn_value &= info->pte_ppn_mask[i];
1656                 *physical &= ~(((target_addr_t)info->pa_ppn_mask[i]) <<
1657                                 info->pa_ppn_shift[i]);
1658                 *physical |= (ppn_value << info->pa_ppn_shift[i]);
1659                 i++;
1660         }
1661         LOG_DEBUG("0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR, virtual,
1662                         *physical);
1663
1664         return ERROR_OK;
1665 }
1666
1667 static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
1668 {
1669         int enabled;
1670         if (riscv_mmu(target, &enabled) == ERROR_OK) {
1671                 if (!enabled)
1672                         return ERROR_FAIL;
1673
1674                 if (riscv_address_translate(target, virtual, physical) == ERROR_OK)
1675                         return ERROR_OK;
1676         }
1677
1678         return ERROR_FAIL;
1679 }
1680
1681 static int riscv_read_phys_memory(struct target *target, target_addr_t phys_address,
1682                         uint32_t size, uint32_t count, uint8_t *buffer)
1683 {
1684         RISCV_INFO(r);
1685         if (riscv_select_current_hart(target) != ERROR_OK)
1686                 return ERROR_FAIL;
1687         return r->read_memory(target, phys_address, size, count, buffer, size);
1688 }
1689
1690 static int riscv_read_memory(struct target *target, target_addr_t address,
1691                 uint32_t size, uint32_t count, uint8_t *buffer)
1692 {
1693         if (count == 0) {
1694                 LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR, address);
1695                 return ERROR_OK;
1696         }
1697
1698         if (riscv_select_current_hart(target) != ERROR_OK)
1699                 return ERROR_FAIL;
1700
1701         target_addr_t physical_addr;
1702         if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1703                 address = physical_addr;
1704
1705         RISCV_INFO(r);
1706         return r->read_memory(target, address, size, count, buffer, size);
1707 }
1708
1709 static int riscv_write_phys_memory(struct target *target, target_addr_t phys_address,
1710                         uint32_t size, uint32_t count, const uint8_t *buffer)
1711 {
1712         if (riscv_select_current_hart(target) != ERROR_OK)
1713                 return ERROR_FAIL;
1714         struct target_type *tt = get_target_type(target);
1715         return tt->write_memory(target, phys_address, size, count, buffer);
1716 }
1717
1718 static int riscv_write_memory(struct target *target, target_addr_t address,
1719                 uint32_t size, uint32_t count, const uint8_t *buffer)
1720 {
1721         if (count == 0) {
1722                 LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR, address);
1723                 return ERROR_OK;
1724         }
1725
1726         if (riscv_select_current_hart(target) != ERROR_OK)
1727                 return ERROR_FAIL;
1728
1729         target_addr_t physical_addr;
1730         if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1731                 address = physical_addr;
1732
1733         struct target_type *tt = get_target_type(target);
1734         return tt->write_memory(target, address, size, count, buffer);
1735 }
1736
1737 const char *riscv_get_gdb_arch(struct target *target)
1738 {
1739         switch (riscv_xlen(target)) {
1740                 case 32:
1741                         return "riscv:rv32";
1742                 case 64:
1743                         return "riscv:rv64";
1744         }
1745         LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target));
1746         return NULL;
1747 }
1748
1749 static int riscv_get_gdb_reg_list_internal(struct target *target,
1750                 struct reg **reg_list[], int *reg_list_size,
1751                 enum target_register_class reg_class, bool read)
1752 {
1753         RISCV_INFO(r);
1754         LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
1755                         target_name(target), r->current_hartid, reg_class, read);
1756
1757         if (!target->reg_cache) {
1758                 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
1759                 return ERROR_FAIL;
1760         }
1761
1762         if (riscv_select_current_hart(target) != ERROR_OK)
1763                 return ERROR_FAIL;
1764
1765         switch (reg_class) {
1766                 case REG_CLASS_GENERAL:
1767                         *reg_list_size = 33;
1768                         break;
1769                 case REG_CLASS_ALL:
1770                         *reg_list_size = target->reg_cache->num_regs;
1771                         break;
1772                 default:
1773                         LOG_ERROR("Unsupported reg_class: %d", reg_class);
1774                         return ERROR_FAIL;
1775         }
1776
1777         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
1778         if (!*reg_list)
1779                 return ERROR_FAIL;
1780
1781         for (int i = 0; i < *reg_list_size; i++) {
1782                 assert(!target->reg_cache->reg_list[i].valid ||
1783                                 target->reg_cache->reg_list[i].size > 0);
1784                 (*reg_list)[i] = &target->reg_cache->reg_list[i];
1785                 if (read &&
1786                                 target->reg_cache->reg_list[i].exist &&
1787                                 !target->reg_cache->reg_list[i].valid) {
1788                         if (target->reg_cache->reg_list[i].type->get(
1789                                                 &target->reg_cache->reg_list[i]) != ERROR_OK)
1790                                 return ERROR_FAIL;
1791                 }
1792         }
1793
1794         return ERROR_OK;
1795 }
1796
1797 static int riscv_get_gdb_reg_list_noread(struct target *target,
1798                 struct reg **reg_list[], int *reg_list_size,
1799                 enum target_register_class reg_class)
1800 {
1801         return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1802                         reg_class, false);
1803 }
1804
1805 static int riscv_get_gdb_reg_list(struct target *target,
1806                 struct reg **reg_list[], int *reg_list_size,
1807                 enum target_register_class reg_class)
1808 {
1809         return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1810                         reg_class, true);
1811 }
1812
1813 static int riscv_arch_state(struct target *target)
1814 {
1815         struct target_type *tt = get_target_type(target);
1816         return tt->arch_state(target);
1817 }
1818
1819 /* Algorithm must end with a software breakpoint instruction. */
1820 static int riscv_run_algorithm(struct target *target, int num_mem_params,
1821                 struct mem_param *mem_params, int num_reg_params,
1822                 struct reg_param *reg_params, target_addr_t entry_point,
1823                 target_addr_t exit_point, int timeout_ms, void *arch_info)
1824 {
1825         RISCV_INFO(info);
1826
1827         if (num_mem_params > 0) {
1828                 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1829                 return ERROR_FAIL;
1830         }
1831
1832         if (target->state != TARGET_HALTED) {
1833                 LOG_WARNING("target not halted");
1834                 return ERROR_TARGET_NOT_HALTED;
1835         }
1836
1837         /* Save registers */
1838         struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", true);
1839         if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
1840                 return ERROR_FAIL;
1841         uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1842         LOG_DEBUG("saved_pc=0x%" PRIx64, saved_pc);
1843
1844         uint64_t saved_regs[32];
1845         for (int i = 0; i < num_reg_params; i++) {
1846                 LOG_DEBUG("save %s", reg_params[i].reg_name);
1847                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1848                 if (!r) {
1849                         LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
1850                         return ERROR_FAIL;
1851                 }
1852
1853                 if (r->size != reg_params[i].size) {
1854                         LOG_ERROR("Register %s is %d bits instead of %d bits.",
1855                                         reg_params[i].reg_name, r->size, reg_params[i].size);
1856                         return ERROR_FAIL;
1857                 }
1858
1859                 if (r->number > GDB_REGNO_XPR31) {
1860                         LOG_ERROR("Only GPRs can be use as argument registers.");
1861                         return ERROR_FAIL;
1862                 }
1863
1864                 if (r->type->get(r) != ERROR_OK)
1865                         return ERROR_FAIL;
1866                 saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
1867
1868                 if (reg_params[i].direction == PARAM_OUT || reg_params[i].direction == PARAM_IN_OUT) {
1869                         if (r->type->set(r, reg_params[i].value) != ERROR_OK)
1870                                 return ERROR_FAIL;
1871                 }
1872         }
1873
1874
1875         /* Disable Interrupts before attempting to run the algorithm. */
1876         uint64_t current_mstatus;
1877         uint8_t mstatus_bytes[8] = { 0 };
1878
1879         LOG_DEBUG("Disabling Interrupts");
1880         struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
1881                         "mstatus", true);
1882         if (!reg_mstatus) {
1883                 LOG_ERROR("Couldn't find mstatus!");
1884                 return ERROR_FAIL;
1885         }
1886
1887         reg_mstatus->type->get(reg_mstatus);
1888         current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
1889         uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
1890         buf_set_u64(mstatus_bytes, 0, info->xlen, set_field(current_mstatus,
1891                                 ie_mask, 0));
1892
1893         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1894
1895         /* Run algorithm */
1896         LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
1897         if (riscv_resume(target, 0, entry_point, 0, 0, true) != ERROR_OK)
1898                 return ERROR_FAIL;
1899
1900         int64_t start = timeval_ms();
1901         while (target->state != TARGET_HALTED) {
1902                 LOG_DEBUG("poll()");
1903                 int64_t now = timeval_ms();
1904                 if (now - start > timeout_ms) {
1905                         LOG_ERROR("Algorithm timed out after %" PRId64 " ms.", now - start);
1906                         riscv_halt(target);
1907                         old_or_new_riscv_poll(target);
1908                         enum gdb_regno regnums[] = {
1909                                 GDB_REGNO_RA, GDB_REGNO_SP, GDB_REGNO_GP, GDB_REGNO_TP,
1910                                 GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_FP,
1911                                 GDB_REGNO_S1, GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2,
1912                                 GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6,
1913                                 GDB_REGNO_A7, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4,
1914                                 GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8,
1915                                 GDB_REGNO_S9, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_T3,
1916                                 GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6,
1917                                 GDB_REGNO_PC,
1918                                 GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE,
1919                         };
1920                         for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) {
1921                                 enum gdb_regno regno = regnums[i];
1922                                 riscv_reg_t reg_value;
1923                                 if (riscv_get_register(target, &reg_value, regno) != ERROR_OK)
1924                                         break;
1925                                 LOG_ERROR("%s = 0x%" PRIx64, gdb_regno_name(regno), reg_value);
1926                         }
1927                         return ERROR_TARGET_TIMEOUT;
1928                 }
1929
1930                 int result = old_or_new_riscv_poll(target);
1931                 if (result != ERROR_OK)
1932                         return result;
1933         }
1934
1935         /* The current hart id might have been changed in poll(). */
1936         if (riscv_select_current_hart(target) != ERROR_OK)
1937                 return ERROR_FAIL;
1938
1939         if (reg_pc->type->get(reg_pc) != ERROR_OK)
1940                 return ERROR_FAIL;
1941         uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1942         if (exit_point && final_pc != exit_point) {
1943                 LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
1944                                 TARGET_PRIxADDR, final_pc, exit_point);
1945                 return ERROR_FAIL;
1946         }
1947
1948         /* Restore Interrupts */
1949         LOG_DEBUG("Restoring Interrupts");
1950         buf_set_u64(mstatus_bytes, 0, info->xlen, current_mstatus);
1951         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1952
1953         /* Restore registers */
1954         uint8_t buf[8] = { 0 };
1955         buf_set_u64(buf, 0, info->xlen, saved_pc);
1956         if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
1957                 return ERROR_FAIL;
1958
1959         for (int i = 0; i < num_reg_params; i++) {
1960                 if (reg_params[i].direction == PARAM_IN ||
1961                                 reg_params[i].direction == PARAM_IN_OUT) {
1962                         struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1963                         if (r->type->get(r) != ERROR_OK) {
1964                                 LOG_ERROR("get(%s) failed", r->name);
1965                                 return ERROR_FAIL;
1966                         }
1967                         buf_cpy(r->value, reg_params[i].value, reg_params[i].size);
1968                 }
1969                 LOG_DEBUG("restore %s", reg_params[i].reg_name);
1970                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1971                 buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]);
1972                 if (r->type->set(r, buf) != ERROR_OK) {
1973                         LOG_ERROR("set(%s) failed", r->name);
1974                         return ERROR_FAIL;
1975                 }
1976         }
1977
1978         return ERROR_OK;
1979 }
1980
1981 static int riscv_checksum_memory(struct target *target,
1982                 target_addr_t address, uint32_t count,
1983                 uint32_t *checksum)
1984 {
1985         struct working_area *crc_algorithm;
1986         struct reg_param reg_params[2];
1987         int retval;
1988
1989         LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
1990
1991         static const uint8_t riscv32_crc_code[] = {
1992 #include "../../../contrib/loaders/checksum/riscv32_crc.inc"
1993         };
1994         static const uint8_t riscv64_crc_code[] = {
1995 #include "../../../contrib/loaders/checksum/riscv64_crc.inc"
1996         };
1997
1998         static const uint8_t *crc_code;
1999
2000         unsigned xlen = riscv_xlen(target);
2001         unsigned crc_code_size;
2002         if (xlen == 32) {
2003                 crc_code = riscv32_crc_code;
2004                 crc_code_size = sizeof(riscv32_crc_code);
2005         } else {
2006                 crc_code = riscv64_crc_code;
2007                 crc_code_size = sizeof(riscv64_crc_code);
2008         }
2009
2010         if (count < crc_code_size * 4) {
2011                 /* Don't use the algorithm for relatively small buffers. It's faster
2012                  * just to read the memory.  target_checksum_memory() will take care of
2013                  * that if we fail. */
2014                 return ERROR_FAIL;
2015         }
2016
2017         retval = target_alloc_working_area(target, crc_code_size, &crc_algorithm);
2018         if (retval != ERROR_OK)
2019                 return retval;
2020
2021         if (crc_algorithm->address + crc_algorithm->size > address &&
2022                         crc_algorithm->address < address + count) {
2023                 /* Region to checksum overlaps with the work area we've been assigned.
2024                  * Bail. (Would be better to manually checksum what we read there, and
2025                  * use the algorithm for the rest.) */
2026                 target_free_working_area(target, crc_algorithm);
2027                 return ERROR_FAIL;
2028         }
2029
2030         retval = target_write_buffer(target, crc_algorithm->address, crc_code_size,
2031                         crc_code);
2032         if (retval != ERROR_OK) {
2033                 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
2034                                 crc_algorithm->address, retval);
2035                 target_free_working_area(target, crc_algorithm);
2036                 return retval;
2037         }
2038
2039         init_reg_param(&reg_params[0], "a0", xlen, PARAM_IN_OUT);
2040         init_reg_param(&reg_params[1], "a1", xlen, PARAM_OUT);
2041         buf_set_u64(reg_params[0].value, 0, xlen, address);
2042         buf_set_u64(reg_params[1].value, 0, xlen, count);
2043
2044         /* 20 second timeout/megabyte */
2045         int timeout = 20000 * (1 + (count / (1024 * 1024)));
2046
2047         retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
2048                         crc_algorithm->address,
2049                         0,      /* Leave exit point unspecified because we don't know. */
2050                         timeout, NULL);
2051
2052         if (retval == ERROR_OK)
2053                 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2054         else
2055                 LOG_ERROR("error executing RISC-V CRC algorithm");
2056
2057         destroy_reg_param(&reg_params[0]);
2058         destroy_reg_param(&reg_params[1]);
2059
2060         target_free_working_area(target, crc_algorithm);
2061
2062         LOG_DEBUG("checksum=0x%" PRIx32 ", result=%d", *checksum, retval);
2063
2064         return retval;
2065 }
2066
2067 /*** OpenOCD Helper Functions ***/
2068
2069 enum riscv_poll_hart {
2070         RPH_NO_CHANGE,
2071         RPH_DISCOVERED_HALTED,
2072         RPH_DISCOVERED_RUNNING,
2073         RPH_ERROR
2074 };
2075 static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
2076 {
2077         RISCV_INFO(r);
2078         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2079                 return RPH_ERROR;
2080
2081         LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
2082
2083         /* If OpenOCD thinks we're running but this hart is halted then it's time
2084          * to raise an event. */
2085         bool halted = riscv_is_halted(target);
2086         if (target->state != TARGET_HALTED && halted) {
2087                 LOG_DEBUG("  triggered a halt");
2088                 r->on_halt(target);
2089                 return RPH_DISCOVERED_HALTED;
2090         } else if (target->state != TARGET_RUNNING && !halted) {
2091                 LOG_DEBUG("  triggered running");
2092                 target->state = TARGET_RUNNING;
2093                 target->debug_reason = DBG_REASON_NOTHALTED;
2094                 return RPH_DISCOVERED_RUNNING;
2095         }
2096
2097         return RPH_NO_CHANGE;
2098 }
2099
2100 int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
2101 {
2102         switch (halt_reason) {
2103                 case RISCV_HALT_BREAKPOINT:
2104                         target->debug_reason = DBG_REASON_BREAKPOINT;
2105                         break;
2106                 case RISCV_HALT_TRIGGER:
2107                         target->debug_reason = DBG_REASON_WATCHPOINT;
2108                         break;
2109                 case RISCV_HALT_INTERRUPT:
2110                 case RISCV_HALT_GROUP:
2111                         target->debug_reason = DBG_REASON_DBGRQ;
2112                         break;
2113                 case RISCV_HALT_SINGLESTEP:
2114                         target->debug_reason = DBG_REASON_SINGLESTEP;
2115                         break;
2116                 case RISCV_HALT_UNKNOWN:
2117                         target->debug_reason = DBG_REASON_UNDEFINED;
2118                         break;
2119                 case RISCV_HALT_ERROR:
2120                         return ERROR_FAIL;
2121         }
2122         LOG_DEBUG("[%s] debug_reason=%d", target_name(target), target->debug_reason);
2123         return ERROR_OK;
2124 }
2125
2126 int sample_memory(struct target *target)
2127 {
2128         RISCV_INFO(r);
2129
2130         if (!r->sample_buf.buf || !r->sample_config.enabled)
2131                 return ERROR_OK;
2132
2133         LOG_DEBUG("buf used/size: %d/%d", r->sample_buf.used, r->sample_buf.size);
2134
2135         uint64_t start = timeval_ms();
2136         riscv_sample_buf_maybe_add_timestamp(target, true);
2137         int result = ERROR_OK;
2138         if (r->sample_memory) {
2139                 result = r->sample_memory(target, &r->sample_buf, &r->sample_config,
2140                                                                           start + TARGET_DEFAULT_POLLING_INTERVAL);
2141                 if (result != ERROR_NOT_IMPLEMENTED)
2142                         goto exit;
2143         }
2144
2145         /* Default slow path. */
2146         while (timeval_ms() - start < TARGET_DEFAULT_POLLING_INTERVAL) {
2147                 for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
2148                         if (r->sample_config.bucket[i].enabled &&
2149                                         r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes < r->sample_buf.size) {
2150                                 assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
2151                                 r->sample_buf.buf[r->sample_buf.used] = i;
2152                                 result = riscv_read_phys_memory(
2153                                         target, r->sample_config.bucket[i].address,
2154                                         r->sample_config.bucket[i].size_bytes, 1,
2155                                         r->sample_buf.buf + r->sample_buf.used + 1);
2156                                 if (result == ERROR_OK)
2157                                         r->sample_buf.used += 1 + r->sample_config.bucket[i].size_bytes;
2158                                 else
2159                                         goto exit;
2160                         }
2161                 }
2162         }
2163
2164 exit:
2165         riscv_sample_buf_maybe_add_timestamp(target, false);
2166         if (result != ERROR_OK) {
2167                 LOG_INFO("Turning off memory sampling because it failed.");
2168                 r->sample_config.enabled = false;
2169         }
2170         return result;
2171 }
2172
2173 /*** OpenOCD Interface ***/
2174 int riscv_openocd_poll(struct target *target)
2175 {
2176         LOG_DEBUG("polling all harts");
2177         int halted_hart = -1;
2178
2179         if (target->smp) {
2180                 unsigned halts_discovered = 0;
2181                 unsigned should_remain_halted = 0;
2182                 unsigned should_resume = 0;
2183                 unsigned i = 0;
2184                 for (struct target_list *list = target->head; list;
2185                                 list = list->next, i++) {
2186                         struct target *t = list->target;
2187                         riscv_info_t *r = riscv_info(t);
2188                         enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
2189                         switch (out) {
2190                         case RPH_NO_CHANGE:
2191                                 break;
2192                         case RPH_DISCOVERED_RUNNING:
2193                                 t->state = TARGET_RUNNING;
2194                                 t->debug_reason = DBG_REASON_NOTHALTED;
2195                                 break;
2196                         case RPH_DISCOVERED_HALTED:
2197                                 halts_discovered++;
2198                                 t->state = TARGET_HALTED;
2199                                 enum riscv_halt_reason halt_reason =
2200                                         riscv_halt_reason(t, r->current_hartid);
2201                                 if (set_debug_reason(t, halt_reason) != ERROR_OK)
2202                                         return ERROR_FAIL;
2203
2204                                 if (halt_reason == RISCV_HALT_BREAKPOINT) {
2205                                         int retval;
2206                                         switch (riscv_semihosting(t, &retval)) {
2207                                         case SEMI_NONE:
2208                                         case SEMI_WAITING:
2209                                                 /* This hart should remain halted. */
2210                                                 should_remain_halted++;
2211                                                 break;
2212                                         case SEMI_HANDLED:
2213                                                 /* This hart should be resumed, along with any other
2214                                                          * harts that halted due to haltgroups. */
2215                                                 should_resume++;
2216                                                 break;
2217                                         case SEMI_ERROR:
2218                                                 return retval;
2219                                         }
2220                                 } else if (halt_reason != RISCV_HALT_GROUP) {
2221                                         should_remain_halted++;
2222                                 }
2223                                 break;
2224
2225                         case RPH_ERROR:
2226                                 return ERROR_FAIL;
2227                         }
2228                 }
2229
2230                 LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
2231                                   should_remain_halted, should_resume);
2232                 if (should_remain_halted && should_resume) {
2233                         LOG_WARNING("%d harts should remain halted, and %d should resume.",
2234                                                 should_remain_halted, should_resume);
2235                 }
2236                 if (should_remain_halted) {
2237                         LOG_DEBUG("halt all");
2238                         riscv_halt(target);
2239                 } else if (should_resume) {
2240                         LOG_DEBUG("resume all");
2241                         riscv_resume(target, true, 0, 0, 0, false);
2242                 }
2243
2244                 /* Sample memory if any target is running. */
2245                 for (struct target_list *list = target->head; list;
2246                                 list = list->next, i++) {
2247                         struct target *t = list->target;
2248                         if (t->state == TARGET_RUNNING) {
2249                                 sample_memory(target);
2250                                 break;
2251                         }
2252                 }
2253
2254                 return ERROR_OK;
2255
2256         } else {
2257                 enum riscv_poll_hart out = riscv_poll_hart(target,
2258                                 riscv_current_hartid(target));
2259                 if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING) {
2260                         if (target->state == TARGET_RUNNING)
2261                                 sample_memory(target);
2262                         return ERROR_OK;
2263                 } else if (out == RPH_ERROR) {
2264                         return ERROR_FAIL;
2265                 }
2266
2267                 halted_hart = riscv_current_hartid(target);
2268                 LOG_DEBUG("  hart %d halted", halted_hart);
2269
2270                 enum riscv_halt_reason halt_reason = riscv_halt_reason(target, halted_hart);
2271                 if (set_debug_reason(target, halt_reason) != ERROR_OK)
2272                         return ERROR_FAIL;
2273                 target->state = TARGET_HALTED;
2274         }
2275
2276         if (target->debug_reason == DBG_REASON_BREAKPOINT) {
2277                 int retval;
2278                 switch (riscv_semihosting(target, &retval)) {
2279                         case SEMI_NONE:
2280                         case SEMI_WAITING:
2281                                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2282                                 break;
2283                         case SEMI_HANDLED:
2284                                 if (riscv_resume(target, true, 0, 0, 0, false) != ERROR_OK)
2285                                         return ERROR_FAIL;
2286                                 break;
2287                         case SEMI_ERROR:
2288                                 return retval;
2289                 }
2290         } else {
2291                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2292         }
2293
2294         return ERROR_OK;
2295 }
2296
2297 int riscv_openocd_step(struct target *target, int current,
2298                 target_addr_t address, int handle_breakpoints)
2299 {
2300         LOG_DEBUG("stepping rtos hart");
2301
2302         if (!current)
2303                 riscv_set_register(target, GDB_REGNO_PC, address);
2304
2305         riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
2306         if (disable_triggers(target, trigger_state) != ERROR_OK)
2307                 return ERROR_FAIL;
2308
2309         int out = riscv_step_rtos_hart(target);
2310         if (out != ERROR_OK) {
2311                 LOG_ERROR("unable to step rtos hart");
2312                 return out;
2313         }
2314
2315         register_cache_invalidate(target->reg_cache);
2316
2317         if (enable_triggers(target, trigger_state) != ERROR_OK)
2318                 return ERROR_FAIL;
2319
2320         target->state = TARGET_RUNNING;
2321         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
2322         target->state = TARGET_HALTED;
2323         target->debug_reason = DBG_REASON_SINGLESTEP;
2324         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2325         return out;
2326 }
2327
2328 /* Command Handlers */
2329 COMMAND_HANDLER(riscv_set_command_timeout_sec)
2330 {
2331         if (CMD_ARGC != 1) {
2332                 LOG_ERROR("Command takes exactly 1 parameter");
2333                 return ERROR_COMMAND_SYNTAX_ERROR;
2334         }
2335         int timeout = atoi(CMD_ARGV[0]);
2336         if (timeout <= 0) {
2337                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2338                 return ERROR_FAIL;
2339         }
2340
2341         riscv_command_timeout_sec = timeout;
2342
2343         return ERROR_OK;
2344 }
2345
2346 COMMAND_HANDLER(riscv_set_reset_timeout_sec)
2347 {
2348         if (CMD_ARGC != 1) {
2349                 LOG_ERROR("Command takes exactly 1 parameter");
2350                 return ERROR_COMMAND_SYNTAX_ERROR;
2351         }
2352         int timeout = atoi(CMD_ARGV[0]);
2353         if (timeout <= 0) {
2354                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2355                 return ERROR_FAIL;
2356         }
2357
2358         riscv_reset_timeout_sec = timeout;
2359         return ERROR_OK;
2360 }
2361
2362 COMMAND_HANDLER(riscv_set_prefer_sba)
2363 {
2364         struct target *target = get_current_target(CMD_CTX);
2365         RISCV_INFO(r);
2366         bool prefer_sba;
2367         LOG_WARNING("`riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.");
2368         if (CMD_ARGC != 1) {
2369                 LOG_ERROR("Command takes exactly 1 parameter");
2370                 return ERROR_COMMAND_SYNTAX_ERROR;
2371         }
2372         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], prefer_sba);
2373         if (prefer_sba) {
2374                 /* Use system bus with highest priority */
2375                 r->mem_access_methods[0] = RISCV_MEM_ACCESS_SYSBUS;
2376                 r->mem_access_methods[1] = RISCV_MEM_ACCESS_PROGBUF;
2377                 r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
2378         } else {
2379                 /* Use progbuf with highest priority */
2380                 r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF;
2381                 r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS;
2382                 r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
2383         }
2384
2385         /* Reset warning flags */
2386         r->mem_access_progbuf_warn = true;
2387         r->mem_access_sysbus_warn = true;
2388         r->mem_access_abstract_warn = true;
2389
2390         return ERROR_OK;
2391 }
2392
2393 COMMAND_HANDLER(riscv_set_mem_access)
2394 {
2395         struct target *target = get_current_target(CMD_CTX);
2396         RISCV_INFO(r);
2397         int progbuf_cnt = 0;
2398         int sysbus_cnt = 0;
2399         int abstract_cnt = 0;
2400
2401         if (CMD_ARGC < 1 || CMD_ARGC > RISCV_NUM_MEM_ACCESS_METHODS) {
2402                 LOG_ERROR("Command takes 1 to %d parameters", RISCV_NUM_MEM_ACCESS_METHODS);
2403                 return ERROR_COMMAND_SYNTAX_ERROR;
2404         }
2405
2406         /* Check argument validity */
2407         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2408                 if (strcmp("progbuf", CMD_ARGV[i]) == 0) {
2409                         progbuf_cnt++;
2410                 } else if (strcmp("sysbus", CMD_ARGV[i]) == 0) {
2411                         sysbus_cnt++;
2412                 } else if (strcmp("abstract", CMD_ARGV[i]) == 0) {
2413                         abstract_cnt++;
2414                 } else {
2415                         LOG_ERROR("Unknown argument '%s'. "
2416                                 "Must be one of: 'progbuf', 'sysbus' or 'abstract'.", CMD_ARGV[i]);
2417                         return ERROR_COMMAND_SYNTAX_ERROR;
2418                 }
2419         }
2420         if (progbuf_cnt > 1 || sysbus_cnt > 1 || abstract_cnt > 1) {
2421                 LOG_ERROR("Syntax error - duplicate arguments to `riscv set_mem_access`.");
2422                 return ERROR_COMMAND_SYNTAX_ERROR;
2423         }
2424
2425         /* Args are valid, store them */
2426         for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
2427                 r->mem_access_methods[i] = RISCV_MEM_ACCESS_UNSPECIFIED;
2428         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2429                 if (strcmp("progbuf", CMD_ARGV[i]) == 0)
2430                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_PROGBUF;
2431                 else if (strcmp("sysbus", CMD_ARGV[i]) == 0)
2432                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_SYSBUS;
2433                 else if (strcmp("abstract", CMD_ARGV[i]) == 0)
2434                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_ABSTRACT;
2435         }
2436
2437         /* Reset warning flags */
2438         r->mem_access_progbuf_warn = true;
2439         r->mem_access_sysbus_warn = true;
2440         r->mem_access_abstract_warn = true;
2441
2442         return ERROR_OK;
2443 }
2444
2445 COMMAND_HANDLER(riscv_set_enable_virtual)
2446 {
2447         if (CMD_ARGC != 1) {
2448                 LOG_ERROR("Command takes exactly 1 parameter");
2449                 return ERROR_COMMAND_SYNTAX_ERROR;
2450         }
2451         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virtual);
2452         return ERROR_OK;
2453 }
2454
2455 int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val)
2456 {
2457         char *args = strdup(tcl_arg);
2458         if (!args)
2459                 return ERROR_FAIL;
2460
2461         /* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */
2462         char *arg = strtok(args, ",");
2463         while (arg) {
2464                 unsigned low = 0;
2465                 unsigned high = 0;
2466                 char *name = NULL;
2467
2468                 char *dash = strchr(arg, '-');
2469                 char *equals = strchr(arg, '=');
2470                 unsigned int pos;
2471
2472                 if (!dash && !equals) {
2473                         /* Expecting single register number. */
2474                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2475                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2476                                 free(args);
2477                                 return ERROR_COMMAND_SYNTAX_ERROR;
2478                         }
2479                 } else if (dash && !equals) {
2480                         /* Expecting register range - two numbers separated by a dash: ##-## */
2481                         *dash = 0;
2482                         dash++;
2483                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2484                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2485                                 free(args);
2486                                 return ERROR_COMMAND_SYNTAX_ERROR;
2487                         }
2488                         if (sscanf(dash, "%u%n", &high, &pos) != 1 || pos != strlen(dash)) {
2489                                 LOG_ERROR("Failed to parse single register number from '%s'.", dash);
2490                                 free(args);
2491                                 return ERROR_COMMAND_SYNTAX_ERROR;
2492                         }
2493                         if (high < low) {
2494                                 LOG_ERROR("Incorrect range encountered [%u, %u].", low, high);
2495                                 free(args);
2496                                 return ERROR_FAIL;
2497                         }
2498                 } else if (!dash && equals) {
2499                         /* Expecting single register number with textual name specified: ##=name */
2500                         *equals = 0;
2501                         equals++;
2502                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2503                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2504                                 free(args);
2505                                 return ERROR_COMMAND_SYNTAX_ERROR;
2506                         }
2507
2508                         name = calloc(1, strlen(equals) + strlen(reg_type) + 2);
2509                         if (!name) {
2510                                 LOG_ERROR("Failed to allocate register name.");
2511                                 free(args);
2512                                 return ERROR_FAIL;
2513                         }
2514
2515                         /* Register prefix: "csr_" or "custom_" */
2516                         strcpy(name, reg_type);
2517                         name[strlen(reg_type)] = '_';
2518
2519                         if (sscanf(equals, "%[_a-zA-Z0-9]%n", name + strlen(reg_type) + 1, &pos) != 1 || pos != strlen(equals)) {
2520                                 LOG_ERROR("Failed to parse register name from '%s'.", equals);
2521                                 free(args);
2522                                 free(name);
2523                                 return ERROR_COMMAND_SYNTAX_ERROR;
2524                         }
2525                 } else {
2526                         LOG_ERROR("Invalid argument '%s'.", arg);
2527                         free(args);
2528                         return ERROR_COMMAND_SYNTAX_ERROR;
2529                 }
2530
2531                 high = high > low ? high : low;
2532
2533                 if (high > max_val) {
2534                         LOG_ERROR("Cannot expose %s register number %u, maximum allowed value is %u.", reg_type, high, max_val);
2535                         free(name);
2536                         free(args);
2537                         return ERROR_FAIL;
2538                 }
2539
2540                 /* Check for overlap, name uniqueness. */
2541                 range_list_t *entry;
2542                 list_for_each_entry(entry, ranges, list) {
2543                         if ((entry->low <= high) && (low <= entry->high)) {
2544                                 if (low == high)
2545                                         LOG_WARNING("Duplicate %s register number - "
2546                                                         "Register %u has already been exposed previously", reg_type, low);
2547                                 else
2548                                         LOG_WARNING("Overlapping register ranges - Register range starting from %u overlaps "
2549                                                         "with already exposed register/range at %u.", low, entry->low);
2550                         }
2551
2552                         if (entry->name && name && (strcasecmp(entry->name, name) == 0)) {
2553                                 LOG_ERROR("Duplicate register name \"%s\" found.", name);
2554                                 free(name);
2555                                 free(args);
2556                                 return ERROR_FAIL;
2557                         }
2558                 }
2559
2560                 range_list_t *range = calloc(1, sizeof(range_list_t));
2561                 if (!range) {
2562                         LOG_ERROR("Failed to allocate range list.");
2563                         free(name);
2564                         free(args);
2565                         return ERROR_FAIL;
2566                 }
2567
2568                 range->low = low;
2569                 range->high = high;
2570                 range->name = name;
2571                 list_add(&range->list, ranges);
2572
2573                 arg = strtok(NULL, ",");
2574         }
2575
2576         free(args);
2577         return ERROR_OK;
2578 }
2579
2580 COMMAND_HANDLER(riscv_set_expose_csrs)
2581 {
2582         if (CMD_ARGC == 0) {
2583                 LOG_ERROR("Command expects parameters");
2584                 return ERROR_COMMAND_SYNTAX_ERROR;
2585         }
2586
2587         struct target *target = get_current_target(CMD_CTX);
2588         RISCV_INFO(info);
2589         int ret = ERROR_OK;
2590
2591         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2592                 ret = parse_ranges(&info->expose_csr, CMD_ARGV[i], "csr", 0xfff);
2593                 if (ret != ERROR_OK)
2594                         break;
2595         }
2596
2597         return ret;
2598 }
2599
2600 COMMAND_HANDLER(riscv_set_expose_custom)
2601 {
2602         if (CMD_ARGC == 0) {
2603                 LOG_ERROR("Command expects parameters");
2604                 return ERROR_COMMAND_SYNTAX_ERROR;
2605         }
2606
2607         struct target *target = get_current_target(CMD_CTX);
2608         RISCV_INFO(info);
2609         int ret = ERROR_OK;
2610
2611         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2612                 ret = parse_ranges(&info->expose_custom, CMD_ARGV[i], "custom", 0x3fff);
2613                 if (ret != ERROR_OK)
2614                         break;
2615         }
2616
2617         return ret;
2618 }
2619
2620 COMMAND_HANDLER(riscv_authdata_read)
2621 {
2622         unsigned int index = 0;
2623         if (CMD_ARGC == 0) {
2624                 /* nop */
2625         } else if (CMD_ARGC == 1) {
2626                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2627         } else {
2628                 LOG_ERROR("Command takes at most one parameter");
2629                 return ERROR_COMMAND_SYNTAX_ERROR;
2630         }
2631
2632         struct target *target = get_current_target(CMD_CTX);
2633         if (!target) {
2634                 LOG_ERROR("target is NULL!");
2635                 return ERROR_FAIL;
2636         }
2637
2638         RISCV_INFO(r);
2639         if (!r) {
2640                 LOG_ERROR("riscv_info is NULL!");
2641                 return ERROR_FAIL;
2642         }
2643
2644         if (r->authdata_read) {
2645                 uint32_t value;
2646                 if (r->authdata_read(target, &value, index) != ERROR_OK)
2647                         return ERROR_FAIL;
2648                 command_print_sameline(CMD, "0x%08" PRIx32, value);
2649                 return ERROR_OK;
2650         } else {
2651                 LOG_ERROR("authdata_read is not implemented for this target.");
2652                 return ERROR_FAIL;
2653         }
2654 }
2655
2656 COMMAND_HANDLER(riscv_authdata_write)
2657 {
2658         uint32_t value;
2659         unsigned int index = 0;
2660
2661         if (CMD_ARGC == 0) {
2662                 /* nop */
2663         } else if (CMD_ARGC == 1) {
2664                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
2665         } else if (CMD_ARGC == 2) {
2666                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2667                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2668         } else {
2669                 LOG_ERROR("Command takes at most 2 arguments");
2670                 return ERROR_COMMAND_SYNTAX_ERROR;
2671         }
2672
2673         struct target *target = get_current_target(CMD_CTX);
2674         RISCV_INFO(r);
2675
2676         if (r->authdata_write) {
2677                 return r->authdata_write(target, value, index);
2678         } else {
2679                 LOG_ERROR("authdata_write is not implemented for this target.");
2680                 return ERROR_FAIL;
2681         }
2682 }
2683
2684 COMMAND_HANDLER(riscv_dmi_read)
2685 {
2686         if (CMD_ARGC != 1) {
2687                 LOG_ERROR("Command takes 1 parameter");
2688                 return ERROR_COMMAND_SYNTAX_ERROR;
2689         }
2690
2691         struct target *target = get_current_target(CMD_CTX);
2692         if (!target) {
2693                 LOG_ERROR("target is NULL!");
2694                 return ERROR_FAIL;
2695         }
2696
2697         RISCV_INFO(r);
2698         if (!r) {
2699                 LOG_ERROR("riscv_info is NULL!");
2700                 return ERROR_FAIL;
2701         }
2702
2703         if (r->dmi_read) {
2704                 uint32_t address, value;
2705                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2706                 if (r->dmi_read(target, &value, address) != ERROR_OK)
2707                         return ERROR_FAIL;
2708                 command_print(CMD, "0x%" PRIx32, value);
2709                 return ERROR_OK;
2710         } else {
2711                 LOG_ERROR("dmi_read is not implemented for this target.");
2712                 return ERROR_FAIL;
2713         }
2714 }
2715
2716
2717 COMMAND_HANDLER(riscv_dmi_write)
2718 {
2719         if (CMD_ARGC != 2) {
2720                 LOG_ERROR("Command takes exactly 2 arguments");
2721                 return ERROR_COMMAND_SYNTAX_ERROR;
2722         }
2723
2724         struct target *target = get_current_target(CMD_CTX);
2725         RISCV_INFO(r);
2726
2727         uint32_t address, value;
2728         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2729         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2730
2731         if (r->dmi_write) {
2732                 return r->dmi_write(target, address, value);
2733         } else {
2734                 LOG_ERROR("dmi_write is not implemented for this target.");
2735                 return ERROR_FAIL;
2736         }
2737 }
2738
2739 COMMAND_HANDLER(riscv_test_sba_config_reg)
2740 {
2741         if (CMD_ARGC != 4) {
2742                 LOG_ERROR("Command takes exactly 4 arguments");
2743                 return ERROR_COMMAND_SYNTAX_ERROR;
2744         }
2745
2746         struct target *target = get_current_target(CMD_CTX);
2747         RISCV_INFO(r);
2748
2749         target_addr_t legal_address;
2750         uint32_t num_words;
2751         target_addr_t illegal_address;
2752         bool run_sbbusyerror_test;
2753
2754         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[0], legal_address);
2755         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words);
2756         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[2], illegal_address);
2757         COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test);
2758
2759         if (r->test_sba_config_reg) {
2760                 return r->test_sba_config_reg(target, legal_address, num_words,
2761                                 illegal_address, run_sbbusyerror_test);
2762         } else {
2763                 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
2764                 return ERROR_FAIL;
2765         }
2766 }
2767
2768 COMMAND_HANDLER(riscv_reset_delays)
2769 {
2770         int wait = 0;
2771
2772         if (CMD_ARGC > 1) {
2773                 LOG_ERROR("Command takes at most one argument");
2774                 return ERROR_COMMAND_SYNTAX_ERROR;
2775         }
2776
2777         if (CMD_ARGC == 1)
2778                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], wait);
2779
2780         struct target *target = get_current_target(CMD_CTX);
2781         RISCV_INFO(r);
2782         r->reset_delays_wait = wait;
2783         return ERROR_OK;
2784 }
2785
2786 COMMAND_HANDLER(riscv_set_ir)
2787 {
2788         if (CMD_ARGC != 2) {
2789                 LOG_ERROR("Command takes exactly 2 arguments");
2790                 return ERROR_COMMAND_SYNTAX_ERROR;
2791         }
2792
2793         uint32_t value;
2794         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2795
2796         if (!strcmp(CMD_ARGV[0], "idcode"))
2797                 buf_set_u32(ir_idcode, 0, 32, value);
2798         else if (!strcmp(CMD_ARGV[0], "dtmcs"))
2799                 buf_set_u32(ir_dtmcontrol, 0, 32, value);
2800         else if (!strcmp(CMD_ARGV[0], "dmi"))
2801                 buf_set_u32(ir_dbus, 0, 32, value);
2802         else
2803                 return ERROR_FAIL;
2804
2805         return ERROR_OK;
2806 }
2807
2808 COMMAND_HANDLER(riscv_resume_order)
2809 {
2810         if (CMD_ARGC > 1) {
2811                 LOG_ERROR("Command takes at most one argument");
2812                 return ERROR_COMMAND_SYNTAX_ERROR;
2813         }
2814
2815         if (!strcmp(CMD_ARGV[0], "normal")) {
2816                 resume_order = RO_NORMAL;
2817         } else if (!strcmp(CMD_ARGV[0], "reversed")) {
2818                 resume_order = RO_REVERSED;
2819         } else {
2820                 LOG_ERROR("Unsupported resume order: %s", CMD_ARGV[0]);
2821                 return ERROR_FAIL;
2822         }
2823
2824         return ERROR_OK;
2825 }
2826
2827 COMMAND_HANDLER(riscv_use_bscan_tunnel)
2828 {
2829         int irwidth = 0;
2830         int tunnel_type = BSCAN_TUNNEL_NESTED_TAP;
2831
2832         if (CMD_ARGC > 2) {
2833                 LOG_ERROR("Command takes at most two arguments");
2834                 return ERROR_COMMAND_SYNTAX_ERROR;
2835         } else if (CMD_ARGC == 1) {
2836                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2837         } else if (CMD_ARGC == 2) {
2838                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2839                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tunnel_type);
2840         }
2841         if (tunnel_type == BSCAN_TUNNEL_NESTED_TAP)
2842                 LOG_INFO("Nested Tap based Bscan Tunnel Selected");
2843         else if (tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
2844                 LOG_INFO("Simple Register based Bscan Tunnel Selected");
2845         else
2846                 LOG_INFO("Invalid Tunnel type selected ! : selecting default Nested Tap Type");
2847
2848         bscan_tunnel_type = tunnel_type;
2849         bscan_tunnel_ir_width = irwidth;
2850         return ERROR_OK;
2851 }
2852
2853 COMMAND_HANDLER(riscv_set_enable_virt2phys)
2854 {
2855         if (CMD_ARGC != 1) {
2856                 LOG_ERROR("Command takes exactly 1 parameter");
2857                 return ERROR_COMMAND_SYNTAX_ERROR;
2858         }
2859         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virt2phys);
2860         return ERROR_OK;
2861 }
2862
2863 COMMAND_HANDLER(riscv_set_ebreakm)
2864 {
2865         if (CMD_ARGC != 1) {
2866                 LOG_ERROR("Command takes exactly 1 parameter");
2867                 return ERROR_COMMAND_SYNTAX_ERROR;
2868         }
2869         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreakm);
2870         return ERROR_OK;
2871 }
2872
2873 COMMAND_HANDLER(riscv_set_ebreaks)
2874 {
2875         if (CMD_ARGC != 1) {
2876                 LOG_ERROR("Command takes exactly 1 parameter");
2877                 return ERROR_COMMAND_SYNTAX_ERROR;
2878         }
2879         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaks);
2880         return ERROR_OK;
2881 }
2882
2883 COMMAND_HANDLER(riscv_set_ebreaku)
2884 {
2885         if (CMD_ARGC != 1) {
2886                 LOG_ERROR("Command takes exactly 1 parameter");
2887                 return ERROR_COMMAND_SYNTAX_ERROR;
2888         }
2889         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaku);
2890         return ERROR_OK;
2891 }
2892
2893 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
2894                            unsigned int value)
2895 {
2896         char full_key[80];
2897         snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
2898         command_print(CMD, "%-21s %3d", full_key, value);
2899         return 0;
2900 }
2901
2902 COMMAND_HANDLER(handle_info)
2903 {
2904         struct target *target = get_current_target(CMD_CTX);
2905         RISCV_INFO(r);
2906
2907         /* This output format can be fed directly into TCL's "array set". */
2908
2909         riscv_print_info_line(CMD, "hart", "xlen", riscv_xlen(target));
2910         riscv_enumerate_triggers(target);
2911         riscv_print_info_line(CMD, "hart", "trigger_count",
2912                                                   r->trigger_count);
2913
2914         if (r->print_info)
2915                 return CALL_COMMAND_HANDLER(r->print_info, target);
2916
2917         return 0;
2918 }
2919
2920 static const struct command_registration riscv_exec_command_handlers[] = {
2921         {
2922                 .name = "info",
2923                 .handler = handle_info,
2924                 .mode = COMMAND_EXEC,
2925                 .usage = "",
2926                 .help = "Displays some information OpenOCD detected about the target."
2927         },
2928         {
2929                 .name = "set_command_timeout_sec",
2930                 .handler = riscv_set_command_timeout_sec,
2931                 .mode = COMMAND_ANY,
2932                 .usage = "[sec]",
2933                 .help = "Set the wall-clock timeout (in seconds) for individual commands"
2934         },
2935         {
2936                 .name = "set_reset_timeout_sec",
2937                 .handler = riscv_set_reset_timeout_sec,
2938                 .mode = COMMAND_ANY,
2939                 .usage = "[sec]",
2940                 .help = "Set the wall-clock timeout (in seconds) after reset is deasserted"
2941         },
2942         {
2943                 .name = "set_prefer_sba",
2944                 .handler = riscv_set_prefer_sba,
2945                 .mode = COMMAND_ANY,
2946                 .usage = "on|off",
2947                 .help = "When on, prefer to use System Bus Access to access memory. "
2948                         "When off (default), prefer to use the Program Buffer to access memory."
2949         },
2950         {
2951                 .name = "set_mem_access",
2952                 .handler = riscv_set_mem_access,
2953                 .mode = COMMAND_ANY,
2954                 .usage = "method1 [method2] [method3]",
2955                 .help = "Set which memory access methods shall be used and in which order "
2956                         "of priority. Method can be one of: 'progbuf', 'sysbus' or 'abstract'."
2957         },
2958         {
2959                 .name = "set_enable_virtual",
2960                 .handler = riscv_set_enable_virtual,
2961                 .mode = COMMAND_ANY,
2962                 .usage = "on|off",
2963                 .help = "When on, memory accesses are performed on physical or virtual "
2964                                 "memory depending on the current system configuration. "
2965                                 "When off (default), all memory accessses are performed on physical memory."
2966         },
2967         {
2968                 .name = "expose_csrs",
2969                 .handler = riscv_set_expose_csrs,
2970                 .mode = COMMAND_CONFIG,
2971                 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2972                 .help = "Configure a list of inclusive ranges for CSRs to expose in "
2973                                 "addition to the standard ones. This must be executed before "
2974                                 "`init`."
2975         },
2976         {
2977                 .name = "expose_custom",
2978                 .handler = riscv_set_expose_custom,
2979                 .mode = COMMAND_CONFIG,
2980                 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2981                 .help = "Configure a list of inclusive ranges for custom registers to "
2982                         "expose. custom0 is accessed as abstract register number 0xc000, "
2983                         "etc. This must be executed before `init`."
2984         },
2985         {
2986                 .name = "authdata_read",
2987                 .handler = riscv_authdata_read,
2988                 .usage = "[index]",
2989                 .mode = COMMAND_ANY,
2990                 .help = "Return the 32-bit value read from authdata or authdata0 "
2991                                 "(index=0), or authdata1 (index=1)."
2992         },
2993         {
2994                 .name = "authdata_write",
2995                 .handler = riscv_authdata_write,
2996                 .mode = COMMAND_ANY,
2997                 .usage = "[index] value",
2998                 .help = "Write the 32-bit value to authdata or authdata0 (index=0), "
2999                                 "or authdata1 (index=1)."
3000         },
3001         {
3002                 .name = "dmi_read",
3003                 .handler = riscv_dmi_read,
3004                 .mode = COMMAND_ANY,
3005                 .usage = "address",
3006                 .help = "Perform a 32-bit DMI read at address, returning the value."
3007         },
3008         {
3009                 .name = "dmi_write",
3010                 .handler = riscv_dmi_write,
3011                 .mode = COMMAND_ANY,
3012                 .usage = "address value",
3013                 .help = "Perform a 32-bit DMI write of value at address."
3014         },
3015         {
3016                 .name = "test_sba_config_reg",
3017                 .handler = riscv_test_sba_config_reg,
3018                 .mode = COMMAND_ANY,
3019                 .usage = "legal_address num_words "
3020                         "illegal_address run_sbbusyerror_test[on/off]",
3021                 .help = "Perform a series of tests on the SBCS register. "
3022                         "Inputs are a legal, 128-byte aligned address and a number of words to "
3023                         "read/write starting at that address (i.e., address range [legal address, "
3024                         "legal_address+word_size*num_words) must be legally readable/writable), "
3025                         "an illegal, 128-byte aligned address for error flag/handling cases, "
3026                         "and whether sbbusyerror test should be run."
3027         },
3028         {
3029                 .name = "reset_delays",
3030                 .handler = riscv_reset_delays,
3031                 .mode = COMMAND_ANY,
3032                 .usage = "[wait]",
3033                 .help = "OpenOCD learns how many Run-Test/Idle cycles are required "
3034                         "between scans to avoid encountering the target being busy. This "
3035                         "command resets those learned values after `wait` scans. It's only "
3036                         "useful for testing OpenOCD itself."
3037         },
3038         {
3039                 .name = "resume_order",
3040                 .handler = riscv_resume_order,
3041                 .mode = COMMAND_ANY,
3042                 .usage = "normal|reversed",
3043                 .help = "Choose the order that harts are resumed in when `hasel` is not "
3044                         "supported. Normal order is from lowest hart index to highest. "
3045                         "Reversed order is from highest hart index to lowest."
3046         },
3047         {
3048                 .name = "set_ir",
3049                 .handler = riscv_set_ir,
3050                 .mode = COMMAND_ANY,
3051                 .usage = "[idcode|dtmcs|dmi] value",
3052                 .help = "Set IR value for specified JTAG register."
3053         },
3054         {
3055                 .name = "use_bscan_tunnel",
3056                 .handler = riscv_use_bscan_tunnel,
3057                 .mode = COMMAND_ANY,
3058                 .usage = "value [type]",
3059                 .help = "Enable or disable use of a BSCAN tunnel to reach DM.  Supply "
3060                         "the width of the DM transport TAP's instruction register to "
3061                         "enable.  Supply a value of 0 to disable. Pass A second argument "
3062                         "(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
3063                         "1: DATA_REGISTER}"
3064         },
3065         {
3066                 .name = "set_enable_virt2phys",
3067                 .handler = riscv_set_enable_virt2phys,
3068                 .mode = COMMAND_ANY,
3069                 .usage = "on|off",
3070                 .help = "When on (default), enable translation from virtual address to "
3071                         "physical address."
3072         },
3073         {
3074                 .name = "set_ebreakm",
3075                 .handler = riscv_set_ebreakm,
3076                 .mode = COMMAND_ANY,
3077                 .usage = "on|off",
3078                 .help = "Control dcsr.ebreakm. When off, M-mode ebreak instructions "
3079                         "don't trap to OpenOCD. Defaults to on."
3080         },
3081         {
3082                 .name = "set_ebreaks",
3083                 .handler = riscv_set_ebreaks,
3084                 .mode = COMMAND_ANY,
3085                 .usage = "on|off",
3086                 .help = "Control dcsr.ebreaks. When off, S-mode ebreak instructions "
3087                         "don't trap to OpenOCD. Defaults to on."
3088         },
3089         {
3090                 .name = "set_ebreaku",
3091                 .handler = riscv_set_ebreaku,
3092                 .mode = COMMAND_ANY,
3093                 .usage = "on|off",
3094                 .help = "Control dcsr.ebreaku. When off, U-mode ebreak instructions "
3095                         "don't trap to OpenOCD. Defaults to on."
3096         },
3097         COMMAND_REGISTRATION_DONE
3098 };
3099
3100 /*
3101  * To be noted that RISC-V targets use the same semihosting commands as
3102  * ARM targets.
3103  *
3104  * The main reason is compatibility with existing tools. For example the
3105  * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
3106  * configure semihosting, which generate commands like `arm semihosting
3107  * enable`.
3108  * A secondary reason is the fact that the protocol used is exactly the
3109  * one specified by ARM. If RISC-V will ever define its own semihosting
3110  * protocol, then a command like `riscv semihosting enable` will make
3111  * sense, but for now all semihosting commands are prefixed with `arm`.
3112  */
3113 extern const struct command_registration semihosting_common_handlers[];
3114
3115 const struct command_registration riscv_command_handlers[] = {
3116         {
3117                 .name = "riscv",
3118                 .mode = COMMAND_ANY,
3119                 .help = "RISC-V Command Group",
3120                 .usage = "",
3121                 .chain = riscv_exec_command_handlers
3122         },
3123         {
3124                 .name = "arm",
3125                 .mode = COMMAND_ANY,
3126                 .help = "ARM Command Group",
3127                 .usage = "",
3128                 .chain = semihosting_common_handlers
3129         },
3130         COMMAND_REGISTRATION_DONE
3131 };
3132
3133 static unsigned riscv_xlen_nonconst(struct target *target)
3134 {
3135         return riscv_xlen(target);
3136 }
3137
3138 static unsigned int riscv_data_bits(struct target *target)
3139 {
3140         RISCV_INFO(r);
3141         if (r->data_bits)
3142                 return r->data_bits(target);
3143         return riscv_xlen(target);
3144 }
3145
3146 struct target_type riscv_target = {
3147         .name = "riscv",
3148
3149         .target_create = riscv_create_target,
3150         .init_target = riscv_init_target,
3151         .deinit_target = riscv_deinit_target,
3152         .examine = riscv_examine,
3153
3154         /* poll current target status */
3155         .poll = old_or_new_riscv_poll,
3156
3157         .halt = riscv_halt,
3158         .resume = riscv_target_resume,
3159         .step = old_or_new_riscv_step,
3160
3161         .assert_reset = riscv_assert_reset,
3162         .deassert_reset = riscv_deassert_reset,
3163
3164         .read_memory = riscv_read_memory,
3165         .write_memory = riscv_write_memory,
3166         .read_phys_memory = riscv_read_phys_memory,
3167         .write_phys_memory = riscv_write_phys_memory,
3168
3169         .checksum_memory = riscv_checksum_memory,
3170
3171         .mmu = riscv_mmu,
3172         .virt2phys = riscv_virt2phys,
3173
3174         .get_gdb_arch = riscv_get_gdb_arch,
3175         .get_gdb_reg_list = riscv_get_gdb_reg_list,
3176         .get_gdb_reg_list_noread = riscv_get_gdb_reg_list_noread,
3177
3178         .add_breakpoint = riscv_add_breakpoint,
3179         .remove_breakpoint = riscv_remove_breakpoint,
3180
3181         .add_watchpoint = riscv_add_watchpoint,
3182         .remove_watchpoint = riscv_remove_watchpoint,
3183         .hit_watchpoint = riscv_hit_watchpoint,
3184
3185         .arch_state = riscv_arch_state,
3186
3187         .run_algorithm = riscv_run_algorithm,
3188
3189         .commands = riscv_command_handlers,
3190
3191         .address_bits = riscv_xlen_nonconst,
3192         .data_bits = riscv_data_bits
3193 };
3194
3195 /*** RISC-V Interface ***/
3196
3197 void riscv_info_init(struct target *target, riscv_info_t *r)
3198 {
3199         memset(r, 0, sizeof(*r));
3200         r->dtm_version = 1;
3201         r->registers_initialized = false;
3202         r->current_hartid = target->coreid;
3203         r->version_specific = NULL;
3204
3205         memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
3206
3207         r->xlen = -1;
3208
3209         r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF;
3210         r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS;
3211         r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
3212
3213         r->mem_access_progbuf_warn = true;
3214         r->mem_access_sysbus_warn = true;
3215         r->mem_access_abstract_warn = true;
3216
3217         INIT_LIST_HEAD(&r->expose_csr);
3218         INIT_LIST_HEAD(&r->expose_custom);
3219 }
3220
3221 static int riscv_resume_go_all_harts(struct target *target)
3222 {
3223         RISCV_INFO(r);
3224
3225         LOG_DEBUG("[%s] resuming hart", target_name(target));
3226         if (riscv_select_current_hart(target) != ERROR_OK)
3227                 return ERROR_FAIL;
3228         if (riscv_is_halted(target)) {
3229                 if (r->resume_go(target) != ERROR_OK)
3230                         return ERROR_FAIL;
3231         } else {
3232                 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
3233                                 target_name(target));
3234         }
3235
3236         riscv_invalidate_register_cache(target);
3237         return ERROR_OK;
3238 }
3239
3240 int riscv_step_rtos_hart(struct target *target)
3241 {
3242         RISCV_INFO(r);
3243         if (riscv_select_current_hart(target) != ERROR_OK)
3244                 return ERROR_FAIL;
3245         LOG_DEBUG("[%s] stepping", target_name(target));
3246
3247         if (!riscv_is_halted(target)) {
3248                 LOG_ERROR("Hart isn't halted before single step!");
3249                 return ERROR_FAIL;
3250         }
3251         riscv_invalidate_register_cache(target);
3252         r->on_step(target);
3253         if (r->step_current_hart(target) != ERROR_OK)
3254                 return ERROR_FAIL;
3255         riscv_invalidate_register_cache(target);
3256         r->on_halt(target);
3257         if (!riscv_is_halted(target)) {
3258                 LOG_ERROR("Hart was not halted after single step!");
3259                 return ERROR_FAIL;
3260         }
3261         return ERROR_OK;
3262 }
3263
3264 bool riscv_supports_extension(struct target *target, char letter)
3265 {
3266         RISCV_INFO(r);
3267         unsigned num;
3268         if (letter >= 'a' && letter <= 'z')
3269                 num = letter - 'a';
3270         else if (letter >= 'A' && letter <= 'Z')
3271                 num = letter - 'A';
3272         else
3273                 return false;
3274         return r->misa & BIT(num);
3275 }
3276
3277 unsigned riscv_xlen(const struct target *target)
3278 {
3279         RISCV_INFO(r);
3280         return r->xlen;
3281 }
3282
3283 int riscv_set_current_hartid(struct target *target, int hartid)
3284 {
3285         RISCV_INFO(r);
3286         if (!r->select_current_hart)
3287                 return ERROR_OK;
3288
3289         int previous_hartid = riscv_current_hartid(target);
3290         r->current_hartid = hartid;
3291         LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
3292         if (r->select_current_hart(target) != ERROR_OK)
3293                 return ERROR_FAIL;
3294
3295         return ERROR_OK;
3296 }
3297
3298 void riscv_invalidate_register_cache(struct target *target)
3299 {
3300         RISCV_INFO(r);
3301
3302         LOG_DEBUG("[%d]", target->coreid);
3303         register_cache_invalidate(target->reg_cache);
3304         for (size_t i = 0; i < target->reg_cache->num_regs; ++i) {
3305                 struct reg *reg = &target->reg_cache->reg_list[i];
3306                 reg->valid = false;
3307         }
3308
3309         r->registers_initialized = true;
3310 }
3311
3312 int riscv_current_hartid(const struct target *target)
3313 {
3314         RISCV_INFO(r);
3315         return r->current_hartid;
3316 }
3317
3318 int riscv_count_harts(struct target *target)
3319 {
3320         if (!target)
3321                 return 1;
3322         RISCV_INFO(r);
3323         if (!r || !r->hart_count)
3324                 return 1;
3325         return r->hart_count(target);
3326 }
3327
3328 /**
3329  * If write is true:
3330  *   return true iff we are guaranteed that the register will contain exactly
3331  *       the value we just wrote when it's read.
3332  * If write is false:
3333  *   return true iff we are guaranteed that the register will read the same
3334  *       value in the future as the value we just read.
3335  */
3336 static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
3337 {
3338         /* GPRs, FPRs, vector registers are just normal data stores. */
3339         if (regno <= GDB_REGNO_XPR31 ||
3340                         (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||
3341                         (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31))
3342                 return true;
3343
3344         /* Most CSRs won't change value on us, but we can't assume it about arbitrary
3345          * CSRs. */
3346         switch (regno) {
3347                 case GDB_REGNO_DPC:
3348                         return true;
3349
3350                 case GDB_REGNO_VSTART:
3351                 case GDB_REGNO_VXSAT:
3352                 case GDB_REGNO_VXRM:
3353                 case GDB_REGNO_VLENB:
3354                 case GDB_REGNO_VL:
3355                 case GDB_REGNO_VTYPE:
3356                 case GDB_REGNO_MISA:
3357                 case GDB_REGNO_DCSR:
3358                 case GDB_REGNO_DSCRATCH0:
3359                 case GDB_REGNO_MSTATUS:
3360                 case GDB_REGNO_MEPC:
3361                 case GDB_REGNO_MCAUSE:
3362                 case GDB_REGNO_SATP:
3363                         /*
3364                          * WARL registers might not contain the value we just wrote, but
3365                          * these ones won't spontaneously change their value either. *
3366                          */
3367                         return !write;
3368
3369                 case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
3370                 case GDB_REGNO_TDATA1:  /* Changes value when tselect is changed. */
3371                 case GDB_REGNO_TDATA2:  /* Changse value when tselect is changed. */
3372                 default:
3373                         return false;
3374         }
3375 }
3376
3377 /**
3378  * This function is called when the debug user wants to change the value of a
3379  * register. The new value may be cached, and may not be written until the hart
3380  * is resumed. */
3381 int riscv_set_register(struct target *target, enum gdb_regno regid, riscv_reg_t value)
3382 {
3383         RISCV_INFO(r);
3384         LOG_DEBUG("[%s] %s <- %" PRIx64, target_name(target), gdb_regno_name(regid), value);
3385         assert(r->set_register);
3386
3387         keep_alive();
3388
3389         /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3390         if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 && value == 0 &&
3391                         riscv_supports_extension(target, 'E'))
3392                 return ERROR_OK;
3393
3394         struct reg *reg = &target->reg_cache->reg_list[regid];
3395         buf_set_u64(reg->value, 0, reg->size, value);
3396
3397         int result = r->set_register(target, regid, value);
3398         if (result == ERROR_OK)
3399                 reg->valid = gdb_regno_cacheable(regid, true);
3400         else
3401                 reg->valid = false;
3402         LOG_DEBUG("[%s] wrote 0x%" PRIx64 " to %s valid=%d",
3403                           target_name(target), value, reg->name, reg->valid);
3404         return result;
3405 }
3406
3407 int riscv_get_register(struct target *target, riscv_reg_t *value,
3408                 enum gdb_regno regid)
3409 {
3410         RISCV_INFO(r);
3411
3412         keep_alive();
3413
3414         struct reg *reg = &target->reg_cache->reg_list[regid];
3415         if (!reg->exist) {
3416                 LOG_DEBUG("[%s] %s does not exist.",
3417                                   target_name(target), gdb_regno_name(regid));
3418                 return ERROR_FAIL;
3419         }
3420
3421         if (reg && reg->valid) {
3422                 *value = buf_get_u64(reg->value, 0, reg->size);
3423                 LOG_DEBUG("[%s] %s: %" PRIx64 " (cached)", target_name(target),
3424                                   gdb_regno_name(regid), *value);
3425                 return ERROR_OK;
3426         }
3427
3428         /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3429         if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 &&
3430                         riscv_supports_extension(target, 'E')) {
3431                 *value = 0;
3432                 return ERROR_OK;
3433         }
3434
3435         int result = r->get_register(target, value, regid);
3436
3437         if (result == ERROR_OK)
3438                 reg->valid = gdb_regno_cacheable(regid, false);
3439
3440         LOG_DEBUG("[%s] %s: %" PRIx64, target_name(target),
3441                         gdb_regno_name(regid), *value);
3442         return result;
3443 }
3444
3445 bool riscv_is_halted(struct target *target)
3446 {
3447         RISCV_INFO(r);
3448         assert(r->is_halted);
3449         return r->is_halted(target);
3450 }
3451
3452 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
3453 {
3454         RISCV_INFO(r);
3455         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
3456                 return RISCV_HALT_ERROR;
3457         if (!riscv_is_halted(target)) {
3458                 LOG_ERROR("Hart is not halted!");
3459                 return RISCV_HALT_UNKNOWN;
3460         }
3461         return r->halt_reason(target);
3462 }
3463
3464 size_t riscv_debug_buffer_size(struct target *target)
3465 {
3466         RISCV_INFO(r);
3467         return r->debug_buffer_size;
3468 }
3469
3470 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
3471 {
3472         RISCV_INFO(r);
3473         r->write_debug_buffer(target, index, insn);
3474         return ERROR_OK;
3475 }
3476
3477 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
3478 {
3479         RISCV_INFO(r);
3480         return r->read_debug_buffer(target, index);
3481 }
3482
3483 int riscv_execute_debug_buffer(struct target *target)
3484 {
3485         RISCV_INFO(r);
3486         return r->execute_debug_buffer(target);
3487 }
3488
3489 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
3490 {
3491         RISCV_INFO(r);
3492         r->fill_dmi_write_u64(target, buf, a, d);
3493 }
3494
3495 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
3496 {
3497         RISCV_INFO(r);
3498         r->fill_dmi_read_u64(target, buf, a);
3499 }
3500
3501 void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
3502 {
3503         RISCV_INFO(r);
3504         r->fill_dmi_nop_u64(target, buf);
3505 }
3506
3507 int riscv_dmi_write_u64_bits(struct target *target)
3508 {
3509         RISCV_INFO(r);
3510         return r->dmi_write_u64_bits(target);
3511 }
3512
3513 /**
3514  * Count triggers, and initialize trigger_count for each hart.
3515  * trigger_count is initialized even if this function fails to discover
3516  * something.
3517  * Disable any hardware triggers that have dmode set. We can't have set them
3518  * ourselves. Maybe they're left over from some killed debug session.
3519  * */
3520 int riscv_enumerate_triggers(struct target *target)
3521 {
3522         RISCV_INFO(r);
3523
3524         if (r->triggers_enumerated)
3525                 return ERROR_OK;
3526
3527         r->triggers_enumerated = true;  /* At the very least we tried. */
3528
3529         riscv_reg_t tselect;
3530         int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
3531         /* If tselect is not readable, the trigger module is likely not
3532                 * implemented. There are no triggers to enumerate then and no error
3533                 * should be thrown. */
3534         if (result != ERROR_OK) {
3535                 LOG_DEBUG("[%s] Cannot access tselect register. "
3536                                 "Assuming that triggers are not implemented.", target_name(target));
3537                 r->trigger_count = 0;
3538                 return ERROR_OK;
3539         }
3540
3541         for (unsigned int t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
3542                 r->trigger_count = t;
3543
3544                 /* If we can't write tselect, then this hart does not support triggers. */
3545                 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
3546                         break;
3547                 uint64_t tselect_rb;
3548                 result = riscv_get_register(target, &tselect_rb, GDB_REGNO_TSELECT);
3549                 if (result != ERROR_OK)
3550                         return result;
3551                 /* Mask off the top bit, which is used as tdrmode in old
3552                         * implementations. */
3553                 tselect_rb &= ~(1ULL << (riscv_xlen(target) - 1));
3554                 if (tselect_rb != t)
3555                         break;
3556                 uint64_t tdata1;
3557                 result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
3558                 if (result != ERROR_OK)
3559                         return result;
3560
3561                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
3562                 if (type == 0)
3563                         break;
3564                 switch (type) {
3565                         case 1:
3566                                 /* On these older cores we don't support software using
3567                                         * triggers. */
3568                                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3569                                 break;
3570                         case 2:
3571                                 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3572                                         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3573                                 break;
3574                         case 6:
3575                                 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3576                                         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3577                                 break;
3578                 }
3579         }
3580
3581         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
3582
3583         LOG_INFO("[%s] Found %d triggers", target_name(target), r->trigger_count);
3584
3585         return ERROR_OK;
3586 }
3587
3588 const char *gdb_regno_name(enum gdb_regno regno)
3589 {
3590         static char buf[32];
3591
3592         switch (regno) {
3593                 case GDB_REGNO_ZERO:
3594                         return "zero";
3595                 case GDB_REGNO_RA:
3596                         return "ra";
3597                 case GDB_REGNO_SP:
3598                         return "sp";
3599                 case GDB_REGNO_GP:
3600                         return "gp";
3601                 case GDB_REGNO_TP:
3602                         return "tp";
3603                 case GDB_REGNO_T0:
3604                         return "t0";
3605                 case GDB_REGNO_T1:
3606                         return "t1";
3607                 case GDB_REGNO_T2:
3608                         return "t2";
3609                 case GDB_REGNO_S0:
3610                         return "s0";
3611                 case GDB_REGNO_S1:
3612                         return "s1";
3613                 case GDB_REGNO_A0:
3614                         return "a0";
3615                 case GDB_REGNO_A1:
3616                         return "a1";
3617                 case GDB_REGNO_A2:
3618                         return "a2";
3619                 case GDB_REGNO_A3:
3620                         return "a3";
3621                 case GDB_REGNO_A4:
3622                         return "a4";
3623                 case GDB_REGNO_A5:
3624                         return "a5";
3625                 case GDB_REGNO_A6:
3626                         return "a6";
3627                 case GDB_REGNO_A7:
3628                         return "a7";
3629                 case GDB_REGNO_S2:
3630                         return "s2";
3631                 case GDB_REGNO_S3:
3632                         return "s3";
3633                 case GDB_REGNO_S4:
3634                         return "s4";
3635                 case GDB_REGNO_S5:
3636                         return "s5";
3637                 case GDB_REGNO_S6:
3638                         return "s6";
3639                 case GDB_REGNO_S7:
3640                         return "s7";
3641                 case GDB_REGNO_S8:
3642                         return "s8";
3643                 case GDB_REGNO_S9:
3644                         return "s9";
3645                 case GDB_REGNO_S10:
3646                         return "s10";
3647                 case GDB_REGNO_S11:
3648                         return "s11";
3649                 case GDB_REGNO_T3:
3650                         return "t3";
3651                 case GDB_REGNO_T4:
3652                         return "t4";
3653                 case GDB_REGNO_T5:
3654                         return "t5";
3655                 case GDB_REGNO_T6:
3656                         return "t6";
3657                 case GDB_REGNO_PC:
3658                         return "pc";
3659                 case GDB_REGNO_FPR0:
3660                         return "fpr0";
3661                 case GDB_REGNO_FPR31:
3662                         return "fpr31";
3663                 case GDB_REGNO_CSR0:
3664                         return "csr0";
3665                 case GDB_REGNO_TSELECT:
3666                         return "tselect";
3667                 case GDB_REGNO_TDATA1:
3668                         return "tdata1";
3669                 case GDB_REGNO_TDATA2:
3670                         return "tdata2";
3671                 case GDB_REGNO_MISA:
3672                         return "misa";
3673                 case GDB_REGNO_DPC:
3674                         return "dpc";
3675                 case GDB_REGNO_DCSR:
3676                         return "dcsr";
3677                 case GDB_REGNO_DSCRATCH0:
3678                         return "dscratch0";
3679                 case GDB_REGNO_MSTATUS:
3680                         return "mstatus";
3681                 case GDB_REGNO_MEPC:
3682                         return "mepc";
3683                 case GDB_REGNO_MCAUSE:
3684                         return "mcause";
3685                 case GDB_REGNO_PRIV:
3686                         return "priv";
3687                 case GDB_REGNO_SATP:
3688                         return "satp";
3689                 case GDB_REGNO_VTYPE:
3690                         return "vtype";
3691                 case GDB_REGNO_VL:
3692                         return "vl";
3693                 case GDB_REGNO_V0:
3694                         return "v0";
3695                 case GDB_REGNO_V1:
3696                         return "v1";
3697                 case GDB_REGNO_V2:
3698                         return "v2";
3699                 case GDB_REGNO_V3:
3700                         return "v3";
3701                 case GDB_REGNO_V4:
3702                         return "v4";
3703                 case GDB_REGNO_V5:
3704                         return "v5";
3705                 case GDB_REGNO_V6:
3706                         return "v6";
3707                 case GDB_REGNO_V7:
3708                         return "v7";
3709                 case GDB_REGNO_V8:
3710                         return "v8";
3711                 case GDB_REGNO_V9:
3712                         return "v9";
3713                 case GDB_REGNO_V10:
3714                         return "v10";
3715                 case GDB_REGNO_V11:
3716                         return "v11";
3717                 case GDB_REGNO_V12:
3718                         return "v12";
3719                 case GDB_REGNO_V13:
3720                         return "v13";
3721                 case GDB_REGNO_V14:
3722                         return "v14";
3723                 case GDB_REGNO_V15:
3724                         return "v15";
3725                 case GDB_REGNO_V16:
3726                         return "v16";
3727                 case GDB_REGNO_V17:
3728                         return "v17";
3729                 case GDB_REGNO_V18:
3730                         return "v18";
3731                 case GDB_REGNO_V19:
3732                         return "v19";
3733                 case GDB_REGNO_V20:
3734                         return "v20";
3735                 case GDB_REGNO_V21:
3736                         return "v21";
3737                 case GDB_REGNO_V22:
3738                         return "v22";
3739                 case GDB_REGNO_V23:
3740                         return "v23";
3741                 case GDB_REGNO_V24:
3742                         return "v24";
3743                 case GDB_REGNO_V25:
3744                         return "v25";
3745                 case GDB_REGNO_V26:
3746                         return "v26";
3747                 case GDB_REGNO_V27:
3748                         return "v27";
3749                 case GDB_REGNO_V28:
3750                         return "v28";
3751                 case GDB_REGNO_V29:
3752                         return "v29";
3753                 case GDB_REGNO_V30:
3754                         return "v30";
3755                 case GDB_REGNO_V31:
3756                         return "v31";
3757                 default:
3758                         if (regno <= GDB_REGNO_XPR31)
3759                                 sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
3760                         else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095)
3761                                 sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0);
3762                         else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31)
3763                                 sprintf(buf, "f%d", regno - GDB_REGNO_FPR0);
3764                         else
3765                                 sprintf(buf, "gdb_regno_%d", regno);
3766                         return buf;
3767         }
3768 }
3769
3770 static int register_get(struct reg *reg)
3771 {
3772         riscv_reg_info_t *reg_info = reg->arch_info;
3773         struct target *target = reg_info->target;
3774         RISCV_INFO(r);
3775
3776         if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3777                 if (!r->get_register_buf) {
3778                         LOG_ERROR("Reading register %s not supported on this RISC-V target.",
3779                                         gdb_regno_name(reg->number));
3780                         return ERROR_FAIL;
3781                 }
3782
3783                 if (r->get_register_buf(target, reg->value, reg->number) != ERROR_OK)
3784                         return ERROR_FAIL;
3785         } else {
3786                 uint64_t value;
3787                 int result = riscv_get_register(target, &value, reg->number);
3788                 if (result != ERROR_OK)
3789                         return result;
3790                 buf_set_u64(reg->value, 0, reg->size, value);
3791         }
3792         reg->valid = gdb_regno_cacheable(reg->number, false);
3793         char *str = buf_to_hex_str(reg->value, reg->size);
3794         LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target),
3795                         str, reg->name, reg->valid);
3796         free(str);
3797         return ERROR_OK;
3798 }
3799
3800 static int register_set(struct reg *reg, uint8_t *buf)
3801 {
3802         riscv_reg_info_t *reg_info = reg->arch_info;
3803         struct target *target = reg_info->target;
3804         RISCV_INFO(r);
3805
3806         char *str = buf_to_hex_str(buf, reg->size);
3807         LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target),
3808                         str, reg->name, reg->valid);
3809         free(str);
3810
3811         /* Exit early for writing x0, which on the hardware would be ignored, and we
3812          * don't want to update our cache. */
3813         if (reg->number == GDB_REGNO_ZERO)
3814                 return ERROR_OK;
3815
3816         memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
3817         reg->valid = gdb_regno_cacheable(reg->number, true);
3818
3819         if (reg->number == GDB_REGNO_TDATA1 ||
3820                         reg->number == GDB_REGNO_TDATA2) {
3821                 r->manual_hwbp_set = true;
3822                 /* When enumerating triggers, we clear any triggers with DMODE set,
3823                  * assuming they were left over from a previous debug session. So make
3824                  * sure that is done before a user might be setting their own triggers.
3825                  */
3826                 if (riscv_enumerate_triggers(target) != ERROR_OK)
3827                         return ERROR_FAIL;
3828         }
3829
3830         if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3831                 if (!r->set_register_buf) {
3832                         LOG_ERROR("Writing register %s not supported on this RISC-V target.",
3833                                         gdb_regno_name(reg->number));
3834                         return ERROR_FAIL;
3835                 }
3836
3837                 if (r->set_register_buf(target, reg->number, reg->value) != ERROR_OK)
3838                         return ERROR_FAIL;
3839         } else {
3840                 uint64_t value = buf_get_u64(buf, 0, reg->size);
3841                 if (riscv_set_register(target, reg->number, value) != ERROR_OK)
3842                         return ERROR_FAIL;
3843         }
3844
3845         return ERROR_OK;
3846 }
3847
3848 static struct reg_arch_type riscv_reg_arch_type = {
3849         .get = register_get,
3850         .set = register_set
3851 };
3852
3853 struct csr_info {
3854         unsigned number;
3855         const char *name;
3856 };
3857
3858 static int cmp_csr_info(const void *p1, const void *p2)
3859 {
3860         return (int) (((struct csr_info *)p1)->number) - (int) (((struct csr_info *)p2)->number);
3861 }
3862
3863 int riscv_init_registers(struct target *target)
3864 {
3865         RISCV_INFO(info);
3866
3867         riscv_free_registers(target);
3868
3869         target->reg_cache = calloc(1, sizeof(*target->reg_cache));
3870         if (!target->reg_cache)
3871                 return ERROR_FAIL;
3872         target->reg_cache->name = "RISC-V Registers";
3873         target->reg_cache->num_regs = GDB_REGNO_COUNT;
3874
3875         if (!list_empty(&info->expose_custom)) {
3876                 range_list_t *entry;
3877                 list_for_each_entry(entry, &info->expose_custom, list)
3878                         target->reg_cache->num_regs += entry->high - entry->low + 1;
3879         }
3880
3881         LOG_DEBUG("create register cache for %d registers",
3882                         target->reg_cache->num_regs);
3883
3884         target->reg_cache->reg_list =
3885                 calloc(target->reg_cache->num_regs, sizeof(struct reg));
3886         if (!target->reg_cache->reg_list)
3887                 return ERROR_FAIL;
3888
3889         const unsigned int max_reg_name_len = 12;
3890         free(info->reg_names);
3891         info->reg_names =
3892                 calloc(target->reg_cache->num_regs, max_reg_name_len);
3893         if (!info->reg_names)
3894                 return ERROR_FAIL;
3895         char *reg_name = info->reg_names;
3896
3897         static struct reg_feature feature_cpu = {
3898                 .name = "org.gnu.gdb.riscv.cpu"
3899         };
3900         static struct reg_feature feature_fpu = {
3901                 .name = "org.gnu.gdb.riscv.fpu"
3902         };
3903         static struct reg_feature feature_csr = {
3904                 .name = "org.gnu.gdb.riscv.csr"
3905         };
3906         static struct reg_feature feature_vector = {
3907                 .name = "org.gnu.gdb.riscv.vector"
3908         };
3909         static struct reg_feature feature_virtual = {
3910                 .name = "org.gnu.gdb.riscv.virtual"
3911         };
3912         static struct reg_feature feature_custom = {
3913                 .name = "org.gnu.gdb.riscv.custom"
3914         };
3915
3916         /* These types are built into gdb. */
3917         static struct reg_data_type type_ieee_single = { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" };
3918         static struct reg_data_type type_ieee_double = { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" };
3919         static struct reg_data_type_union_field single_double_fields[] = {
3920                 {"float", &type_ieee_single, single_double_fields + 1},
3921                 {"double", &type_ieee_double, NULL},
3922         };
3923         static struct reg_data_type_union single_double_union = {
3924                 .fields = single_double_fields
3925         };
3926         static struct reg_data_type type_ieee_single_double = {
3927                 .type = REG_TYPE_ARCH_DEFINED,
3928                 .id = "FPU_FD",
3929                 .type_class = REG_TYPE_CLASS_UNION,
3930                 .reg_type_union = &single_double_union
3931         };
3932         static struct reg_data_type type_uint8 = { .type = REG_TYPE_UINT8, .id = "uint8" };
3933         static struct reg_data_type type_uint16 = { .type = REG_TYPE_UINT16, .id = "uint16" };
3934         static struct reg_data_type type_uint32 = { .type = REG_TYPE_UINT32, .id = "uint32" };
3935         static struct reg_data_type type_uint64 = { .type = REG_TYPE_UINT64, .id = "uint64" };
3936         static struct reg_data_type type_uint128 = { .type = REG_TYPE_UINT128, .id = "uint128" };
3937
3938         /* This is roughly the XML we want:
3939          * <vector id="bytes" type="uint8" count="16"/>
3940          * <vector id="shorts" type="uint16" count="8"/>
3941          * <vector id="words" type="uint32" count="4"/>
3942          * <vector id="longs" type="uint64" count="2"/>
3943          * <vector id="quads" type="uint128" count="1"/>
3944          * <union id="riscv_vector_type">
3945          *   <field name="b" type="bytes"/>
3946          *   <field name="s" type="shorts"/>
3947          *   <field name="w" type="words"/>
3948          *   <field name="l" type="longs"/>
3949          *   <field name="q" type="quads"/>
3950          * </union>
3951          */
3952
3953         info->vector_uint8.type = &type_uint8;
3954         info->vector_uint8.count = info->vlenb;
3955         info->type_uint8_vector.type = REG_TYPE_ARCH_DEFINED;
3956         info->type_uint8_vector.id = "bytes";
3957         info->type_uint8_vector.type_class = REG_TYPE_CLASS_VECTOR;
3958         info->type_uint8_vector.reg_type_vector = &info->vector_uint8;
3959
3960         info->vector_uint16.type = &type_uint16;
3961         info->vector_uint16.count = info->vlenb / 2;
3962         info->type_uint16_vector.type = REG_TYPE_ARCH_DEFINED;
3963         info->type_uint16_vector.id = "shorts";
3964         info->type_uint16_vector.type_class = REG_TYPE_CLASS_VECTOR;
3965         info->type_uint16_vector.reg_type_vector = &info->vector_uint16;
3966
3967         info->vector_uint32.type = &type_uint32;
3968         info->vector_uint32.count = info->vlenb / 4;
3969         info->type_uint32_vector.type = REG_TYPE_ARCH_DEFINED;
3970         info->type_uint32_vector.id = "words";
3971         info->type_uint32_vector.type_class = REG_TYPE_CLASS_VECTOR;
3972         info->type_uint32_vector.reg_type_vector = &info->vector_uint32;
3973
3974         info->vector_uint64.type = &type_uint64;
3975         info->vector_uint64.count = info->vlenb / 8;
3976         info->type_uint64_vector.type = REG_TYPE_ARCH_DEFINED;
3977         info->type_uint64_vector.id = "longs";
3978         info->type_uint64_vector.type_class = REG_TYPE_CLASS_VECTOR;
3979         info->type_uint64_vector.reg_type_vector = &info->vector_uint64;
3980
3981         info->vector_uint128.type = &type_uint128;
3982         info->vector_uint128.count = info->vlenb / 16;
3983         info->type_uint128_vector.type = REG_TYPE_ARCH_DEFINED;
3984         info->type_uint128_vector.id = "quads";
3985         info->type_uint128_vector.type_class = REG_TYPE_CLASS_VECTOR;
3986         info->type_uint128_vector.reg_type_vector = &info->vector_uint128;
3987
3988         info->vector_fields[0].name = "b";
3989         info->vector_fields[0].type = &info->type_uint8_vector;
3990         if (info->vlenb >= 2) {
3991                 info->vector_fields[0].next = info->vector_fields + 1;
3992                 info->vector_fields[1].name = "s";
3993                 info->vector_fields[1].type = &info->type_uint16_vector;
3994         } else {
3995                 info->vector_fields[0].next = NULL;
3996         }
3997         if (info->vlenb >= 4) {
3998                 info->vector_fields[1].next = info->vector_fields + 2;
3999                 info->vector_fields[2].name = "w";
4000                 info->vector_fields[2].type = &info->type_uint32_vector;
4001         } else {
4002                 info->vector_fields[1].next = NULL;
4003         }
4004         if (info->vlenb >= 8) {
4005                 info->vector_fields[2].next = info->vector_fields + 3;
4006                 info->vector_fields[3].name = "l";
4007                 info->vector_fields[3].type = &info->type_uint64_vector;
4008         } else {
4009                 info->vector_fields[2].next = NULL;
4010         }
4011         if (info->vlenb >= 16) {
4012                 info->vector_fields[3].next = info->vector_fields + 4;
4013                 info->vector_fields[4].name = "q";
4014                 info->vector_fields[4].type = &info->type_uint128_vector;
4015         } else {
4016                 info->vector_fields[3].next = NULL;
4017         }
4018         info->vector_fields[4].next = NULL;
4019
4020         info->vector_union.fields = info->vector_fields;
4021
4022         info->type_vector.type = REG_TYPE_ARCH_DEFINED;
4023         info->type_vector.id = "riscv_vector";
4024         info->type_vector.type_class = REG_TYPE_CLASS_UNION;
4025         info->type_vector.reg_type_union = &info->vector_union;
4026
4027         struct csr_info csr_info[] = {
4028 #define DECLARE_CSR(name, number) { number, #name },
4029 #include "encoding.h"
4030 #undef DECLARE_CSR
4031         };
4032         /* encoding.h does not contain the registers in sorted order. */
4033         qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info);
4034         unsigned csr_info_index = 0;
4035
4036         int custom_within_range = 0;
4037
4038         riscv_reg_info_t *shared_reg_info = calloc(1, sizeof(riscv_reg_info_t));
4039         if (!shared_reg_info)
4040                 return ERROR_FAIL;
4041         shared_reg_info->target = target;
4042
4043         /* When gdb requests register N, gdb_get_register_packet() assumes that this
4044          * is register at index N in reg_list. So if there are certain registers
4045          * that don't exist, we need to leave holes in the list (or renumber, but
4046          * it would be nice not to have yet another set of numbers to translate
4047          * between). */
4048         for (uint32_t number = 0; number < target->reg_cache->num_regs; number++) {
4049                 struct reg *r = &target->reg_cache->reg_list[number];
4050                 r->dirty = false;
4051                 r->valid = false;
4052                 r->exist = true;
4053                 r->type = &riscv_reg_arch_type;
4054                 r->arch_info = shared_reg_info;
4055                 r->number = number;
4056                 r->size = riscv_xlen(target);
4057                 /* r->size is set in riscv_invalidate_register_cache, maybe because the
4058                  * target is in theory allowed to change XLEN on us. But I expect a lot
4059                  * of other things to break in that case as well. */
4060                 if (number <= GDB_REGNO_XPR31) {
4061                         r->exist = number <= GDB_REGNO_XPR15 ||
4062                                 !riscv_supports_extension(target, 'E');
4063                         /* TODO: For now we fake that all GPRs exist because otherwise gdb
4064                          * doesn't work. */
4065                         r->exist = true;
4066                         r->caller_save = true;
4067                         switch (number) {
4068                                 case GDB_REGNO_ZERO:
4069                                         r->name = "zero";
4070                                         break;
4071                                 case GDB_REGNO_RA:
4072                                         r->name = "ra";
4073                                         break;
4074                                 case GDB_REGNO_SP:
4075                                         r->name = "sp";
4076                                         break;
4077                                 case GDB_REGNO_GP:
4078                                         r->name = "gp";
4079                                         break;
4080                                 case GDB_REGNO_TP:
4081                                         r->name = "tp";
4082                                         break;
4083                                 case GDB_REGNO_T0:
4084                                         r->name = "t0";
4085                                         break;
4086                                 case GDB_REGNO_T1:
4087                                         r->name = "t1";
4088                                         break;
4089                                 case GDB_REGNO_T2:
4090                                         r->name = "t2";
4091                                         break;
4092                                 case GDB_REGNO_FP:
4093                                         r->name = "fp";
4094                                         break;
4095                                 case GDB_REGNO_S1:
4096                                         r->name = "s1";
4097                                         break;
4098                                 case GDB_REGNO_A0:
4099                                         r->name = "a0";
4100                                         break;
4101                                 case GDB_REGNO_A1:
4102                                         r->name = "a1";
4103                                         break;
4104                                 case GDB_REGNO_A2:
4105                                         r->name = "a2";
4106                                         break;
4107                                 case GDB_REGNO_A3:
4108                                         r->name = "a3";
4109                                         break;
4110                                 case GDB_REGNO_A4:
4111                                         r->name = "a4";
4112                                         break;
4113                                 case GDB_REGNO_A5:
4114                                         r->name = "a5";
4115                                         break;
4116                                 case GDB_REGNO_A6:
4117                                         r->name = "a6";
4118                                         break;
4119                                 case GDB_REGNO_A7:
4120                                         r->name = "a7";
4121                                         break;
4122                                 case GDB_REGNO_S2:
4123                                         r->name = "s2";
4124                                         break;
4125                                 case GDB_REGNO_S3:
4126                                         r->name = "s3";
4127                                         break;
4128                                 case GDB_REGNO_S4:
4129                                         r->name = "s4";
4130                                         break;
4131                                 case GDB_REGNO_S5:
4132                                         r->name = "s5";
4133                                         break;
4134                                 case GDB_REGNO_S6:
4135                                         r->name = "s6";
4136                                         break;
4137                                 case GDB_REGNO_S7:
4138                                         r->name = "s7";
4139                                         break;
4140                                 case GDB_REGNO_S8:
4141                                         r->name = "s8";
4142                                         break;
4143                                 case GDB_REGNO_S9:
4144                                         r->name = "s9";
4145                                         break;
4146                                 case GDB_REGNO_S10:
4147                                         r->name = "s10";
4148                                         break;
4149                                 case GDB_REGNO_S11:
4150                                         r->name = "s11";
4151                                         break;
4152                                 case GDB_REGNO_T3:
4153                                         r->name = "t3";
4154                                         break;
4155                                 case GDB_REGNO_T4:
4156                                         r->name = "t4";
4157                                         break;
4158                                 case GDB_REGNO_T5:
4159                                         r->name = "t5";
4160                                         break;
4161                                 case GDB_REGNO_T6:
4162                                         r->name = "t6";
4163                                         break;
4164                         }
4165                         r->group = "general";
4166                         r->feature = &feature_cpu;
4167                 } else if (number == GDB_REGNO_PC) {
4168                         r->caller_save = true;
4169                         sprintf(reg_name, "pc");
4170                         r->group = "general";
4171                         r->feature = &feature_cpu;
4172                 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
4173                         r->caller_save = true;
4174                         if (riscv_supports_extension(target, 'D')) {
4175                                 r->size = 64;
4176                                 if (riscv_supports_extension(target, 'F'))
4177                                         r->reg_data_type = &type_ieee_single_double;
4178                                 else
4179                                         r->reg_data_type = &type_ieee_double;
4180                         } else if (riscv_supports_extension(target, 'F')) {
4181                                 r->reg_data_type = &type_ieee_single;
4182                                 r->size = 32;
4183                         } else {
4184                                 r->exist = false;
4185                         }
4186                         switch (number) {
4187                                 case GDB_REGNO_FT0:
4188                                         r->name = "ft0";
4189                                         break;
4190                                 case GDB_REGNO_FT1:
4191                                         r->name = "ft1";
4192                                         break;
4193                                 case GDB_REGNO_FT2:
4194                                         r->name = "ft2";
4195                                         break;
4196                                 case GDB_REGNO_FT3:
4197                                         r->name = "ft3";
4198                                         break;
4199                                 case GDB_REGNO_FT4:
4200                                         r->name = "ft4";
4201                                         break;
4202                                 case GDB_REGNO_FT5:
4203                                         r->name = "ft5";
4204                                         break;
4205                                 case GDB_REGNO_FT6:
4206                                         r->name = "ft6";
4207                                         break;
4208                                 case GDB_REGNO_FT7:
4209                                         r->name = "ft7";
4210                                         break;
4211                                 case GDB_REGNO_FS0:
4212                                         r->name = "fs0";
4213                                         break;
4214                                 case GDB_REGNO_FS1:
4215                                         r->name = "fs1";
4216                                         break;
4217                                 case GDB_REGNO_FA0:
4218                                         r->name = "fa0";
4219                                         break;
4220                                 case GDB_REGNO_FA1:
4221                                         r->name = "fa1";
4222                                         break;
4223                                 case GDB_REGNO_FA2:
4224                                         r->name = "fa2";
4225                                         break;
4226                                 case GDB_REGNO_FA3:
4227                                         r->name = "fa3";
4228                                         break;
4229                                 case GDB_REGNO_FA4:
4230                                         r->name = "fa4";
4231                                         break;
4232                                 case GDB_REGNO_FA5:
4233                                         r->name = "fa5";
4234                                         break;
4235                                 case GDB_REGNO_FA6:
4236                                         r->name = "fa6";
4237                                         break;
4238                                 case GDB_REGNO_FA7:
4239                                         r->name = "fa7";
4240                                         break;
4241                                 case GDB_REGNO_FS2:
4242                                         r->name = "fs2";
4243                                         break;
4244                                 case GDB_REGNO_FS3:
4245                                         r->name = "fs3";
4246                                         break;
4247                                 case GDB_REGNO_FS4:
4248                                         r->name = "fs4";
4249                                         break;
4250                                 case GDB_REGNO_FS5:
4251                                         r->name = "fs5";
4252                                         break;
4253                                 case GDB_REGNO_FS6:
4254                                         r->name = "fs6";
4255                                         break;
4256                                 case GDB_REGNO_FS7:
4257                                         r->name = "fs7";
4258                                         break;
4259                                 case GDB_REGNO_FS8:
4260                                         r->name = "fs8";
4261                                         break;
4262                                 case GDB_REGNO_FS9:
4263                                         r->name = "fs9";
4264                                         break;
4265                                 case GDB_REGNO_FS10:
4266                                         r->name = "fs10";
4267                                         break;
4268                                 case GDB_REGNO_FS11:
4269                                         r->name = "fs11";
4270                                         break;
4271                                 case GDB_REGNO_FT8:
4272                                         r->name = "ft8";
4273                                         break;
4274                                 case GDB_REGNO_FT9:
4275                                         r->name = "ft9";
4276                                         break;
4277                                 case GDB_REGNO_FT10:
4278                                         r->name = "ft10";
4279                                         break;
4280                                 case GDB_REGNO_FT11:
4281                                         r->name = "ft11";
4282                                         break;
4283                         }
4284                         r->group = "float";
4285                         r->feature = &feature_fpu;
4286                 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
4287                         r->group = "csr";
4288                         r->feature = &feature_csr;
4289                         unsigned csr_number = number - GDB_REGNO_CSR0;
4290
4291                         while (csr_info[csr_info_index].number < csr_number &&
4292                                         csr_info_index < ARRAY_SIZE(csr_info) - 1) {
4293                                 csr_info_index++;
4294                         }
4295                         if (csr_info[csr_info_index].number == csr_number) {
4296                                 r->name = csr_info[csr_info_index].name;
4297                         } else {
4298                                 sprintf(reg_name, "csr%d", csr_number);
4299                                 /* Assume unnamed registers don't exist, unless we have some
4300                                  * configuration that tells us otherwise. That's important
4301                                  * because eg. Eclipse crashes if a target has too many
4302                                  * registers, and apparently has no way of only showing a
4303                                  * subset of registers in any case. */
4304                                 r->exist = false;
4305                         }
4306
4307                         switch (csr_number) {
4308                                 case CSR_FFLAGS:
4309                                 case CSR_FRM:
4310                                 case CSR_FCSR:
4311                                         r->exist = riscv_supports_extension(target, 'F');
4312                                         r->group = "float";
4313                                         r->feature = &feature_fpu;
4314                                         break;
4315                                 case CSR_SSTATUS:
4316                                 case CSR_STVEC:
4317                                 case CSR_SIP:
4318                                 case CSR_SIE:
4319                                 case CSR_SCOUNTEREN:
4320                                 case CSR_SSCRATCH:
4321                                 case CSR_SEPC:
4322                                 case CSR_SCAUSE:
4323                                 case CSR_STVAL:
4324                                 case CSR_SATP:
4325                                         r->exist = riscv_supports_extension(target, 'S');
4326                                         break;
4327                                 case CSR_MEDELEG:
4328                                 case CSR_MIDELEG:
4329                                         /* "In systems with only M-mode, or with both M-mode and
4330                                          * U-mode but without U-mode trap support, the medeleg and
4331                                          * mideleg registers should not exist." */
4332                                         r->exist = riscv_supports_extension(target, 'S') ||
4333                                                 riscv_supports_extension(target, 'N');
4334                                         break;
4335
4336                                 case CSR_PMPCFG1:
4337                                 case CSR_PMPCFG3:
4338                                 case CSR_CYCLEH:
4339                                 case CSR_TIMEH:
4340                                 case CSR_INSTRETH:
4341                                 case CSR_HPMCOUNTER3H:
4342                                 case CSR_HPMCOUNTER4H:
4343                                 case CSR_HPMCOUNTER5H:
4344                                 case CSR_HPMCOUNTER6H:
4345                                 case CSR_HPMCOUNTER7H:
4346                                 case CSR_HPMCOUNTER8H:
4347                                 case CSR_HPMCOUNTER9H:
4348                                 case CSR_HPMCOUNTER10H:
4349                                 case CSR_HPMCOUNTER11H:
4350                                 case CSR_HPMCOUNTER12H:
4351                                 case CSR_HPMCOUNTER13H:
4352                                 case CSR_HPMCOUNTER14H:
4353                                 case CSR_HPMCOUNTER15H:
4354                                 case CSR_HPMCOUNTER16H:
4355                                 case CSR_HPMCOUNTER17H:
4356                                 case CSR_HPMCOUNTER18H:
4357                                 case CSR_HPMCOUNTER19H:
4358                                 case CSR_HPMCOUNTER20H:
4359                                 case CSR_HPMCOUNTER21H:
4360                                 case CSR_HPMCOUNTER22H:
4361                                 case CSR_HPMCOUNTER23H:
4362                                 case CSR_HPMCOUNTER24H:
4363                                 case CSR_HPMCOUNTER25H:
4364                                 case CSR_HPMCOUNTER26H:
4365                                 case CSR_HPMCOUNTER27H:
4366                                 case CSR_HPMCOUNTER28H:
4367                                 case CSR_HPMCOUNTER29H:
4368                                 case CSR_HPMCOUNTER30H:
4369                                 case CSR_HPMCOUNTER31H:
4370                                 case CSR_MCYCLEH:
4371                                 case CSR_MINSTRETH:
4372                                 case CSR_MHPMCOUNTER3H:
4373                                 case CSR_MHPMCOUNTER4H:
4374                                 case CSR_MHPMCOUNTER5H:
4375                                 case CSR_MHPMCOUNTER6H:
4376                                 case CSR_MHPMCOUNTER7H:
4377                                 case CSR_MHPMCOUNTER8H:
4378                                 case CSR_MHPMCOUNTER9H:
4379                                 case CSR_MHPMCOUNTER10H:
4380                                 case CSR_MHPMCOUNTER11H:
4381                                 case CSR_MHPMCOUNTER12H:
4382                                 case CSR_MHPMCOUNTER13H:
4383                                 case CSR_MHPMCOUNTER14H:
4384                                 case CSR_MHPMCOUNTER15H:
4385                                 case CSR_MHPMCOUNTER16H:
4386                                 case CSR_MHPMCOUNTER17H:
4387                                 case CSR_MHPMCOUNTER18H:
4388                                 case CSR_MHPMCOUNTER19H:
4389                                 case CSR_MHPMCOUNTER20H:
4390                                 case CSR_MHPMCOUNTER21H:
4391                                 case CSR_MHPMCOUNTER22H:
4392                                 case CSR_MHPMCOUNTER23H:
4393                                 case CSR_MHPMCOUNTER24H:
4394                                 case CSR_MHPMCOUNTER25H:
4395                                 case CSR_MHPMCOUNTER26H:
4396                                 case CSR_MHPMCOUNTER27H:
4397                                 case CSR_MHPMCOUNTER28H:
4398                                 case CSR_MHPMCOUNTER29H:
4399                                 case CSR_MHPMCOUNTER30H:
4400                                 case CSR_MHPMCOUNTER31H:
4401                                         r->exist = riscv_xlen(target) == 32;
4402                                         break;
4403
4404                                 case CSR_VSTART:
4405                                 case CSR_VXSAT:
4406                                 case CSR_VXRM:
4407                                 case CSR_VL:
4408                                 case CSR_VTYPE:
4409                                 case CSR_VLENB:
4410                                         r->exist = riscv_supports_extension(target, 'V');
4411                                         break;
4412                         }
4413
4414                         if (!r->exist && !list_empty(&info->expose_csr)) {
4415                                 range_list_t *entry;
4416                                 list_for_each_entry(entry, &info->expose_csr, list)
4417                                         if ((entry->low <= csr_number) && (csr_number <= entry->high)) {
4418                                                 if (entry->name) {
4419                                                         *reg_name = 0;
4420                                                         r->name = entry->name;
4421                                                 }
4422
4423                                                 LOG_DEBUG("Exposing additional CSR %d (name=%s)",
4424                                                                 csr_number, entry->name ? entry->name : reg_name);
4425
4426                                                 r->exist = true;
4427                                                 break;
4428                                         }
4429                         }
4430
4431                 } else if (number == GDB_REGNO_PRIV) {
4432                         sprintf(reg_name, "priv");
4433                         r->group = "general";
4434                         r->feature = &feature_virtual;
4435                         r->size = 8;
4436
4437                 } else if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31) {
4438                         r->caller_save = false;
4439                         r->exist = riscv_supports_extension(target, 'V') && info->vlenb;
4440                         r->size = info->vlenb * 8;
4441                         sprintf(reg_name, "v%d", number - GDB_REGNO_V0);
4442                         r->group = "vector";
4443                         r->feature = &feature_vector;
4444                         r->reg_data_type = &info->type_vector;
4445
4446                 } else if (number >= GDB_REGNO_COUNT) {
4447                         /* Custom registers. */
4448                         assert(!list_empty(&info->expose_custom));
4449
4450                         range_list_t *range = list_first_entry(&info->expose_custom, range_list_t, list);
4451
4452                         unsigned custom_number = range->low + custom_within_range;
4453
4454                         r->group = "custom";
4455                         r->feature = &feature_custom;
4456                         r->arch_info = calloc(1, sizeof(riscv_reg_info_t));
4457                         if (!r->arch_info)
4458                                 return ERROR_FAIL;
4459                         ((riscv_reg_info_t *) r->arch_info)->target = target;
4460                         ((riscv_reg_info_t *) r->arch_info)->custom_number = custom_number;
4461                         sprintf(reg_name, "custom%d", custom_number);
4462
4463                         if (range->name) {
4464                                 *reg_name = 0;
4465                                 r->name = range->name;
4466                         }
4467
4468                         LOG_DEBUG("Exposing additional custom register %d (name=%s)",
4469                                         number, range->name ? range->name : reg_name);
4470
4471                         custom_within_range++;
4472                         if (custom_within_range > range->high - range->low) {
4473                                 custom_within_range = 0;
4474                                 list_rotate_left(&info->expose_custom);
4475                         }
4476                 }
4477
4478                 if (reg_name[0]) {
4479                         r->name = reg_name;
4480                         reg_name += strlen(reg_name) + 1;
4481                         assert(reg_name < info->reg_names + target->reg_cache->num_regs *
4482                                         max_reg_name_len);
4483                 }
4484                 r->value = calloc(1, DIV_ROUND_UP(r->size, 8));
4485         }
4486
4487         return ERROR_OK;
4488 }
4489
4490
4491 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
4492                                         riscv_bscan_tunneled_scan_context_t *ctxt)
4493 {
4494         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
4495
4496         memset(ctxt->tunneled_dr, 0, sizeof(ctxt->tunneled_dr));
4497         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
4498                 ctxt->tunneled_dr[3].num_bits = 1;
4499                 ctxt->tunneled_dr[3].out_value = bscan_one;
4500                 ctxt->tunneled_dr[2].num_bits = 7;
4501                 ctxt->tunneled_dr_width = field->num_bits;
4502                 ctxt->tunneled_dr[2].out_value = &ctxt->tunneled_dr_width;
4503                 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4504                    scanning num_bits + 1, and then will right shift the input field after executing the queues */
4505
4506                 ctxt->tunneled_dr[1].num_bits = field->num_bits + 1;
4507                 ctxt->tunneled_dr[1].out_value = field->out_value;
4508                 ctxt->tunneled_dr[1].in_value = field->in_value;
4509
4510                 ctxt->tunneled_dr[0].num_bits = 3;
4511                 ctxt->tunneled_dr[0].out_value = bscan_zero;
4512         } else {
4513                 /* BSCAN_TUNNEL_NESTED_TAP */
4514                 ctxt->tunneled_dr[0].num_bits = 1;
4515                 ctxt->tunneled_dr[0].out_value = bscan_one;
4516                 ctxt->tunneled_dr[1].num_bits = 7;
4517                 ctxt->tunneled_dr_width = field->num_bits;
4518                 ctxt->tunneled_dr[1].out_value = &ctxt->tunneled_dr_width;
4519                 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4520                    scanning num_bits + 1, and then will right shift the input field after executing the queues */
4521                 ctxt->tunneled_dr[2].num_bits = field->num_bits + 1;
4522                 ctxt->tunneled_dr[2].out_value = field->out_value;
4523                 ctxt->tunneled_dr[2].in_value = field->in_value;
4524                 ctxt->tunneled_dr[3].num_bits = 3;
4525                 ctxt->tunneled_dr[3].out_value = bscan_zero;
4526         }
4527         jtag_add_dr_scan(target->tap, ARRAY_SIZE(ctxt->tunneled_dr), ctxt->tunneled_dr, TAP_IDLE);
4528 }