git.gag.com Git - fw/openocd/blob - src/target/riscv/riscv.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <assert.h>
   4 #include <stdlib.h>
   5 #include <time.h>
   6
   7 #ifdef HAVE_CONFIG_H
   8 #include "config.h"
   9 #endif
  10
  11 #include <helper/log.h>
  12 #include <helper/time_support.h>
  13 #include "target/target.h"
  14 #include "target/algorithm.h"
  15 #include "target/target_type.h"
  16 #include <target/smp.h>
  17 #include "jtag/jtag.h"
  18 #include "target/register.h"
  19 #include "target/breakpoints.h"
  20 #include "riscv.h"
  21 #include "gdb_regs.h"
  22 #include "rtos/rtos.h"
  23 #include "debug_defines.h"
  24 #include <helper/bits.h>
  25
  26 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
  27 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
  28
  29 /* Constants for legacy SiFive hardware breakpoints. */
  30 #define CSR_BPCONTROL_X                 (1<<0)
  31 #define CSR_BPCONTROL_W                 (1<<1)
  32 #define CSR_BPCONTROL_R                 (1<<2)
  33 #define CSR_BPCONTROL_U                 (1<<3)
  34 #define CSR_BPCONTROL_S                 (1<<4)
  35 #define CSR_BPCONTROL_H                 (1<<5)
  36 #define CSR_BPCONTROL_M                 (1<<6)
  37 #define CSR_BPCONTROL_BPMATCH   (0xf<<7)
  38 #define CSR_BPCONTROL_BPACTION  (0xff<<11)
  39
  40 #define DEBUG_ROM_START         0x800
  41 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
  42 #define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
  43 #define DEBUG_RAM_START         0x400
  44
  45 #define SETHALTNOT                              0x10c
  46
  47 /*** JTAG registers. ***/
  48
  49 #define DTMCONTROL                                      0x10
  50 #define DTMCONTROL_DBUS_RESET           (1<<16)
  51 #define DTMCONTROL_IDLE                         (7<<10)
  52 #define DTMCONTROL_ADDRBITS                     (0xf<<4)
  53 #define DTMCONTROL_VERSION                      (0xf)
  54
  55 #define DBUS                                            0x11
  56 #define DBUS_OP_START                           0
  57 #define DBUS_OP_SIZE                            2
  58 typedef enum {
  59         DBUS_OP_NOP = 0,
  60         DBUS_OP_READ = 1,
  61         DBUS_OP_WRITE = 2
  62 } dbus_op_t;
  63 typedef enum {
  64         DBUS_STATUS_SUCCESS = 0,
  65         DBUS_STATUS_FAILED = 2,
  66         DBUS_STATUS_BUSY = 3
  67 } dbus_status_t;
  68 #define DBUS_DATA_START                         2
  69 #define DBUS_DATA_SIZE                          34
  70 #define DBUS_ADDRESS_START                      36
  71
  72 typedef enum slot {
  73         SLOT0,
  74         SLOT1,
  75         SLOT_LAST,
  76 } slot_t;
  77
  78 /*** Debug Bus registers. ***/
  79
  80 #define DMCONTROL                               0x10
  81 #define DMCONTROL_INTERRUPT             (((uint64_t)1)<<33)
  82 #define DMCONTROL_HALTNOT               (((uint64_t)1)<<32)
  83 #define DMCONTROL_BUSERROR              (7<<19)
  84 #define DMCONTROL_SERIAL                (3<<16)
  85 #define DMCONTROL_AUTOINCREMENT (1<<15)
  86 #define DMCONTROL_ACCESS                (7<<12)
  87 #define DMCONTROL_HARTID                (0x3ff<<2)
  88 #define DMCONTROL_NDRESET               (1<<1)
  89 #define DMCONTROL_FULLRESET             1
  90
  91 #define DMINFO                                  0x11
  92 #define DMINFO_ABUSSIZE                 (0x7fU<<25)
  93 #define DMINFO_SERIALCOUNT              (0xf<<21)
  94 #define DMINFO_ACCESS128                (1<<20)
  95 #define DMINFO_ACCESS64                 (1<<19)
  96 #define DMINFO_ACCESS32                 (1<<18)
  97 #define DMINFO_ACCESS16                 (1<<17)
  98 #define DMINFO_ACCESS8                  (1<<16)
  99 #define DMINFO_DRAMSIZE                 (0x3f<<10)
 100 #define DMINFO_AUTHENTICATED    (1<<5)
 101 #define DMINFO_AUTHBUSY                 (1<<4)
 102 #define DMINFO_AUTHTYPE                 (3<<2)
 103 #define DMINFO_VERSION                  3
 104
 105 /*** Info about the core being debugged. ***/
 106
 107 #define DBUS_ADDRESS_UNKNOWN    0xffff
 108
 109 #define MAX_HWBPS                       16
 110 #define DRAM_CACHE_SIZE         16
 111
 112 uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
 113 struct scan_field select_dtmcontrol = {
 114         .in_value = NULL,
 115         .out_value = ir_dtmcontrol
 116 };
 117 uint8_t ir_dbus[4] = {DBUS};
 118 struct scan_field select_dbus = {
 119         .in_value = NULL,
 120         .out_value = ir_dbus
 121 };
 122 uint8_t ir_idcode[4] = {0x1};
 123 struct scan_field select_idcode = {
 124         .in_value = NULL,
 125         .out_value = ir_idcode
 126 };
 127
 128 bscan_tunnel_type_t bscan_tunnel_type;
 129 int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
 130
 131 static const uint8_t bscan_zero[4] = {0};
 132 static const uint8_t bscan_one[4] = {1};
 133
 134 uint8_t ir_user4[4];
 135 struct scan_field select_user4 = {
 136         .in_value = NULL,
 137         .out_value = ir_user4
 138 };
 139
 140
 141 uint8_t bscan_tunneled_ir_width[4] = {5};  /* overridden by assignment in riscv_init_target */
 142 struct scan_field _bscan_tunnel_data_register_select_dmi[] = {
 143                 {
 144                         .num_bits = 3,
 145                         .out_value = bscan_zero,
 146                         .in_value = NULL,
 147                 },
 148                 {
 149                         .num_bits = 5, /* initialized in riscv_init_target to ir width of DM */
 150                         .out_value = ir_dbus,
 151                         .in_value = NULL,
 152                 },
 153                 {
 154                         .num_bits = 7,
 155                         .out_value = bscan_tunneled_ir_width,
 156                         .in_value = NULL,
 157                 },
 158                 {
 159                         .num_bits = 1,
 160                         .out_value = bscan_zero,
 161                         .in_value = NULL,
 162                 }
 163 };
 164
 165 struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = {
 166                 {
 167                         .num_bits = 1,
 168                         .out_value = bscan_zero,
 169                         .in_value = NULL,
 170                 },
 171                 {
 172                         .num_bits = 7,
 173                         .out_value = bscan_tunneled_ir_width,
 174                         .in_value = NULL,
 175                 },
 176                 {
 177                         .num_bits = 0, /* initialized in riscv_init_target to ir width of DM */
 178                         .out_value = ir_dbus,
 179                         .in_value = NULL,
 180                 },
 181                 {
 182                         .num_bits = 3,
 183                         .out_value = bscan_zero,
 184                         .in_value = NULL,
 185                 }
 186 };
 187 struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi;
 188 uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi);
 189
 190 struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi;
 191 uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi);
 192
 193 struct trigger {
 194         uint64_t address;
 195         uint32_t length;
 196         uint64_t mask;
 197         uint64_t value;
 198         bool read, write, execute;
 199         int unique_id;
 200 };
 201
 202 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 203 int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
 204
 205 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 206 int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
 207
 208 bool riscv_enable_virt2phys = true;
 209 bool riscv_ebreakm = true;
 210 bool riscv_ebreaks = true;
 211 bool riscv_ebreaku = true;
 212
 213 bool riscv_enable_virtual;
 214
 215 static enum {
 216         RO_NORMAL,
 217         RO_REVERSED
 218 } resume_order;
 219
 220 const virt2phys_info_t sv32 = {
 221         .name = "Sv32",
 222         .va_bits = 32,
 223         .level = 2,
 224         .pte_shift = 2,
 225         .vpn_shift = {12, 22},
 226         .vpn_mask = {0x3ff, 0x3ff},
 227         .pte_ppn_shift = {10, 20},
 228         .pte_ppn_mask = {0x3ff, 0xfff},
 229         .pa_ppn_shift = {12, 22},
 230         .pa_ppn_mask = {0x3ff, 0xfff},
 231 };
 232
 233 const virt2phys_info_t sv39 = {
 234         .name = "Sv39",
 235         .va_bits = 39,
 236         .level = 3,
 237         .pte_shift = 3,
 238         .vpn_shift = {12, 21, 30},
 239         .vpn_mask = {0x1ff, 0x1ff, 0x1ff},
 240         .pte_ppn_shift = {10, 19, 28},
 241         .pte_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
 242         .pa_ppn_shift = {12, 21, 30},
 243         .pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
 244 };
 245
 246 const virt2phys_info_t sv48 = {
 247         .name = "Sv48",
 248         .va_bits = 48,
 249         .level = 4,
 250         .pte_shift = 3,
 251         .vpn_shift = {12, 21, 30, 39},
 252         .vpn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff},
 253         .pte_ppn_shift = {10, 19, 28, 37},
 254         .pte_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
 255         .pa_ppn_shift = {12, 21, 30, 39},
 256         .pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
 257 };
 258
 259 void riscv_sample_buf_maybe_add_timestamp(struct target *target, bool before)
 260 {
 261         RISCV_INFO(r);
 262         uint32_t now = timeval_ms() & 0xffffffff;
 263         if (r->sample_buf.used + 5 < r->sample_buf.size) {
 264                 if (before)
 265                         r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE;
 266                 else
 267                         r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_AFTER;
 268                 r->sample_buf.buf[r->sample_buf.used++] = now & 0xff;
 269                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 8) & 0xff;
 270                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 16) & 0xff;
 271                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 24) & 0xff;
 272         }
 273 }
 274
 275 static int riscv_resume_go_all_harts(struct target *target);
 276
 277 void select_dmi_via_bscan(struct target *target)
 278 {
 279         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
 280         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
 281                 jtag_add_dr_scan(target->tap, bscan_tunnel_data_register_select_dmi_num_fields,
 282                                                                                 bscan_tunnel_data_register_select_dmi, TAP_IDLE);
 283         else /* BSCAN_TUNNEL_NESTED_TAP */
 284                 jtag_add_dr_scan(target->tap, bscan_tunnel_nested_tap_select_dmi_num_fields,
 285                                                                                 bscan_tunnel_nested_tap_select_dmi, TAP_IDLE);
 286 }
 287
 288 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
 289 {
 290         /* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
 291         uint8_t tunneled_ir_width[4] = {bscan_tunnel_ir_width};
 292         uint8_t tunneled_dr_width[4] = {32};
 293         uint8_t out_value[5] = {0};
 294         uint8_t in_value[5] = {0};
 295
 296         buf_set_u32(out_value, 0, 32, out);
 297         struct scan_field tunneled_ir[4] = {};
 298         struct scan_field tunneled_dr[4] = {};
 299
 300         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
 301                 tunneled_ir[0].num_bits = 3;
 302                 tunneled_ir[0].out_value = bscan_zero;
 303                 tunneled_ir[0].in_value = NULL;
 304                 tunneled_ir[1].num_bits = bscan_tunnel_ir_width;
 305                 tunneled_ir[1].out_value = ir_dtmcontrol;
 306                 tunneled_ir[1].in_value = NULL;
 307                 tunneled_ir[2].num_bits = 7;
 308                 tunneled_ir[2].out_value = tunneled_ir_width;
 309                 tunneled_ir[2].in_value = NULL;
 310                 tunneled_ir[3].num_bits = 1;
 311                 tunneled_ir[3].out_value = bscan_zero;
 312                 tunneled_ir[3].in_value = NULL;
 313
 314                 tunneled_dr[0].num_bits = 3;
 315                 tunneled_dr[0].out_value = bscan_zero;
 316                 tunneled_dr[0].in_value = NULL;
 317                 tunneled_dr[1].num_bits = 32 + 1;
 318                 tunneled_dr[1].out_value = out_value;
 319                 tunneled_dr[1].in_value = in_value;
 320                 tunneled_dr[2].num_bits = 7;
 321                 tunneled_dr[2].out_value = tunneled_dr_width;
 322                 tunneled_dr[2].in_value = NULL;
 323                 tunneled_dr[3].num_bits = 1;
 324                 tunneled_dr[3].out_value = bscan_one;
 325                 tunneled_dr[3].in_value = NULL;
 326         } else {
 327                 /* BSCAN_TUNNEL_NESTED_TAP */
 328                 tunneled_ir[3].num_bits = 3;
 329                 tunneled_ir[3].out_value = bscan_zero;
 330                 tunneled_ir[3].in_value = NULL;
 331                 tunneled_ir[2].num_bits = bscan_tunnel_ir_width;
 332                 tunneled_ir[2].out_value = ir_dtmcontrol;
 333                 tunneled_ir[1].in_value = NULL;
 334                 tunneled_ir[1].num_bits = 7;
 335                 tunneled_ir[1].out_value = tunneled_ir_width;
 336                 tunneled_ir[2].in_value = NULL;
 337                 tunneled_ir[0].num_bits = 1;
 338                 tunneled_ir[0].out_value = bscan_zero;
 339                 tunneled_ir[0].in_value = NULL;
 340
 341                 tunneled_dr[3].num_bits = 3;
 342                 tunneled_dr[3].out_value = bscan_zero;
 343                 tunneled_dr[3].in_value = NULL;
 344                 tunneled_dr[2].num_bits = 32 + 1;
 345                 tunneled_dr[2].out_value = out_value;
 346                 tunneled_dr[2].in_value = in_value;
 347                 tunneled_dr[1].num_bits = 7;
 348                 tunneled_dr[1].out_value = tunneled_dr_width;
 349                 tunneled_dr[1].in_value = NULL;
 350                 tunneled_dr[0].num_bits = 1;
 351                 tunneled_dr[0].out_value = bscan_one;
 352                 tunneled_dr[0].in_value = NULL;
 353         }
 354         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
 355         jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_ir), tunneled_ir, TAP_IDLE);
 356         jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_dr), tunneled_dr, TAP_IDLE);
 357         select_dmi_via_bscan(target);
 358
 359         int retval = jtag_execute_queue();
 360         if (retval != ERROR_OK) {
 361                 LOG_ERROR("failed jtag scan: %d", retval);
 362                 return retval;
 363         }
 364         /* Note the starting offset is bit 1, not bit 0.  In BSCAN tunnel, there is a one-bit TCK skew between
 365            output and input */
 366         uint32_t in = buf_get_u32(in_value, 1, 32);
 367         LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
 368
 369         return in;
 370 }
 371
 372 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
 373 {
 374         struct scan_field field;
 375         uint8_t in_value[4];
 376         uint8_t out_value[4] = { 0 };
 377
 378         if (bscan_tunnel_ir_width != 0)
 379                 return dtmcontrol_scan_via_bscan(target, out);
 380
 381
 382         buf_set_u32(out_value, 0, 32, out);
 383
 384         jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
 385
 386         field.num_bits = 32;
 387         field.out_value = out_value;
 388         field.in_value = in_value;
 389         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 390
 391         /* Always return to dbus. */
 392         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 393
 394         int retval = jtag_execute_queue();
 395         if (retval != ERROR_OK) {
 396                 LOG_ERROR("failed jtag scan: %d", retval);
 397                 return retval;
 398         }
 399
 400         uint32_t in = buf_get_u32(field.in_value, 0, 32);
 401         LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
 402
 403         return in;
 404 }
 405
 406 static struct target_type *get_target_type(struct target *target)
 407 {
 408         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 409
 410         if (!info) {
 411                 LOG_ERROR("Target has not been initialized");
 412                 return NULL;
 413         }
 414
 415         switch (info->dtm_version) {
 416                 case 0:
 417                         return &riscv011_target;
 418                 case 1:
 419                         return &riscv013_target;
 420                 default:
 421                         LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
 422                         return NULL;
 423         }
 424 }
 425
 426 static int riscv_create_target(struct target *target, Jim_Interp *interp)
 427 {
 428         LOG_DEBUG("riscv_create_target()");
 429         target->arch_info = calloc(1, sizeof(riscv_info_t));
 430         if (!target->arch_info) {
 431                 LOG_ERROR("Failed to allocate RISC-V target structure.");
 432                 return ERROR_FAIL;
 433         }
 434         riscv_info_init(target, target->arch_info);
 435         return ERROR_OK;
 436 }
 437
 438 static int riscv_init_target(struct command_context *cmd_ctx,
 439                 struct target *target)
 440 {
 441         LOG_DEBUG("riscv_init_target()");
 442         RISCV_INFO(info);
 443         info->cmd_ctx = cmd_ctx;
 444
 445         select_dtmcontrol.num_bits = target->tap->ir_length;
 446         select_dbus.num_bits = target->tap->ir_length;
 447         select_idcode.num_bits = target->tap->ir_length;
 448
 449         if (bscan_tunnel_ir_width != 0) {
 450                 assert(target->tap->ir_length >= 6);
 451                 uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
 452                 ir_user4[0] = (uint8_t)ir_user4_raw;
 453                 ir_user4[1] = (uint8_t)(ir_user4_raw >>= 8);
 454                 ir_user4[2] = (uint8_t)(ir_user4_raw >>= 8);
 455                 ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8);
 456                 select_user4.num_bits = target->tap->ir_length;
 457                 bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width;
 458                 if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
 459                         bscan_tunnel_data_register_select_dmi[1].num_bits = bscan_tunnel_ir_width;
 460                 else /* BSCAN_TUNNEL_NESTED_TAP */
 461                         bscan_tunnel_nested_tap_select_dmi[2].num_bits = bscan_tunnel_ir_width;
 462         }
 463
 464         riscv_semihosting_init(target);
 465
 466         target->debug_reason = DBG_REASON_DBGRQ;
 467
 468         return ERROR_OK;
 469 }
 470
 471 static void riscv_free_registers(struct target *target)
 472 {
 473         /* Free the shared structure use for most registers. */
 474         if (target->reg_cache) {
 475                 if (target->reg_cache->reg_list) {
 476                         free(target->reg_cache->reg_list[0].arch_info);
 477                         /* Free the ones we allocated separately. */
 478                         for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
 479                                 free(target->reg_cache->reg_list[i].arch_info);
 480                         for (unsigned int i = 0; i < target->reg_cache->num_regs; i++)
 481                                 free(target->reg_cache->reg_list[i].value);
 482                         free(target->reg_cache->reg_list);
 483                 }
 484                 free(target->reg_cache);
 485         }
 486 }
 487
 488 static void riscv_deinit_target(struct target *target)
 489 {
 490         LOG_DEBUG("riscv_deinit_target()");
 491
 492         riscv_info_t *info = target->arch_info;
 493         struct target_type *tt = get_target_type(target);
 494
 495         if (tt && info->version_specific)
 496                 tt->deinit_target(target);
 497
 498         riscv_free_registers(target);
 499
 500         range_list_t *entry, *tmp;
 501         list_for_each_entry_safe(entry, tmp, &info->expose_csr, list) {
 502                 free(entry->name);
 503                 free(entry);
 504         }
 505
 506         list_for_each_entry_safe(entry, tmp, &info->expose_custom, list) {
 507                 free(entry->name);
 508                 free(entry);
 509         }
 510
 511         free(info->reg_names);
 512         free(target->arch_info);
 513
 514         target->arch_info = NULL;
 515 }
 516
 517 static void trigger_from_breakpoint(struct trigger *trigger,
 518                 const struct breakpoint *breakpoint)
 519 {
 520         trigger->address = breakpoint->address;
 521         trigger->length = breakpoint->length;
 522         trigger->mask = ~0LL;
 523         trigger->read = false;
 524         trigger->write = false;
 525         trigger->execute = true;
 526         /* unique_id is unique across both breakpoints and watchpoints. */
 527         trigger->unique_id = breakpoint->unique_id;
 528 }
 529
 530 static int maybe_add_trigger_t1(struct target *target,
 531                 struct trigger *trigger, uint64_t tdata1)
 532 {
 533         RISCV_INFO(r);
 534
 535         const uint32_t bpcontrol_x = 1<<0;
 536         const uint32_t bpcontrol_w = 1<<1;
 537         const uint32_t bpcontrol_r = 1<<2;
 538         const uint32_t bpcontrol_u = 1<<3;
 539         const uint32_t bpcontrol_s = 1<<4;
 540         const uint32_t bpcontrol_h = 1<<5;
 541         const uint32_t bpcontrol_m = 1<<6;
 542         const uint32_t bpcontrol_bpmatch = 0xf << 7;
 543         const uint32_t bpcontrol_bpaction = 0xff << 11;
 544
 545         if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
 546                 /* Trigger is already in use, presumably by user code. */
 547                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 548         }
 549
 550         tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
 551         tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
 552         tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
 553         tdata1 = set_field(tdata1, bpcontrol_u,
 554                         !!(r->misa & BIT('U' - 'A')));
 555         tdata1 = set_field(tdata1, bpcontrol_s,
 556                         !!(r->misa & BIT('S' - 'A')));
 557         tdata1 = set_field(tdata1, bpcontrol_h,
 558                         !!(r->misa & BIT('H' - 'A')));
 559         tdata1 |= bpcontrol_m;
 560         tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
 561         tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
 562
 563         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 564
 565         riscv_reg_t tdata1_rb;
 566         if (riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1) != ERROR_OK)
 567                 return ERROR_FAIL;
 568         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 569
 570         if (tdata1 != tdata1_rb) {
 571                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 572                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 573                                 tdata1, tdata1_rb);
 574                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 575                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 576         }
 577
 578         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 579
 580         return ERROR_OK;
 581 }
 582
 583 static int maybe_add_trigger_t2(struct target *target,
 584                 struct trigger *trigger, uint64_t tdata1)
 585 {
 586         RISCV_INFO(r);
 587
 588         /* tselect is already set */
 589         if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
 590                 /* Trigger is already in use, presumably by user code. */
 591                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 592         }
 593
 594         /* address/data match trigger */
 595         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 596         tdata1 = set_field(tdata1, MCONTROL_ACTION,
 597                         MCONTROL_ACTION_DEBUG_MODE);
 598         tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
 599         tdata1 |= MCONTROL_M;
 600         if (r->misa & (1 << ('S' - 'A')))
 601                 tdata1 |= MCONTROL_S;
 602         if (r->misa & (1 << ('U' - 'A')))
 603                 tdata1 |= MCONTROL_U;
 604
 605         if (trigger->execute)
 606                 tdata1 |= MCONTROL_EXECUTE;
 607         if (trigger->read)
 608                 tdata1 |= MCONTROL_LOAD;
 609         if (trigger->write)
 610                 tdata1 |= MCONTROL_STORE;
 611
 612         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 613
 614         uint64_t tdata1_rb;
 615         int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
 616         if (result != ERROR_OK)
 617                 return result;
 618         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 619
 620         if (tdata1 != tdata1_rb) {
 621                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 622                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 623                                 tdata1, tdata1_rb);
 624                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 625                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 626         }
 627
 628         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 629
 630         return ERROR_OK;
 631 }
 632
 633 static int maybe_add_trigger_t6(struct target *target,
 634                 struct trigger *trigger, uint64_t tdata1)
 635 {
 636         RISCV_INFO(r);
 637
 638         /* tselect is already set */
 639         if (tdata1 & (CSR_MCONTROL6_EXECUTE | CSR_MCONTROL6_STORE | CSR_MCONTROL6_LOAD)) {
 640                 /* Trigger is already in use, presumably by user code. */
 641                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 642         }
 643
 644         /* address/data match trigger */
 645         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 646         tdata1 = set_field(tdata1, CSR_MCONTROL6_ACTION,
 647                         MCONTROL_ACTION_DEBUG_MODE);
 648         tdata1 = set_field(tdata1, CSR_MCONTROL6_MATCH, MCONTROL_MATCH_EQUAL);
 649         tdata1 |= CSR_MCONTROL6_M;
 650         if (r->misa & (1 << ('H' - 'A')))
 651                 tdata1 |= CSR_MCONTROL6_VS | CSR_MCONTROL6_VU;
 652         if (r->misa & (1 << ('S' - 'A')))
 653                 tdata1 |= CSR_MCONTROL6_S;
 654         if (r->misa & (1 << ('U' - 'A')))
 655                 tdata1 |= CSR_MCONTROL6_U;
 656
 657         if (trigger->execute)
 658                 tdata1 |= CSR_MCONTROL6_EXECUTE;
 659         if (trigger->read)
 660                 tdata1 |= CSR_MCONTROL6_LOAD;
 661         if (trigger->write)
 662                 tdata1 |= CSR_MCONTROL6_STORE;
 663
 664         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 665
 666         uint64_t tdata1_rb;
 667         int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
 668         if (result != ERROR_OK)
 669                 return result;
 670         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 671
 672         if (tdata1 != tdata1_rb) {
 673                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 674                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 675                                 tdata1, tdata1_rb);
 676                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 677                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 678         }
 679
 680         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 681
 682         return ERROR_OK;
 683 }
 684
 685 static int add_trigger(struct target *target, struct trigger *trigger)
 686 {
 687         RISCV_INFO(r);
 688
 689         if (riscv_enumerate_triggers(target) != ERROR_OK)
 690                 return ERROR_FAIL;
 691
 692         riscv_reg_t tselect;
 693         if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
 694                 return ERROR_FAIL;
 695
 696         unsigned int i;
 697         for (i = 0; i < r->trigger_count; i++) {
 698                 if (r->trigger_unique_id[i] != -1)
 699                         continue;
 700
 701                 riscv_set_register(target, GDB_REGNO_TSELECT, i);
 702
 703                 uint64_t tdata1;
 704                 int result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
 705                 if (result != ERROR_OK)
 706                         return result;
 707                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
 708
 709                 result = ERROR_OK;
 710                 switch (type) {
 711                         case 1:
 712                                 result = maybe_add_trigger_t1(target, trigger, tdata1);
 713                                 break;
 714                         case 2:
 715                                 result = maybe_add_trigger_t2(target, trigger, tdata1);
 716                                 break;
 717                         case 6:
 718                                 result = maybe_add_trigger_t6(target, trigger, tdata1);
 719                                 break;
 720                         default:
 721                                 LOG_DEBUG("trigger %d has unknown type %d", i, type);
 722                                 continue;
 723                 }
 724
 725                 if (result != ERROR_OK)
 726                         continue;
 727
 728                 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
 729                                 i, type, trigger->unique_id);
 730                 r->trigger_unique_id[i] = trigger->unique_id;
 731                 break;
 732         }
 733
 734         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
 735
 736         if (i >= r->trigger_count) {
 737                 LOG_ERROR("Couldn't find an available hardware trigger.");
 738                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 739         }
 740
 741         return ERROR_OK;
 742 }
 743
 744 /**
 745  * Write one memory item of given "size". Use memory access of given "access_size".
 746  * Utilize read-modify-write, if needed.
 747  * */
 748 static int write_by_given_size(struct target *target, target_addr_t address,
 749                 uint32_t size, uint8_t *buffer, uint32_t access_size)
 750 {
 751         assert(size == 1 || size == 2 || size == 4 || size == 8);
 752         assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
 753
 754         if (access_size <= size && address % access_size == 0)
 755                 /* Can do the memory access directly without a helper buffer. */
 756                 return target_write_memory(target, address, access_size, size / access_size, buffer);
 757
 758         unsigned int offset_head = address % access_size;
 759         unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 760         uint8_t helper_buf[n_blocks * access_size];
 761
 762         /* Read from memory */
 763         if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
 764                 return ERROR_FAIL;
 765
 766         /* Modify and write back */
 767         memcpy(helper_buf + offset_head, buffer, size);
 768         return target_write_memory(target, address - offset_head, access_size, n_blocks, helper_buf);
 769 }
 770
 771 /**
 772  * Read one memory item of given "size". Use memory access of given "access_size".
 773  * Read larger section of memory and pick out the required portion, if needed.
 774  * */
 775 static int read_by_given_size(struct target *target, target_addr_t address,
 776         uint32_t size, uint8_t *buffer, uint32_t access_size)
 777 {
 778         assert(size == 1 || size == 2 || size == 4 || size == 8);
 779         assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
 780
 781         if (access_size <= size && address % access_size == 0)
 782                 /* Can do the memory access directly without a helper buffer. */
 783                 return target_read_memory(target, address, access_size, size / access_size, buffer);
 784
 785         unsigned int offset_head = address % access_size;
 786         unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 787         uint8_t helper_buf[n_blocks * access_size];
 788
 789         /* Read from memory */
 790         if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
 791                 return ERROR_FAIL;
 792
 793         /* Pick the requested portion from the buffer */
 794         memcpy(buffer, helper_buf + offset_head, size);
 795         return ERROR_OK;
 796 }
 797
 798 /**
 799  * Write one memory item using any memory access size that will work.
 800  * Utilize read-modify-write, if needed.
 801  * */
 802 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 803 {
 804         assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 805
 806         /* Find access size that correspond to data size and the alignment. */
 807         unsigned int preferred_size = size;
 808         while (address % preferred_size != 0)
 809                 preferred_size /= 2;
 810
 811         /* First try the preferred (most natural) access size. */
 812         if (write_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
 813                 return ERROR_OK;
 814
 815         /* On failure, try other access sizes.
 816            Minimize the number of accesses by trying first the largest size. */
 817         for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 818                 if (access_size == preferred_size)
 819                         /* Already tried this size. */
 820                         continue;
 821
 822                 if (write_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
 823                         return ERROR_OK;
 824         }
 825
 826         /* No access attempt succeeded. */
 827         return ERROR_FAIL;
 828 }
 829
 830 /**
 831  * Read one memory item using any memory access size that will work.
 832  * Read larger section of memory and pick out the required portion, if needed.
 833  * */
 834 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 835 {
 836         assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 837
 838         /* Find access size that correspond to data size and the alignment. */
 839         unsigned int preferred_size = size;
 840         while (address % preferred_size != 0)
 841                 preferred_size /= 2;
 842
 843         /* First try the preferred (most natural) access size. */
 844         if (read_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
 845                 return ERROR_OK;
 846
 847         /* On failure, try other access sizes.
 848            Minimize the number of accesses by trying first the largest size. */
 849         for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 850                 if (access_size == preferred_size)
 851                         /* Already tried this size. */
 852                         continue;
 853
 854                 if (read_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
 855                         return ERROR_OK;
 856         }
 857
 858         /* No access attempt succeeded. */
 859         return ERROR_FAIL;
 860 }
 861
 862 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 863 {
 864         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
 865         assert(breakpoint);
 866         if (breakpoint->type == BKPT_SOFT) {
 867                 /** @todo check RVC for size/alignment */
 868                 if (!(breakpoint->length == 4 || breakpoint->length == 2)) {
 869                         LOG_ERROR("Invalid breakpoint length %d", breakpoint->length);
 870                         return ERROR_FAIL;
 871                 }
 872
 873                 if (0 != (breakpoint->address % 2)) {
 874                         LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR, breakpoint->address);
 875                         return ERROR_FAIL;
 876                 }
 877
 878                 /* Read the original instruction. */
 879                 if (riscv_read_by_any_size(
 880                                 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
 881                         LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
 882                                         breakpoint->address);
 883                         return ERROR_FAIL;
 884                 }
 885
 886                 uint8_t buff[4] = { 0 };
 887                 buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
 888                 /* Write the ebreak instruction. */
 889                 if (riscv_write_by_any_size(target, breakpoint->address, breakpoint->length, buff) != ERROR_OK) {
 890                         LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
 891                                         TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 892                         return ERROR_FAIL;
 893                 }
 894
 895         } else if (breakpoint->type == BKPT_HARD) {
 896                 struct trigger trigger;
 897                 trigger_from_breakpoint(&trigger, breakpoint);
 898                 int const result = add_trigger(target, &trigger);
 899                 if (result != ERROR_OK)
 900                         return result;
 901         } else {
 902                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 903                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 904         }
 905
 906         breakpoint->is_set = true;
 907         return ERROR_OK;
 908 }
 909
 910 static int remove_trigger(struct target *target, struct trigger *trigger)
 911 {
 912         RISCV_INFO(r);
 913
 914         if (riscv_enumerate_triggers(target) != ERROR_OK)
 915                 return ERROR_FAIL;
 916
 917         unsigned int i;
 918         for (i = 0; i < r->trigger_count; i++) {
 919                 if (r->trigger_unique_id[i] == trigger->unique_id)
 920                         break;
 921         }
 922         if (i >= r->trigger_count) {
 923                 LOG_ERROR("Couldn't find the hardware resources used by hardware "
 924                                 "trigger.");
 925                 return ERROR_FAIL;
 926         }
 927         LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
 928                         trigger->unique_id);
 929
 930         riscv_reg_t tselect;
 931         int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
 932         if (result != ERROR_OK)
 933                 return result;
 934         riscv_set_register(target, GDB_REGNO_TSELECT, i);
 935         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 936         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
 937         r->trigger_unique_id[i] = -1;
 938
 939         return ERROR_OK;
 940 }
 941
 942 int riscv_remove_breakpoint(struct target *target,
 943                 struct breakpoint *breakpoint)
 944 {
 945         if (breakpoint->type == BKPT_SOFT) {
 946                 /* Write the original instruction. */
 947                 if (riscv_write_by_any_size(
 948                                 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
 949                         LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
 950                                         "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 951                         return ERROR_FAIL;
 952                 }
 953
 954         } else if (breakpoint->type == BKPT_HARD) {
 955                 struct trigger trigger;
 956                 trigger_from_breakpoint(&trigger, breakpoint);
 957                 int result = remove_trigger(target, &trigger);
 958                 if (result != ERROR_OK)
 959                         return result;
 960
 961         } else {
 962                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 963                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 964         }
 965
 966         breakpoint->is_set = false;
 967
 968         return ERROR_OK;
 969 }
 970
 971 static void trigger_from_watchpoint(struct trigger *trigger,
 972                 const struct watchpoint *watchpoint)
 973 {
 974         trigger->address = watchpoint->address;
 975         trigger->length = watchpoint->length;
 976         trigger->mask = watchpoint->mask;
 977         trigger->value = watchpoint->value;
 978         trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
 979         trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
 980         trigger->execute = false;
 981         /* unique_id is unique across both breakpoints and watchpoints. */
 982         trigger->unique_id = watchpoint->unique_id;
 983 }
 984
 985 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 986 {
 987         struct trigger trigger;
 988         trigger_from_watchpoint(&trigger, watchpoint);
 989
 990         int result = add_trigger(target, &trigger);
 991         if (result != ERROR_OK)
 992                 return result;
 993         watchpoint->is_set = true;
 994
 995         return ERROR_OK;
 996 }
 997
 998 int riscv_remove_watchpoint(struct target *target,
 999                 struct watchpoint *watchpoint)
1000 {
1001         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
1002
1003         struct trigger trigger;
1004         trigger_from_watchpoint(&trigger, watchpoint);
1005
1006         int result = remove_trigger(target, &trigger);
1007         if (result != ERROR_OK)
1008                 return result;
1009         watchpoint->is_set = false;
1010
1011         return ERROR_OK;
1012 }
1013
1014 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
1015  * current halt.
1016  *
1017  * The GDB server uses this information to tell GDB what data address has
1018  * been hit, which enables GDB to print the hit variable along with its old
1019  * and new value. */
1020 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1021 {
1022         struct watchpoint *wp = target->watchpoints;
1023
1024         LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
1025
1026         /*TODO instead of disassembling the instruction that we think caused the
1027          * trigger, check the hit bit of each watchpoint first. The hit bit is
1028          * simpler and more reliable to check but as it is optional and relatively
1029          * new, not all hardware will implement it  */
1030         riscv_reg_t dpc;
1031         riscv_get_register(target, &dpc, GDB_REGNO_DPC);
1032         const uint8_t length = 4;
1033         LOG_DEBUG("dpc is 0x%" PRIx64, dpc);
1034
1035         /* fetch the instruction at dpc */
1036         uint8_t buffer[length];
1037         if (target_read_buffer(target, dpc, length, buffer) != ERROR_OK) {
1038                 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64, dpc);
1039                 return ERROR_FAIL;
1040         }
1041
1042         uint32_t instruction = 0;
1043
1044         for (int i = 0; i < length; i++) {
1045                 LOG_DEBUG("Next byte is %x", buffer[i]);
1046                 instruction += (buffer[i] << 8 * i);
1047         }
1048         LOG_DEBUG("Full instruction is %x", instruction);
1049
1050         /* find out which memory address is accessed by the instruction at dpc */
1051         /* opcode is first 7 bits of the instruction */
1052         uint8_t opcode = instruction & 0x7F;
1053         uint32_t rs1;
1054         int16_t imm;
1055         riscv_reg_t mem_addr;
1056
1057         if (opcode == MATCH_LB || opcode == MATCH_SB) {
1058                 rs1 = (instruction & 0xf8000) >> 15;
1059                 riscv_get_register(target, &mem_addr, rs1);
1060
1061                 if (opcode == MATCH_SB) {
1062                         LOG_DEBUG("%x is store instruction", instruction);
1063                         imm = ((instruction & 0xf80) >> 7) | ((instruction & 0xfe000000) >> 20);
1064                 } else {
1065                         LOG_DEBUG("%x is load instruction", instruction);
1066                         imm = (instruction & 0xfff00000) >> 20;
1067                 }
1068                 /* sign extend 12-bit imm to 16-bits */
1069                 if (imm & (1 << 11))
1070                         imm |= 0xf000;
1071                 mem_addr += imm;
1072                 LOG_DEBUG("memory address=0x%" PRIx64, mem_addr);
1073         } else {
1074                 LOG_DEBUG("%x is not a RV32I load or store", instruction);
1075                 return ERROR_FAIL;
1076         }
1077
1078         while (wp) {
1079                 /*TODO support length/mask */
1080                 if (wp->address == mem_addr) {
1081                         *hit_watchpoint = wp;
1082                         LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address);
1083                         return ERROR_OK;
1084                 }
1085                 wp = wp->next;
1086         }
1087
1088         /* No match found - either we hit a watchpoint caused by an instruction that
1089          * this function does not yet disassemble, or we hit a breakpoint.
1090          *
1091          * OpenOCD will behave as if this function had never been implemented i.e.
1092          * report the halt to GDB with no address information. */
1093         return ERROR_FAIL;
1094 }
1095
1096
1097 static int oldriscv_step(struct target *target, int current, uint32_t address,
1098                 int handle_breakpoints)
1099 {
1100         struct target_type *tt = get_target_type(target);
1101         return tt->step(target, current, address, handle_breakpoints);
1102 }
1103
1104 static int old_or_new_riscv_step(struct target *target, int current,
1105                 target_addr_t address, int handle_breakpoints)
1106 {
1107         RISCV_INFO(r);
1108         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1109         if (!r->is_halted)
1110                 return oldriscv_step(target, current, address, handle_breakpoints);
1111         else
1112                 return riscv_openocd_step(target, current, address, handle_breakpoints);
1113 }
1114
1115
1116 static int riscv_examine(struct target *target)
1117 {
1118         LOG_DEBUG("riscv_examine()");
1119         if (target_was_examined(target)) {
1120                 LOG_DEBUG("Target was already examined.");
1121                 return ERROR_OK;
1122         }
1123
1124         /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1125
1126         RISCV_INFO(info);
1127         uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1128         LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1129         info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
1130         LOG_DEBUG("  version=0x%x", info->dtm_version);
1131
1132         struct target_type *tt = get_target_type(target);
1133         if (!tt)
1134                 return ERROR_FAIL;
1135
1136         int result = tt->init_target(info->cmd_ctx, target);
1137         if (result != ERROR_OK)
1138                 return result;
1139
1140         return tt->examine(target);
1141 }
1142
1143 static int oldriscv_poll(struct target *target)
1144 {
1145         struct target_type *tt = get_target_type(target);
1146         return tt->poll(target);
1147 }
1148
1149 static int old_or_new_riscv_poll(struct target *target)
1150 {
1151         RISCV_INFO(r);
1152         if (!r->is_halted)
1153                 return oldriscv_poll(target);
1154         else
1155                 return riscv_openocd_poll(target);
1156 }
1157
1158 int riscv_select_current_hart(struct target *target)
1159 {
1160         return riscv_set_current_hartid(target, target->coreid);
1161 }
1162
1163 int halt_prep(struct target *target)
1164 {
1165         RISCV_INFO(r);
1166
1167         LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target),
1168                                 target->debug_reason);
1169         if (riscv_select_current_hart(target) != ERROR_OK)
1170                 return ERROR_FAIL;
1171         if (riscv_is_halted(target)) {
1172                 LOG_DEBUG("[%s] Hart is already halted (reason=%d).",
1173                                 target_name(target), target->debug_reason);
1174         } else {
1175                 if (r->halt_prep(target) != ERROR_OK)
1176                         return ERROR_FAIL;
1177                 r->prepped = true;
1178         }
1179
1180         return ERROR_OK;
1181 }
1182
1183 int riscv_halt_go_all_harts(struct target *target)
1184 {
1185         RISCV_INFO(r);
1186
1187         if (riscv_select_current_hart(target) != ERROR_OK)
1188                 return ERROR_FAIL;
1189         if (riscv_is_halted(target)) {
1190                 LOG_DEBUG("[%s] Hart is already halted.", target_name(target));
1191         } else {
1192                 if (r->halt_go(target) != ERROR_OK)
1193                         return ERROR_FAIL;
1194         }
1195
1196         riscv_invalidate_register_cache(target);
1197
1198         return ERROR_OK;
1199 }
1200
1201 int halt_go(struct target *target)
1202 {
1203         riscv_info_t *r = riscv_info(target);
1204         int result;
1205         if (!r->is_halted) {
1206                 struct target_type *tt = get_target_type(target);
1207                 result = tt->halt(target);
1208         } else {
1209                 result = riscv_halt_go_all_harts(target);
1210         }
1211         target->state = TARGET_HALTED;
1212         if (target->debug_reason == DBG_REASON_NOTHALTED)
1213                 target->debug_reason = DBG_REASON_DBGRQ;
1214
1215         return result;
1216 }
1217
1218 static int halt_finish(struct target *target)
1219 {
1220         return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1221 }
1222
1223 int riscv_halt(struct target *target)
1224 {
1225         RISCV_INFO(r);
1226
1227         if (!r->is_halted) {
1228                 struct target_type *tt = get_target_type(target);
1229                 return tt->halt(target);
1230         }
1231
1232         LOG_DEBUG("[%d] halting all harts", target->coreid);
1233
1234         int result = ERROR_OK;
1235         if (target->smp) {
1236                 struct target_list *tlist;
1237                 foreach_smp_target(tlist, target->smp_targets) {
1238                         struct target *t = tlist->target;
1239                         if (halt_prep(t) != ERROR_OK)
1240                                 result = ERROR_FAIL;
1241                 }
1242
1243                 foreach_smp_target(tlist, target->smp_targets) {
1244                         struct target *t = tlist->target;
1245                         riscv_info_t *i = riscv_info(t);
1246                         if (i->prepped) {
1247                                 if (halt_go(t) != ERROR_OK)
1248                                         result = ERROR_FAIL;
1249                         }
1250                 }
1251
1252                 foreach_smp_target(tlist, target->smp_targets) {
1253                         struct target *t = tlist->target;
1254                         if (halt_finish(t) != ERROR_OK)
1255                                 return ERROR_FAIL;
1256                 }
1257
1258         } else {
1259                 if (halt_prep(target) != ERROR_OK)
1260                         result = ERROR_FAIL;
1261                 if (halt_go(target) != ERROR_OK)
1262                         result = ERROR_FAIL;
1263                 if (halt_finish(target) != ERROR_OK)
1264                         return ERROR_FAIL;
1265         }
1266
1267         return result;
1268 }
1269
1270 static int riscv_assert_reset(struct target *target)
1271 {
1272         LOG_DEBUG("[%d]", target->coreid);
1273         struct target_type *tt = get_target_type(target);
1274         riscv_invalidate_register_cache(target);
1275         return tt->assert_reset(target);
1276 }
1277
1278 static int riscv_deassert_reset(struct target *target)
1279 {
1280         LOG_DEBUG("[%d]", target->coreid);
1281         struct target_type *tt = get_target_type(target);
1282         return tt->deassert_reset(target);
1283 }
1284
1285 int riscv_resume_prep_all_harts(struct target *target)
1286 {
1287         RISCV_INFO(r);
1288
1289         LOG_DEBUG("[%s] prep hart", target_name(target));
1290         if (riscv_select_current_hart(target) != ERROR_OK)
1291                 return ERROR_FAIL;
1292         if (riscv_is_halted(target)) {
1293                 if (r->resume_prep(target) != ERROR_OK)
1294                         return ERROR_FAIL;
1295         } else {
1296                 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
1297                                 target_name(target));
1298         }
1299
1300         LOG_DEBUG("[%s] mark as prepped", target_name(target));
1301         r->prepped = true;
1302
1303         return ERROR_OK;
1304 }
1305
1306 /* state must be riscv_reg_t state[RISCV_MAX_HWBPS] = {0}; */
1307 static int disable_triggers(struct target *target, riscv_reg_t *state)
1308 {
1309         RISCV_INFO(r);
1310
1311         LOG_DEBUG("deal with triggers");
1312
1313         if (riscv_enumerate_triggers(target) != ERROR_OK)
1314                 return ERROR_FAIL;
1315
1316         if (r->manual_hwbp_set) {
1317                 /* Look at every trigger that may have been set. */
1318                 riscv_reg_t tselect;
1319                 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1320                         return ERROR_FAIL;
1321                 for (unsigned int t = 0; t < r->trigger_count; t++) {
1322                         if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1323                                 return ERROR_FAIL;
1324                         riscv_reg_t tdata1;
1325                         if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK)
1326                                 return ERROR_FAIL;
1327                         if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) {
1328                                 state[t] = tdata1;
1329                                 if (riscv_set_register(target, GDB_REGNO_TDATA1, 0) != ERROR_OK)
1330                                         return ERROR_FAIL;
1331                         }
1332                 }
1333                 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1334                         return ERROR_FAIL;
1335
1336         } else {
1337                 /* Just go through the triggers we manage. */
1338                 struct watchpoint *watchpoint = target->watchpoints;
1339                 int i = 0;
1340                 while (watchpoint) {
1341                         LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->is_set);
1342                         state[i] = watchpoint->is_set;
1343                         if (watchpoint->is_set) {
1344                                 if (riscv_remove_watchpoint(target, watchpoint) != ERROR_OK)
1345                                         return ERROR_FAIL;
1346                         }
1347                         watchpoint = watchpoint->next;
1348                         i++;
1349                 }
1350         }
1351
1352         return ERROR_OK;
1353 }
1354
1355 static int enable_triggers(struct target *target, riscv_reg_t *state)
1356 {
1357         RISCV_INFO(r);
1358
1359         if (r->manual_hwbp_set) {
1360                 /* Look at every trigger that may have been set. */
1361                 riscv_reg_t tselect;
1362                 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1363                         return ERROR_FAIL;
1364                 for (unsigned int t = 0; t < r->trigger_count; t++) {
1365                         if (state[t] != 0) {
1366                                 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1367                                         return ERROR_FAIL;
1368                                 if (riscv_set_register(target, GDB_REGNO_TDATA1, state[t]) != ERROR_OK)
1369                                         return ERROR_FAIL;
1370                         }
1371                 }
1372                 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1373                         return ERROR_FAIL;
1374
1375         } else {
1376                 struct watchpoint *watchpoint = target->watchpoints;
1377                 int i = 0;
1378                 while (watchpoint) {
1379                         LOG_DEBUG("watchpoint %d: cleared=%" PRId64, i, state[i]);
1380                         if (state[i]) {
1381                                 if (riscv_add_watchpoint(target, watchpoint) != ERROR_OK)
1382                                         return ERROR_FAIL;
1383                         }
1384                         watchpoint = watchpoint->next;
1385                         i++;
1386                 }
1387         }
1388
1389         return ERROR_OK;
1390 }
1391
1392 /**
1393  * Get everything ready to resume.
1394  */
1395 static int resume_prep(struct target *target, int current,
1396                 target_addr_t address, int handle_breakpoints, int debug_execution)
1397 {
1398         RISCV_INFO(r);
1399         LOG_DEBUG("[%d]", target->coreid);
1400
1401         if (!current)
1402                 riscv_set_register(target, GDB_REGNO_PC, address);
1403
1404         if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1405                 /* To be able to run off a trigger, disable all the triggers, step, and
1406                  * then resume as usual. */
1407                 riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
1408
1409                 if (disable_triggers(target, trigger_state) != ERROR_OK)
1410                         return ERROR_FAIL;
1411
1412                 if (old_or_new_riscv_step(target, true, 0, false) != ERROR_OK)
1413                         return ERROR_FAIL;
1414
1415                 if (enable_triggers(target, trigger_state) != ERROR_OK)
1416                         return ERROR_FAIL;
1417         }
1418
1419         if (r->is_halted) {
1420                 if (riscv_resume_prep_all_harts(target) != ERROR_OK)
1421                         return ERROR_FAIL;
1422         }
1423
1424         LOG_DEBUG("[%d] mark as prepped", target->coreid);
1425         r->prepped = true;
1426
1427         return ERROR_OK;
1428 }
1429
1430 /**
1431  * Resume all the harts that have been prepped, as close to instantaneous as
1432  * possible.
1433  */
1434 static int resume_go(struct target *target, int current,
1435                 target_addr_t address, int handle_breakpoints, int debug_execution)
1436 {
1437         riscv_info_t *r = riscv_info(target);
1438         int result;
1439         if (!r->is_halted) {
1440                 struct target_type *tt = get_target_type(target);
1441                 result = tt->resume(target, current, address, handle_breakpoints,
1442                                 debug_execution);
1443         } else {
1444                 result = riscv_resume_go_all_harts(target);
1445         }
1446
1447         return result;
1448 }
1449
1450 static int resume_finish(struct target *target)
1451 {
1452         register_cache_invalidate(target->reg_cache);
1453
1454         target->state = TARGET_RUNNING;
1455         target->debug_reason = DBG_REASON_NOTHALTED;
1456         return target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1457 }
1458
1459 /**
1460  * @par single_hart When true, only resume a single hart even if SMP is
1461  * configured.  This is used to run algorithms on just one hart.
1462  */
1463 int riscv_resume(
1464                 struct target *target,
1465                 int current,
1466                 target_addr_t address,
1467                 int handle_breakpoints,
1468                 int debug_execution,
1469                 bool single_hart)
1470 {
1471         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1472         int result = ERROR_OK;
1473         if (target->smp && !single_hart) {
1474                 struct target_list *tlist;
1475                 foreach_smp_target_direction(resume_order == RO_NORMAL,
1476                                                                          tlist, target->smp_targets) {
1477                         struct target *t = tlist->target;
1478                         if (resume_prep(t, current, address, handle_breakpoints,
1479                                                 debug_execution) != ERROR_OK)
1480                                 result = ERROR_FAIL;
1481                 }
1482
1483                 foreach_smp_target_direction(resume_order == RO_NORMAL,
1484                                                                          tlist, target->smp_targets) {
1485                         struct target *t = tlist->target;
1486                         riscv_info_t *i = riscv_info(t);
1487                         if (i->prepped) {
1488                                 if (resume_go(t, current, address, handle_breakpoints,
1489                                                         debug_execution) != ERROR_OK)
1490                                         result = ERROR_FAIL;
1491                         }
1492                 }
1493
1494                 foreach_smp_target_direction(resume_order == RO_NORMAL,
1495                                                                          tlist, target->smp_targets) {
1496                         struct target *t = tlist->target;
1497                         if (resume_finish(t) != ERROR_OK)
1498                                 return ERROR_FAIL;
1499                 }
1500
1501         } else {
1502                 if (resume_prep(target, current, address, handle_breakpoints,
1503                                         debug_execution) != ERROR_OK)
1504                         result = ERROR_FAIL;
1505                 if (resume_go(target, current, address, handle_breakpoints,
1506                                         debug_execution) != ERROR_OK)
1507                         result = ERROR_FAIL;
1508                 if (resume_finish(target) != ERROR_OK)
1509                         return ERROR_FAIL;
1510         }
1511
1512         return result;
1513 }
1514
1515 static int riscv_target_resume(struct target *target, int current, target_addr_t address,
1516                 int handle_breakpoints, int debug_execution)
1517 {
1518         return riscv_resume(target, current, address, handle_breakpoints,
1519                         debug_execution, false);
1520 }
1521
1522 static int riscv_mmu(struct target *target, int *enabled)
1523 {
1524         if (!riscv_enable_virt2phys) {
1525                 *enabled = 0;
1526                 return ERROR_OK;
1527         }
1528
1529         /* Don't use MMU in explicit or effective M (machine) mode */
1530         riscv_reg_t priv;
1531         if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) {
1532                 LOG_ERROR("Failed to read priv register.");
1533                 return ERROR_FAIL;
1534         }
1535
1536         riscv_reg_t mstatus;
1537         if (riscv_get_register(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK) {
1538                 LOG_ERROR("Failed to read mstatus register.");
1539                 return ERROR_FAIL;
1540         }
1541
1542         if ((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP) : priv) == PRV_M) {
1543                 LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
1544                 *enabled = 0;
1545                 return ERROR_OK;
1546         }
1547
1548         riscv_reg_t satp;
1549         if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) {
1550                 LOG_DEBUG("Couldn't read SATP.");
1551                 /* If we can't read SATP, then there must not be an MMU. */
1552                 *enabled = 0;
1553                 return ERROR_OK;
1554         }
1555
1556         if (get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF) {
1557                 LOG_DEBUG("MMU is disabled.");
1558                 *enabled = 0;
1559         } else {
1560                 LOG_DEBUG("MMU is enabled.");
1561                 *enabled = 1;
1562         }
1563
1564         return ERROR_OK;
1565 }
1566
1567 static int riscv_address_translate(struct target *target,
1568                 target_addr_t virtual, target_addr_t *physical)
1569 {
1570         RISCV_INFO(r);
1571         riscv_reg_t satp_value;
1572         int mode;
1573         uint64_t ppn_value;
1574         target_addr_t table_address;
1575         const virt2phys_info_t *info;
1576         uint64_t pte = 0;
1577         int i;
1578
1579         int result = riscv_get_register(target, &satp_value, GDB_REGNO_SATP);
1580         if (result != ERROR_OK)
1581                 return result;
1582
1583         unsigned xlen = riscv_xlen(target);
1584         mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
1585         switch (mode) {
1586                 case SATP_MODE_SV32:
1587                         info = &sv32;
1588                         break;
1589                 case SATP_MODE_SV39:
1590                         info = &sv39;
1591                         break;
1592                 case SATP_MODE_SV48:
1593                         info = &sv48;
1594                         break;
1595                 case SATP_MODE_OFF:
1596                         LOG_ERROR("No translation or protection." \
1597                                       " (satp: 0x%" PRIx64 ")", satp_value);
1598                         return ERROR_FAIL;
1599                 default:
1600                         LOG_ERROR("The translation mode is not supported." \
1601                                       " (satp: 0x%" PRIx64 ")", satp_value);
1602                         return ERROR_FAIL;
1603         }
1604         LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
1605
1606         /* verify bits xlen-1:va_bits-1 are all equal */
1607         target_addr_t mask = ((target_addr_t)1 << (xlen - (info->va_bits - 1))) - 1;
1608         target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask;
1609         if (masked_msbs != 0 && masked_msbs != mask) {
1610                 LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR " is not sign-extended "
1611                                 "for %s mode.", virtual, info->name);
1612                 return ERROR_FAIL;
1613         }
1614
1615         ppn_value = get_field(satp_value, RISCV_SATP_PPN(xlen));
1616         table_address = ppn_value << RISCV_PGSHIFT;
1617         i = info->level - 1;
1618         while (i >= 0) {
1619                 uint64_t vpn = virtual >> info->vpn_shift[i];
1620                 vpn &= info->vpn_mask[i];
1621                 target_addr_t pte_address = table_address +
1622                                                                         (vpn << info->pte_shift);
1623                 uint8_t buffer[8];
1624                 assert(info->pte_shift <= 3);
1625                 int retval = r->read_memory(target, pte_address,
1626                                 4, (1 << info->pte_shift) / 4, buffer, 4);
1627                 if (retval != ERROR_OK)
1628                         return ERROR_FAIL;
1629
1630                 if (info->pte_shift == 2)
1631                         pte = buf_get_u32(buffer, 0, 32);
1632                 else
1633                         pte = buf_get_u64(buffer, 0, 64);
1634
1635                 LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
1636                                 pte_address, pte);
1637
1638                 if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W)))
1639                         return ERROR_FAIL;
1640
1641                 if ((pte & PTE_R) || (pte & PTE_X)) /* Found leaf PTE. */
1642                         break;
1643
1644                 i--;
1645                 if (i < 0)
1646                         break;
1647                 ppn_value = pte >> PTE_PPN_SHIFT;
1648                 table_address = ppn_value << RISCV_PGSHIFT;
1649         }
1650
1651         if (i < 0) {
1652                 LOG_ERROR("Couldn't find the PTE.");
1653                 return ERROR_FAIL;
1654         }
1655
1656         /* Make sure to clear out the high bits that may be set. */
1657         *physical = virtual & (((target_addr_t)1 << info->va_bits) - 1);
1658
1659         while (i < info->level) {
1660                 ppn_value = pte >> info->pte_ppn_shift[i];
1661                 ppn_value &= info->pte_ppn_mask[i];
1662                 *physical &= ~(((target_addr_t)info->pa_ppn_mask[i]) <<
1663                                 info->pa_ppn_shift[i]);
1664                 *physical |= (ppn_value << info->pa_ppn_shift[i]);
1665                 i++;
1666         }
1667         LOG_DEBUG("0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR, virtual,
1668                         *physical);
1669
1670         return ERROR_OK;
1671 }
1672
1673 static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
1674 {
1675         int enabled;
1676         if (riscv_mmu(target, &enabled) == ERROR_OK) {
1677                 if (!enabled)
1678                         return ERROR_FAIL;
1679
1680                 if (riscv_address_translate(target, virtual, physical) == ERROR_OK)
1681                         return ERROR_OK;
1682         }
1683
1684         return ERROR_FAIL;
1685 }
1686
1687 static int riscv_read_phys_memory(struct target *target, target_addr_t phys_address,
1688                         uint32_t size, uint32_t count, uint8_t *buffer)
1689 {
1690         RISCV_INFO(r);
1691         if (riscv_select_current_hart(target) != ERROR_OK)
1692                 return ERROR_FAIL;
1693         return r->read_memory(target, phys_address, size, count, buffer, size);
1694 }
1695
1696 static int riscv_read_memory(struct target *target, target_addr_t address,
1697                 uint32_t size, uint32_t count, uint8_t *buffer)
1698 {
1699         if (count == 0) {
1700                 LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR, address);
1701                 return ERROR_OK;
1702         }
1703
1704         if (riscv_select_current_hart(target) != ERROR_OK)
1705                 return ERROR_FAIL;
1706
1707         target_addr_t physical_addr;
1708         if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1709                 address = physical_addr;
1710
1711         RISCV_INFO(r);
1712         return r->read_memory(target, address, size, count, buffer, size);
1713 }
1714
1715 static int riscv_write_phys_memory(struct target *target, target_addr_t phys_address,
1716                         uint32_t size, uint32_t count, const uint8_t *buffer)
1717 {
1718         if (riscv_select_current_hart(target) != ERROR_OK)
1719                 return ERROR_FAIL;
1720         struct target_type *tt = get_target_type(target);
1721         return tt->write_memory(target, phys_address, size, count, buffer);
1722 }
1723
1724 static int riscv_write_memory(struct target *target, target_addr_t address,
1725                 uint32_t size, uint32_t count, const uint8_t *buffer)
1726 {
1727         if (count == 0) {
1728                 LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR, address);
1729                 return ERROR_OK;
1730         }
1731
1732         if (riscv_select_current_hart(target) != ERROR_OK)
1733                 return ERROR_FAIL;
1734
1735         target_addr_t physical_addr;
1736         if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1737                 address = physical_addr;
1738
1739         struct target_type *tt = get_target_type(target);
1740         return tt->write_memory(target, address, size, count, buffer);
1741 }
1742
1743 const char *riscv_get_gdb_arch(struct target *target)
1744 {
1745         switch (riscv_xlen(target)) {
1746                 case 32:
1747                         return "riscv:rv32";
1748                 case 64:
1749                         return "riscv:rv64";
1750         }
1751         LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target));
1752         return NULL;
1753 }
1754
1755 static int riscv_get_gdb_reg_list_internal(struct target *target,
1756                 struct reg **reg_list[], int *reg_list_size,
1757                 enum target_register_class reg_class, bool read)
1758 {
1759         RISCV_INFO(r);
1760         LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
1761                         target_name(target), r->current_hartid, reg_class, read);
1762
1763         if (!target->reg_cache) {
1764                 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
1765                 return ERROR_FAIL;
1766         }
1767
1768         if (riscv_select_current_hart(target) != ERROR_OK)
1769                 return ERROR_FAIL;
1770
1771         switch (reg_class) {
1772                 case REG_CLASS_GENERAL:
1773                         *reg_list_size = 33;
1774                         break;
1775                 case REG_CLASS_ALL:
1776                         *reg_list_size = target->reg_cache->num_regs;
1777                         break;
1778                 default:
1779                         LOG_ERROR("Unsupported reg_class: %d", reg_class);
1780                         return ERROR_FAIL;
1781         }
1782
1783         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
1784         if (!*reg_list)
1785                 return ERROR_FAIL;
1786
1787         for (int i = 0; i < *reg_list_size; i++) {
1788                 assert(!target->reg_cache->reg_list[i].valid ||
1789                                 target->reg_cache->reg_list[i].size > 0);
1790                 (*reg_list)[i] = &target->reg_cache->reg_list[i];
1791                 if (read &&
1792                                 target->reg_cache->reg_list[i].exist &&
1793                                 !target->reg_cache->reg_list[i].valid) {
1794                         if (target->reg_cache->reg_list[i].type->get(
1795                                                 &target->reg_cache->reg_list[i]) != ERROR_OK)
1796                                 return ERROR_FAIL;
1797                 }
1798         }
1799
1800         return ERROR_OK;
1801 }
1802
1803 static int riscv_get_gdb_reg_list_noread(struct target *target,
1804                 struct reg **reg_list[], int *reg_list_size,
1805                 enum target_register_class reg_class)
1806 {
1807         return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1808                         reg_class, false);
1809 }
1810
1811 static int riscv_get_gdb_reg_list(struct target *target,
1812                 struct reg **reg_list[], int *reg_list_size,
1813                 enum target_register_class reg_class)
1814 {
1815         return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1816                         reg_class, true);
1817 }
1818
1819 static int riscv_arch_state(struct target *target)
1820 {
1821         struct target_type *tt = get_target_type(target);
1822         return tt->arch_state(target);
1823 }
1824
1825 /* Algorithm must end with a software breakpoint instruction. */
1826 static int riscv_run_algorithm(struct target *target, int num_mem_params,
1827                 struct mem_param *mem_params, int num_reg_params,
1828                 struct reg_param *reg_params, target_addr_t entry_point,
1829                 target_addr_t exit_point, int timeout_ms, void *arch_info)
1830 {
1831         RISCV_INFO(info);
1832
1833         if (num_mem_params > 0) {
1834                 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1835                 return ERROR_FAIL;
1836         }
1837
1838         if (target->state != TARGET_HALTED) {
1839                 LOG_WARNING("target not halted");
1840                 return ERROR_TARGET_NOT_HALTED;
1841         }
1842
1843         /* Save registers */
1844         struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", true);
1845         if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
1846                 return ERROR_FAIL;
1847         uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1848         LOG_DEBUG("saved_pc=0x%" PRIx64, saved_pc);
1849
1850         uint64_t saved_regs[32];
1851         for (int i = 0; i < num_reg_params; i++) {
1852                 LOG_DEBUG("save %s", reg_params[i].reg_name);
1853                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1854                 if (!r) {
1855                         LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
1856                         return ERROR_FAIL;
1857                 }
1858
1859                 if (r->size != reg_params[i].size) {
1860                         LOG_ERROR("Register %s is %d bits instead of %d bits.",
1861                                         reg_params[i].reg_name, r->size, reg_params[i].size);
1862                         return ERROR_FAIL;
1863                 }
1864
1865                 if (r->number > GDB_REGNO_XPR31) {
1866                         LOG_ERROR("Only GPRs can be use as argument registers.");
1867                         return ERROR_FAIL;
1868                 }
1869
1870                 if (r->type->get(r) != ERROR_OK)
1871                         return ERROR_FAIL;
1872                 saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
1873
1874                 if (reg_params[i].direction == PARAM_OUT || reg_params[i].direction == PARAM_IN_OUT) {
1875                         if (r->type->set(r, reg_params[i].value) != ERROR_OK)
1876                                 return ERROR_FAIL;
1877                 }
1878         }
1879
1880
1881         /* Disable Interrupts before attempting to run the algorithm. */
1882         uint64_t current_mstatus;
1883         uint8_t mstatus_bytes[8] = { 0 };
1884
1885         LOG_DEBUG("Disabling Interrupts");
1886         struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
1887                         "mstatus", true);
1888         if (!reg_mstatus) {
1889                 LOG_ERROR("Couldn't find mstatus!");
1890                 return ERROR_FAIL;
1891         }
1892
1893         reg_mstatus->type->get(reg_mstatus);
1894         current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
1895         uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
1896         buf_set_u64(mstatus_bytes, 0, info->xlen, set_field(current_mstatus,
1897                                 ie_mask, 0));
1898
1899         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1900
1901         /* Run algorithm */
1902         LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
1903         if (riscv_resume(target, 0, entry_point, 0, 0, true) != ERROR_OK)
1904                 return ERROR_FAIL;
1905
1906         int64_t start = timeval_ms();
1907         while (target->state != TARGET_HALTED) {
1908                 LOG_DEBUG("poll()");
1909                 int64_t now = timeval_ms();
1910                 if (now - start > timeout_ms) {
1911                         LOG_ERROR("Algorithm timed out after %" PRId64 " ms.", now - start);
1912                         riscv_halt(target);
1913                         old_or_new_riscv_poll(target);
1914                         enum gdb_regno regnums[] = {
1915                                 GDB_REGNO_RA, GDB_REGNO_SP, GDB_REGNO_GP, GDB_REGNO_TP,
1916                                 GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_FP,
1917                                 GDB_REGNO_S1, GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2,
1918                                 GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6,
1919                                 GDB_REGNO_A7, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4,
1920                                 GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8,
1921                                 GDB_REGNO_S9, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_T3,
1922                                 GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6,
1923                                 GDB_REGNO_PC,
1924                                 GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE,
1925                         };
1926                         for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) {
1927                                 enum gdb_regno regno = regnums[i];
1928                                 riscv_reg_t reg_value;
1929                                 if (riscv_get_register(target, &reg_value, regno) != ERROR_OK)
1930                                         break;
1931                                 LOG_ERROR("%s = 0x%" PRIx64, gdb_regno_name(regno), reg_value);
1932                         }
1933                         return ERROR_TARGET_TIMEOUT;
1934                 }
1935
1936                 int result = old_or_new_riscv_poll(target);
1937                 if (result != ERROR_OK)
1938                         return result;
1939         }
1940
1941         /* The current hart id might have been changed in poll(). */
1942         if (riscv_select_current_hart(target) != ERROR_OK)
1943                 return ERROR_FAIL;
1944
1945         if (reg_pc->type->get(reg_pc) != ERROR_OK)
1946                 return ERROR_FAIL;
1947         uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1948         if (exit_point && final_pc != exit_point) {
1949                 LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
1950                                 TARGET_PRIxADDR, final_pc, exit_point);
1951                 return ERROR_FAIL;
1952         }
1953
1954         /* Restore Interrupts */
1955         LOG_DEBUG("Restoring Interrupts");
1956         buf_set_u64(mstatus_bytes, 0, info->xlen, current_mstatus);
1957         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1958
1959         /* Restore registers */
1960         uint8_t buf[8] = { 0 };
1961         buf_set_u64(buf, 0, info->xlen, saved_pc);
1962         if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
1963                 return ERROR_FAIL;
1964
1965         for (int i = 0; i < num_reg_params; i++) {
1966                 if (reg_params[i].direction == PARAM_IN ||
1967                                 reg_params[i].direction == PARAM_IN_OUT) {
1968                         struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1969                         if (r->type->get(r) != ERROR_OK) {
1970                                 LOG_ERROR("get(%s) failed", r->name);
1971                                 return ERROR_FAIL;
1972                         }
1973                         buf_cpy(r->value, reg_params[i].value, reg_params[i].size);
1974                 }
1975                 LOG_DEBUG("restore %s", reg_params[i].reg_name);
1976                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1977                 buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]);
1978                 if (r->type->set(r, buf) != ERROR_OK) {
1979                         LOG_ERROR("set(%s) failed", r->name);
1980                         return ERROR_FAIL;
1981                 }
1982         }
1983
1984         return ERROR_OK;
1985 }
1986
1987 static int riscv_checksum_memory(struct target *target,
1988                 target_addr_t address, uint32_t count,
1989                 uint32_t *checksum)
1990 {
1991         struct working_area *crc_algorithm;
1992         struct reg_param reg_params[2];
1993         int retval;
1994
1995         LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
1996
1997         static const uint8_t riscv32_crc_code[] = {
1998 #include "../../../contrib/loaders/checksum/riscv32_crc.inc"
1999         };
2000         static const uint8_t riscv64_crc_code[] = {
2001 #include "../../../contrib/loaders/checksum/riscv64_crc.inc"
2002         };
2003
2004         static const uint8_t *crc_code;
2005
2006         unsigned xlen = riscv_xlen(target);
2007         unsigned crc_code_size;
2008         if (xlen == 32) {
2009                 crc_code = riscv32_crc_code;
2010                 crc_code_size = sizeof(riscv32_crc_code);
2011         } else {
2012                 crc_code = riscv64_crc_code;
2013                 crc_code_size = sizeof(riscv64_crc_code);
2014         }
2015
2016         if (count < crc_code_size * 4) {
2017                 /* Don't use the algorithm for relatively small buffers. It's faster
2018                  * just to read the memory.  target_checksum_memory() will take care of
2019                  * that if we fail. */
2020                 return ERROR_FAIL;
2021         }
2022
2023         retval = target_alloc_working_area(target, crc_code_size, &crc_algorithm);
2024         if (retval != ERROR_OK)
2025                 return retval;
2026
2027         if (crc_algorithm->address + crc_algorithm->size > address &&
2028                         crc_algorithm->address < address + count) {
2029                 /* Region to checksum overlaps with the work area we've been assigned.
2030                  * Bail. (Would be better to manually checksum what we read there, and
2031                  * use the algorithm for the rest.) */
2032                 target_free_working_area(target, crc_algorithm);
2033                 return ERROR_FAIL;
2034         }
2035
2036         retval = target_write_buffer(target, crc_algorithm->address, crc_code_size,
2037                         crc_code);
2038         if (retval != ERROR_OK) {
2039                 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
2040                                 crc_algorithm->address, retval);
2041                 target_free_working_area(target, crc_algorithm);
2042                 return retval;
2043         }
2044
2045         init_reg_param(&reg_params[0], "a0", xlen, PARAM_IN_OUT);
2046         init_reg_param(&reg_params[1], "a1", xlen, PARAM_OUT);
2047         buf_set_u64(reg_params[0].value, 0, xlen, address);
2048         buf_set_u64(reg_params[1].value, 0, xlen, count);
2049
2050         /* 20 second timeout/megabyte */
2051         int timeout = 20000 * (1 + (count / (1024 * 1024)));
2052
2053         retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
2054                         crc_algorithm->address,
2055                         0,      /* Leave exit point unspecified because we don't know. */
2056                         timeout, NULL);
2057
2058         if (retval == ERROR_OK)
2059                 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2060         else
2061                 LOG_ERROR("error executing RISC-V CRC algorithm");
2062
2063         destroy_reg_param(&reg_params[0]);
2064         destroy_reg_param(&reg_params[1]);
2065
2066         target_free_working_area(target, crc_algorithm);
2067
2068         LOG_DEBUG("checksum=0x%" PRIx32 ", result=%d", *checksum, retval);
2069
2070         return retval;
2071 }
2072
2073 /*** OpenOCD Helper Functions ***/
2074
2075 enum riscv_poll_hart {
2076         RPH_NO_CHANGE,
2077         RPH_DISCOVERED_HALTED,
2078         RPH_DISCOVERED_RUNNING,
2079         RPH_ERROR
2080 };
2081 static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
2082 {
2083         RISCV_INFO(r);
2084         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2085                 return RPH_ERROR;
2086
2087         LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
2088
2089         /* If OpenOCD thinks we're running but this hart is halted then it's time
2090          * to raise an event. */
2091         bool halted = riscv_is_halted(target);
2092         if (target->state != TARGET_HALTED && halted) {
2093                 LOG_DEBUG("  triggered a halt");
2094                 r->on_halt(target);
2095                 return RPH_DISCOVERED_HALTED;
2096         } else if (target->state != TARGET_RUNNING && !halted) {
2097                 LOG_DEBUG("  triggered running");
2098                 target->state = TARGET_RUNNING;
2099                 target->debug_reason = DBG_REASON_NOTHALTED;
2100                 return RPH_DISCOVERED_RUNNING;
2101         }
2102
2103         return RPH_NO_CHANGE;
2104 }
2105
2106 int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
2107 {
2108         switch (halt_reason) {
2109                 case RISCV_HALT_BREAKPOINT:
2110                         target->debug_reason = DBG_REASON_BREAKPOINT;
2111                         break;
2112                 case RISCV_HALT_TRIGGER:
2113                         target->debug_reason = DBG_REASON_WATCHPOINT;
2114                         break;
2115                 case RISCV_HALT_INTERRUPT:
2116                 case RISCV_HALT_GROUP:
2117                         target->debug_reason = DBG_REASON_DBGRQ;
2118                         break;
2119                 case RISCV_HALT_SINGLESTEP:
2120                         target->debug_reason = DBG_REASON_SINGLESTEP;
2121                         break;
2122                 case RISCV_HALT_UNKNOWN:
2123                         target->debug_reason = DBG_REASON_UNDEFINED;
2124                         break;
2125                 case RISCV_HALT_ERROR:
2126                         return ERROR_FAIL;
2127         }
2128         LOG_DEBUG("[%s] debug_reason=%d", target_name(target), target->debug_reason);
2129         return ERROR_OK;
2130 }
2131
2132 int sample_memory(struct target *target)
2133 {
2134         RISCV_INFO(r);
2135
2136         if (!r->sample_buf.buf || !r->sample_config.enabled)
2137                 return ERROR_OK;
2138
2139         LOG_DEBUG("buf used/size: %d/%d", r->sample_buf.used, r->sample_buf.size);
2140
2141         uint64_t start = timeval_ms();
2142         riscv_sample_buf_maybe_add_timestamp(target, true);
2143         int result = ERROR_OK;
2144         if (r->sample_memory) {
2145                 result = r->sample_memory(target, &r->sample_buf, &r->sample_config,
2146                                                                           start + TARGET_DEFAULT_POLLING_INTERVAL);
2147                 if (result != ERROR_NOT_IMPLEMENTED)
2148                         goto exit;
2149         }
2150
2151         /* Default slow path. */
2152         while (timeval_ms() - start < TARGET_DEFAULT_POLLING_INTERVAL) {
2153                 for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
2154                         if (r->sample_config.bucket[i].enabled &&
2155                                         r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes < r->sample_buf.size) {
2156                                 assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
2157                                 r->sample_buf.buf[r->sample_buf.used] = i;
2158                                 result = riscv_read_phys_memory(
2159                                         target, r->sample_config.bucket[i].address,
2160                                         r->sample_config.bucket[i].size_bytes, 1,
2161                                         r->sample_buf.buf + r->sample_buf.used + 1);
2162                                 if (result == ERROR_OK)
2163                                         r->sample_buf.used += 1 + r->sample_config.bucket[i].size_bytes;
2164                                 else
2165                                         goto exit;
2166                         }
2167                 }
2168         }
2169
2170 exit:
2171         riscv_sample_buf_maybe_add_timestamp(target, false);
2172         if (result != ERROR_OK) {
2173                 LOG_INFO("Turning off memory sampling because it failed.");
2174                 r->sample_config.enabled = false;
2175         }
2176         return result;
2177 }
2178
2179 /*** OpenOCD Interface ***/
2180 int riscv_openocd_poll(struct target *target)
2181 {
2182         LOG_DEBUG("polling all harts");
2183         int halted_hart = -1;
2184
2185         if (target->smp) {
2186                 unsigned halts_discovered = 0;
2187                 unsigned should_remain_halted = 0;
2188                 unsigned should_resume = 0;
2189                 struct target_list *list;
2190                 foreach_smp_target(list, target->smp_targets) {
2191                         struct target *t = list->target;
2192                         riscv_info_t *r = riscv_info(t);
2193                         enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
2194                         switch (out) {
2195                         case RPH_NO_CHANGE:
2196                                 break;
2197                         case RPH_DISCOVERED_RUNNING:
2198                                 t->state = TARGET_RUNNING;
2199                                 t->debug_reason = DBG_REASON_NOTHALTED;
2200                                 break;
2201                         case RPH_DISCOVERED_HALTED:
2202                                 halts_discovered++;
2203                                 t->state = TARGET_HALTED;
2204                                 enum riscv_halt_reason halt_reason =
2205                                         riscv_halt_reason(t, r->current_hartid);
2206                                 if (set_debug_reason(t, halt_reason) != ERROR_OK)
2207                                         return ERROR_FAIL;
2208
2209                                 if (halt_reason == RISCV_HALT_BREAKPOINT) {
2210                                         int retval;
2211                                         switch (riscv_semihosting(t, &retval)) {
2212                                         case SEMI_NONE:
2213                                         case SEMI_WAITING:
2214                                                 /* This hart should remain halted. */
2215                                                 should_remain_halted++;
2216                                                 break;
2217                                         case SEMI_HANDLED:
2218                                                 /* This hart should be resumed, along with any other
2219                                                          * harts that halted due to haltgroups. */
2220                                                 should_resume++;
2221                                                 break;
2222                                         case SEMI_ERROR:
2223                                                 return retval;
2224                                         }
2225                                 } else if (halt_reason != RISCV_HALT_GROUP) {
2226                                         should_remain_halted++;
2227                                 }
2228                                 break;
2229
2230                         case RPH_ERROR:
2231                                 return ERROR_FAIL;
2232                         }
2233                 }
2234
2235                 LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
2236                                   should_remain_halted, should_resume);
2237                 if (should_remain_halted && should_resume) {
2238                         LOG_WARNING("%d harts should remain halted, and %d should resume.",
2239                                                 should_remain_halted, should_resume);
2240                 }
2241                 if (should_remain_halted) {
2242                         LOG_DEBUG("halt all");
2243                         riscv_halt(target);
2244                 } else if (should_resume) {
2245                         LOG_DEBUG("resume all");
2246                         riscv_resume(target, true, 0, 0, 0, false);
2247                 }
2248
2249                 /* Sample memory if any target is running. */
2250                 foreach_smp_target(list, target->smp_targets) {
2251                         struct target *t = list->target;
2252                         if (t->state == TARGET_RUNNING) {
2253                                 sample_memory(target);
2254                                 break;
2255                         }
2256                 }
2257
2258                 return ERROR_OK;
2259
2260         } else {
2261                 enum riscv_poll_hart out = riscv_poll_hart(target,
2262                                 riscv_current_hartid(target));
2263                 if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING) {
2264                         if (target->state == TARGET_RUNNING)
2265                                 sample_memory(target);
2266                         return ERROR_OK;
2267                 } else if (out == RPH_ERROR) {
2268                         return ERROR_FAIL;
2269                 }
2270
2271                 halted_hart = riscv_current_hartid(target);
2272                 LOG_DEBUG("  hart %d halted", halted_hart);
2273
2274                 enum riscv_halt_reason halt_reason = riscv_halt_reason(target, halted_hart);
2275                 if (set_debug_reason(target, halt_reason) != ERROR_OK)
2276                         return ERROR_FAIL;
2277                 target->state = TARGET_HALTED;
2278         }
2279
2280         if (target->debug_reason == DBG_REASON_BREAKPOINT) {
2281                 int retval;
2282                 switch (riscv_semihosting(target, &retval)) {
2283                         case SEMI_NONE:
2284                         case SEMI_WAITING:
2285                                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2286                                 break;
2287                         case SEMI_HANDLED:
2288                                 if (riscv_resume(target, true, 0, 0, 0, false) != ERROR_OK)
2289                                         return ERROR_FAIL;
2290                                 break;
2291                         case SEMI_ERROR:
2292                                 return retval;
2293                 }
2294         } else {
2295                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2296         }
2297
2298         return ERROR_OK;
2299 }
2300
2301 int riscv_openocd_step(struct target *target, int current,
2302                 target_addr_t address, int handle_breakpoints)
2303 {
2304         LOG_DEBUG("stepping rtos hart");
2305
2306         if (!current)
2307                 riscv_set_register(target, GDB_REGNO_PC, address);
2308
2309         riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
2310         if (disable_triggers(target, trigger_state) != ERROR_OK)
2311                 return ERROR_FAIL;
2312
2313         int out = riscv_step_rtos_hart(target);
2314         if (out != ERROR_OK) {
2315                 LOG_ERROR("unable to step rtos hart");
2316                 return out;
2317         }
2318
2319         register_cache_invalidate(target->reg_cache);
2320
2321         if (enable_triggers(target, trigger_state) != ERROR_OK)
2322                 return ERROR_FAIL;
2323
2324         target->state = TARGET_RUNNING;
2325         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
2326         target->state = TARGET_HALTED;
2327         target->debug_reason = DBG_REASON_SINGLESTEP;
2328         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2329         return out;
2330 }
2331
2332 /* Command Handlers */
2333 COMMAND_HANDLER(riscv_set_command_timeout_sec)
2334 {
2335         if (CMD_ARGC != 1) {
2336                 LOG_ERROR("Command takes exactly 1 parameter");
2337                 return ERROR_COMMAND_SYNTAX_ERROR;
2338         }
2339         int timeout = atoi(CMD_ARGV[0]);
2340         if (timeout <= 0) {
2341                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2342                 return ERROR_FAIL;
2343         }
2344
2345         riscv_command_timeout_sec = timeout;
2346
2347         return ERROR_OK;
2348 }
2349
2350 COMMAND_HANDLER(riscv_set_reset_timeout_sec)
2351 {
2352         if (CMD_ARGC != 1) {
2353                 LOG_ERROR("Command takes exactly 1 parameter");
2354                 return ERROR_COMMAND_SYNTAX_ERROR;
2355         }
2356         int timeout = atoi(CMD_ARGV[0]);
2357         if (timeout <= 0) {
2358                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2359                 return ERROR_FAIL;
2360         }
2361
2362         riscv_reset_timeout_sec = timeout;
2363         return ERROR_OK;
2364 }
2365
2366 COMMAND_HANDLER(riscv_set_prefer_sba)
2367 {
2368         struct target *target = get_current_target(CMD_CTX);
2369         RISCV_INFO(r);
2370         bool prefer_sba;
2371         LOG_WARNING("`riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.");
2372         if (CMD_ARGC != 1) {
2373                 LOG_ERROR("Command takes exactly 1 parameter");
2374                 return ERROR_COMMAND_SYNTAX_ERROR;
2375         }
2376         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], prefer_sba);
2377         if (prefer_sba) {
2378                 /* Use system bus with highest priority */
2379                 r->mem_access_methods[0] = RISCV_MEM_ACCESS_SYSBUS;
2380                 r->mem_access_methods[1] = RISCV_MEM_ACCESS_PROGBUF;
2381                 r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
2382         } else {
2383                 /* Use progbuf with highest priority */
2384                 r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF;
2385                 r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS;
2386                 r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
2387         }
2388
2389         /* Reset warning flags */
2390         r->mem_access_progbuf_warn = true;
2391         r->mem_access_sysbus_warn = true;
2392         r->mem_access_abstract_warn = true;
2393
2394         return ERROR_OK;
2395 }
2396
2397 COMMAND_HANDLER(riscv_set_mem_access)
2398 {
2399         struct target *target = get_current_target(CMD_CTX);
2400         RISCV_INFO(r);
2401         int progbuf_cnt = 0;
2402         int sysbus_cnt = 0;
2403         int abstract_cnt = 0;
2404
2405         if (CMD_ARGC < 1 || CMD_ARGC > RISCV_NUM_MEM_ACCESS_METHODS) {
2406                 LOG_ERROR("Command takes 1 to %d parameters", RISCV_NUM_MEM_ACCESS_METHODS);
2407                 return ERROR_COMMAND_SYNTAX_ERROR;
2408         }
2409
2410         /* Check argument validity */
2411         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2412                 if (strcmp("progbuf", CMD_ARGV[i]) == 0) {
2413                         progbuf_cnt++;
2414                 } else if (strcmp("sysbus", CMD_ARGV[i]) == 0) {
2415                         sysbus_cnt++;
2416                 } else if (strcmp("abstract", CMD_ARGV[i]) == 0) {
2417                         abstract_cnt++;
2418                 } else {
2419                         LOG_ERROR("Unknown argument '%s'. "
2420                                 "Must be one of: 'progbuf', 'sysbus' or 'abstract'.", CMD_ARGV[i]);
2421                         return ERROR_COMMAND_SYNTAX_ERROR;
2422                 }
2423         }
2424         if (progbuf_cnt > 1 || sysbus_cnt > 1 || abstract_cnt > 1) {
2425                 LOG_ERROR("Syntax error - duplicate arguments to `riscv set_mem_access`.");
2426                 return ERROR_COMMAND_SYNTAX_ERROR;
2427         }
2428
2429         /* Args are valid, store them */
2430         for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
2431                 r->mem_access_methods[i] = RISCV_MEM_ACCESS_UNSPECIFIED;
2432         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2433                 if (strcmp("progbuf", CMD_ARGV[i]) == 0)
2434                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_PROGBUF;
2435                 else if (strcmp("sysbus", CMD_ARGV[i]) == 0)
2436                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_SYSBUS;
2437                 else if (strcmp("abstract", CMD_ARGV[i]) == 0)
2438                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_ABSTRACT;
2439         }
2440
2441         /* Reset warning flags */
2442         r->mem_access_progbuf_warn = true;
2443         r->mem_access_sysbus_warn = true;
2444         r->mem_access_abstract_warn = true;
2445
2446         return ERROR_OK;
2447 }
2448
2449 COMMAND_HANDLER(riscv_set_enable_virtual)
2450 {
2451         if (CMD_ARGC != 1) {
2452                 LOG_ERROR("Command takes exactly 1 parameter");
2453                 return ERROR_COMMAND_SYNTAX_ERROR;
2454         }
2455         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virtual);
2456         return ERROR_OK;
2457 }
2458
2459 int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val)
2460 {
2461         char *args = strdup(tcl_arg);
2462         if (!args)
2463                 return ERROR_FAIL;
2464
2465         /* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */
2466         char *arg = strtok(args, ",");
2467         while (arg) {
2468                 unsigned low = 0;
2469                 unsigned high = 0;
2470                 char *name = NULL;
2471
2472                 char *dash = strchr(arg, '-');
2473                 char *equals = strchr(arg, '=');
2474                 unsigned int pos;
2475
2476                 if (!dash && !equals) {
2477                         /* Expecting single register number. */
2478                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2479                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2480                                 free(args);
2481                                 return ERROR_COMMAND_SYNTAX_ERROR;
2482                         }
2483                 } else if (dash && !equals) {
2484                         /* Expecting register range - two numbers separated by a dash: ##-## */
2485                         *dash = 0;
2486                         dash++;
2487                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2488                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2489                                 free(args);
2490                                 return ERROR_COMMAND_SYNTAX_ERROR;
2491                         }
2492                         if (sscanf(dash, "%u%n", &high, &pos) != 1 || pos != strlen(dash)) {
2493                                 LOG_ERROR("Failed to parse single register number from '%s'.", dash);
2494                                 free(args);
2495                                 return ERROR_COMMAND_SYNTAX_ERROR;
2496                         }
2497                         if (high < low) {
2498                                 LOG_ERROR("Incorrect range encountered [%u, %u].", low, high);
2499                                 free(args);
2500                                 return ERROR_FAIL;
2501                         }
2502                 } else if (!dash && equals) {
2503                         /* Expecting single register number with textual name specified: ##=name */
2504                         *equals = 0;
2505                         equals++;
2506                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2507                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2508                                 free(args);
2509                                 return ERROR_COMMAND_SYNTAX_ERROR;
2510                         }
2511
2512                         name = calloc(1, strlen(equals) + strlen(reg_type) + 2);
2513                         if (!name) {
2514                                 LOG_ERROR("Failed to allocate register name.");
2515                                 free(args);
2516                                 return ERROR_FAIL;
2517                         }
2518
2519                         /* Register prefix: "csr_" or "custom_" */
2520                         strcpy(name, reg_type);
2521                         name[strlen(reg_type)] = '_';
2522
2523                         if (sscanf(equals, "%[_a-zA-Z0-9]%n", name + strlen(reg_type) + 1, &pos) != 1 || pos != strlen(equals)) {
2524                                 LOG_ERROR("Failed to parse register name from '%s'.", equals);
2525                                 free(args);
2526                                 free(name);
2527                                 return ERROR_COMMAND_SYNTAX_ERROR;
2528                         }
2529                 } else {
2530                         LOG_ERROR("Invalid argument '%s'.", arg);
2531                         free(args);
2532                         return ERROR_COMMAND_SYNTAX_ERROR;
2533                 }
2534
2535                 high = high > low ? high : low;
2536
2537                 if (high > max_val) {
2538                         LOG_ERROR("Cannot expose %s register number %u, maximum allowed value is %u.", reg_type, high, max_val);
2539                         free(name);
2540                         free(args);
2541                         return ERROR_FAIL;
2542                 }
2543
2544                 /* Check for overlap, name uniqueness. */
2545                 range_list_t *entry;
2546                 list_for_each_entry(entry, ranges, list) {
2547                         if ((entry->low <= high) && (low <= entry->high)) {
2548                                 if (low == high)
2549                                         LOG_WARNING("Duplicate %s register number - "
2550                                                         "Register %u has already been exposed previously", reg_type, low);
2551                                 else
2552                                         LOG_WARNING("Overlapping register ranges - Register range starting from %u overlaps "
2553                                                         "with already exposed register/range at %u.", low, entry->low);
2554                         }
2555
2556                         if (entry->name && name && (strcasecmp(entry->name, name) == 0)) {
2557                                 LOG_ERROR("Duplicate register name \"%s\" found.", name);
2558                                 free(name);
2559                                 free(args);
2560                                 return ERROR_FAIL;
2561                         }
2562                 }
2563
2564                 range_list_t *range = calloc(1, sizeof(range_list_t));
2565                 if (!range) {
2566                         LOG_ERROR("Failed to allocate range list.");
2567                         free(name);
2568                         free(args);
2569                         return ERROR_FAIL;
2570                 }
2571
2572                 range->low = low;
2573                 range->high = high;
2574                 range->name = name;
2575                 list_add(&range->list, ranges);
2576
2577                 arg = strtok(NULL, ",");
2578         }
2579
2580         free(args);
2581         return ERROR_OK;
2582 }
2583
2584 COMMAND_HANDLER(riscv_set_expose_csrs)
2585 {
2586         if (CMD_ARGC == 0) {
2587                 LOG_ERROR("Command expects parameters");
2588                 return ERROR_COMMAND_SYNTAX_ERROR;
2589         }
2590
2591         struct target *target = get_current_target(CMD_CTX);
2592         RISCV_INFO(info);
2593         int ret = ERROR_OK;
2594
2595         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2596                 ret = parse_ranges(&info->expose_csr, CMD_ARGV[i], "csr", 0xfff);
2597                 if (ret != ERROR_OK)
2598                         break;
2599         }
2600
2601         return ret;
2602 }
2603
2604 COMMAND_HANDLER(riscv_set_expose_custom)
2605 {
2606         if (CMD_ARGC == 0) {
2607                 LOG_ERROR("Command expects parameters");
2608                 return ERROR_COMMAND_SYNTAX_ERROR;
2609         }
2610
2611         struct target *target = get_current_target(CMD_CTX);
2612         RISCV_INFO(info);
2613         int ret = ERROR_OK;
2614
2615         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2616                 ret = parse_ranges(&info->expose_custom, CMD_ARGV[i], "custom", 0x3fff);
2617                 if (ret != ERROR_OK)
2618                         break;
2619         }
2620
2621         return ret;
2622 }
2623
2624 COMMAND_HANDLER(riscv_authdata_read)
2625 {
2626         unsigned int index = 0;
2627         if (CMD_ARGC == 0) {
2628                 /* nop */
2629         } else if (CMD_ARGC == 1) {
2630                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2631         } else {
2632                 LOG_ERROR("Command takes at most one parameter");
2633                 return ERROR_COMMAND_SYNTAX_ERROR;
2634         }
2635
2636         struct target *target = get_current_target(CMD_CTX);
2637         if (!target) {
2638                 LOG_ERROR("target is NULL!");
2639                 return ERROR_FAIL;
2640         }
2641
2642         RISCV_INFO(r);
2643         if (!r) {
2644                 LOG_ERROR("riscv_info is NULL!");
2645                 return ERROR_FAIL;
2646         }
2647
2648         if (r->authdata_read) {
2649                 uint32_t value;
2650                 if (r->authdata_read(target, &value, index) != ERROR_OK)
2651                         return ERROR_FAIL;
2652                 command_print_sameline(CMD, "0x%08" PRIx32, value);
2653                 return ERROR_OK;
2654         } else {
2655                 LOG_ERROR("authdata_read is not implemented for this target.");
2656                 return ERROR_FAIL;
2657         }
2658 }
2659
2660 COMMAND_HANDLER(riscv_authdata_write)
2661 {
2662         uint32_t value;
2663         unsigned int index = 0;
2664
2665         if (CMD_ARGC == 0) {
2666                 /* nop */
2667         } else if (CMD_ARGC == 1) {
2668                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
2669         } else if (CMD_ARGC == 2) {
2670                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2671                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2672         } else {
2673                 LOG_ERROR("Command takes at most 2 arguments");
2674                 return ERROR_COMMAND_SYNTAX_ERROR;
2675         }
2676
2677         struct target *target = get_current_target(CMD_CTX);
2678         RISCV_INFO(r);
2679
2680         if (r->authdata_write) {
2681                 return r->authdata_write(target, value, index);
2682         } else {
2683                 LOG_ERROR("authdata_write is not implemented for this target.");
2684                 return ERROR_FAIL;
2685         }
2686 }
2687
2688 COMMAND_HANDLER(riscv_dmi_read)
2689 {
2690         if (CMD_ARGC != 1) {
2691                 LOG_ERROR("Command takes 1 parameter");
2692                 return ERROR_COMMAND_SYNTAX_ERROR;
2693         }
2694
2695         struct target *target = get_current_target(CMD_CTX);
2696         if (!target) {
2697                 LOG_ERROR("target is NULL!");
2698                 return ERROR_FAIL;
2699         }
2700
2701         RISCV_INFO(r);
2702         if (!r) {
2703                 LOG_ERROR("riscv_info is NULL!");
2704                 return ERROR_FAIL;
2705         }
2706
2707         if (r->dmi_read) {
2708                 uint32_t address, value;
2709                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2710                 if (r->dmi_read(target, &value, address) != ERROR_OK)
2711                         return ERROR_FAIL;
2712                 command_print(CMD, "0x%" PRIx32, value);
2713                 return ERROR_OK;
2714         } else {
2715                 LOG_ERROR("dmi_read is not implemented for this target.");
2716                 return ERROR_FAIL;
2717         }
2718 }
2719
2720
2721 COMMAND_HANDLER(riscv_dmi_write)
2722 {
2723         if (CMD_ARGC != 2) {
2724                 LOG_ERROR("Command takes exactly 2 arguments");
2725                 return ERROR_COMMAND_SYNTAX_ERROR;
2726         }
2727
2728         struct target *target = get_current_target(CMD_CTX);
2729         RISCV_INFO(r);
2730
2731         uint32_t address, value;
2732         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2733         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2734
2735         if (r->dmi_write) {
2736                 return r->dmi_write(target, address, value);
2737         } else {
2738                 LOG_ERROR("dmi_write is not implemented for this target.");
2739                 return ERROR_FAIL;
2740         }
2741 }
2742
2743 COMMAND_HANDLER(riscv_test_sba_config_reg)
2744 {
2745         if (CMD_ARGC != 4) {
2746                 LOG_ERROR("Command takes exactly 4 arguments");
2747                 return ERROR_COMMAND_SYNTAX_ERROR;
2748         }
2749
2750         struct target *target = get_current_target(CMD_CTX);
2751         RISCV_INFO(r);
2752
2753         target_addr_t legal_address;
2754         uint32_t num_words;
2755         target_addr_t illegal_address;
2756         bool run_sbbusyerror_test;
2757
2758         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[0], legal_address);
2759         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words);
2760         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[2], illegal_address);
2761         COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test);
2762
2763         if (r->test_sba_config_reg) {
2764                 return r->test_sba_config_reg(target, legal_address, num_words,
2765                                 illegal_address, run_sbbusyerror_test);
2766         } else {
2767                 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
2768                 return ERROR_FAIL;
2769         }
2770 }
2771
2772 COMMAND_HANDLER(riscv_reset_delays)
2773 {
2774         int wait = 0;
2775
2776         if (CMD_ARGC > 1) {
2777                 LOG_ERROR("Command takes at most one argument");
2778                 return ERROR_COMMAND_SYNTAX_ERROR;
2779         }
2780
2781         if (CMD_ARGC == 1)
2782                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], wait);
2783
2784         struct target *target = get_current_target(CMD_CTX);
2785         RISCV_INFO(r);
2786         r->reset_delays_wait = wait;
2787         return ERROR_OK;
2788 }
2789
2790 COMMAND_HANDLER(riscv_set_ir)
2791 {
2792         if (CMD_ARGC != 2) {
2793                 LOG_ERROR("Command takes exactly 2 arguments");
2794                 return ERROR_COMMAND_SYNTAX_ERROR;
2795         }
2796
2797         uint32_t value;
2798         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2799
2800         if (!strcmp(CMD_ARGV[0], "idcode"))
2801                 buf_set_u32(ir_idcode, 0, 32, value);
2802         else if (!strcmp(CMD_ARGV[0], "dtmcs"))
2803                 buf_set_u32(ir_dtmcontrol, 0, 32, value);
2804         else if (!strcmp(CMD_ARGV[0], "dmi"))
2805                 buf_set_u32(ir_dbus, 0, 32, value);
2806         else
2807                 return ERROR_FAIL;
2808
2809         return ERROR_OK;
2810 }
2811
2812 COMMAND_HANDLER(riscv_resume_order)
2813 {
2814         if (CMD_ARGC > 1) {
2815                 LOG_ERROR("Command takes at most one argument");
2816                 return ERROR_COMMAND_SYNTAX_ERROR;
2817         }
2818
2819         if (!strcmp(CMD_ARGV[0], "normal")) {
2820                 resume_order = RO_NORMAL;
2821         } else if (!strcmp(CMD_ARGV[0], "reversed")) {
2822                 resume_order = RO_REVERSED;
2823         } else {
2824                 LOG_ERROR("Unsupported resume order: %s", CMD_ARGV[0]);
2825                 return ERROR_FAIL;
2826         }
2827
2828         return ERROR_OK;
2829 }
2830
2831 COMMAND_HANDLER(riscv_use_bscan_tunnel)
2832 {
2833         int irwidth = 0;
2834         int tunnel_type = BSCAN_TUNNEL_NESTED_TAP;
2835
2836         if (CMD_ARGC > 2) {
2837                 LOG_ERROR("Command takes at most two arguments");
2838                 return ERROR_COMMAND_SYNTAX_ERROR;
2839         } else if (CMD_ARGC == 1) {
2840                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2841         } else if (CMD_ARGC == 2) {
2842                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2843                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tunnel_type);
2844         }
2845         if (tunnel_type == BSCAN_TUNNEL_NESTED_TAP)
2846                 LOG_INFO("Nested Tap based Bscan Tunnel Selected");
2847         else if (tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
2848                 LOG_INFO("Simple Register based Bscan Tunnel Selected");
2849         else
2850                 LOG_INFO("Invalid Tunnel type selected ! : selecting default Nested Tap Type");
2851
2852         bscan_tunnel_type = tunnel_type;
2853         bscan_tunnel_ir_width = irwidth;
2854         return ERROR_OK;
2855 }
2856
2857 COMMAND_HANDLER(riscv_set_enable_virt2phys)
2858 {
2859         if (CMD_ARGC != 1) {
2860                 LOG_ERROR("Command takes exactly 1 parameter");
2861                 return ERROR_COMMAND_SYNTAX_ERROR;
2862         }
2863         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virt2phys);
2864         return ERROR_OK;
2865 }
2866
2867 COMMAND_HANDLER(riscv_set_ebreakm)
2868 {
2869         if (CMD_ARGC != 1) {
2870                 LOG_ERROR("Command takes exactly 1 parameter");
2871                 return ERROR_COMMAND_SYNTAX_ERROR;
2872         }
2873         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreakm);
2874         return ERROR_OK;
2875 }
2876
2877 COMMAND_HANDLER(riscv_set_ebreaks)
2878 {
2879         if (CMD_ARGC != 1) {
2880                 LOG_ERROR("Command takes exactly 1 parameter");
2881                 return ERROR_COMMAND_SYNTAX_ERROR;
2882         }
2883         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaks);
2884         return ERROR_OK;
2885 }
2886
2887 COMMAND_HANDLER(riscv_set_ebreaku)
2888 {
2889         if (CMD_ARGC != 1) {
2890                 LOG_ERROR("Command takes exactly 1 parameter");
2891                 return ERROR_COMMAND_SYNTAX_ERROR;
2892         }
2893         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaku);
2894         return ERROR_OK;
2895 }
2896
2897 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
2898                            unsigned int value)
2899 {
2900         char full_key[80];
2901         snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
2902         command_print(CMD, "%-21s %3d", full_key, value);
2903         return 0;
2904 }
2905
2906 COMMAND_HANDLER(handle_info)
2907 {
2908         struct target *target = get_current_target(CMD_CTX);
2909         RISCV_INFO(r);
2910
2911         /* This output format can be fed directly into TCL's "array set". */
2912
2913         riscv_print_info_line(CMD, "hart", "xlen", riscv_xlen(target));
2914         riscv_enumerate_triggers(target);
2915         riscv_print_info_line(CMD, "hart", "trigger_count",
2916                                                   r->trigger_count);
2917
2918         if (r->print_info)
2919                 return CALL_COMMAND_HANDLER(r->print_info, target);
2920
2921         return 0;
2922 }
2923
2924 static const struct command_registration riscv_exec_command_handlers[] = {
2925         {
2926                 .name = "info",
2927                 .handler = handle_info,
2928                 .mode = COMMAND_EXEC,
2929                 .usage = "",
2930                 .help = "Displays some information OpenOCD detected about the target."
2931         },
2932         {
2933                 .name = "set_command_timeout_sec",
2934                 .handler = riscv_set_command_timeout_sec,
2935                 .mode = COMMAND_ANY,
2936                 .usage = "[sec]",
2937                 .help = "Set the wall-clock timeout (in seconds) for individual commands"
2938         },
2939         {
2940                 .name = "set_reset_timeout_sec",
2941                 .handler = riscv_set_reset_timeout_sec,
2942                 .mode = COMMAND_ANY,
2943                 .usage = "[sec]",
2944                 .help = "Set the wall-clock timeout (in seconds) after reset is deasserted"
2945         },
2946         {
2947                 .name = "set_prefer_sba",
2948                 .handler = riscv_set_prefer_sba,
2949                 .mode = COMMAND_ANY,
2950                 .usage = "on|off",
2951                 .help = "When on, prefer to use System Bus Access to access memory. "
2952                         "When off (default), prefer to use the Program Buffer to access memory."
2953         },
2954         {
2955                 .name = "set_mem_access",
2956                 .handler = riscv_set_mem_access,
2957                 .mode = COMMAND_ANY,
2958                 .usage = "method1 [method2] [method3]",
2959                 .help = "Set which memory access methods shall be used and in which order "
2960                         "of priority. Method can be one of: 'progbuf', 'sysbus' or 'abstract'."
2961         },
2962         {
2963                 .name = "set_enable_virtual",
2964                 .handler = riscv_set_enable_virtual,
2965                 .mode = COMMAND_ANY,
2966                 .usage = "on|off",
2967                 .help = "When on, memory accesses are performed on physical or virtual "
2968                                 "memory depending on the current system configuration. "
2969                                 "When off (default), all memory accessses are performed on physical memory."
2970         },
2971         {
2972                 .name = "expose_csrs",
2973                 .handler = riscv_set_expose_csrs,
2974                 .mode = COMMAND_CONFIG,
2975                 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2976                 .help = "Configure a list of inclusive ranges for CSRs to expose in "
2977                                 "addition to the standard ones. This must be executed before "
2978                                 "`init`."
2979         },
2980         {
2981                 .name = "expose_custom",
2982                 .handler = riscv_set_expose_custom,
2983                 .mode = COMMAND_CONFIG,
2984                 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2985                 .help = "Configure a list of inclusive ranges for custom registers to "
2986                         "expose. custom0 is accessed as abstract register number 0xc000, "
2987                         "etc. This must be executed before `init`."
2988         },
2989         {
2990                 .name = "authdata_read",
2991                 .handler = riscv_authdata_read,
2992                 .usage = "[index]",
2993                 .mode = COMMAND_ANY,
2994                 .help = "Return the 32-bit value read from authdata or authdata0 "
2995                                 "(index=0), or authdata1 (index=1)."
2996         },
2997         {
2998                 .name = "authdata_write",
2999                 .handler = riscv_authdata_write,
3000                 .mode = COMMAND_ANY,
3001                 .usage = "[index] value",
3002                 .help = "Write the 32-bit value to authdata or authdata0 (index=0), "
3003                                 "or authdata1 (index=1)."
3004         },
3005         {
3006                 .name = "dmi_read",
3007                 .handler = riscv_dmi_read,
3008                 .mode = COMMAND_ANY,
3009                 .usage = "address",
3010                 .help = "Perform a 32-bit DMI read at address, returning the value."
3011         },
3012         {
3013                 .name = "dmi_write",
3014                 .handler = riscv_dmi_write,
3015                 .mode = COMMAND_ANY,
3016                 .usage = "address value",
3017                 .help = "Perform a 32-bit DMI write of value at address."
3018         },
3019         {
3020                 .name = "test_sba_config_reg",
3021                 .handler = riscv_test_sba_config_reg,
3022                 .mode = COMMAND_ANY,
3023                 .usage = "legal_address num_words "
3024                         "illegal_address run_sbbusyerror_test[on/off]",
3025                 .help = "Perform a series of tests on the SBCS register. "
3026                         "Inputs are a legal, 128-byte aligned address and a number of words to "
3027                         "read/write starting at that address (i.e., address range [legal address, "
3028                         "legal_address+word_size*num_words) must be legally readable/writable), "
3029                         "an illegal, 128-byte aligned address for error flag/handling cases, "
3030                         "and whether sbbusyerror test should be run."
3031         },
3032         {
3033                 .name = "reset_delays",
3034                 .handler = riscv_reset_delays,
3035                 .mode = COMMAND_ANY,
3036                 .usage = "[wait]",
3037                 .help = "OpenOCD learns how many Run-Test/Idle cycles are required "
3038                         "between scans to avoid encountering the target being busy. This "
3039                         "command resets those learned values after `wait` scans. It's only "
3040                         "useful for testing OpenOCD itself."
3041         },
3042         {
3043                 .name = "resume_order",
3044                 .handler = riscv_resume_order,
3045                 .mode = COMMAND_ANY,
3046                 .usage = "normal|reversed",
3047                 .help = "Choose the order that harts are resumed in when `hasel` is not "
3048                         "supported. Normal order is from lowest hart index to highest. "
3049                         "Reversed order is from highest hart index to lowest."
3050         },
3051         {
3052                 .name = "set_ir",
3053                 .handler = riscv_set_ir,
3054                 .mode = COMMAND_ANY,
3055                 .usage = "[idcode|dtmcs|dmi] value",
3056                 .help = "Set IR value for specified JTAG register."
3057         },
3058         {
3059                 .name = "use_bscan_tunnel",
3060                 .handler = riscv_use_bscan_tunnel,
3061                 .mode = COMMAND_ANY,
3062                 .usage = "value [type]",
3063                 .help = "Enable or disable use of a BSCAN tunnel to reach DM.  Supply "
3064                         "the width of the DM transport TAP's instruction register to "
3065                         "enable.  Supply a value of 0 to disable. Pass A second argument "
3066                         "(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
3067                         "1: DATA_REGISTER}"
3068         },
3069         {
3070                 .name = "set_enable_virt2phys",
3071                 .handler = riscv_set_enable_virt2phys,
3072                 .mode = COMMAND_ANY,
3073                 .usage = "on|off",
3074                 .help = "When on (default), enable translation from virtual address to "
3075                         "physical address."
3076         },
3077         {
3078                 .name = "set_ebreakm",
3079                 .handler = riscv_set_ebreakm,
3080                 .mode = COMMAND_ANY,
3081                 .usage = "on|off",
3082                 .help = "Control dcsr.ebreakm. When off, M-mode ebreak instructions "
3083                         "don't trap to OpenOCD. Defaults to on."
3084         },
3085         {
3086                 .name = "set_ebreaks",
3087                 .handler = riscv_set_ebreaks,
3088                 .mode = COMMAND_ANY,
3089                 .usage = "on|off",
3090                 .help = "Control dcsr.ebreaks. When off, S-mode ebreak instructions "
3091                         "don't trap to OpenOCD. Defaults to on."
3092         },
3093         {
3094                 .name = "set_ebreaku",
3095                 .handler = riscv_set_ebreaku,
3096                 .mode = COMMAND_ANY,
3097                 .usage = "on|off",
3098                 .help = "Control dcsr.ebreaku. When off, U-mode ebreak instructions "
3099                         "don't trap to OpenOCD. Defaults to on."
3100         },
3101         COMMAND_REGISTRATION_DONE
3102 };
3103
3104 /*
3105  * To be noted that RISC-V targets use the same semihosting commands as
3106  * ARM targets.
3107  *
3108  * The main reason is compatibility with existing tools. For example the
3109  * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
3110  * configure semihosting, which generate commands like `arm semihosting
3111  * enable`.
3112  * A secondary reason is the fact that the protocol used is exactly the
3113  * one specified by ARM. If RISC-V will ever define its own semihosting
3114  * protocol, then a command like `riscv semihosting enable` will make
3115  * sense, but for now all semihosting commands are prefixed with `arm`.
3116  */
3117 extern const struct command_registration semihosting_common_handlers[];
3118
3119 const struct command_registration riscv_command_handlers[] = {
3120         {
3121                 .name = "riscv",
3122                 .mode = COMMAND_ANY,
3123                 .help = "RISC-V Command Group",
3124                 .usage = "",
3125                 .chain = riscv_exec_command_handlers
3126         },
3127         {
3128                 .name = "arm",
3129                 .mode = COMMAND_ANY,
3130                 .help = "ARM Command Group",
3131                 .usage = "",
3132                 .chain = semihosting_common_handlers
3133         },
3134         COMMAND_REGISTRATION_DONE
3135 };
3136
3137 static unsigned riscv_xlen_nonconst(struct target *target)
3138 {
3139         return riscv_xlen(target);
3140 }
3141
3142 static unsigned int riscv_data_bits(struct target *target)
3143 {
3144         RISCV_INFO(r);
3145         if (r->data_bits)
3146                 return r->data_bits(target);
3147         return riscv_xlen(target);
3148 }
3149
3150 struct target_type riscv_target = {
3151         .name = "riscv",
3152
3153         .target_create = riscv_create_target,
3154         .init_target = riscv_init_target,
3155         .deinit_target = riscv_deinit_target,
3156         .examine = riscv_examine,
3157
3158         /* poll current target status */
3159         .poll = old_or_new_riscv_poll,
3160
3161         .halt = riscv_halt,
3162         .resume = riscv_target_resume,
3163         .step = old_or_new_riscv_step,
3164
3165         .assert_reset = riscv_assert_reset,
3166         .deassert_reset = riscv_deassert_reset,
3167
3168         .read_memory = riscv_read_memory,
3169         .write_memory = riscv_write_memory,
3170         .read_phys_memory = riscv_read_phys_memory,
3171         .write_phys_memory = riscv_write_phys_memory,
3172
3173         .checksum_memory = riscv_checksum_memory,
3174
3175         .mmu = riscv_mmu,
3176         .virt2phys = riscv_virt2phys,
3177
3178         .get_gdb_arch = riscv_get_gdb_arch,
3179         .get_gdb_reg_list = riscv_get_gdb_reg_list,
3180         .get_gdb_reg_list_noread = riscv_get_gdb_reg_list_noread,
3181
3182         .add_breakpoint = riscv_add_breakpoint,
3183         .remove_breakpoint = riscv_remove_breakpoint,
3184
3185         .add_watchpoint = riscv_add_watchpoint,
3186         .remove_watchpoint = riscv_remove_watchpoint,
3187         .hit_watchpoint = riscv_hit_watchpoint,
3188
3189         .arch_state = riscv_arch_state,
3190
3191         .run_algorithm = riscv_run_algorithm,
3192
3193         .commands = riscv_command_handlers,
3194
3195         .address_bits = riscv_xlen_nonconst,
3196         .data_bits = riscv_data_bits
3197 };
3198
3199 /*** RISC-V Interface ***/
3200
3201 void riscv_info_init(struct target *target, riscv_info_t *r)
3202 {
3203         memset(r, 0, sizeof(*r));
3204         r->dtm_version = 1;
3205         r->registers_initialized = false;
3206         r->current_hartid = target->coreid;
3207         r->version_specific = NULL;
3208
3209         memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
3210
3211         r->xlen = -1;
3212
3213         r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF;
3214         r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS;
3215         r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
3216
3217         r->mem_access_progbuf_warn = true;
3218         r->mem_access_sysbus_warn = true;
3219         r->mem_access_abstract_warn = true;
3220
3221         INIT_LIST_HEAD(&r->expose_csr);
3222         INIT_LIST_HEAD(&r->expose_custom);
3223 }
3224
3225 static int riscv_resume_go_all_harts(struct target *target)
3226 {
3227         RISCV_INFO(r);
3228
3229         LOG_DEBUG("[%s] resuming hart", target_name(target));
3230         if (riscv_select_current_hart(target) != ERROR_OK)
3231                 return ERROR_FAIL;
3232         if (riscv_is_halted(target)) {
3233                 if (r->resume_go(target) != ERROR_OK)
3234                         return ERROR_FAIL;
3235         } else {
3236                 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
3237                                 target_name(target));
3238         }
3239
3240         riscv_invalidate_register_cache(target);
3241         return ERROR_OK;
3242 }
3243
3244 int riscv_step_rtos_hart(struct target *target)
3245 {
3246         RISCV_INFO(r);
3247         if (riscv_select_current_hart(target) != ERROR_OK)
3248                 return ERROR_FAIL;
3249         LOG_DEBUG("[%s] stepping", target_name(target));
3250
3251         if (!riscv_is_halted(target)) {
3252                 LOG_ERROR("Hart isn't halted before single step!");
3253                 return ERROR_FAIL;
3254         }
3255         riscv_invalidate_register_cache(target);
3256         r->on_step(target);
3257         if (r->step_current_hart(target) != ERROR_OK)
3258                 return ERROR_FAIL;
3259         riscv_invalidate_register_cache(target);
3260         r->on_halt(target);
3261         if (!riscv_is_halted(target)) {
3262                 LOG_ERROR("Hart was not halted after single step!");
3263                 return ERROR_FAIL;
3264         }
3265         return ERROR_OK;
3266 }
3267
3268 bool riscv_supports_extension(struct target *target, char letter)
3269 {
3270         RISCV_INFO(r);
3271         unsigned num;
3272         if (letter >= 'a' && letter <= 'z')
3273                 num = letter - 'a';
3274         else if (letter >= 'A' && letter <= 'Z')
3275                 num = letter - 'A';
3276         else
3277                 return false;
3278         return r->misa & BIT(num);
3279 }
3280
3281 unsigned riscv_xlen(const struct target *target)
3282 {
3283         RISCV_INFO(r);
3284         return r->xlen;
3285 }
3286
3287 int riscv_set_current_hartid(struct target *target, int hartid)
3288 {
3289         RISCV_INFO(r);
3290         if (!r->select_current_hart)
3291                 return ERROR_OK;
3292
3293         int previous_hartid = riscv_current_hartid(target);
3294         r->current_hartid = hartid;
3295         LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
3296         if (r->select_current_hart(target) != ERROR_OK)
3297                 return ERROR_FAIL;
3298
3299         return ERROR_OK;
3300 }
3301
3302 void riscv_invalidate_register_cache(struct target *target)
3303 {
3304         RISCV_INFO(r);
3305
3306         LOG_DEBUG("[%d]", target->coreid);
3307         register_cache_invalidate(target->reg_cache);
3308         for (size_t i = 0; i < target->reg_cache->num_regs; ++i) {
3309                 struct reg *reg = &target->reg_cache->reg_list[i];
3310                 reg->valid = false;
3311         }
3312
3313         r->registers_initialized = true;
3314 }
3315
3316 int riscv_current_hartid(const struct target *target)
3317 {
3318         RISCV_INFO(r);
3319         return r->current_hartid;
3320 }
3321
3322 int riscv_count_harts(struct target *target)
3323 {
3324         if (!target)
3325                 return 1;
3326         RISCV_INFO(r);
3327         if (!r || !r->hart_count)
3328                 return 1;
3329         return r->hart_count(target);
3330 }
3331
3332 /**
3333  * If write is true:
3334  *   return true iff we are guaranteed that the register will contain exactly
3335  *       the value we just wrote when it's read.
3336  * If write is false:
3337  *   return true iff we are guaranteed that the register will read the same
3338  *       value in the future as the value we just read.
3339  */
3340 static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
3341 {
3342         /* GPRs, FPRs, vector registers are just normal data stores. */
3343         if (regno <= GDB_REGNO_XPR31 ||
3344                         (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||
3345                         (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31))
3346                 return true;
3347
3348         /* Most CSRs won't change value on us, but we can't assume it about arbitrary
3349          * CSRs. */
3350         switch (regno) {
3351                 case GDB_REGNO_DPC:
3352                         return true;
3353
3354                 case GDB_REGNO_VSTART:
3355                 case GDB_REGNO_VXSAT:
3356                 case GDB_REGNO_VXRM:
3357                 case GDB_REGNO_VLENB:
3358                 case GDB_REGNO_VL:
3359                 case GDB_REGNO_VTYPE:
3360                 case GDB_REGNO_MISA:
3361                 case GDB_REGNO_DCSR:
3362                 case GDB_REGNO_DSCRATCH0:
3363                 case GDB_REGNO_MSTATUS:
3364                 case GDB_REGNO_MEPC:
3365                 case GDB_REGNO_MCAUSE:
3366                 case GDB_REGNO_SATP:
3367                         /*
3368                          * WARL registers might not contain the value we just wrote, but
3369                          * these ones won't spontaneously change their value either. *
3370                          */
3371                         return !write;
3372
3373                 case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
3374                 case GDB_REGNO_TDATA1:  /* Changes value when tselect is changed. */
3375                 case GDB_REGNO_TDATA2:  /* Changse value when tselect is changed. */
3376                 default:
3377                         return false;
3378         }
3379 }
3380
3381 /**
3382  * This function is called when the debug user wants to change the value of a
3383  * register. The new value may be cached, and may not be written until the hart
3384  * is resumed. */
3385 int riscv_set_register(struct target *target, enum gdb_regno regid, riscv_reg_t value)
3386 {
3387         RISCV_INFO(r);
3388         LOG_DEBUG("[%s] %s <- %" PRIx64, target_name(target), gdb_regno_name(regid), value);
3389         assert(r->set_register);
3390
3391         keep_alive();
3392
3393         /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3394         if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 && value == 0 &&
3395                         riscv_supports_extension(target, 'E'))
3396                 return ERROR_OK;
3397
3398         struct reg *reg = &target->reg_cache->reg_list[regid];
3399         buf_set_u64(reg->value, 0, reg->size, value);
3400
3401         int result = r->set_register(target, regid, value);
3402         if (result == ERROR_OK)
3403                 reg->valid = gdb_regno_cacheable(regid, true);
3404         else
3405                 reg->valid = false;
3406         LOG_DEBUG("[%s] wrote 0x%" PRIx64 " to %s valid=%d",
3407                           target_name(target), value, reg->name, reg->valid);
3408         return result;
3409 }
3410
3411 int riscv_get_register(struct target *target, riscv_reg_t *value,
3412                 enum gdb_regno regid)
3413 {
3414         RISCV_INFO(r);
3415
3416         keep_alive();
3417
3418         struct reg *reg = &target->reg_cache->reg_list[regid];
3419         if (!reg->exist) {
3420                 LOG_DEBUG("[%s] %s does not exist.",
3421                                   target_name(target), gdb_regno_name(regid));
3422                 return ERROR_FAIL;
3423         }
3424
3425         if (reg && reg->valid) {
3426                 *value = buf_get_u64(reg->value, 0, reg->size);
3427                 LOG_DEBUG("[%s] %s: %" PRIx64 " (cached)", target_name(target),
3428                                   gdb_regno_name(regid), *value);
3429                 return ERROR_OK;
3430         }
3431
3432         /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3433         if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 &&
3434                         riscv_supports_extension(target, 'E')) {
3435                 *value = 0;
3436                 return ERROR_OK;
3437         }
3438
3439         int result = r->get_register(target, value, regid);
3440
3441         if (result == ERROR_OK)
3442                 reg->valid = gdb_regno_cacheable(regid, false);
3443
3444         LOG_DEBUG("[%s] %s: %" PRIx64, target_name(target),
3445                         gdb_regno_name(regid), *value);
3446         return result;
3447 }
3448
3449 bool riscv_is_halted(struct target *target)
3450 {
3451         RISCV_INFO(r);
3452         assert(r->is_halted);
3453         return r->is_halted(target);
3454 }
3455
3456 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
3457 {
3458         RISCV_INFO(r);
3459         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
3460                 return RISCV_HALT_ERROR;
3461         if (!riscv_is_halted(target)) {
3462                 LOG_ERROR("Hart is not halted!");
3463                 return RISCV_HALT_UNKNOWN;
3464         }
3465         return r->halt_reason(target);
3466 }
3467
3468 size_t riscv_debug_buffer_size(struct target *target)
3469 {
3470         RISCV_INFO(r);
3471         return r->debug_buffer_size;
3472 }
3473
3474 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
3475 {
3476         RISCV_INFO(r);
3477         r->write_debug_buffer(target, index, insn);
3478         return ERROR_OK;
3479 }
3480
3481 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
3482 {
3483         RISCV_INFO(r);
3484         return r->read_debug_buffer(target, index);
3485 }
3486
3487 int riscv_execute_debug_buffer(struct target *target)
3488 {
3489         RISCV_INFO(r);
3490         return r->execute_debug_buffer(target);
3491 }
3492
3493 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
3494 {
3495         RISCV_INFO(r);
3496         r->fill_dmi_write_u64(target, buf, a, d);
3497 }
3498
3499 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
3500 {
3501         RISCV_INFO(r);
3502         r->fill_dmi_read_u64(target, buf, a);
3503 }
3504
3505 void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
3506 {
3507         RISCV_INFO(r);
3508         r->fill_dmi_nop_u64(target, buf);
3509 }
3510
3511 int riscv_dmi_write_u64_bits(struct target *target)
3512 {
3513         RISCV_INFO(r);
3514         return r->dmi_write_u64_bits(target);
3515 }
3516
3517 /**
3518  * Count triggers, and initialize trigger_count for each hart.
3519  * trigger_count is initialized even if this function fails to discover
3520  * something.
3521  * Disable any hardware triggers that have dmode set. We can't have set them
3522  * ourselves. Maybe they're left over from some killed debug session.
3523  * */
3524 int riscv_enumerate_triggers(struct target *target)
3525 {
3526         RISCV_INFO(r);
3527
3528         if (r->triggers_enumerated)
3529                 return ERROR_OK;
3530
3531         r->triggers_enumerated = true;  /* At the very least we tried. */
3532
3533         riscv_reg_t tselect;
3534         int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
3535         /* If tselect is not readable, the trigger module is likely not
3536                 * implemented. There are no triggers to enumerate then and no error
3537                 * should be thrown. */
3538         if (result != ERROR_OK) {
3539                 LOG_DEBUG("[%s] Cannot access tselect register. "
3540                                 "Assuming that triggers are not implemented.", target_name(target));
3541                 r->trigger_count = 0;
3542                 return ERROR_OK;
3543         }
3544
3545         for (unsigned int t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
3546                 r->trigger_count = t;
3547
3548                 /* If we can't write tselect, then this hart does not support triggers. */
3549                 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
3550                         break;
3551                 uint64_t tselect_rb;
3552                 result = riscv_get_register(target, &tselect_rb, GDB_REGNO_TSELECT);
3553                 if (result != ERROR_OK)
3554                         return result;
3555                 /* Mask off the top bit, which is used as tdrmode in old
3556                         * implementations. */
3557                 tselect_rb &= ~(1ULL << (riscv_xlen(target) - 1));
3558                 if (tselect_rb != t)
3559                         break;
3560                 uint64_t tdata1;
3561                 result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
3562                 if (result != ERROR_OK)
3563                         return result;
3564
3565                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
3566                 if (type == 0)
3567                         break;
3568                 switch (type) {
3569                         case 1:
3570                                 /* On these older cores we don't support software using
3571                                         * triggers. */
3572                                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3573                                 break;
3574                         case 2:
3575                                 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3576                                         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3577                                 break;
3578                         case 6:
3579                                 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3580                                         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3581                                 break;
3582                 }
3583         }
3584
3585         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
3586
3587         LOG_INFO("[%s] Found %d triggers", target_name(target), r->trigger_count);
3588
3589         return ERROR_OK;
3590 }
3591
3592 const char *gdb_regno_name(enum gdb_regno regno)
3593 {
3594         static char buf[32];
3595
3596         switch (regno) {
3597                 case GDB_REGNO_ZERO:
3598                         return "zero";
3599                 case GDB_REGNO_RA:
3600                         return "ra";
3601                 case GDB_REGNO_SP:
3602                         return "sp";
3603                 case GDB_REGNO_GP:
3604                         return "gp";
3605                 case GDB_REGNO_TP:
3606                         return "tp";
3607                 case GDB_REGNO_T0:
3608                         return "t0";
3609                 case GDB_REGNO_T1:
3610                         return "t1";
3611                 case GDB_REGNO_T2:
3612                         return "t2";
3613                 case GDB_REGNO_S0:
3614                         return "s0";
3615                 case GDB_REGNO_S1:
3616                         return "s1";
3617                 case GDB_REGNO_A0:
3618                         return "a0";
3619                 case GDB_REGNO_A1:
3620                         return "a1";
3621                 case GDB_REGNO_A2:
3622                         return "a2";
3623                 case GDB_REGNO_A3:
3624                         return "a3";
3625                 case GDB_REGNO_A4:
3626                         return "a4";
3627                 case GDB_REGNO_A5:
3628                         return "a5";
3629                 case GDB_REGNO_A6:
3630                         return "a6";
3631                 case GDB_REGNO_A7:
3632                         return "a7";
3633                 case GDB_REGNO_S2:
3634                         return "s2";
3635                 case GDB_REGNO_S3:
3636                         return "s3";
3637                 case GDB_REGNO_S4:
3638                         return "s4";
3639                 case GDB_REGNO_S5:
3640                         return "s5";
3641                 case GDB_REGNO_S6:
3642                         return "s6";
3643                 case GDB_REGNO_S7:
3644                         return "s7";
3645                 case GDB_REGNO_S8:
3646                         return "s8";
3647                 case GDB_REGNO_S9:
3648                         return "s9";
3649                 case GDB_REGNO_S10:
3650                         return "s10";
3651                 case GDB_REGNO_S11:
3652                         return "s11";
3653                 case GDB_REGNO_T3:
3654                         return "t3";
3655                 case GDB_REGNO_T4:
3656                         return "t4";
3657                 case GDB_REGNO_T5:
3658                         return "t5";
3659                 case GDB_REGNO_T6:
3660                         return "t6";
3661                 case GDB_REGNO_PC:
3662                         return "pc";
3663                 case GDB_REGNO_FPR0:
3664                         return "fpr0";
3665                 case GDB_REGNO_FPR31:
3666                         return "fpr31";
3667                 case GDB_REGNO_CSR0:
3668                         return "csr0";
3669                 case GDB_REGNO_TSELECT:
3670                         return "tselect";
3671                 case GDB_REGNO_TDATA1:
3672                         return "tdata1";
3673                 case GDB_REGNO_TDATA2:
3674                         return "tdata2";
3675                 case GDB_REGNO_MISA:
3676                         return "misa";
3677                 case GDB_REGNO_DPC:
3678                         return "dpc";
3679                 case GDB_REGNO_DCSR:
3680                         return "dcsr";
3681                 case GDB_REGNO_DSCRATCH0:
3682                         return "dscratch0";
3683                 case GDB_REGNO_MSTATUS:
3684                         return "mstatus";
3685                 case GDB_REGNO_MEPC:
3686                         return "mepc";
3687                 case GDB_REGNO_MCAUSE:
3688                         return "mcause";
3689                 case GDB_REGNO_PRIV:
3690                         return "priv";
3691                 case GDB_REGNO_SATP:
3692                         return "satp";
3693                 case GDB_REGNO_VTYPE:
3694                         return "vtype";
3695                 case GDB_REGNO_VL:
3696                         return "vl";
3697                 case GDB_REGNO_V0:
3698                         return "v0";
3699                 case GDB_REGNO_V1:
3700                         return "v1";
3701                 case GDB_REGNO_V2:
3702                         return "v2";
3703                 case GDB_REGNO_V3:
3704                         return "v3";
3705                 case GDB_REGNO_V4:
3706                         return "v4";
3707                 case GDB_REGNO_V5:
3708                         return "v5";
3709                 case GDB_REGNO_V6:
3710                         return "v6";
3711                 case GDB_REGNO_V7:
3712                         return "v7";
3713                 case GDB_REGNO_V8:
3714                         return "v8";
3715                 case GDB_REGNO_V9:
3716                         return "v9";
3717                 case GDB_REGNO_V10:
3718                         return "v10";
3719                 case GDB_REGNO_V11:
3720                         return "v11";
3721                 case GDB_REGNO_V12:
3722                         return "v12";
3723                 case GDB_REGNO_V13:
3724                         return "v13";
3725                 case GDB_REGNO_V14:
3726                         return "v14";
3727                 case GDB_REGNO_V15:
3728                         return "v15";
3729                 case GDB_REGNO_V16:
3730                         return "v16";
3731                 case GDB_REGNO_V17:
3732                         return "v17";
3733                 case GDB_REGNO_V18:
3734                         return "v18";
3735                 case GDB_REGNO_V19:
3736                         return "v19";
3737                 case GDB_REGNO_V20:
3738                         return "v20";
3739                 case GDB_REGNO_V21:
3740                         return "v21";
3741                 case GDB_REGNO_V22:
3742                         return "v22";
3743                 case GDB_REGNO_V23:
3744                         return "v23";
3745                 case GDB_REGNO_V24:
3746                         return "v24";
3747                 case GDB_REGNO_V25:
3748                         return "v25";
3749                 case GDB_REGNO_V26:
3750                         return "v26";
3751                 case GDB_REGNO_V27:
3752                         return "v27";
3753                 case GDB_REGNO_V28:
3754                         return "v28";
3755                 case GDB_REGNO_V29:
3756                         return "v29";
3757                 case GDB_REGNO_V30:
3758                         return "v30";
3759                 case GDB_REGNO_V31:
3760                         return "v31";
3761                 default:
3762                         if (regno <= GDB_REGNO_XPR31)
3763                                 sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
3764                         else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095)
3765                                 sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0);
3766                         else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31)
3767                                 sprintf(buf, "f%d", regno - GDB_REGNO_FPR0);
3768                         else
3769                                 sprintf(buf, "gdb_regno_%d", regno);
3770                         return buf;
3771         }
3772 }
3773
3774 static int register_get(struct reg *reg)
3775 {
3776         riscv_reg_info_t *reg_info = reg->arch_info;
3777         struct target *target = reg_info->target;
3778         RISCV_INFO(r);
3779
3780         if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3781                 if (!r->get_register_buf) {
3782                         LOG_ERROR("Reading register %s not supported on this RISC-V target.",
3783                                         gdb_regno_name(reg->number));
3784                         return ERROR_FAIL;
3785                 }
3786
3787                 if (r->get_register_buf(target, reg->value, reg->number) != ERROR_OK)
3788                         return ERROR_FAIL;
3789         } else {
3790                 uint64_t value;
3791                 int result = riscv_get_register(target, &value, reg->number);
3792                 if (result != ERROR_OK)
3793                         return result;
3794                 buf_set_u64(reg->value, 0, reg->size, value);
3795         }
3796         reg->valid = gdb_regno_cacheable(reg->number, false);
3797         char *str = buf_to_hex_str(reg->value, reg->size);
3798         LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target),
3799                         str, reg->name, reg->valid);
3800         free(str);
3801         return ERROR_OK;
3802 }
3803
3804 static int register_set(struct reg *reg, uint8_t *buf)
3805 {
3806         riscv_reg_info_t *reg_info = reg->arch_info;
3807         struct target *target = reg_info->target;
3808         RISCV_INFO(r);
3809
3810         char *str = buf_to_hex_str(buf, reg->size);
3811         LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target),
3812                         str, reg->name, reg->valid);
3813         free(str);
3814
3815         /* Exit early for writing x0, which on the hardware would be ignored, and we
3816          * don't want to update our cache. */
3817         if (reg->number == GDB_REGNO_ZERO)
3818                 return ERROR_OK;
3819
3820         memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
3821         reg->valid = gdb_regno_cacheable(reg->number, true);
3822
3823         if (reg->number == GDB_REGNO_TDATA1 ||
3824                         reg->number == GDB_REGNO_TDATA2) {
3825                 r->manual_hwbp_set = true;
3826                 /* When enumerating triggers, we clear any triggers with DMODE set,
3827                  * assuming they were left over from a previous debug session. So make
3828                  * sure that is done before a user might be setting their own triggers.
3829                  */
3830                 if (riscv_enumerate_triggers(target) != ERROR_OK)
3831                         return ERROR_FAIL;
3832         }
3833
3834         if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3835                 if (!r->set_register_buf) {
3836                         LOG_ERROR("Writing register %s not supported on this RISC-V target.",
3837                                         gdb_regno_name(reg->number));
3838                         return ERROR_FAIL;
3839                 }
3840
3841                 if (r->set_register_buf(target, reg->number, reg->value) != ERROR_OK)
3842                         return ERROR_FAIL;
3843         } else {
3844                 uint64_t value = buf_get_u64(buf, 0, reg->size);
3845                 if (riscv_set_register(target, reg->number, value) != ERROR_OK)
3846                         return ERROR_FAIL;
3847         }
3848
3849         return ERROR_OK;
3850 }
3851
3852 static struct reg_arch_type riscv_reg_arch_type = {
3853         .get = register_get,
3854         .set = register_set
3855 };
3856
3857 struct csr_info {
3858         unsigned number;
3859         const char *name;
3860 };
3861
3862 static int cmp_csr_info(const void *p1, const void *p2)
3863 {
3864         return (int) (((struct csr_info *)p1)->number) - (int) (((struct csr_info *)p2)->number);
3865 }
3866
3867 int riscv_init_registers(struct target *target)
3868 {
3869         RISCV_INFO(info);
3870
3871         riscv_free_registers(target);
3872
3873         target->reg_cache = calloc(1, sizeof(*target->reg_cache));
3874         if (!target->reg_cache)
3875                 return ERROR_FAIL;
3876         target->reg_cache->name = "RISC-V Registers";
3877         target->reg_cache->num_regs = GDB_REGNO_COUNT;
3878
3879         if (!list_empty(&info->expose_custom)) {
3880                 range_list_t *entry;
3881                 list_for_each_entry(entry, &info->expose_custom, list)
3882                         target->reg_cache->num_regs += entry->high - entry->low + 1;
3883         }
3884
3885         LOG_DEBUG("create register cache for %d registers",
3886                         target->reg_cache->num_regs);
3887
3888         target->reg_cache->reg_list =
3889                 calloc(target->reg_cache->num_regs, sizeof(struct reg));
3890         if (!target->reg_cache->reg_list)
3891                 return ERROR_FAIL;
3892
3893         const unsigned int max_reg_name_len = 12;
3894         free(info->reg_names);
3895         info->reg_names =
3896                 calloc(target->reg_cache->num_regs, max_reg_name_len);
3897         if (!info->reg_names)
3898                 return ERROR_FAIL;
3899         char *reg_name = info->reg_names;
3900
3901         static struct reg_feature feature_cpu = {
3902                 .name = "org.gnu.gdb.riscv.cpu"
3903         };
3904         static struct reg_feature feature_fpu = {
3905                 .name = "org.gnu.gdb.riscv.fpu"
3906         };
3907         static struct reg_feature feature_csr = {
3908                 .name = "org.gnu.gdb.riscv.csr"
3909         };
3910         static struct reg_feature feature_vector = {
3911                 .name = "org.gnu.gdb.riscv.vector"
3912         };
3913         static struct reg_feature feature_virtual = {
3914                 .name = "org.gnu.gdb.riscv.virtual"
3915         };
3916         static struct reg_feature feature_custom = {
3917                 .name = "org.gnu.gdb.riscv.custom"
3918         };
3919
3920         /* These types are built into gdb. */
3921         static struct reg_data_type type_ieee_single = { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" };
3922         static struct reg_data_type type_ieee_double = { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" };
3923         static struct reg_data_type_union_field single_double_fields[] = {
3924                 {"float", &type_ieee_single, single_double_fields + 1},
3925                 {"double", &type_ieee_double, NULL},
3926         };
3927         static struct reg_data_type_union single_double_union = {
3928                 .fields = single_double_fields
3929         };
3930         static struct reg_data_type type_ieee_single_double = {
3931                 .type = REG_TYPE_ARCH_DEFINED,
3932                 .id = "FPU_FD",
3933                 .type_class = REG_TYPE_CLASS_UNION,
3934                 .reg_type_union = &single_double_union
3935         };
3936         static struct reg_data_type type_uint8 = { .type = REG_TYPE_UINT8, .id = "uint8" };
3937         static struct reg_data_type type_uint16 = { .type = REG_TYPE_UINT16, .id = "uint16" };
3938         static struct reg_data_type type_uint32 = { .type = REG_TYPE_UINT32, .id = "uint32" };
3939         static struct reg_data_type type_uint64 = { .type = REG_TYPE_UINT64, .id = "uint64" };
3940         static struct reg_data_type type_uint128 = { .type = REG_TYPE_UINT128, .id = "uint128" };
3941
3942         /* This is roughly the XML we want:
3943          * <vector id="bytes" type="uint8" count="16"/>
3944          * <vector id="shorts" type="uint16" count="8"/>
3945          * <vector id="words" type="uint32" count="4"/>
3946          * <vector id="longs" type="uint64" count="2"/>
3947          * <vector id="quads" type="uint128" count="1"/>
3948          * <union id="riscv_vector_type">
3949          *   <field name="b" type="bytes"/>
3950          *   <field name="s" type="shorts"/>
3951          *   <field name="w" type="words"/>
3952          *   <field name="l" type="longs"/>
3953          *   <field name="q" type="quads"/>
3954          * </union>
3955          */
3956
3957         info->vector_uint8.type = &type_uint8;
3958         info->vector_uint8.count = info->vlenb;
3959         info->type_uint8_vector.type = REG_TYPE_ARCH_DEFINED;
3960         info->type_uint8_vector.id = "bytes";
3961         info->type_uint8_vector.type_class = REG_TYPE_CLASS_VECTOR;
3962         info->type_uint8_vector.reg_type_vector = &info->vector_uint8;
3963
3964         info->vector_uint16.type = &type_uint16;
3965         info->vector_uint16.count = info->vlenb / 2;
3966         info->type_uint16_vector.type = REG_TYPE_ARCH_DEFINED;
3967         info->type_uint16_vector.id = "shorts";
3968         info->type_uint16_vector.type_class = REG_TYPE_CLASS_VECTOR;
3969         info->type_uint16_vector.reg_type_vector = &info->vector_uint16;
3970
3971         info->vector_uint32.type = &type_uint32;
3972         info->vector_uint32.count = info->vlenb / 4;
3973         info->type_uint32_vector.type = REG_TYPE_ARCH_DEFINED;
3974         info->type_uint32_vector.id = "words";
3975         info->type_uint32_vector.type_class = REG_TYPE_CLASS_VECTOR;
3976         info->type_uint32_vector.reg_type_vector = &info->vector_uint32;
3977
3978         info->vector_uint64.type = &type_uint64;
3979         info->vector_uint64.count = info->vlenb / 8;
3980         info->type_uint64_vector.type = REG_TYPE_ARCH_DEFINED;
3981         info->type_uint64_vector.id = "longs";
3982         info->type_uint64_vector.type_class = REG_TYPE_CLASS_VECTOR;
3983         info->type_uint64_vector.reg_type_vector = &info->vector_uint64;
3984
3985         info->vector_uint128.type = &type_uint128;
3986         info->vector_uint128.count = info->vlenb / 16;
3987         info->type_uint128_vector.type = REG_TYPE_ARCH_DEFINED;
3988         info->type_uint128_vector.id = "quads";
3989         info->type_uint128_vector.type_class = REG_TYPE_CLASS_VECTOR;
3990         info->type_uint128_vector.reg_type_vector = &info->vector_uint128;
3991
3992         info->vector_fields[0].name = "b";
3993         info->vector_fields[0].type = &info->type_uint8_vector;
3994         if (info->vlenb >= 2) {
3995                 info->vector_fields[0].next = info->vector_fields + 1;
3996                 info->vector_fields[1].name = "s";
3997                 info->vector_fields[1].type = &info->type_uint16_vector;
3998         } else {
3999                 info->vector_fields[0].next = NULL;
4000         }
4001         if (info->vlenb >= 4) {
4002                 info->vector_fields[1].next = info->vector_fields + 2;
4003                 info->vector_fields[2].name = "w";
4004                 info->vector_fields[2].type = &info->type_uint32_vector;
4005         } else {
4006                 info->vector_fields[1].next = NULL;
4007         }
4008         if (info->vlenb >= 8) {
4009                 info->vector_fields[2].next = info->vector_fields + 3;
4010                 info->vector_fields[3].name = "l";
4011                 info->vector_fields[3].type = &info->type_uint64_vector;
4012         } else {
4013                 info->vector_fields[2].next = NULL;
4014         }
4015         if (info->vlenb >= 16) {
4016                 info->vector_fields[3].next = info->vector_fields + 4;
4017                 info->vector_fields[4].name = "q";
4018                 info->vector_fields[4].type = &info->type_uint128_vector;
4019         } else {
4020                 info->vector_fields[3].next = NULL;
4021         }
4022         info->vector_fields[4].next = NULL;
4023
4024         info->vector_union.fields = info->vector_fields;
4025
4026         info->type_vector.type = REG_TYPE_ARCH_DEFINED;
4027         info->type_vector.id = "riscv_vector";
4028         info->type_vector.type_class = REG_TYPE_CLASS_UNION;
4029         info->type_vector.reg_type_union = &info->vector_union;
4030
4031         struct csr_info csr_info[] = {
4032 #define DECLARE_CSR(name, number) { number, #name },
4033 #include "encoding.h"
4034 #undef DECLARE_CSR
4035         };
4036         /* encoding.h does not contain the registers in sorted order. */
4037         qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info);
4038         unsigned csr_info_index = 0;
4039
4040         int custom_within_range = 0;
4041
4042         riscv_reg_info_t *shared_reg_info = calloc(1, sizeof(riscv_reg_info_t));
4043         if (!shared_reg_info)
4044                 return ERROR_FAIL;
4045         shared_reg_info->target = target;
4046
4047         /* When gdb requests register N, gdb_get_register_packet() assumes that this
4048          * is register at index N in reg_list. So if there are certain registers
4049          * that don't exist, we need to leave holes in the list (or renumber, but
4050          * it would be nice not to have yet another set of numbers to translate
4051          * between). */
4052         for (uint32_t number = 0; number < target->reg_cache->num_regs; number++) {
4053                 struct reg *r = &target->reg_cache->reg_list[number];
4054                 r->dirty = false;
4055                 r->valid = false;
4056                 r->exist = true;
4057                 r->type = &riscv_reg_arch_type;
4058                 r->arch_info = shared_reg_info;
4059                 r->number = number;
4060                 r->size = riscv_xlen(target);
4061                 /* r->size is set in riscv_invalidate_register_cache, maybe because the
4062                  * target is in theory allowed to change XLEN on us. But I expect a lot
4063                  * of other things to break in that case as well. */
4064                 if (number <= GDB_REGNO_XPR31) {
4065                         r->exist = number <= GDB_REGNO_XPR15 ||
4066                                 !riscv_supports_extension(target, 'E');
4067                         /* TODO: For now we fake that all GPRs exist because otherwise gdb
4068                          * doesn't work. */
4069                         r->exist = true;
4070                         r->caller_save = true;
4071                         switch (number) {
4072                                 case GDB_REGNO_ZERO:
4073                                         r->name = "zero";
4074                                         break;
4075                                 case GDB_REGNO_RA:
4076                                         r->name = "ra";
4077                                         break;
4078                                 case GDB_REGNO_SP:
4079                                         r->name = "sp";
4080                                         break;
4081                                 case GDB_REGNO_GP:
4082                                         r->name = "gp";
4083                                         break;
4084                                 case GDB_REGNO_TP:
4085                                         r->name = "tp";
4086                                         break;
4087                                 case GDB_REGNO_T0:
4088                                         r->name = "t0";
4089                                         break;
4090                                 case GDB_REGNO_T1:
4091                                         r->name = "t1";
4092                                         break;
4093                                 case GDB_REGNO_T2:
4094                                         r->name = "t2";
4095                                         break;
4096                                 case GDB_REGNO_FP:
4097                                         r->name = "fp";
4098                                         break;
4099                                 case GDB_REGNO_S1:
4100                                         r->name = "s1";
4101                                         break;
4102                                 case GDB_REGNO_A0:
4103                                         r->name = "a0";
4104                                         break;
4105                                 case GDB_REGNO_A1:
4106                                         r->name = "a1";
4107                                         break;
4108                                 case GDB_REGNO_A2:
4109                                         r->name = "a2";
4110                                         break;
4111                                 case GDB_REGNO_A3:
4112                                         r->name = "a3";
4113                                         break;
4114                                 case GDB_REGNO_A4:
4115                                         r->name = "a4";
4116                                         break;
4117                                 case GDB_REGNO_A5:
4118                                         r->name = "a5";
4119                                         break;
4120                                 case GDB_REGNO_A6:
4121                                         r->name = "a6";
4122                                         break;
4123                                 case GDB_REGNO_A7:
4124                                         r->name = "a7";
4125                                         break;
4126                                 case GDB_REGNO_S2:
4127                                         r->name = "s2";
4128                                         break;
4129                                 case GDB_REGNO_S3:
4130                                         r->name = "s3";
4131                                         break;
4132                                 case GDB_REGNO_S4:
4133                                         r->name = "s4";
4134                                         break;
4135                                 case GDB_REGNO_S5:
4136                                         r->name = "s5";
4137                                         break;
4138                                 case GDB_REGNO_S6:
4139                                         r->name = "s6";
4140                                         break;
4141                                 case GDB_REGNO_S7:
4142                                         r->name = "s7";
4143                                         break;
4144                                 case GDB_REGNO_S8:
4145                                         r->name = "s8";
4146                                         break;
4147                                 case GDB_REGNO_S9:
4148                                         r->name = "s9";
4149                                         break;
4150                                 case GDB_REGNO_S10:
4151                                         r->name = "s10";
4152                                         break;
4153                                 case GDB_REGNO_S11:
4154                                         r->name = "s11";
4155                                         break;
4156                                 case GDB_REGNO_T3:
4157                                         r->name = "t3";
4158                                         break;
4159                                 case GDB_REGNO_T4:
4160                                         r->name = "t4";
4161                                         break;
4162                                 case GDB_REGNO_T5:
4163                                         r->name = "t5";
4164                                         break;
4165                                 case GDB_REGNO_T6:
4166                                         r->name = "t6";
4167                                         break;
4168                         }
4169                         r->group = "general";
4170                         r->feature = &feature_cpu;
4171                 } else if (number == GDB_REGNO_PC) {
4172                         r->caller_save = true;
4173                         sprintf(reg_name, "pc");
4174                         r->group = "general";
4175                         r->feature = &feature_cpu;
4176                 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
4177                         r->caller_save = true;
4178                         if (riscv_supports_extension(target, 'D')) {
4179                                 r->size = 64;
4180                                 if (riscv_supports_extension(target, 'F'))
4181                                         r->reg_data_type = &type_ieee_single_double;
4182                                 else
4183                                         r->reg_data_type = &type_ieee_double;
4184                         } else if (riscv_supports_extension(target, 'F')) {
4185                                 r->reg_data_type = &type_ieee_single;
4186                                 r->size = 32;
4187                         } else {
4188                                 r->exist = false;
4189                         }
4190                         switch (number) {
4191                                 case GDB_REGNO_FT0:
4192                                         r->name = "ft0";
4193                                         break;
4194                                 case GDB_REGNO_FT1:
4195                                         r->name = "ft1";
4196                                         break;
4197                                 case GDB_REGNO_FT2:
4198                                         r->name = "ft2";
4199                                         break;
4200                                 case GDB_REGNO_FT3:
4201                                         r->name = "ft3";
4202                                         break;
4203                                 case GDB_REGNO_FT4:
4204                                         r->name = "ft4";
4205                                         break;
4206                                 case GDB_REGNO_FT5:
4207                                         r->name = "ft5";
4208                                         break;
4209                                 case GDB_REGNO_FT6:
4210                                         r->name = "ft6";
4211                                         break;
4212                                 case GDB_REGNO_FT7:
4213                                         r->name = "ft7";
4214                                         break;
4215                                 case GDB_REGNO_FS0:
4216                                         r->name = "fs0";
4217                                         break;
4218                                 case GDB_REGNO_FS1:
4219                                         r->name = "fs1";
4220                                         break;
4221                                 case GDB_REGNO_FA0:
4222                                         r->name = "fa0";
4223                                         break;
4224                                 case GDB_REGNO_FA1:
4225                                         r->name = "fa1";
4226                                         break;
4227                                 case GDB_REGNO_FA2:
4228                                         r->name = "fa2";
4229                                         break;
4230                                 case GDB_REGNO_FA3:
4231                                         r->name = "fa3";
4232                                         break;
4233                                 case GDB_REGNO_FA4:
4234                                         r->name = "fa4";
4235                                         break;
4236                                 case GDB_REGNO_FA5:
4237                                         r->name = "fa5";
4238                                         break;
4239                                 case GDB_REGNO_FA6:
4240                                         r->name = "fa6";
4241                                         break;
4242                                 case GDB_REGNO_FA7:
4243                                         r->name = "fa7";
4244                                         break;
4245                                 case GDB_REGNO_FS2:
4246                                         r->name = "fs2";
4247                                         break;
4248                                 case GDB_REGNO_FS3:
4249                                         r->name = "fs3";
4250                                         break;
4251                                 case GDB_REGNO_FS4:
4252                                         r->name = "fs4";
4253                                         break;
4254                                 case GDB_REGNO_FS5:
4255                                         r->name = "fs5";
4256                                         break;
4257                                 case GDB_REGNO_FS6:
4258                                         r->name = "fs6";
4259                                         break;
4260                                 case GDB_REGNO_FS7:
4261                                         r->name = "fs7";
4262                                         break;
4263                                 case GDB_REGNO_FS8:
4264                                         r->name = "fs8";
4265                                         break;
4266                                 case GDB_REGNO_FS9:
4267                                         r->name = "fs9";
4268                                         break;
4269                                 case GDB_REGNO_FS10:
4270                                         r->name = "fs10";
4271                                         break;
4272                                 case GDB_REGNO_FS11:
4273                                         r->name = "fs11";
4274                                         break;
4275                                 case GDB_REGNO_FT8:
4276                                         r->name = "ft8";
4277                                         break;
4278                                 case GDB_REGNO_FT9:
4279                                         r->name = "ft9";
4280                                         break;
4281                                 case GDB_REGNO_FT10:
4282                                         r->name = "ft10";
4283                                         break;
4284                                 case GDB_REGNO_FT11:
4285                                         r->name = "ft11";
4286                                         break;
4287                         }
4288                         r->group = "float";
4289                         r->feature = &feature_fpu;
4290                 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
4291                         r->group = "csr";
4292                         r->feature = &feature_csr;
4293                         unsigned csr_number = number - GDB_REGNO_CSR0;
4294
4295                         while (csr_info[csr_info_index].number < csr_number &&
4296                                         csr_info_index < ARRAY_SIZE(csr_info) - 1) {
4297                                 csr_info_index++;
4298                         }
4299                         if (csr_info[csr_info_index].number == csr_number) {
4300                                 r->name = csr_info[csr_info_index].name;
4301                         } else {
4302                                 sprintf(reg_name, "csr%d", csr_number);
4303                                 /* Assume unnamed registers don't exist, unless we have some
4304                                  * configuration that tells us otherwise. That's important
4305                                  * because eg. Eclipse crashes if a target has too many
4306                                  * registers, and apparently has no way of only showing a
4307                                  * subset of registers in any case. */
4308                                 r->exist = false;
4309                         }
4310
4311                         switch (csr_number) {
4312                                 case CSR_FFLAGS:
4313                                 case CSR_FRM:
4314                                 case CSR_FCSR:
4315                                         r->exist = riscv_supports_extension(target, 'F');
4316                                         r->group = "float";
4317                                         r->feature = &feature_fpu;
4318                                         break;
4319                                 case CSR_SSTATUS:
4320                                 case CSR_STVEC:
4321                                 case CSR_SIP:
4322                                 case CSR_SIE:
4323                                 case CSR_SCOUNTEREN:
4324                                 case CSR_SSCRATCH:
4325                                 case CSR_SEPC:
4326                                 case CSR_SCAUSE:
4327                                 case CSR_STVAL:
4328                                 case CSR_SATP:
4329                                         r->exist = riscv_supports_extension(target, 'S');
4330                                         break;
4331                                 case CSR_MEDELEG:
4332                                 case CSR_MIDELEG:
4333                                         /* "In systems with only M-mode, or with both M-mode and
4334                                          * U-mode but without U-mode trap support, the medeleg and
4335                                          * mideleg registers should not exist." */
4336                                         r->exist = riscv_supports_extension(target, 'S') ||
4337                                                 riscv_supports_extension(target, 'N');
4338                                         break;
4339
4340                                 case CSR_PMPCFG1:
4341                                 case CSR_PMPCFG3:
4342                                 case CSR_CYCLEH:
4343                                 case CSR_TIMEH:
4344                                 case CSR_INSTRETH:
4345                                 case CSR_HPMCOUNTER3H:
4346                                 case CSR_HPMCOUNTER4H:
4347                                 case CSR_HPMCOUNTER5H:
4348                                 case CSR_HPMCOUNTER6H:
4349                                 case CSR_HPMCOUNTER7H:
4350                                 case CSR_HPMCOUNTER8H:
4351                                 case CSR_HPMCOUNTER9H:
4352                                 case CSR_HPMCOUNTER10H:
4353                                 case CSR_HPMCOUNTER11H:
4354                                 case CSR_HPMCOUNTER12H:
4355                                 case CSR_HPMCOUNTER13H:
4356                                 case CSR_HPMCOUNTER14H:
4357                                 case CSR_HPMCOUNTER15H:
4358                                 case CSR_HPMCOUNTER16H:
4359                                 case CSR_HPMCOUNTER17H:
4360                                 case CSR_HPMCOUNTER18H:
4361                                 case CSR_HPMCOUNTER19H:
4362                                 case CSR_HPMCOUNTER20H:
4363                                 case CSR_HPMCOUNTER21H:
4364                                 case CSR_HPMCOUNTER22H:
4365                                 case CSR_HPMCOUNTER23H:
4366                                 case CSR_HPMCOUNTER24H:
4367                                 case CSR_HPMCOUNTER25H:
4368                                 case CSR_HPMCOUNTER26H:
4369                                 case CSR_HPMCOUNTER27H:
4370                                 case CSR_HPMCOUNTER28H:
4371                                 case CSR_HPMCOUNTER29H:
4372                                 case CSR_HPMCOUNTER30H:
4373                                 case CSR_HPMCOUNTER31H:
4374                                 case CSR_MCYCLEH:
4375                                 case CSR_MINSTRETH:
4376                                 case CSR_MHPMCOUNTER3H:
4377                                 case CSR_MHPMCOUNTER4H:
4378                                 case CSR_MHPMCOUNTER5H:
4379                                 case CSR_MHPMCOUNTER6H:
4380                                 case CSR_MHPMCOUNTER7H:
4381                                 case CSR_MHPMCOUNTER8H:
4382                                 case CSR_MHPMCOUNTER9H:
4383                                 case CSR_MHPMCOUNTER10H:
4384                                 case CSR_MHPMCOUNTER11H:
4385                                 case CSR_MHPMCOUNTER12H:
4386                                 case CSR_MHPMCOUNTER13H:
4387                                 case CSR_MHPMCOUNTER14H:
4388                                 case CSR_MHPMCOUNTER15H:
4389                                 case CSR_MHPMCOUNTER16H:
4390                                 case CSR_MHPMCOUNTER17H:
4391                                 case CSR_MHPMCOUNTER18H:
4392                                 case CSR_MHPMCOUNTER19H:
4393                                 case CSR_MHPMCOUNTER20H:
4394                                 case CSR_MHPMCOUNTER21H:
4395                                 case CSR_MHPMCOUNTER22H:
4396                                 case CSR_MHPMCOUNTER23H:
4397                                 case CSR_MHPMCOUNTER24H:
4398                                 case CSR_MHPMCOUNTER25H:
4399                                 case CSR_MHPMCOUNTER26H:
4400                                 case CSR_MHPMCOUNTER27H:
4401                                 case CSR_MHPMCOUNTER28H:
4402                                 case CSR_MHPMCOUNTER29H:
4403                                 case CSR_MHPMCOUNTER30H:
4404                                 case CSR_MHPMCOUNTER31H:
4405                                         r->exist = riscv_xlen(target) == 32;
4406                                         break;
4407
4408                                 case CSR_VSTART:
4409                                 case CSR_VXSAT:
4410                                 case CSR_VXRM:
4411                                 case CSR_VL:
4412                                 case CSR_VTYPE:
4413                                 case CSR_VLENB:
4414                                         r->exist = riscv_supports_extension(target, 'V');
4415                                         break;
4416                         }
4417
4418                         if (!r->exist && !list_empty(&info->expose_csr)) {
4419                                 range_list_t *entry;
4420                                 list_for_each_entry(entry, &info->expose_csr, list)
4421                                         if ((entry->low <= csr_number) && (csr_number <= entry->high)) {
4422                                                 if (entry->name) {
4423                                                         *reg_name = 0;
4424                                                         r->name = entry->name;
4425                                                 }
4426
4427                                                 LOG_DEBUG("Exposing additional CSR %d (name=%s)",
4428                                                                 csr_number, entry->name ? entry->name : reg_name);
4429
4430                                                 r->exist = true;
4431                                                 break;
4432                                         }
4433                         }
4434
4435                 } else if (number == GDB_REGNO_PRIV) {
4436                         sprintf(reg_name, "priv");
4437                         r->group = "general";
4438                         r->feature = &feature_virtual;
4439                         r->size = 8;
4440
4441                 } else if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31) {
4442                         r->caller_save = false;
4443                         r->exist = riscv_supports_extension(target, 'V') && info->vlenb;
4444                         r->size = info->vlenb * 8;
4445                         sprintf(reg_name, "v%d", number - GDB_REGNO_V0);
4446                         r->group = "vector";
4447                         r->feature = &feature_vector;
4448                         r->reg_data_type = &info->type_vector;
4449
4450                 } else if (number >= GDB_REGNO_COUNT) {
4451                         /* Custom registers. */
4452                         assert(!list_empty(&info->expose_custom));
4453
4454                         range_list_t *range = list_first_entry(&info->expose_custom, range_list_t, list);
4455
4456                         unsigned custom_number = range->low + custom_within_range;
4457
4458                         r->group = "custom";
4459                         r->feature = &feature_custom;
4460                         r->arch_info = calloc(1, sizeof(riscv_reg_info_t));
4461                         if (!r->arch_info)
4462                                 return ERROR_FAIL;
4463                         ((riscv_reg_info_t *) r->arch_info)->target = target;
4464                         ((riscv_reg_info_t *) r->arch_info)->custom_number = custom_number;
4465                         sprintf(reg_name, "custom%d", custom_number);
4466
4467                         if (range->name) {
4468                                 *reg_name = 0;
4469                                 r->name = range->name;
4470                         }
4471
4472                         LOG_DEBUG("Exposing additional custom register %d (name=%s)",
4473                                         number, range->name ? range->name : reg_name);
4474
4475                         custom_within_range++;
4476                         if (custom_within_range > range->high - range->low) {
4477                                 custom_within_range = 0;
4478                                 list_rotate_left(&info->expose_custom);
4479                         }
4480                 }
4481
4482                 if (reg_name[0]) {
4483                         r->name = reg_name;
4484                         reg_name += strlen(reg_name) + 1;
4485                         assert(reg_name < info->reg_names + target->reg_cache->num_regs *
4486                                         max_reg_name_len);
4487                 }
4488                 r->value = calloc(1, DIV_ROUND_UP(r->size, 8));
4489         }
4490
4491         return ERROR_OK;
4492 }
4493
4494
4495 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
4496                                         riscv_bscan_tunneled_scan_context_t *ctxt)
4497 {
4498         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
4499
4500         memset(ctxt->tunneled_dr, 0, sizeof(ctxt->tunneled_dr));
4501         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
4502                 ctxt->tunneled_dr[3].num_bits = 1;
4503                 ctxt->tunneled_dr[3].out_value = bscan_one;
4504                 ctxt->tunneled_dr[2].num_bits = 7;
4505                 ctxt->tunneled_dr_width = field->num_bits;
4506                 ctxt->tunneled_dr[2].out_value = &ctxt->tunneled_dr_width;
4507                 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4508                    scanning num_bits + 1, and then will right shift the input field after executing the queues */
4509
4510                 ctxt->tunneled_dr[1].num_bits = field->num_bits + 1;
4511                 ctxt->tunneled_dr[1].out_value = field->out_value;
4512                 ctxt->tunneled_dr[1].in_value = field->in_value;
4513
4514                 ctxt->tunneled_dr[0].num_bits = 3;
4515                 ctxt->tunneled_dr[0].out_value = bscan_zero;
4516         } else {
4517                 /* BSCAN_TUNNEL_NESTED_TAP */
4518                 ctxt->tunneled_dr[0].num_bits = 1;
4519                 ctxt->tunneled_dr[0].out_value = bscan_one;
4520                 ctxt->tunneled_dr[1].num_bits = 7;
4521                 ctxt->tunneled_dr_width = field->num_bits;
4522                 ctxt->tunneled_dr[1].out_value = &ctxt->tunneled_dr_width;
4523                 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4524                    scanning num_bits + 1, and then will right shift the input field after executing the queues */
4525                 ctxt->tunneled_dr[2].num_bits = field->num_bits + 1;
4526                 ctxt->tunneled_dr[2].out_value = field->out_value;
4527                 ctxt->tunneled_dr[2].in_value = field->in_value;
4528                 ctxt->tunneled_dr[3].num_bits = 3;
4529                 ctxt->tunneled_dr[3].out_value = bscan_zero;
4530         }
4531         jtag_add_dr_scan(target->tap, ARRAY_SIZE(ctxt->tunneled_dr), ctxt->tunneled_dr, TAP_IDLE);
4532 }