git.gag.com Git - fw/openocd/blob - src/target/riscv/riscv-011.c

   1 /*
   2  * Support for RISC-V, debug version 0.11. This was never an officially adopted
   3  * spec, but SiFive made some silicon that uses it.
   4  */
   5
   6 #include <assert.h>
   7 #include <stdlib.h>
   8 #include <time.h>
   9
  10 #ifdef HAVE_CONFIG_H
  11 #include "config.h"
  12 #endif
  13
  14 #include "target/target.h"
  15 #include "target/algorithm.h"
  16 #include "target/target_type.h"
  17 #include "log.h"
  18 #include "jtag/jtag.h"
  19 #include "target/register.h"
  20 #include "target/breakpoints.h"
  21 #include "helper/time_support.h"
  22 #include "riscv.h"
  23 #include "asm.h"
  24 #include "gdb_regs.h"
  25
  26 /**
  27  * Since almost everything can be accomplish by scanning the dbus register, all
  28  * functions here assume dbus is already selected. The exception are functions
  29  * called directly by OpenOCD, which can't assume anything about what's
  30  * currently in IR. They should set IR to dbus explicitly.
  31  */
  32
  33 /**
  34  * Code structure
  35  *
  36  * At the bottom of the stack are the OpenOCD JTAG functions:
  37  *     jtag_add_[id]r_scan
  38  *     jtag_execute_query
  39  *     jtag_add_runtest
  40  *
  41  * There are a few functions to just instantly shift a register and get its
  42  * value:
  43  *    dtmcontrol_scan
  44  *    idcode_scan
  45  *    dbus_scan
  46  *
  47  * Because doing one scan and waiting for the result is slow, most functions
  48  * batch up a bunch of dbus writes and then execute them all at once. They use
  49  * the scans "class" for this:
  50  *    scans_new
  51  *    scans_delete
  52  *    scans_execute
  53  *    scans_add_...
  54  * Usually you new(), call a bunch of add functions, then execute() and look
  55  * at the results by calling scans_get...()
  56  *
  57  * Optimized functions will directly use the scans class above, but slightly
  58  * lazier code will use the cache functions that in turn use the scans
  59  * functions:
  60  *    cache_get...
  61  *    cache_set...
  62  *    cache_write
  63  * cache_set... update a local structure, which is then synced to the target
  64  * with cache_write(). Only Debug RAM words that are actually changed are sent
  65  * to the target. Afterwards use cache_get... to read results.
  66  */
  67
  68 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
  69 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
  70
  71 #define DIM(x)          (sizeof(x)/sizeof(*x))
  72
  73 /* Constants for legacy SiFive hardware breakpoints. */
  74 #define CSR_BPCONTROL_X                 (1<<0)
  75 #define CSR_BPCONTROL_W                 (1<<1)
  76 #define CSR_BPCONTROL_R                 (1<<2)
  77 #define CSR_BPCONTROL_U                 (1<<3)
  78 #define CSR_BPCONTROL_S                 (1<<4)
  79 #define CSR_BPCONTROL_H                 (1<<5)
  80 #define CSR_BPCONTROL_M                 (1<<6)
  81 #define CSR_BPCONTROL_BPMATCH   (0xf<<7)
  82 #define CSR_BPCONTROL_BPACTION  (0xff<<11)
  83
  84 #define DEBUG_ROM_START         0x800
  85 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
  86 #define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
  87 #define DEBUG_RAM_START         0x400
  88
  89 #define SETHALTNOT                              0x10c
  90
  91 /*** JTAG registers. ***/
  92
  93 #define DTMCONTROL                                      0x10
  94 #define DTMCONTROL_DBUS_RESET           (1<<16)
  95 #define DTMCONTROL_IDLE                         (7<<10)
  96 #define DTMCONTROL_ADDRBITS                     (0xf<<4)
  97 #define DTMCONTROL_VERSION                      (0xf)
  98
  99 #define DBUS                                            0x11
 100 #define DBUS_OP_START                           0
 101 #define DBUS_OP_SIZE                            2
 102 typedef enum {
 103         DBUS_OP_NOP = 0,
 104         DBUS_OP_READ = 1,
 105         DBUS_OP_WRITE = 2
 106 } dbus_op_t;
 107 typedef enum {
 108         DBUS_STATUS_SUCCESS = 0,
 109         DBUS_STATUS_FAILED = 2,
 110         DBUS_STATUS_BUSY = 3
 111 } dbus_status_t;
 112 #define DBUS_DATA_START                         2
 113 #define DBUS_DATA_SIZE                          34
 114 #define DBUS_ADDRESS_START                      36
 115
 116 typedef enum {
 117         RE_OK,
 118         RE_FAIL,
 119         RE_AGAIN
 120 } riscv_error_t;
 121
 122 typedef enum slot {
 123         SLOT0,
 124         SLOT1,
 125         SLOT_LAST,
 126 } slot_t;
 127
 128 /*** Debug Bus registers. ***/
 129
 130 #define DMCONTROL                               0x10
 131 #define DMCONTROL_INTERRUPT             (((uint64_t)1)<<33)
 132 #define DMCONTROL_HALTNOT               (((uint64_t)1)<<32)
 133 #define DMCONTROL_BUSERROR              (7<<19)
 134 #define DMCONTROL_SERIAL                (3<<16)
 135 #define DMCONTROL_AUTOINCREMENT (1<<15)
 136 #define DMCONTROL_ACCESS                (7<<12)
 137 #define DMCONTROL_HARTID                (0x3ff<<2)
 138 #define DMCONTROL_NDRESET               (1<<1)
 139 #define DMCONTROL_FULLRESET             1
 140
 141 #define DMINFO                                  0x11
 142 #define DMINFO_ABUSSIZE                 (0x7fU<<25)
 143 #define DMINFO_SERIALCOUNT              (0xf<<21)
 144 #define DMINFO_ACCESS128                (1<<20)
 145 #define DMINFO_ACCESS64                 (1<<19)
 146 #define DMINFO_ACCESS32                 (1<<18)
 147 #define DMINFO_ACCESS16                 (1<<17)
 148 #define DMINFO_ACCESS8                  (1<<16)
 149 #define DMINFO_DRAMSIZE                 (0x3f<<10)
 150 #define DMINFO_AUTHENTICATED    (1<<5)
 151 #define DMINFO_AUTHBUSY                 (1<<4)
 152 #define DMINFO_AUTHTYPE                 (3<<2)
 153 #define DMINFO_VERSION                  3
 154
 155 /*** Info about the core being debugged. ***/
 156
 157 #define DBUS_ADDRESS_UNKNOWN    0xffff
 158
 159 #define DRAM_CACHE_SIZE         16
 160
 161 struct trigger {
 162         uint64_t address;
 163         uint32_t length;
 164         uint64_t mask;
 165         uint64_t value;
 166         bool read, write, execute;
 167         int unique_id;
 168 };
 169
 170 struct memory_cache_line {
 171         uint32_t data;
 172         bool valid;
 173         bool dirty;
 174 };
 175
 176 typedef struct {
 177         /* Number of address bits in the dbus register. */
 178         uint8_t addrbits;
 179         /* Number of words in Debug RAM. */
 180         unsigned int dramsize;
 181         uint64_t dcsr;
 182         uint64_t dpc;
 183         uint64_t tselect;
 184         bool tselect_dirty;
 185         /* The value that mstatus actually has on the target right now. This is not
 186          * the value we present to the user. That one may be stored in the
 187          * reg_cache. */
 188         uint64_t mstatus_actual;
 189
 190         struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
 191
 192         /* Number of run-test/idle cycles the target requests we do after each dbus
 193          * access. */
 194         unsigned int dtmcontrol_idle;
 195
 196         /* This value is incremented every time a dbus access comes back as "busy".
 197          * It's used to determine how many run-test/idle cycles to feed the target
 198          * in between accesses. */
 199         unsigned int dbus_busy_delay;
 200
 201         /* This value is incremented every time we read the debug interrupt as
 202          * high.  It's used to add extra run-test/idle cycles after setting debug
 203          * interrupt high, so ideally we never have to perform a whole extra scan
 204          * before the interrupt is cleared. */
 205         unsigned int interrupt_high_delay;
 206
 207         bool need_strict_step;
 208         bool never_halted;
 209 } riscv011_info_t;
 210
 211 typedef struct {
 212         bool haltnot;
 213         bool interrupt;
 214 } bits_t;
 215
 216 /*** Necessary prototypes. ***/
 217
 218 static int poll_target(struct target *target, bool announce);
 219 static int riscv011_poll(struct target *target);
 220 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
 221                 int regid);
 222
 223 /*** Utility functions. ***/
 224
 225 #define DEBUG_LENGTH    264
 226
 227 static riscv011_info_t *get_info(const struct target *target)
 228 {
 229         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 230         return (riscv011_info_t *) info->version_specific;
 231 }
 232
 233 static unsigned int slot_offset(const struct target *target, slot_t slot)
 234 {
 235         riscv011_info_t *info = get_info(target);
 236         switch (riscv_xlen(target)) {
 237                 case 32:
 238                         switch (slot) {
 239                                 case SLOT0: return 4;
 240                                 case SLOT1: return 5;
 241                                 case SLOT_LAST: return info->dramsize-1;
 242                         }
 243                         break;
 244                 case 64:
 245                         switch (slot) {
 246                                 case SLOT0: return 4;
 247                                 case SLOT1: return 6;
 248                                 case SLOT_LAST: return info->dramsize-2;
 249                         }
 250         }
 251         LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
 252                         riscv_xlen(target), slot);
 253         assert(0);
 254         return 0; /* Silence -Werror=return-type */
 255 }
 256
 257 static uint32_t load_slot(const struct target *target, unsigned int dest,
 258                 slot_t slot)
 259 {
 260         unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
 261         return load(target, dest, ZERO, offset);
 262 }
 263
 264 static uint32_t store_slot(const struct target *target, unsigned int src,
 265                 slot_t slot)
 266 {
 267         unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
 268         return store(target, src, ZERO, offset);
 269 }
 270
 271 static uint16_t dram_address(unsigned int index)
 272 {
 273         if (index < 0x10)
 274                 return index;
 275         else
 276                 return 0x40 + index - 0x10;
 277 }
 278
 279 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
 280 {
 281         struct scan_field field;
 282         uint8_t in_value[4];
 283         uint8_t out_value[4] = { 0 };
 284
 285         buf_set_u32(out_value, 0, 32, out);
 286
 287         jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
 288
 289         field.num_bits = 32;
 290         field.out_value = out_value;
 291         field.in_value = in_value;
 292         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 293
 294         /* Always return to dbus. */
 295         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 296
 297         int retval = jtag_execute_queue();
 298         if (retval != ERROR_OK) {
 299                 LOG_ERROR("failed jtag scan: %d", retval);
 300                 return retval;
 301         }
 302
 303         uint32_t in = buf_get_u32(field.in_value, 0, 32);
 304         LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
 305
 306         return in;
 307 }
 308
 309 static uint32_t idcode_scan(struct target *target)
 310 {
 311         struct scan_field field;
 312         uint8_t in_value[4];
 313
 314         jtag_add_ir_scan(target->tap, &select_idcode, TAP_IDLE);
 315
 316         field.num_bits = 32;
 317         field.out_value = NULL;
 318         field.in_value = in_value;
 319         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 320
 321         int retval = jtag_execute_queue();
 322         if (retval != ERROR_OK) {
 323                 LOG_ERROR("failed jtag scan: %d", retval);
 324                 return retval;
 325         }
 326
 327         /* Always return to dbus. */
 328         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 329
 330         uint32_t in = buf_get_u32(field.in_value, 0, 32);
 331         LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
 332
 333         return in;
 334 }
 335
 336 static void increase_dbus_busy_delay(struct target *target)
 337 {
 338         riscv011_info_t *info = get_info(target);
 339         info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
 340         LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
 341                         info->dtmcontrol_idle, info->dbus_busy_delay,
 342                         info->interrupt_high_delay);
 343
 344         dtmcontrol_scan(target, DTMCONTROL_DBUS_RESET);
 345 }
 346
 347 static void increase_interrupt_high_delay(struct target *target)
 348 {
 349         riscv011_info_t *info = get_info(target);
 350         info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
 351         LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
 352                         info->dtmcontrol_idle, info->dbus_busy_delay,
 353                         info->interrupt_high_delay);
 354 }
 355
 356 static void add_dbus_scan(const struct target *target, struct scan_field *field,
 357                 uint8_t *out_value, uint8_t *in_value, dbus_op_t op,
 358                 uint16_t address, uint64_t data)
 359 {
 360         riscv011_info_t *info = get_info(target);
 361         RISCV_INFO(r);
 362
 363         if (r->reset_delays_wait >= 0) {
 364                 r->reset_delays_wait--;
 365                 if (r->reset_delays_wait < 0) {
 366                         info->dbus_busy_delay = 0;
 367                         info->interrupt_high_delay = 0;
 368                 }
 369         }
 370
 371         field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
 372         field->in_value = in_value;
 373         field->out_value = out_value;
 374
 375         buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
 376         buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
 377         buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
 378
 379         jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
 380
 381         int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
 382         if (data & DMCONTROL_INTERRUPT)
 383                 idle_count += info->interrupt_high_delay;
 384
 385         if (idle_count)
 386                 jtag_add_runtest(idle_count, TAP_IDLE);
 387 }
 388
 389 static void dump_field(const struct scan_field *field)
 390 {
 391         static const char * const op_string[] = {"nop", "r", "w", "?"};
 392         static const char * const status_string[] = {"+", "?", "F", "b"};
 393
 394         if (debug_level < LOG_LVL_DEBUG)
 395                 return;
 396
 397         uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
 398         unsigned int out_op = (out >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
 399         char out_interrupt = ((out >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
 400         char out_haltnot = ((out >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
 401         unsigned int out_data = out >> 2;
 402         unsigned int out_address = out >> DBUS_ADDRESS_START;
 403         uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
 404         unsigned int in_op = (in >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
 405         char in_interrupt = ((in >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
 406         char in_haltnot = ((in >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
 407         unsigned int in_data = in >> 2;
 408         unsigned int in_address = in >> DBUS_ADDRESS_START;
 409
 410         log_printf_lf(LOG_LVL_DEBUG,
 411                         __FILE__, __LINE__, "scan",
 412                         "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x",
 413                         field->num_bits,
 414                         op_string[out_op], out_interrupt, out_haltnot, out_data,
 415                         out_address,
 416                         status_string[in_op], in_interrupt, in_haltnot, in_data,
 417                         in_address);
 418 }
 419
 420 static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
 421                 uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
 422 {
 423         riscv011_info_t *info = get_info(target);
 424         uint8_t in[8] = {0};
 425         uint8_t out[8] = {0};
 426         struct scan_field field = {
 427                 .num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
 428                 .out_value = out,
 429                 .in_value = in
 430         };
 431
 432         assert(info->addrbits != 0);
 433
 434         buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
 435         buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
 436         buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address_out);
 437
 438         /* Assume dbus is already selected. */
 439         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 440
 441         int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
 442
 443         if (idle_count)
 444                 jtag_add_runtest(idle_count, TAP_IDLE);
 445
 446         int retval = jtag_execute_queue();
 447         if (retval != ERROR_OK) {
 448                 LOG_ERROR("dbus_scan failed jtag scan");
 449                 return DBUS_STATUS_FAILED;
 450         }
 451
 452         if (data_in)
 453                 *data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
 454
 455         if (address_in)
 456                 *address_in = buf_get_u32(in, DBUS_ADDRESS_START, info->addrbits);
 457
 458         dump_field(&field);
 459
 460         return buf_get_u32(in, DBUS_OP_START, DBUS_OP_SIZE);
 461 }
 462
 463 static uint64_t dbus_read(struct target *target, uint16_t address)
 464 {
 465         uint64_t value;
 466         dbus_status_t status;
 467         uint16_t address_in;
 468
 469         /* If the previous read/write was to the same address, we will get the read data
 470          * from the previous access.
 471          * While somewhat nonintuitive, this is an efficient way to get the data.
 472          */
 473
 474         unsigned i = 0;
 475         do {
 476                 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
 477                 if (status == DBUS_STATUS_BUSY)
 478                         increase_dbus_busy_delay(target);
 479                 if (status == DBUS_STATUS_FAILED) {
 480                         LOG_ERROR("dbus_read(0x%x) failed!", address);
 481                         return 0;
 482                 }
 483         } while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
 484                         i++ < 256);
 485
 486         if (status != DBUS_STATUS_SUCCESS)
 487                 LOG_ERROR("failed read from 0x%x; value=0x%" PRIx64 ", status=%d\n", address, value, status);
 488
 489         return value;
 490 }
 491
 492 static void dbus_write(struct target *target, uint16_t address, uint64_t value)
 493 {
 494         dbus_status_t status = DBUS_STATUS_BUSY;
 495         unsigned i = 0;
 496         while (status == DBUS_STATUS_BUSY && i++ < 256) {
 497                 status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
 498                 if (status == DBUS_STATUS_BUSY)
 499                         increase_dbus_busy_delay(target);
 500         }
 501         if (status != DBUS_STATUS_SUCCESS)
 502                 LOG_ERROR("failed to write 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
 503 }
 504
 505 /*** scans "class" ***/
 506
 507 typedef struct {
 508         /* Number of scans that space is reserved for. */
 509         unsigned int scan_count;
 510         /* Size reserved in memory for each scan, in bytes. */
 511         unsigned int scan_size;
 512         unsigned int next_scan;
 513         uint8_t *in;
 514         uint8_t *out;
 515         struct scan_field *field;
 516         const struct target *target;
 517 } scans_t;
 518
 519 static scans_t *scans_new(struct target *target, unsigned int scan_count)
 520 {
 521         scans_t *scans = malloc(sizeof(scans_t));
 522         scans->scan_count = scan_count;
 523         /* This code also gets called before xlen is detected. */
 524         if (riscv_xlen(target))
 525                 scans->scan_size = 2 + riscv_xlen(target) / 8;
 526         else
 527                 scans->scan_size = 2 + 128 / 8;
 528         scans->next_scan = 0;
 529         scans->in = calloc(scans->scan_size, scans->scan_count);
 530         scans->out = calloc(scans->scan_size, scans->scan_count);
 531         scans->field = calloc(scans->scan_count, sizeof(struct scan_field));
 532         scans->target = target;
 533         return scans;
 534 }
 535
 536 static scans_t *scans_delete(scans_t *scans)
 537 {
 538         assert(scans);
 539         free(scans->field);
 540         free(scans->out);
 541         free(scans->in);
 542         free(scans);
 543         return NULL;
 544 }
 545
 546 static void scans_reset(scans_t *scans)
 547 {
 548         scans->next_scan = 0;
 549 }
 550
 551 static void scans_dump(scans_t *scans)
 552 {
 553         for (unsigned int i = 0; i < scans->next_scan; i++)
 554                 dump_field(&scans->field[i]);
 555 }
 556
 557 static int scans_execute(scans_t *scans)
 558 {
 559         int retval = jtag_execute_queue();
 560         if (retval != ERROR_OK) {
 561                 LOG_ERROR("failed jtag scan: %d", retval);
 562                 return retval;
 563         }
 564
 565         scans_dump(scans);
 566
 567         return ERROR_OK;
 568 }
 569
 570 /** Add a 32-bit dbus write to the scans structure. */
 571 static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
 572                 bool set_interrupt)
 573 {
 574         const unsigned int i = scans->next_scan;
 575         int data_offset = scans->scan_size * i;
 576         add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
 577                         scans->in + data_offset, DBUS_OP_WRITE, address,
 578                         (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT | data);
 579         scans->next_scan++;
 580         assert(scans->next_scan <= scans->scan_count);
 581 }
 582
 583 /** Add a 32-bit dbus write for an instruction that jumps to the beginning of
 584  * debug RAM. */
 585 static void scans_add_write_jump(scans_t *scans, uint16_t address,
 586                 bool set_interrupt)
 587 {
 588         scans_add_write32(scans, address,
 589                         jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
 590                         set_interrupt);
 591 }
 592
 593 /** Add a 32-bit dbus write for an instruction that loads from the indicated
 594  * slot. */
 595 static void scans_add_write_load(scans_t *scans, uint16_t address,
 596                 unsigned int reg, slot_t slot, bool set_interrupt)
 597 {
 598         scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
 599                         set_interrupt);
 600 }
 601
 602 /** Add a 32-bit dbus write for an instruction that stores to the indicated
 603  * slot. */
 604 static void scans_add_write_store(scans_t *scans, uint16_t address,
 605                 unsigned int reg, slot_t slot, bool set_interrupt)
 606 {
 607         scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
 608                         set_interrupt);
 609 }
 610
 611 /** Add a 32-bit dbus read. */
 612 static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
 613 {
 614         assert(scans->next_scan < scans->scan_count);
 615         const unsigned int i = scans->next_scan;
 616         int data_offset = scans->scan_size * i;
 617         add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
 618                         scans->in + data_offset, DBUS_OP_READ, address,
 619                         (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT);
 620         scans->next_scan++;
 621 }
 622
 623 /** Add one or more scans to read the indicated slot. */
 624 static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
 625 {
 626         const struct target *target = scans->target;
 627         switch (riscv_xlen(target)) {
 628                 case 32:
 629                         scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
 630                         break;
 631                 case 64:
 632                         scans_add_read32(scans, slot_offset(target, slot), false);
 633                         scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
 634                         break;
 635         }
 636 }
 637
 638 static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
 639                 unsigned first, unsigned num)
 640 {
 641         return buf_get_u32(scans->in + scans->scan_size * index, first, num);
 642 }
 643
 644 static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
 645                 unsigned first, unsigned num)
 646 {
 647         return buf_get_u64(scans->in + scans->scan_size * index, first, num);
 648 }
 649
 650 /*** end of scans class ***/
 651
 652 static uint32_t dram_read32(struct target *target, unsigned int index)
 653 {
 654         uint16_t address = dram_address(index);
 655         uint32_t value = dbus_read(target, address);
 656         return value;
 657 }
 658
 659 static void dram_write32(struct target *target, unsigned int index, uint32_t value,
 660                 bool set_interrupt)
 661 {
 662         uint64_t dbus_value = DMCONTROL_HALTNOT | value;
 663         if (set_interrupt)
 664                 dbus_value |= DMCONTROL_INTERRUPT;
 665         dbus_write(target, dram_address(index), dbus_value);
 666 }
 667
 668 /** Read the haltnot and interrupt bits. */
 669 static bits_t read_bits(struct target *target)
 670 {
 671         uint64_t value;
 672         dbus_status_t status;
 673         uint16_t address_in;
 674         riscv011_info_t *info = get_info(target);
 675
 676         bits_t err_result = {
 677                 .haltnot = 0,
 678                 .interrupt = 0
 679         };
 680
 681         do {
 682                 unsigned i = 0;
 683                 do {
 684                         status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
 685                         if (status == DBUS_STATUS_BUSY) {
 686                                 if (address_in == (1<<info->addrbits) - 1 &&
 687                                                 value == (1ULL<<DBUS_DATA_SIZE) - 1) {
 688                                         LOG_ERROR("TDO seems to be stuck high.");
 689                                         return err_result;
 690                                 }
 691                                 increase_dbus_busy_delay(target);
 692                         } else if (status == DBUS_STATUS_FAILED) {
 693                                 /* TODO: return an actual error */
 694                                 return err_result;
 695                         }
 696                 } while (status == DBUS_STATUS_BUSY && i++ < 256);
 697
 698                 if (i >= 256) {
 699                         LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status);
 700                         return err_result;
 701                 }
 702         } while (address_in > 0x10 && address_in != DMCONTROL);
 703
 704         bits_t result = {
 705                 .haltnot = get_field(value, DMCONTROL_HALTNOT),
 706                 .interrupt = get_field(value, DMCONTROL_INTERRUPT)
 707         };
 708         return result;
 709 }
 710
 711 static int wait_for_debugint_clear(struct target *target, bool ignore_first)
 712 {
 713         time_t start = time(NULL);
 714         if (ignore_first) {
 715                 /* Throw away the results of the first read, since they'll contain the
 716                  * result of the read that happened just before debugint was set.
 717                  * (Assuming the last scan before calling this function was one that
 718                  * sets debugint.) */
 719                 read_bits(target);
 720         }
 721         while (1) {
 722                 bits_t bits = read_bits(target);
 723                 if (!bits.interrupt)
 724                         return ERROR_OK;
 725                 if (time(NULL) - start > riscv_command_timeout_sec) {
 726                         LOG_ERROR("Timed out waiting for debug int to clear."
 727                                   "Increase timeout with riscv set_command_timeout_sec.");
 728                         return ERROR_FAIL;
 729                 }
 730         }
 731 }
 732
 733 static int dram_check32(struct target *target, unsigned int index,
 734                 uint32_t expected)
 735 {
 736         uint16_t address = dram_address(index);
 737         uint32_t actual = dbus_read(target, address);
 738         if (expected != actual) {
 739                 LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
 740                                 expected, index, actual);
 741                 return ERROR_FAIL;
 742         }
 743         return ERROR_OK;
 744 }
 745
 746 static void cache_set32(struct target *target, unsigned int index, uint32_t data)
 747 {
 748         riscv011_info_t *info = get_info(target);
 749         if (info->dram_cache[index].valid &&
 750                         info->dram_cache[index].data == data) {
 751                 /* This is already preset on the target. */
 752                 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
 753                 return;
 754         }
 755         LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
 756         info->dram_cache[index].data = data;
 757         info->dram_cache[index].valid = true;
 758         info->dram_cache[index].dirty = true;
 759 }
 760
 761 static void cache_set(struct target *target, slot_t slot, uint64_t data)
 762 {
 763         unsigned int offset = slot_offset(target, slot);
 764         cache_set32(target, offset, data);
 765         if (riscv_xlen(target) > 32)
 766                 cache_set32(target, offset + 1, data >> 32);
 767 }
 768
 769 static void cache_set_jump(struct target *target, unsigned int index)
 770 {
 771         cache_set32(target, index,
 772                         jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
 773 }
 774
 775 static void cache_set_load(struct target *target, unsigned int index,
 776                 unsigned int reg, slot_t slot)
 777 {
 778         uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
 779         cache_set32(target, index, load(target, reg, ZERO, offset));
 780 }
 781
 782 static void cache_set_store(struct target *target, unsigned int index,
 783                 unsigned int reg, slot_t slot)
 784 {
 785         uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
 786         cache_set32(target, index, store(target, reg, ZERO, offset));
 787 }
 788
 789 static void dump_debug_ram(struct target *target)
 790 {
 791         for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
 792                 uint32_t value = dram_read32(target, i);
 793                 LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
 794         }
 795 }
 796
 797 /* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
 798 static void cache_invalidate(struct target *target)
 799 {
 800         riscv011_info_t *info = get_info(target);
 801         for (unsigned int i = 0; i < info->dramsize; i++) {
 802                 info->dram_cache[i].valid = false;
 803                 info->dram_cache[i].dirty = false;
 804         }
 805 }
 806
 807 /* Called by cache_write() after the program has run. Also call this if you're
 808  * running programs without calling cache_write(). */
 809 static void cache_clean(struct target *target)
 810 {
 811         riscv011_info_t *info = get_info(target);
 812         for (unsigned int i = 0; i < info->dramsize; i++) {
 813                 if (i >= 4)
 814                         info->dram_cache[i].valid = false;
 815                 info->dram_cache[i].dirty = false;
 816         }
 817 }
 818
 819 static int cache_check(struct target *target)
 820 {
 821         riscv011_info_t *info = get_info(target);
 822         int error = 0;
 823
 824         for (unsigned int i = 0; i < info->dramsize; i++) {
 825                 if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
 826                         if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK)
 827                                 error++;
 828                 }
 829         }
 830
 831         if (error) {
 832                 dump_debug_ram(target);
 833                 return ERROR_FAIL;
 834         }
 835
 836         return ERROR_OK;
 837 }
 838
 839 /** Write cache to the target, and optionally run the program.
 840  * Then read the value at address into the cache, assuming address < 128. */
 841 #define CACHE_NO_READ   128
 842 static int cache_write(struct target *target, unsigned int address, bool run)
 843 {
 844         LOG_DEBUG("enter");
 845         riscv011_info_t *info = get_info(target);
 846         scans_t *scans = scans_new(target, info->dramsize + 2);
 847
 848         unsigned int last = info->dramsize;
 849         for (unsigned int i = 0; i < info->dramsize; i++) {
 850                 if (info->dram_cache[i].dirty)
 851                         last = i;
 852         }
 853
 854         if (last == info->dramsize) {
 855                 /* Nothing needs to be written to RAM. */
 856                 dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | (run ? DMCONTROL_INTERRUPT : 0));
 857
 858         } else {
 859                 for (unsigned int i = 0; i < info->dramsize; i++) {
 860                         if (info->dram_cache[i].dirty) {
 861                                 bool set_interrupt = (i == last && run);
 862                                 scans_add_write32(scans, i, info->dram_cache[i].data,
 863                                                 set_interrupt);
 864                         }
 865                 }
 866         }
 867
 868         if (run || address < CACHE_NO_READ) {
 869                 /* Throw away the results of the first read, since it'll contain the
 870                  * result of the read that happened just before debugint was set. */
 871                 scans_add_read32(scans, address, false);
 872
 873                 /* This scan contains the results of the read the caller requested, as
 874                  * well as an interrupt bit worth looking at. */
 875                 scans_add_read32(scans, address, false);
 876         }
 877
 878         int retval = scans_execute(scans);
 879         if (retval != ERROR_OK) {
 880                 scans_delete(scans);
 881                 LOG_ERROR("JTAG execute failed.");
 882                 return retval;
 883         }
 884
 885         int errors = 0;
 886         for (unsigned int i = 0; i < scans->next_scan; i++) {
 887                 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
 888                                 DBUS_OP_SIZE);
 889                 switch (status) {
 890                         case DBUS_STATUS_SUCCESS:
 891                                 break;
 892                         case DBUS_STATUS_FAILED:
 893                                 LOG_ERROR("Debug RAM write failed. Hardware error?");
 894                                 scans_delete(scans);
 895                                 return ERROR_FAIL;
 896                         case DBUS_STATUS_BUSY:
 897                                 errors++;
 898                                 break;
 899                         default:
 900                                 LOG_ERROR("Got invalid bus access status: %d", status);
 901                                 scans_delete(scans);
 902                                 return ERROR_FAIL;
 903                 }
 904         }
 905
 906         if (errors) {
 907                 increase_dbus_busy_delay(target);
 908
 909                 /* Try again, using the slow careful code.
 910                  * Write all RAM, just to be extra cautious. */
 911                 for (unsigned int i = 0; i < info->dramsize; i++) {
 912                         if (i == last && run)
 913                                 dram_write32(target, last, info->dram_cache[last].data, true);
 914                         else
 915                                 dram_write32(target, i, info->dram_cache[i].data, false);
 916                         info->dram_cache[i].dirty = false;
 917                 }
 918                 if (run)
 919                         cache_clean(target);
 920
 921                 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
 922                         LOG_ERROR("Debug interrupt didn't clear.");
 923                         dump_debug_ram(target);
 924                         scans_delete(scans);
 925                         return ERROR_FAIL;
 926                 }
 927
 928         } else {
 929                 if (run) {
 930                         cache_clean(target);
 931                 } else {
 932                         for (unsigned int i = 0; i < info->dramsize; i++)
 933                                 info->dram_cache[i].dirty = false;
 934                 }
 935
 936                 if (run || address < CACHE_NO_READ) {
 937                         int interrupt = scans_get_u32(scans, scans->next_scan-1,
 938                                         DBUS_DATA_START + 33, 1);
 939                         if (interrupt) {
 940                                 increase_interrupt_high_delay(target);
 941                                 /* Slow path wait for it to clear. */
 942                                 if (wait_for_debugint_clear(target, false) != ERROR_OK) {
 943                                         LOG_ERROR("Debug interrupt didn't clear.");
 944                                         dump_debug_ram(target);
 945                                         scans_delete(scans);
 946                                         return ERROR_FAIL;
 947                                 }
 948                         } else {
 949                                 /* We read a useful value in that last scan. */
 950                                 unsigned int read_addr = scans_get_u32(scans, scans->next_scan-1,
 951                                                 DBUS_ADDRESS_START, info->addrbits);
 952                                 if (read_addr != address) {
 953                                         LOG_INFO("Got data from 0x%x but expected it from 0x%x",
 954                                                         read_addr, address);
 955                                 }
 956                                 info->dram_cache[read_addr].data =
 957                                         scans_get_u32(scans, scans->next_scan-1, DBUS_DATA_START, 32);
 958                                 info->dram_cache[read_addr].valid = true;
 959                         }
 960                 }
 961         }
 962
 963         scans_delete(scans);
 964         LOG_DEBUG("exit");
 965
 966         return ERROR_OK;
 967 }
 968
 969 static uint32_t cache_get32(struct target *target, unsigned int address)
 970 {
 971         riscv011_info_t *info = get_info(target);
 972         if (!info->dram_cache[address].valid) {
 973                 info->dram_cache[address].data = dram_read32(target, address);
 974                 info->dram_cache[address].valid = true;
 975         }
 976         return info->dram_cache[address].data;
 977 }
 978
 979 static uint64_t cache_get(struct target *target, slot_t slot)
 980 {
 981         unsigned int offset = slot_offset(target, slot);
 982         uint64_t value = cache_get32(target, offset);
 983         if (riscv_xlen(target) > 32)
 984                 value |= ((uint64_t) cache_get32(target, offset + 1)) << 32;
 985         return value;
 986 }
 987
 988 /* Write instruction that jumps from the specified word in Debug RAM to resume
 989  * in Debug ROM. */
 990 static void dram_write_jump(struct target *target, unsigned int index,
 991                 bool set_interrupt)
 992 {
 993         dram_write32(target, index,
 994                         jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
 995                         set_interrupt);
 996 }
 997
 998 static int wait_for_state(struct target *target, enum target_state state)
 999 {
1000         time_t start = time(NULL);
1001         while (1) {
1002                 int result = riscv011_poll(target);
1003                 if (result != ERROR_OK)
1004                         return result;
1005                 if (target->state == state)
1006                         return ERROR_OK;
1007                 if (time(NULL) - start > riscv_command_timeout_sec) {
1008                         LOG_ERROR("Timed out waiting for state %d. "
1009                                   "Increase timeout with riscv set_command_timeout_sec.", state);
1010                         return ERROR_FAIL;
1011                 }
1012         }
1013 }
1014
1015 static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
1016 {
1017         riscv011_info_t *info = get_info(target);
1018         cache_set32(target, 0, csrr(S0, csr));
1019         cache_set_store(target, 1, S0, SLOT0);
1020         cache_set_jump(target, 2);
1021         if (cache_write(target, 4, true) != ERROR_OK)
1022                 return ERROR_FAIL;
1023         *value = cache_get(target, SLOT0);
1024         LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
1025
1026         uint32_t exception = cache_get32(target, info->dramsize-1);
1027         if (exception) {
1028                 LOG_WARNING("Got exception 0x%x when reading %s", exception,
1029                                 gdb_regno_name(GDB_REGNO_CSR0 + csr));
1030                 *value = ~0;
1031                 return ERROR_FAIL;
1032         }
1033
1034         return ERROR_OK;
1035 }
1036
1037 static int write_csr(struct target *target, uint32_t csr, uint64_t value)
1038 {
1039         LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
1040         cache_set_load(target, 0, S0, SLOT0);
1041         cache_set32(target, 1, csrw(S0, csr));
1042         cache_set_jump(target, 2);
1043         cache_set(target, SLOT0, value);
1044         if (cache_write(target, 4, true) != ERROR_OK)
1045                 return ERROR_FAIL;
1046
1047         return ERROR_OK;
1048 }
1049
1050 static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
1051 {
1052         cache_set_load(target, 0, gpr, SLOT0);
1053         cache_set_jump(target, 1);
1054         cache_set(target, SLOT0, value);
1055         if (cache_write(target, 4, true) != ERROR_OK)
1056                 return ERROR_FAIL;
1057         return ERROR_OK;
1058 }
1059
1060 static int maybe_read_tselect(struct target *target)
1061 {
1062         riscv011_info_t *info = get_info(target);
1063
1064         if (info->tselect_dirty) {
1065                 int result = read_csr(target, &info->tselect, CSR_TSELECT);
1066                 if (result != ERROR_OK)
1067                         return result;
1068                 info->tselect_dirty = false;
1069         }
1070
1071         return ERROR_OK;
1072 }
1073
1074 static int maybe_write_tselect(struct target *target)
1075 {
1076         riscv011_info_t *info = get_info(target);
1077
1078         if (!info->tselect_dirty) {
1079                 int result = write_csr(target, CSR_TSELECT, info->tselect);
1080                 if (result != ERROR_OK)
1081                         return result;
1082                 info->tselect_dirty = true;
1083         }
1084
1085         return ERROR_OK;
1086 }
1087
1088 static int execute_resume(struct target *target, bool step)
1089 {
1090         riscv011_info_t *info = get_info(target);
1091
1092         LOG_DEBUG("step=%d", step);
1093
1094         maybe_write_tselect(target);
1095
1096         /* TODO: check if dpc is dirty (which also is true if an exception was hit
1097          * at any time) */
1098         cache_set_load(target, 0, S0, SLOT0);
1099         cache_set32(target, 1, csrw(S0, CSR_DPC));
1100         cache_set_jump(target, 2);
1101         cache_set(target, SLOT0, info->dpc);
1102         if (cache_write(target, 4, true) != ERROR_OK)
1103                 return ERROR_FAIL;
1104
1105         struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1106         if (mstatus_reg->valid) {
1107                 uint64_t mstatus_user = buf_get_u64(mstatus_reg->value, 0, riscv_xlen(target));
1108                 if (mstatus_user != info->mstatus_actual) {
1109                         cache_set_load(target, 0, S0, SLOT0);
1110                         cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
1111                         cache_set_jump(target, 2);
1112                         cache_set(target, SLOT0, mstatus_user);
1113                         if (cache_write(target, 4, true) != ERROR_OK)
1114                                 return ERROR_FAIL;
1115                 }
1116         }
1117
1118         info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS | DCSR_EBREAKU;
1119         info->dcsr &= ~DCSR_HALT;
1120
1121         if (step)
1122                 info->dcsr |= DCSR_STEP;
1123         else
1124                 info->dcsr &= ~DCSR_STEP;
1125
1126         dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1127         dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1128         dram_write32(target, 2, fence_i(), false);
1129         dram_write_jump(target, 3, false);
1130
1131         /* Write DCSR value, set interrupt and clear haltnot. */
1132         uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
1133         dbus_write(target, dram_address(4), dbus_value);
1134
1135         cache_invalidate(target);
1136
1137         if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1138                 LOG_ERROR("Debug interrupt didn't clear.");
1139                 return ERROR_FAIL;
1140         }
1141
1142         target->state = TARGET_RUNNING;
1143         register_cache_invalidate(target->reg_cache);
1144
1145         return ERROR_OK;
1146 }
1147
1148 /* Execute a step, and wait for reentry into Debug Mode. */
1149 static int full_step(struct target *target, bool announce)
1150 {
1151         int result = execute_resume(target, true);
1152         if (result != ERROR_OK)
1153                 return result;
1154         time_t start = time(NULL);
1155         while (1) {
1156                 result = poll_target(target, announce);
1157                 if (result != ERROR_OK)
1158                         return result;
1159                 if (target->state != TARGET_DEBUG_RUNNING)
1160                         break;
1161                 if (time(NULL) - start > riscv_command_timeout_sec) {
1162                         LOG_ERROR("Timed out waiting for step to complete."
1163                                         "Increase timeout with riscv set_command_timeout_sec");
1164                         return ERROR_FAIL;
1165                 }
1166         }
1167         return ERROR_OK;
1168 }
1169
1170 static int resume(struct target *target, int debug_execution, bool step)
1171 {
1172         if (debug_execution) {
1173                 LOG_ERROR("TODO: debug_execution is true");
1174                 return ERROR_FAIL;
1175         }
1176
1177         return execute_resume(target, step);
1178 }
1179
1180 static uint64_t reg_cache_get(struct target *target, unsigned int number)
1181 {
1182         struct reg *r = &target->reg_cache->reg_list[number];
1183         if (!r->valid) {
1184                 LOG_ERROR("Register cache entry for %d is invalid!", number);
1185                 assert(r->valid);
1186         }
1187         uint64_t value = buf_get_u64(r->value, 0, r->size);
1188         LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
1189         return value;
1190 }
1191
1192 static void reg_cache_set(struct target *target, unsigned int number,
1193                 uint64_t value)
1194 {
1195         struct reg *r = &target->reg_cache->reg_list[number];
1196         LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
1197         r->valid = true;
1198         buf_set_u64(r->value, 0, r->size, value);
1199 }
1200
1201 static int update_mstatus_actual(struct target *target)
1202 {
1203         struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1204         if (mstatus_reg->valid) {
1205                 /* We previously made it valid. */
1206                 return ERROR_OK;
1207         }
1208
1209         /* Force reading the register. In that process mstatus_actual will be
1210          * updated. */
1211         riscv_reg_t mstatus;
1212         return get_register(target, &mstatus, 0, GDB_REGNO_MSTATUS);
1213 }
1214
1215 /*** OpenOCD target functions. ***/
1216
1217 static int register_read(struct target *target, riscv_reg_t *value, int regnum)
1218 {
1219         riscv011_info_t *info = get_info(target);
1220         if (regnum >= GDB_REGNO_CSR0 && regnum <= GDB_REGNO_CSR4095) {
1221                 cache_set32(target, 0, csrr(S0, regnum - GDB_REGNO_CSR0));
1222                 cache_set_store(target, 1, S0, SLOT0);
1223                 cache_set_jump(target, 2);
1224         } else {
1225                 LOG_ERROR("Don't know how to read register %d", regnum);
1226                 return ERROR_FAIL;
1227         }
1228
1229         if (cache_write(target, 4, true) != ERROR_OK)
1230                 return ERROR_FAIL;
1231
1232         uint32_t exception = cache_get32(target, info->dramsize-1);
1233         if (exception) {
1234                 LOG_WARNING("Got exception 0x%x when reading %s", exception, gdb_regno_name(regnum));
1235                 *value = ~0;
1236                 return ERROR_FAIL;
1237         }
1238
1239         *value = cache_get(target, SLOT0);
1240         LOG_DEBUG("reg[%d]=0x%" PRIx64, regnum, *value);
1241
1242         if (regnum == GDB_REGNO_MSTATUS)
1243                 info->mstatus_actual = *value;
1244
1245         return ERROR_OK;
1246 }
1247
1248 /* Write the register. No caching or games. */
1249 static int register_write(struct target *target, unsigned int number,
1250                 uint64_t value)
1251 {
1252         riscv011_info_t *info = get_info(target);
1253
1254         maybe_write_tselect(target);
1255
1256         if (number == S0) {
1257                 cache_set_load(target, 0, S0, SLOT0);
1258                 cache_set32(target, 1, csrw(S0, CSR_DSCRATCH));
1259                 cache_set_jump(target, 2);
1260         } else if (number == S1) {
1261                 cache_set_load(target, 0, S0, SLOT0);
1262                 cache_set_store(target, 1, S0, SLOT_LAST);
1263                 cache_set_jump(target, 2);
1264         } else if (number <= GDB_REGNO_XPR31) {
1265                 cache_set_load(target, 0, number - GDB_REGNO_ZERO, SLOT0);
1266                 cache_set_jump(target, 1);
1267         } else if (number == GDB_REGNO_PC) {
1268                 info->dpc = value;
1269                 return ERROR_OK;
1270         } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
1271                 int result = update_mstatus_actual(target);
1272                 if (result != ERROR_OK)
1273                         return result;
1274                 unsigned i = 0;
1275                 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1276                         info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1277                         cache_set_load(target, i++, S0, SLOT1);
1278                         cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1279                         cache_set(target, SLOT1, info->mstatus_actual);
1280                 }
1281
1282                 if (riscv_xlen(target) == 32)
1283                         cache_set32(target, i++, flw(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1284                 else
1285                         cache_set32(target, i++, fld(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1286                 cache_set_jump(target, i++);
1287         } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
1288                 cache_set_load(target, 0, S0, SLOT0);
1289                 cache_set32(target, 1, csrw(S0, number - GDB_REGNO_CSR0));
1290                 cache_set_jump(target, 2);
1291
1292                 if (number == GDB_REGNO_MSTATUS)
1293                         info->mstatus_actual = value;
1294         } else if (number == GDB_REGNO_PRIV) {
1295                 info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
1296                 return ERROR_OK;
1297         } else {
1298                 LOG_ERROR("Don't know how to write register %d", number);
1299                 return ERROR_FAIL;
1300         }
1301
1302         cache_set(target, SLOT0, value);
1303         if (cache_write(target, info->dramsize - 1, true) != ERROR_OK)
1304                 return ERROR_FAIL;
1305
1306         uint32_t exception = cache_get32(target, info->dramsize-1);
1307         if (exception) {
1308                 LOG_WARNING("Got exception 0x%x when writing %s", exception,
1309                                 gdb_regno_name(number));
1310                 return ERROR_FAIL;
1311         }
1312
1313         return ERROR_OK;
1314 }
1315
1316 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
1317                 int regid)
1318 {
1319         assert(hartid == 0);
1320         riscv011_info_t *info = get_info(target);
1321
1322         maybe_write_tselect(target);
1323
1324         if (regid <= GDB_REGNO_XPR31) {
1325                 *value = reg_cache_get(target, regid);
1326         } else if (regid == GDB_REGNO_PC) {
1327                 *value = info->dpc;
1328         } else if (regid >= GDB_REGNO_FPR0 && regid <= GDB_REGNO_FPR31) {
1329                 int result = update_mstatus_actual(target);
1330                 if (result != ERROR_OK)
1331                         return result;
1332                 unsigned i = 0;
1333                 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1334                         info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1335                         cache_set_load(target, i++, S0, SLOT1);
1336                         cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1337                         cache_set(target, SLOT1, info->mstatus_actual);
1338                 }
1339
1340                 if (riscv_xlen(target) == 32)
1341                         cache_set32(target, i++, fsw(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1342                 else
1343                         cache_set32(target, i++, fsd(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1344                 cache_set_jump(target, i++);
1345
1346                 if (cache_write(target, 4, true) != ERROR_OK)
1347                         return ERROR_FAIL;
1348         } else if (regid == GDB_REGNO_PRIV) {
1349                 *value = get_field(info->dcsr, DCSR_PRV);
1350         } else {
1351                 int result = register_read(target, value, regid);
1352                 if (result != ERROR_OK)
1353                         return result;
1354         }
1355
1356         if (regid == GDB_REGNO_MSTATUS)
1357                 target->reg_cache->reg_list[regid].valid = true;
1358
1359         return ERROR_OK;
1360 }
1361
1362 static int set_register(struct target *target, int hartid, int regid,
1363                 uint64_t value)
1364 {
1365         assert(hartid == 0);
1366         return register_write(target, regid, value);
1367 }
1368
1369 static int halt(struct target *target)
1370 {
1371         LOG_DEBUG("riscv_halt()");
1372         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1373
1374         cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
1375         cache_set32(target, 1, csrr(S0, CSR_MHARTID));
1376         cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
1377         cache_set_jump(target, 3);
1378
1379         if (cache_write(target, 4, true) != ERROR_OK) {
1380                 LOG_ERROR("cache_write() failed.");
1381                 return ERROR_FAIL;
1382         }
1383
1384         return ERROR_OK;
1385 }
1386
1387 static int init_target(struct command_context *cmd_ctx,
1388                 struct target *target)
1389 {
1390         LOG_DEBUG("init");
1391         riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
1392         generic_info->get_register = get_register;
1393         generic_info->set_register = set_register;
1394
1395         generic_info->version_specific = calloc(1, sizeof(riscv011_info_t));
1396         if (!generic_info->version_specific)
1397                 return ERROR_FAIL;
1398
1399         /* Assume 32-bit until we discover the real value in examine(). */
1400         generic_info->xlen[0] = 32;
1401         riscv_init_registers(target);
1402
1403         return ERROR_OK;
1404 }
1405
1406 static void deinit_target(struct target *target)
1407 {
1408         LOG_DEBUG("riscv_deinit_target()");
1409         riscv_info_t *info = (riscv_info_t *) target->arch_info;
1410         free(info->version_specific);
1411         info->version_specific = NULL;
1412 }
1413
1414 static int strict_step(struct target *target, bool announce)
1415 {
1416         riscv011_info_t *info = get_info(target);
1417
1418         LOG_DEBUG("enter");
1419
1420         struct watchpoint *watchpoint = target->watchpoints;
1421         while (watchpoint) {
1422                 riscv_remove_watchpoint(target, watchpoint);
1423                 watchpoint = watchpoint->next;
1424         }
1425
1426         int result = full_step(target, announce);
1427         if (result != ERROR_OK)
1428                 return result;
1429
1430         watchpoint = target->watchpoints;
1431         while (watchpoint) {
1432                 riscv_add_watchpoint(target, watchpoint);
1433                 watchpoint = watchpoint->next;
1434         }
1435
1436         info->need_strict_step = false;
1437
1438         return ERROR_OK;
1439 }
1440
1441 static int step(struct target *target, int current, target_addr_t address,
1442                 int handle_breakpoints)
1443 {
1444         riscv011_info_t *info = get_info(target);
1445
1446         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1447
1448         if (!current) {
1449                 if (riscv_xlen(target) > 32) {
1450                         LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
1451                                         riscv_xlen(target));
1452                 }
1453                 int result = register_write(target, GDB_REGNO_PC, address);
1454                 if (result != ERROR_OK)
1455                         return result;
1456         }
1457
1458         if (info->need_strict_step || handle_breakpoints) {
1459                 int result = strict_step(target, true);
1460                 if (result != ERROR_OK)
1461                         return result;
1462         } else {
1463                 return full_step(target, false);
1464         }
1465
1466         return ERROR_OK;
1467 }
1468
1469 static int examine(struct target *target)
1470 {
1471         /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1472
1473         uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1474         LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1475         LOG_DEBUG("  addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
1476         LOG_DEBUG("  version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
1477         LOG_DEBUG("  idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
1478         if (dtmcontrol == 0) {
1479                 LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
1480                 return ERROR_FAIL;
1481         }
1482         if (get_field(dtmcontrol, DTMCONTROL_VERSION) != 0) {
1483                 LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
1484                                 get_field(dtmcontrol, DTMCONTROL_VERSION), dtmcontrol);
1485                 return ERROR_FAIL;
1486         }
1487
1488         RISCV_INFO(r);
1489         r->hart_count = 1;
1490
1491         riscv011_info_t *info = get_info(target);
1492         info->addrbits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS);
1493         info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE);
1494         if (info->dtmcontrol_idle == 0) {
1495                 /* Some old SiFive cores don't set idle but need it to be 1. */
1496                 uint32_t idcode = idcode_scan(target);
1497                 if (idcode == 0x10e31913)
1498                         info->dtmcontrol_idle = 1;
1499         }
1500
1501         uint32_t dminfo = dbus_read(target, DMINFO);
1502         LOG_DEBUG("dminfo: 0x%08x", dminfo);
1503         LOG_DEBUG("  abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
1504         LOG_DEBUG("  serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
1505         LOG_DEBUG("  access128=%d", get_field(dminfo, DMINFO_ACCESS128));
1506         LOG_DEBUG("  access64=%d", get_field(dminfo, DMINFO_ACCESS64));
1507         LOG_DEBUG("  access32=%d", get_field(dminfo, DMINFO_ACCESS32));
1508         LOG_DEBUG("  access16=%d", get_field(dminfo, DMINFO_ACCESS16));
1509         LOG_DEBUG("  access8=%d", get_field(dminfo, DMINFO_ACCESS8));
1510         LOG_DEBUG("  dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
1511         LOG_DEBUG("  authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
1512         LOG_DEBUG("  authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
1513         LOG_DEBUG("  authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
1514         LOG_DEBUG("  version=0x%x", get_field(dminfo, DMINFO_VERSION));
1515
1516         if (get_field(dminfo, DMINFO_VERSION) != 1) {
1517                 LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
1518                                 "(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
1519                 return ERROR_FAIL;
1520         }
1521
1522         info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
1523
1524         if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
1525                 LOG_ERROR("Authentication required by RISC-V core but not "
1526                                 "supported by OpenOCD. dminfo=0x%x", dminfo);
1527                 return ERROR_FAIL;
1528         }
1529
1530         /* Pretend this is a 32-bit system until we have found out the true value. */
1531         r->xlen[0] = 32;
1532
1533         /* Figure out XLEN, and test writing all of Debug RAM while we're at it. */
1534         cache_set32(target, 0, xori(S1, ZERO, -1));
1535         /* 0xffffffff  0xffffffff:ffffffff  0xffffffff:ffffffff:ffffffff:ffffffff */
1536         cache_set32(target, 1, srli(S1, S1, 31));
1537         /* 0x00000001  0x00000001:ffffffff  0x00000001:ffffffff:ffffffff:ffffffff */
1538         cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
1539         cache_set32(target, 3, srli(S1, S1, 31));
1540         /* 0x00000000  0x00000000:00000003  0x00000000:00000003:ffffffff:ffffffff */
1541         cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
1542         cache_set_jump(target, 5);
1543         for (unsigned i = 6; i < info->dramsize; i++)
1544                 cache_set32(target, i, i * 0x01020304);
1545
1546         cache_write(target, 0, false);
1547
1548         /* Check that we can actually read/write dram. */
1549         if (cache_check(target) != ERROR_OK)
1550                 return ERROR_FAIL;
1551
1552         cache_write(target, 0, true);
1553         cache_invalidate(target);
1554
1555         uint32_t word0 = cache_get32(target, 0);
1556         uint32_t word1 = cache_get32(target, 1);
1557         riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
1558         if (word0 == 1 && word1 == 0) {
1559                 generic_info->xlen[0] = 32;
1560         } else if (word0 == 0xffffffff && word1 == 3) {
1561                 generic_info->xlen[0] = 64;
1562         } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
1563                 generic_info->xlen[0] = 128;
1564         } else {
1565                 uint32_t exception = cache_get32(target, info->dramsize-1);
1566                 LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
1567                                 word0, word1, exception);
1568                 dump_debug_ram(target);
1569                 return ERROR_FAIL;
1570         }
1571         LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target));
1572
1573         if (read_csr(target, &r->misa[0], CSR_MISA) != ERROR_OK) {
1574                 const unsigned old_csr_misa = 0xf10;
1575                 LOG_WARNING("Failed to read misa at 0x%x; trying 0x%x.", CSR_MISA,
1576                                 old_csr_misa);
1577                 if (read_csr(target, &r->misa[0], old_csr_misa) != ERROR_OK) {
1578                         /* Maybe this is an old core that still has $misa at the old
1579                          * address. */
1580                         LOG_ERROR("Failed to read misa at 0x%x.", old_csr_misa);
1581                         return ERROR_FAIL;
1582                 }
1583         }
1584
1585         /* Update register list to match discovered XLEN/supported extensions. */
1586         riscv_init_registers(target);
1587
1588         info->never_halted = true;
1589
1590         int result = riscv011_poll(target);
1591         if (result != ERROR_OK)
1592                 return result;
1593
1594         target_set_examined(target);
1595         riscv_set_current_hartid(target, 0);
1596         for (size_t i = 0; i < 32; ++i)
1597                 reg_cache_set(target, i, -1);
1598         LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64,
1599                         riscv_xlen(target), r->misa[0]);
1600
1601         return ERROR_OK;
1602 }
1603
1604 static riscv_error_t handle_halt_routine(struct target *target)
1605 {
1606         riscv011_info_t *info = get_info(target);
1607
1608         scans_t *scans = scans_new(target, 256);
1609
1610         /* Read all GPRs as fast as we can, because gdb is going to ask for them
1611          * anyway. Reading them one at a time is much slower. */
1612
1613         /* Write the jump back to address 1. */
1614         scans_add_write_jump(scans, 1, false);
1615         for (int reg = 1; reg < 32; reg++) {
1616                 if (reg == S0 || reg == S1)
1617                         continue;
1618
1619                 /* Write store instruction. */
1620                 scans_add_write_store(scans, 0, reg, SLOT0, true);
1621
1622                 /* Read value. */
1623                 scans_add_read(scans, SLOT0, false);
1624         }
1625
1626         /* Write store of s0 at index 1. */
1627         scans_add_write_store(scans, 1, S0, SLOT0, false);
1628         /* Write jump at index 2. */
1629         scans_add_write_jump(scans, 2, false);
1630
1631         /* Read S1 from debug RAM */
1632         scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
1633         /* Read value. */
1634         scans_add_read(scans, SLOT0, false);
1635
1636         /* Read S0 from dscratch */
1637         unsigned int csr[] = {CSR_DSCRATCH, CSR_DPC, CSR_DCSR};
1638         for (unsigned int i = 0; i < DIM(csr); i++) {
1639                 scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
1640                 scans_add_read(scans, SLOT0, false);
1641         }
1642
1643         /* Final read to get the last value out. */
1644         scans_add_read32(scans, 4, false);
1645
1646         int retval = scans_execute(scans);
1647         if (retval != ERROR_OK) {
1648                 LOG_ERROR("JTAG execute failed: %d", retval);
1649                 goto error;
1650         }
1651
1652         unsigned int dbus_busy = 0;
1653         unsigned int interrupt_set = 0;
1654         unsigned result = 0;
1655         uint64_t value = 0;
1656         reg_cache_set(target, 0, 0);
1657         /* The first scan result is the result from something old we don't care
1658          * about. */
1659         for (unsigned int i = 1; i < scans->next_scan && dbus_busy == 0; i++) {
1660                 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
1661                                 DBUS_OP_SIZE);
1662                 uint64_t data = scans_get_u64(scans, i, DBUS_DATA_START, DBUS_DATA_SIZE);
1663                 uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
1664                                 info->addrbits);
1665                 switch (status) {
1666                         case DBUS_STATUS_SUCCESS:
1667                                 break;
1668                         case DBUS_STATUS_FAILED:
1669                                 LOG_ERROR("Debug access failed. Hardware error?");
1670                                 goto error;
1671                         case DBUS_STATUS_BUSY:
1672                                 dbus_busy++;
1673                                 break;
1674                         default:
1675                                 LOG_ERROR("Got invalid bus access status: %d", status);
1676                                 goto error;
1677                 }
1678                 if (data & DMCONTROL_INTERRUPT) {
1679                         interrupt_set++;
1680                         break;
1681                 }
1682                 if (address == 4 || address == 5) {
1683                         unsigned int reg;
1684                         switch (result) {
1685                                 case 0:
1686                                         reg = 1;
1687                                         break;
1688                                 case 1:
1689                                         reg = 2;
1690                                         break;
1691                                 case 2:
1692                                         reg = 3;
1693                                         break;
1694                                 case 3:
1695                                         reg = 4;
1696                                         break;
1697                                 case 4:
1698                                         reg = 5;
1699                                         break;
1700                                 case 5:
1701                                         reg = 6;
1702                                         break;
1703                                 case 6:
1704                                         reg = 7;
1705                                         break;
1706                                         /* S0 */
1707                                         /* S1 */
1708                                 case 7:
1709                                         reg = 10;
1710                                         break;
1711                                 case 8:
1712                                         reg = 11;
1713                                         break;
1714                                 case 9:
1715                                         reg = 12;
1716                                         break;
1717                                 case 10:
1718                                         reg = 13;
1719                                         break;
1720                                 case 11:
1721                                         reg = 14;
1722                                         break;
1723                                 case 12:
1724                                         reg = 15;
1725                                         break;
1726                                 case 13:
1727                                         reg = 16;
1728                                         break;
1729                                 case 14:
1730                                         reg = 17;
1731                                         break;
1732                                 case 15:
1733                                         reg = 18;
1734                                         break;
1735                                 case 16:
1736                                         reg = 19;
1737                                         break;
1738                                 case 17:
1739                                         reg = 20;
1740                                         break;
1741                                 case 18:
1742                                         reg = 21;
1743                                         break;
1744                                 case 19:
1745                                         reg = 22;
1746                                         break;
1747                                 case 20:
1748                                         reg = 23;
1749                                         break;
1750                                 case 21:
1751                                         reg = 24;
1752                                         break;
1753                                 case 22:
1754                                         reg = 25;
1755                                         break;
1756                                 case 23:
1757                                         reg = 26;
1758                                         break;
1759                                 case 24:
1760                                         reg = 27;
1761                                         break;
1762                                 case 25:
1763                                         reg = 28;
1764                                         break;
1765                                 case 26:
1766                                         reg = 29;
1767                                         break;
1768                                 case 27:
1769                                         reg = 30;
1770                                         break;
1771                                 case 28:
1772                                         reg = 31;
1773                                         break;
1774                                 case 29:
1775                                         reg = S1;
1776                                         break;
1777                                 case 30:
1778                                         reg = S0;
1779                                         break;
1780                                 case 31:
1781                                         reg = CSR_DPC;
1782                                         break;
1783                                 case 32:
1784                                         reg = CSR_DCSR;
1785                                         break;
1786                                 default:
1787                                         assert(0);
1788                                         LOG_ERROR("Got invalid register result %d", result);
1789                                         goto error;
1790                         }
1791                         if (riscv_xlen(target) == 32) {
1792                                 reg_cache_set(target, reg, data & 0xffffffff);
1793                                 result++;
1794                         } else if (riscv_xlen(target) == 64) {
1795                                 if (address == 4) {
1796                                         value = data & 0xffffffff;
1797                                 } else if (address == 5) {
1798                                         reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
1799                                         value = 0;
1800                                         result++;
1801                                 }
1802                         }
1803                 }
1804         }
1805
1806         scans_delete(scans);
1807
1808         if (dbus_busy) {
1809                 increase_dbus_busy_delay(target);
1810                 return RE_AGAIN;
1811         }
1812         if (interrupt_set) {
1813                 increase_interrupt_high_delay(target);
1814                 return RE_AGAIN;
1815         }
1816
1817         /* TODO: get rid of those 2 variables and talk to the cache directly. */
1818         info->dpc = reg_cache_get(target, CSR_DPC);
1819         info->dcsr = reg_cache_get(target, CSR_DCSR);
1820
1821         cache_invalidate(target);
1822
1823         return RE_OK;
1824
1825 error:
1826         scans_delete(scans);
1827         return RE_FAIL;
1828 }
1829
1830 static int handle_halt(struct target *target, bool announce)
1831 {
1832         riscv011_info_t *info = get_info(target);
1833         target->state = TARGET_HALTED;
1834
1835         riscv_error_t re;
1836         do {
1837                 re = handle_halt_routine(target);
1838         } while (re == RE_AGAIN);
1839         if (re != RE_OK) {
1840                 LOG_ERROR("handle_halt_routine failed");
1841                 return ERROR_FAIL;
1842         }
1843
1844         int cause = get_field(info->dcsr, DCSR_CAUSE);
1845         switch (cause) {
1846                 case DCSR_CAUSE_SWBP:
1847                         target->debug_reason = DBG_REASON_BREAKPOINT;
1848                         break;
1849                 case DCSR_CAUSE_HWBP:
1850                         target->debug_reason = DBG_REASON_WATCHPOINT;
1851                         /* If we halted because of a data trigger, gdb doesn't know to do
1852                          * the disable-breakpoints-step-enable-breakpoints dance. */
1853                         info->need_strict_step = true;
1854                         break;
1855                 case DCSR_CAUSE_DEBUGINT:
1856                         target->debug_reason = DBG_REASON_DBGRQ;
1857                         break;
1858                 case DCSR_CAUSE_STEP:
1859                         target->debug_reason = DBG_REASON_SINGLESTEP;
1860                         break;
1861                 case DCSR_CAUSE_HALT:
1862                 default:
1863                         LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
1864                                         cause, info->dcsr);
1865         }
1866
1867         if (info->never_halted) {
1868                 info->never_halted = false;
1869
1870                 int result = maybe_read_tselect(target);
1871                 if (result != ERROR_OK)
1872                         return result;
1873                 riscv_enumerate_triggers(target);
1874         }
1875
1876         if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1877                 int retval;
1878                 if (riscv_semihosting(target, &retval) != 0)
1879                         return retval;
1880         }
1881
1882         if (announce)
1883                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1884
1885         const char *cause_string[] = {
1886                 "none",
1887                 "software breakpoint",
1888                 "hardware trigger",
1889                 "debug interrupt",
1890                 "step",
1891                 "halt"
1892         };
1893         /* This is logged to the user so that gdb will show it when a user types
1894          * 'monitor reset init'. At that time gdb appears to have the pc cached
1895          * still so if a user manually inspects the pc it will still have the old
1896          * value. */
1897         LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
1898
1899         return ERROR_OK;
1900 }
1901
1902 static int poll_target(struct target *target, bool announce)
1903 {
1904         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1905
1906         /* Inhibit debug logging during poll(), which isn't usually interesting and
1907          * just fills up the screen/logs with clutter. */
1908         int old_debug_level = debug_level;
1909         if (debug_level >= LOG_LVL_DEBUG)
1910                 debug_level = LOG_LVL_INFO;
1911         bits_t bits = read_bits(target);
1912         debug_level = old_debug_level;
1913
1914         if (bits.haltnot && bits.interrupt) {
1915                 target->state = TARGET_DEBUG_RUNNING;
1916                 LOG_DEBUG("debug running");
1917         } else if (bits.haltnot && !bits.interrupt) {
1918                 if (target->state != TARGET_HALTED)
1919                         return handle_halt(target, announce);
1920         } else if (!bits.haltnot && bits.interrupt) {
1921                 /* Target is halting. There is no state for that, so don't change anything. */
1922                 LOG_DEBUG("halting");
1923         } else if (!bits.haltnot && !bits.interrupt) {
1924                 target->state = TARGET_RUNNING;
1925         }
1926
1927         return ERROR_OK;
1928 }
1929
1930 static int riscv011_poll(struct target *target)
1931 {
1932         return poll_target(target, true);
1933 }
1934
1935 static int riscv011_resume(struct target *target, int current,
1936                 target_addr_t address, int handle_breakpoints, int debug_execution)
1937 {
1938         riscv011_info_t *info = get_info(target);
1939
1940         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1941
1942         if (!current) {
1943                 if (riscv_xlen(target) > 32) {
1944                         LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
1945                                         riscv_xlen(target));
1946                 }
1947                 int result = register_write(target, GDB_REGNO_PC, address);
1948                 if (result != ERROR_OK)
1949                         return result;
1950         }
1951
1952         if (info->need_strict_step || handle_breakpoints) {
1953                 int result = strict_step(target, false);
1954                 if (result != ERROR_OK)
1955                         return result;
1956         }
1957
1958         return resume(target, debug_execution, false);
1959 }
1960
1961 static int assert_reset(struct target *target)
1962 {
1963         riscv011_info_t *info = get_info(target);
1964         /* TODO: Maybe what I implemented here is more like soft_reset_halt()? */
1965
1966         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1967
1968         /* The only assumption we can make is that the TAP was reset. */
1969         if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1970                 LOG_ERROR("Debug interrupt didn't clear.");
1971                 return ERROR_FAIL;
1972         }
1973
1974         /* Not sure what we should do when there are multiple cores.
1975          * Here just reset the single hart we're talking to. */
1976         info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS |
1977                 DCSR_EBREAKU | DCSR_HALT;
1978         if (target->reset_halt)
1979                 info->dcsr |= DCSR_NDRESET;
1980         else
1981                 info->dcsr |= DCSR_FULLRESET;
1982         dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1983         dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1984         /* We shouldn't actually need the jump because a reset should happen. */
1985         dram_write_jump(target, 2, false);
1986         dram_write32(target, 4, info->dcsr, true);
1987         cache_invalidate(target);
1988
1989         target->state = TARGET_RESET;
1990
1991         return ERROR_OK;
1992 }
1993
1994 static int deassert_reset(struct target *target)
1995 {
1996         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1997         if (target->reset_halt)
1998                 return wait_for_state(target, TARGET_HALTED);
1999         else
2000                 return wait_for_state(target, TARGET_RUNNING);
2001 }
2002
2003 static int read_memory(struct target *target, target_addr_t address,
2004                 uint32_t size, uint32_t count, uint8_t *buffer)
2005 {
2006         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2007
2008         cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
2009         switch (size) {
2010                 case 1:
2011                         cache_set32(target, 1, lb(S1, S0, 0));
2012                         cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2013                         break;
2014                 case 2:
2015                         cache_set32(target, 1, lh(S1, S0, 0));
2016                         cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2017                         break;
2018                 case 4:
2019                         cache_set32(target, 1, lw(S1, S0, 0));
2020                         cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2021                         break;
2022                 default:
2023                         LOG_ERROR("Unsupported size: %d", size);
2024                         return ERROR_FAIL;
2025         }
2026         cache_set_jump(target, 3);
2027         cache_write(target, CACHE_NO_READ, false);
2028
2029         riscv011_info_t *info = get_info(target);
2030         const unsigned max_batch_size = 256;
2031         scans_t *scans = scans_new(target, max_batch_size);
2032
2033         uint32_t result_value = 0x777;
2034         uint32_t i = 0;
2035         while (i < count + 3) {
2036                 unsigned int batch_size = MIN(count + 3 - i, max_batch_size);
2037                 scans_reset(scans);
2038
2039                 for (unsigned int j = 0; j < batch_size; j++) {
2040                         if (i + j == count) {
2041                                 /* Just insert a read so we can scan out the last value. */
2042                                 scans_add_read32(scans, 4, false);
2043                         } else if (i + j >= count + 1) {
2044                                 /* And check for errors. */
2045                                 scans_add_read32(scans, info->dramsize-1, false);
2046                         } else {
2047                                 /* Write the next address and set interrupt. */
2048                                 uint32_t offset = size * (i + j);
2049                                 scans_add_write32(scans, 4, address + offset, true);
2050                         }
2051                 }
2052
2053                 int retval = scans_execute(scans);
2054                 if (retval != ERROR_OK) {
2055                         LOG_ERROR("JTAG execute failed: %d", retval);
2056                         goto error;
2057                 }
2058
2059                 int dbus_busy = 0;
2060                 int execute_busy = 0;
2061                 for (unsigned int j = 0; j < batch_size; j++) {
2062                         dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2063                                         DBUS_OP_SIZE);
2064                         switch (status) {
2065                                 case DBUS_STATUS_SUCCESS:
2066                                         break;
2067                                 case DBUS_STATUS_FAILED:
2068                                         LOG_ERROR("Debug RAM write failed. Hardware error?");
2069                                         goto error;
2070                                 case DBUS_STATUS_BUSY:
2071                                         dbus_busy++;
2072                                         break;
2073                                 default:
2074                                         LOG_ERROR("Got invalid bus access status: %d", status);
2075                                         return ERROR_FAIL;
2076                         }
2077                         uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
2078                                         DBUS_DATA_SIZE);
2079                         if (data & DMCONTROL_INTERRUPT)
2080                                 execute_busy++;
2081                         if (i + j == count + 2) {
2082                                 result_value = data;
2083                         } else if (i + j > 1) {
2084                                 uint32_t offset = size * (i + j - 2);
2085                                 switch (size) {
2086                                         case 1:
2087                                                 buffer[offset] = data;
2088                                                 break;
2089                                         case 2:
2090                                                 buffer[offset] = data;
2091                                                 buffer[offset+1] = data >> 8;
2092                                                 break;
2093                                         case 4:
2094                                                 buffer[offset] = data;
2095                                                 buffer[offset+1] = data >> 8;
2096                                                 buffer[offset+2] = data >> 16;
2097                                                 buffer[offset+3] = data >> 24;
2098                                                 break;
2099                                 }
2100                         }
2101                         LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
2102                 }
2103                 if (dbus_busy)
2104                         increase_dbus_busy_delay(target);
2105                 if (execute_busy)
2106                         increase_interrupt_high_delay(target);
2107                 if (dbus_busy || execute_busy) {
2108                         wait_for_debugint_clear(target, false);
2109
2110                         /* Retry. */
2111                         LOG_INFO("Retrying memory read starting from 0x%" TARGET_PRIxADDR
2112                                         " with more delays", address + size * i);
2113                 } else {
2114                         i += batch_size;
2115                 }
2116         }
2117
2118         if (result_value != 0) {
2119                 LOG_USER("Core got an exception (0x%x) while reading from 0x%"
2120                                 TARGET_PRIxADDR, result_value, address + size * (count-1));
2121                 if (count > 1) {
2122                         LOG_USER("(It may have failed between 0x%" TARGET_PRIxADDR
2123                                         " and 0x%" TARGET_PRIxADDR " as well, but we "
2124                                         "didn't check then.)",
2125                                         address, address + size * (count-2) + size - 1);
2126                 }
2127                 goto error;
2128         }
2129
2130         scans_delete(scans);
2131         cache_clean(target);
2132         return ERROR_OK;
2133
2134 error:
2135         scans_delete(scans);
2136         cache_clean(target);
2137         return ERROR_FAIL;
2138 }
2139
2140 static int setup_write_memory(struct target *target, uint32_t size)
2141 {
2142         switch (size) {
2143                 case 1:
2144                         cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
2145                         cache_set32(target, 1, sb(S0, T0, 0));
2146                         break;
2147                 case 2:
2148                         cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
2149                         cache_set32(target, 1, sh(S0, T0, 0));
2150                         break;
2151                 case 4:
2152                         cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
2153                         cache_set32(target, 1, sw(S0, T0, 0));
2154                         break;
2155                 default:
2156                         LOG_ERROR("Unsupported size: %d", size);
2157                         return ERROR_FAIL;
2158         }
2159         cache_set32(target, 2, addi(T0, T0, size));
2160         cache_set_jump(target, 3);
2161         cache_write(target, 4, false);
2162
2163         return ERROR_OK;
2164 }
2165
2166 static int write_memory(struct target *target, target_addr_t address,
2167                 uint32_t size, uint32_t count, const uint8_t *buffer)
2168 {
2169         riscv011_info_t *info = get_info(target);
2170         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2171
2172         /* Set up the address. */
2173         cache_set_store(target, 0, T0, SLOT1);
2174         cache_set_load(target, 1, T0, SLOT0);
2175         cache_set_jump(target, 2);
2176         cache_set(target, SLOT0, address);
2177         if (cache_write(target, 5, true) != ERROR_OK)
2178                 return ERROR_FAIL;
2179
2180         uint64_t t0 = cache_get(target, SLOT1);
2181         LOG_DEBUG("t0 is 0x%" PRIx64, t0);
2182
2183         if (setup_write_memory(target, size) != ERROR_OK)
2184                 return ERROR_FAIL;
2185
2186         const unsigned max_batch_size = 256;
2187         scans_t *scans = scans_new(target, max_batch_size);
2188
2189         uint32_t result_value = 0x777;
2190         uint32_t i = 0;
2191         while (i < count + 2) {
2192                 unsigned int batch_size = MIN(count + 2 - i, max_batch_size);
2193                 scans_reset(scans);
2194
2195                 for (unsigned int j = 0; j < batch_size; j++) {
2196                         if (i + j >= count) {
2197                                 /* Check for an exception. */
2198                                 scans_add_read32(scans, info->dramsize-1, false);
2199                         } else {
2200                                 /* Write the next value and set interrupt. */
2201                                 uint32_t value;
2202                                 uint32_t offset = size * (i + j);
2203                                 switch (size) {
2204                                         case 1:
2205                                                 value = buffer[offset];
2206                                                 break;
2207                                         case 2:
2208                                                 value = buffer[offset] |
2209                                                         (buffer[offset+1] << 8);
2210                                                 break;
2211                                         case 4:
2212                                                 value = buffer[offset] |
2213                                                         ((uint32_t) buffer[offset+1] << 8) |
2214                                                         ((uint32_t) buffer[offset+2] << 16) |
2215                                                         ((uint32_t) buffer[offset+3] << 24);
2216                                                 break;
2217                                         default:
2218                                                 goto error;
2219                                 }
2220
2221                                 scans_add_write32(scans, 4, value, true);
2222                         }
2223                 }
2224
2225                 int retval = scans_execute(scans);
2226                 if (retval != ERROR_OK) {
2227                         LOG_ERROR("JTAG execute failed: %d", retval);
2228                         goto error;
2229                 }
2230
2231                 int dbus_busy = 0;
2232                 int execute_busy = 0;
2233                 for (unsigned int j = 0; j < batch_size; j++) {
2234                         dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2235                                         DBUS_OP_SIZE);
2236                         switch (status) {
2237                                 case DBUS_STATUS_SUCCESS:
2238                                         break;
2239                                 case DBUS_STATUS_FAILED:
2240                                         LOG_ERROR("Debug RAM write failed. Hardware error?");
2241                                         goto error;
2242                                 case DBUS_STATUS_BUSY:
2243                                         dbus_busy++;
2244                                         break;
2245                                 default:
2246                                         LOG_ERROR("Got invalid bus access status: %d", status);
2247                                         return ERROR_FAIL;
2248                         }
2249                         int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
2250                         if (interrupt)
2251                                 execute_busy++;
2252                         if (i + j == count + 1)
2253                                 result_value = scans_get_u32(scans, j, DBUS_DATA_START, 32);
2254                 }
2255                 if (dbus_busy)
2256                         increase_dbus_busy_delay(target);
2257                 if (execute_busy)
2258                         increase_interrupt_high_delay(target);
2259                 if (dbus_busy || execute_busy) {
2260                         wait_for_debugint_clear(target, false);
2261
2262                         /* Retry.
2263                          * Set t0 back to what it should have been at the beginning of this
2264                          * batch. */
2265                         LOG_INFO("Retrying memory write starting from 0x%" TARGET_PRIxADDR
2266                                         " with more delays", address + size * i);
2267
2268                         cache_clean(target);
2269
2270                         if (write_gpr(target, T0, address + size * i) != ERROR_OK)
2271                                 goto error;
2272
2273                         if (setup_write_memory(target, size) != ERROR_OK)
2274                                 goto error;
2275                 } else {
2276                         i += batch_size;
2277                 }
2278         }
2279
2280         if (result_value != 0) {
2281                 LOG_ERROR("Core got an exception (0x%x) while writing to 0x%"
2282                                 TARGET_PRIxADDR, result_value, address + size * (count-1));
2283                 if (count > 1) {
2284                         LOG_ERROR("(It may have failed between 0x%" TARGET_PRIxADDR
2285                                         " and 0x%" TARGET_PRIxADDR " as well, but we "
2286                                         "didn't check then.)",
2287                                         address, address + size * (count-2) + size - 1);
2288                 }
2289                 goto error;
2290         }
2291
2292         scans_delete(scans);
2293         cache_clean(target);
2294         return register_write(target, T0, t0);
2295
2296 error:
2297         scans_delete(scans);
2298         cache_clean(target);
2299         return ERROR_FAIL;
2300 }
2301
2302 static int arch_state(struct target *target)
2303 {
2304         return ERROR_OK;
2305 }
2306
2307 struct target_type riscv011_target = {
2308         .name = "riscv",
2309
2310         .init_target = init_target,
2311         .deinit_target = deinit_target,
2312         .examine = examine,
2313
2314         /* poll current target status */
2315         .poll = riscv011_poll,
2316
2317         .halt = halt,
2318         .resume = riscv011_resume,
2319         .step = step,
2320
2321         .assert_reset = assert_reset,
2322         .deassert_reset = deassert_reset,
2323
2324         .read_memory = read_memory,
2325         .write_memory = write_memory,
2326
2327         .arch_state = arch_state,
2328 };