1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Support for RISC-V, debug version 0.11. This was never an officially adopted
5 * spec, but SiFive made some silicon that uses it.
16 #include "target/target.h"
17 #include "target/algorithm.h"
18 #include "target/target_type.h"
20 #include "jtag/jtag.h"
21 #include "target/register.h"
22 #include "target/breakpoints.h"
23 #include "helper/time_support.h"
29 * Since almost everything can be accomplish by scanning the dbus register, all
30 * functions here assume dbus is already selected. The exception are functions
31 * called directly by OpenOCD, which can't assume anything about what's
32 * currently in IR. They should set IR to dbus explicitly.
38 * At the bottom of the stack are the OpenOCD JTAG functions:
43 * There are a few functions to just instantly shift a register and get its
49 * Because doing one scan and waiting for the result is slow, most functions
50 * batch up a bunch of dbus writes and then execute them all at once. They use
51 * the scans "class" for this:
56 * Usually you new(), call a bunch of add functions, then execute() and look
57 * at the results by calling scans_get...()
59 * Optimized functions will directly use the scans class above, but slightly
60 * lazier code will use the cache functions that in turn use the scans
65 * cache_set... update a local structure, which is then synced to the target
66 * with cache_write(). Only Debug RAM words that are actually changed are sent
67 * to the target. Afterwards use cache_get... to read results.
70 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
71 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
73 #define DIM(x) (sizeof(x)/sizeof(*x))
75 /* Constants for legacy SiFive hardware breakpoints. */
76 #define CSR_BPCONTROL_X (1<<0)
77 #define CSR_BPCONTROL_W (1<<1)
78 #define CSR_BPCONTROL_R (1<<2)
79 #define CSR_BPCONTROL_U (1<<3)
80 #define CSR_BPCONTROL_S (1<<4)
81 #define CSR_BPCONTROL_H (1<<5)
82 #define CSR_BPCONTROL_M (1<<6)
83 #define CSR_BPCONTROL_BPMATCH (0xf<<7)
84 #define CSR_BPCONTROL_BPACTION (0xff<<11)
86 #define DEBUG_ROM_START 0x800
87 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
88 #define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
89 #define DEBUG_RAM_START 0x400
91 #define SETHALTNOT 0x10c
93 /*** JTAG registers. ***/
95 #define DTMCONTROL 0x10
96 #define DTMCONTROL_DBUS_RESET (1<<16)
97 #define DTMCONTROL_IDLE (7<<10)
98 #define DTMCONTROL_ADDRBITS (0xf<<4)
99 #define DTMCONTROL_VERSION (0xf)
102 #define DBUS_OP_START 0
103 #define DBUS_OP_SIZE 2
110 DBUS_STATUS_SUCCESS = 0,
111 DBUS_STATUS_FAILED = 2,
114 #define DBUS_DATA_START 2
115 #define DBUS_DATA_SIZE 34
116 #define DBUS_ADDRESS_START 36
130 /*** Debug Bus registers. ***/
132 #define DMCONTROL 0x10
133 #define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
134 #define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
135 #define DMCONTROL_BUSERROR (7<<19)
136 #define DMCONTROL_SERIAL (3<<16)
137 #define DMCONTROL_AUTOINCREMENT (1<<15)
138 #define DMCONTROL_ACCESS (7<<12)
139 #define DMCONTROL_HARTID (0x3ff<<2)
140 #define DMCONTROL_NDRESET (1<<1)
141 #define DMCONTROL_FULLRESET 1
144 #define DMINFO_ABUSSIZE (0x7fU<<25)
145 #define DMINFO_SERIALCOUNT (0xf<<21)
146 #define DMINFO_ACCESS128 (1<<20)
147 #define DMINFO_ACCESS64 (1<<19)
148 #define DMINFO_ACCESS32 (1<<18)
149 #define DMINFO_ACCESS16 (1<<17)
150 #define DMINFO_ACCESS8 (1<<16)
151 #define DMINFO_DRAMSIZE (0x3f<<10)
152 #define DMINFO_AUTHENTICATED (1<<5)
153 #define DMINFO_AUTHBUSY (1<<4)
154 #define DMINFO_AUTHTYPE (3<<2)
155 #define DMINFO_VERSION 3
157 /*** Info about the core being debugged. ***/
159 #define DBUS_ADDRESS_UNKNOWN 0xffff
161 #define DRAM_CACHE_SIZE 16
168 bool read, write, execute;
172 struct memory_cache_line {
179 /* Number of address bits in the dbus register. */
181 /* Number of words in Debug RAM. */
182 unsigned int dramsize;
187 /* The value that mstatus actually has on the target right now. This is not
188 * the value we present to the user. That one may be stored in the
190 uint64_t mstatus_actual;
192 struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
194 /* Number of run-test/idle cycles the target requests we do after each dbus
196 unsigned int dtmcontrol_idle;
198 /* This value is incremented every time a dbus access comes back as "busy".
199 * It's used to determine how many run-test/idle cycles to feed the target
200 * in between accesses. */
201 unsigned int dbus_busy_delay;
203 /* This value is incremented every time we read the debug interrupt as
204 * high. It's used to add extra run-test/idle cycles after setting debug
205 * interrupt high, so ideally we never have to perform a whole extra scan
206 * before the interrupt is cleared. */
207 unsigned int interrupt_high_delay;
217 /*** Necessary prototypes. ***/
219 static int poll_target(struct target *target, bool announce);
220 static int riscv011_poll(struct target *target);
221 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
224 /*** Utility functions. ***/
226 #define DEBUG_LENGTH 264
228 static riscv011_info_t *get_info(const struct target *target)
230 riscv_info_t *info = (riscv_info_t *) target->arch_info;
231 return (riscv011_info_t *) info->version_specific;
234 static unsigned int slot_offset(const struct target *target, slot_t slot)
236 riscv011_info_t *info = get_info(target);
237 switch (riscv_xlen(target)) {
240 case SLOT0: return 4;
241 case SLOT1: return 5;
242 case SLOT_LAST: return info->dramsize-1;
247 case SLOT0: return 4;
248 case SLOT1: return 6;
249 case SLOT_LAST: return info->dramsize-2;
252 LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
253 riscv_xlen(target), slot);
255 return 0; /* Silence -Werror=return-type */
258 static uint32_t load_slot(const struct target *target, unsigned int dest,
261 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
262 return load(target, dest, ZERO, offset);
265 static uint32_t store_slot(const struct target *target, unsigned int src,
268 unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
269 return store(target, src, ZERO, offset);
272 static uint16_t dram_address(unsigned int index)
277 return 0x40 + index - 0x10;
280 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
282 struct scan_field field;
284 uint8_t out_value[4] = { 0 };
286 buf_set_u32(out_value, 0, 32, out);
288 jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
291 field.out_value = out_value;
292 field.in_value = in_value;
293 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
295 /* Always return to dbus. */
296 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
298 int retval = jtag_execute_queue();
299 if (retval != ERROR_OK) {
300 LOG_ERROR("failed jtag scan: %d", retval);
304 uint32_t in = buf_get_u32(field.in_value, 0, 32);
305 LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
310 static uint32_t idcode_scan(struct target *target)
312 struct scan_field field;
315 jtag_add_ir_scan(target->tap, &select_idcode, TAP_IDLE);
318 field.out_value = NULL;
319 field.in_value = in_value;
320 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
322 int retval = jtag_execute_queue();
323 if (retval != ERROR_OK) {
324 LOG_ERROR("failed jtag scan: %d", retval);
328 /* Always return to dbus. */
329 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
331 uint32_t in = buf_get_u32(field.in_value, 0, 32);
332 LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
337 static void increase_dbus_busy_delay(struct target *target)
339 riscv011_info_t *info = get_info(target);
340 info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
341 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
342 info->dtmcontrol_idle, info->dbus_busy_delay,
343 info->interrupt_high_delay);
345 dtmcontrol_scan(target, DTMCONTROL_DBUS_RESET);
348 static void increase_interrupt_high_delay(struct target *target)
350 riscv011_info_t *info = get_info(target);
351 info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
352 LOG_DEBUG("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
353 info->dtmcontrol_idle, info->dbus_busy_delay,
354 info->interrupt_high_delay);
357 static void add_dbus_scan(const struct target *target, struct scan_field *field,
358 uint8_t *out_value, uint8_t *in_value, dbus_op_t op,
359 uint16_t address, uint64_t data)
361 riscv011_info_t *info = get_info(target);
364 if (r->reset_delays_wait >= 0) {
365 r->reset_delays_wait--;
366 if (r->reset_delays_wait < 0) {
367 info->dbus_busy_delay = 0;
368 info->interrupt_high_delay = 0;
372 field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
373 field->in_value = in_value;
374 field->out_value = out_value;
376 buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
377 buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
378 buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
380 jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
382 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
383 if (data & DMCONTROL_INTERRUPT)
384 idle_count += info->interrupt_high_delay;
387 jtag_add_runtest(idle_count, TAP_IDLE);
390 static void dump_field(const struct scan_field *field)
392 static const char * const op_string[] = {"nop", "r", "w", "?"};
393 static const char * const status_string[] = {"+", "?", "F", "b"};
395 if (debug_level < LOG_LVL_DEBUG)
398 uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
399 unsigned int out_op = (out >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
400 char out_interrupt = ((out >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
401 char out_haltnot = ((out >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
402 unsigned int out_data = out >> 2;
403 unsigned int out_address = out >> DBUS_ADDRESS_START;
404 uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
405 unsigned int in_op = (in >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
406 char in_interrupt = ((in >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
407 char in_haltnot = ((in >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
408 unsigned int in_data = in >> 2;
409 unsigned int in_address = in >> DBUS_ADDRESS_START;
411 log_printf_lf(LOG_LVL_DEBUG,
412 __FILE__, __LINE__, "scan",
413 "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x",
415 op_string[out_op], out_interrupt, out_haltnot, out_data,
417 status_string[in_op], in_interrupt, in_haltnot, in_data,
421 static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
422 uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
424 riscv011_info_t *info = get_info(target);
426 uint8_t out[8] = {0};
427 struct scan_field field = {
428 .num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
433 assert(info->addrbits != 0);
435 buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
436 buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
437 buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address_out);
439 /* Assume dbus is already selected. */
440 jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
442 int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
445 jtag_add_runtest(idle_count, TAP_IDLE);
447 int retval = jtag_execute_queue();
448 if (retval != ERROR_OK) {
449 LOG_ERROR("dbus_scan failed jtag scan");
450 return DBUS_STATUS_FAILED;
454 *data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
457 *address_in = buf_get_u32(in, DBUS_ADDRESS_START, info->addrbits);
461 return buf_get_u32(in, DBUS_OP_START, DBUS_OP_SIZE);
464 static uint64_t dbus_read(struct target *target, uint16_t address)
467 dbus_status_t status;
470 /* If the previous read/write was to the same address, we will get the read data
471 * from the previous access.
472 * While somewhat nonintuitive, this is an efficient way to get the data.
477 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
478 if (status == DBUS_STATUS_BUSY)
479 increase_dbus_busy_delay(target);
480 if (status == DBUS_STATUS_FAILED) {
481 LOG_ERROR("dbus_read(0x%x) failed!", address);
484 } while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
487 if (status != DBUS_STATUS_SUCCESS)
488 LOG_ERROR("failed read from 0x%x; value=0x%" PRIx64 ", status=%d\n", address, value, status);
493 static void dbus_write(struct target *target, uint16_t address, uint64_t value)
495 dbus_status_t status = DBUS_STATUS_BUSY;
497 while (status == DBUS_STATUS_BUSY && i++ < 256) {
498 status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
499 if (status == DBUS_STATUS_BUSY)
500 increase_dbus_busy_delay(target);
502 if (status != DBUS_STATUS_SUCCESS)
503 LOG_ERROR("failed to write 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
506 /*** scans "class" ***/
509 /* Number of scans that space is reserved for. */
510 unsigned int scan_count;
511 /* Size reserved in memory for each scan, in bytes. */
512 unsigned int scan_size;
513 unsigned int next_scan;
516 struct scan_field *field;
517 const struct target *target;
520 static scans_t *scans_new(struct target *target, unsigned int scan_count)
522 scans_t *scans = malloc(sizeof(scans_t));
525 scans->scan_count = scan_count;
526 /* This code also gets called before xlen is detected. */
527 if (riscv_xlen(target))
528 scans->scan_size = 2 + riscv_xlen(target) / 8;
530 scans->scan_size = 2 + 128 / 8;
531 scans->next_scan = 0;
532 scans->in = calloc(scans->scan_size, scans->scan_count);
535 scans->out = calloc(scans->scan_size, scans->scan_count);
538 scans->field = calloc(scans->scan_count, sizeof(struct scan_field));
541 scans->target = target;
554 static scans_t *scans_delete(scans_t *scans)
564 static void scans_reset(scans_t *scans)
566 scans->next_scan = 0;
569 static void scans_dump(scans_t *scans)
571 for (unsigned int i = 0; i < scans->next_scan; i++)
572 dump_field(&scans->field[i]);
575 static int scans_execute(scans_t *scans)
577 int retval = jtag_execute_queue();
578 if (retval != ERROR_OK) {
579 LOG_ERROR("failed jtag scan: %d", retval);
588 /** Add a 32-bit dbus write to the scans structure. */
589 static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
592 const unsigned int i = scans->next_scan;
593 int data_offset = scans->scan_size * i;
594 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
595 scans->in + data_offset, DBUS_OP_WRITE, address,
596 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT | data);
598 assert(scans->next_scan <= scans->scan_count);
601 /** Add a 32-bit dbus write for an instruction that jumps to the beginning of
603 static void scans_add_write_jump(scans_t *scans, uint16_t address,
606 scans_add_write32(scans, address,
607 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
611 /** Add a 32-bit dbus write for an instruction that loads from the indicated
613 static void scans_add_write_load(scans_t *scans, uint16_t address,
614 unsigned int reg, slot_t slot, bool set_interrupt)
616 scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
620 /** Add a 32-bit dbus write for an instruction that stores to the indicated
622 static void scans_add_write_store(scans_t *scans, uint16_t address,
623 unsigned int reg, slot_t slot, bool set_interrupt)
625 scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
629 /** Add a 32-bit dbus read. */
630 static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
632 assert(scans->next_scan < scans->scan_count);
633 const unsigned int i = scans->next_scan;
634 int data_offset = scans->scan_size * i;
635 add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
636 scans->in + data_offset, DBUS_OP_READ, address,
637 (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT);
641 /** Add one or more scans to read the indicated slot. */
642 static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
644 const struct target *target = scans->target;
645 switch (riscv_xlen(target)) {
647 scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
650 scans_add_read32(scans, slot_offset(target, slot), false);
651 scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
656 static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
657 unsigned first, unsigned num)
659 return buf_get_u32(scans->in + scans->scan_size * index, first, num);
662 static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
663 unsigned first, unsigned num)
665 return buf_get_u64(scans->in + scans->scan_size * index, first, num);
668 /*** end of scans class ***/
670 static uint32_t dram_read32(struct target *target, unsigned int index)
672 uint16_t address = dram_address(index);
673 uint32_t value = dbus_read(target, address);
677 static void dram_write32(struct target *target, unsigned int index, uint32_t value,
680 uint64_t dbus_value = DMCONTROL_HALTNOT | value;
682 dbus_value |= DMCONTROL_INTERRUPT;
683 dbus_write(target, dram_address(index), dbus_value);
686 /** Read the haltnot and interrupt bits. */
687 static bits_t read_bits(struct target *target)
690 dbus_status_t status;
692 riscv011_info_t *info = get_info(target);
694 bits_t err_result = {
702 status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
703 if (status == DBUS_STATUS_BUSY) {
704 if (address_in == (1<<info->addrbits) - 1 &&
705 value == (1ULL<<DBUS_DATA_SIZE) - 1) {
706 LOG_ERROR("TDO seems to be stuck high.");
709 increase_dbus_busy_delay(target);
710 } else if (status == DBUS_STATUS_FAILED) {
711 /* TODO: return an actual error */
714 } while (status == DBUS_STATUS_BUSY && i++ < 256);
717 LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status);
720 } while (address_in > 0x10 && address_in != DMCONTROL);
723 .haltnot = get_field(value, DMCONTROL_HALTNOT),
724 .interrupt = get_field(value, DMCONTROL_INTERRUPT)
729 static int wait_for_debugint_clear(struct target *target, bool ignore_first)
731 time_t start = time(NULL);
733 /* Throw away the results of the first read, since they'll contain the
734 * result of the read that happened just before debugint was set.
735 * (Assuming the last scan before calling this function was one that
740 bits_t bits = read_bits(target);
743 if (time(NULL) - start > riscv_command_timeout_sec) {
744 LOG_ERROR("Timed out waiting for debug int to clear."
745 "Increase timeout with riscv set_command_timeout_sec.");
751 static int dram_check32(struct target *target, unsigned int index,
754 uint16_t address = dram_address(index);
755 uint32_t actual = dbus_read(target, address);
756 if (expected != actual) {
757 LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
758 expected, index, actual);
764 static void cache_set32(struct target *target, unsigned int index, uint32_t data)
766 riscv011_info_t *info = get_info(target);
767 if (info->dram_cache[index].valid &&
768 info->dram_cache[index].data == data) {
769 /* This is already preset on the target. */
770 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
773 LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
774 info->dram_cache[index].data = data;
775 info->dram_cache[index].valid = true;
776 info->dram_cache[index].dirty = true;
779 static void cache_set(struct target *target, slot_t slot, uint64_t data)
781 unsigned int offset = slot_offset(target, slot);
782 cache_set32(target, offset, data);
783 if (riscv_xlen(target) > 32)
784 cache_set32(target, offset + 1, data >> 32);
787 static void cache_set_jump(struct target *target, unsigned int index)
789 cache_set32(target, index,
790 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
793 static void cache_set_load(struct target *target, unsigned int index,
794 unsigned int reg, slot_t slot)
796 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
797 cache_set32(target, index, load(target, reg, ZERO, offset));
800 static void cache_set_store(struct target *target, unsigned int index,
801 unsigned int reg, slot_t slot)
803 uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
804 cache_set32(target, index, store(target, reg, ZERO, offset));
807 static void dump_debug_ram(struct target *target)
809 for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
810 uint32_t value = dram_read32(target, i);
811 LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
815 /* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
816 static void cache_invalidate(struct target *target)
818 riscv011_info_t *info = get_info(target);
819 for (unsigned int i = 0; i < info->dramsize; i++) {
820 info->dram_cache[i].valid = false;
821 info->dram_cache[i].dirty = false;
825 /* Called by cache_write() after the program has run. Also call this if you're
826 * running programs without calling cache_write(). */
827 static void cache_clean(struct target *target)
829 riscv011_info_t *info = get_info(target);
830 for (unsigned int i = 0; i < info->dramsize; i++) {
832 info->dram_cache[i].valid = false;
833 info->dram_cache[i].dirty = false;
837 static int cache_check(struct target *target)
839 riscv011_info_t *info = get_info(target);
842 for (unsigned int i = 0; i < info->dramsize; i++) {
843 if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
844 if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK)
850 dump_debug_ram(target);
857 /** Write cache to the target, and optionally run the program.
858 * Then read the value at address into the cache, assuming address < 128. */
859 #define CACHE_NO_READ 128
860 static int cache_write(struct target *target, unsigned int address, bool run)
863 riscv011_info_t *info = get_info(target);
864 scans_t *scans = scans_new(target, info->dramsize + 2);
868 unsigned int last = info->dramsize;
869 for (unsigned int i = 0; i < info->dramsize; i++) {
870 if (info->dram_cache[i].dirty)
874 if (last == info->dramsize) {
875 /* Nothing needs to be written to RAM. */
876 dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | (run ? DMCONTROL_INTERRUPT : 0));
879 for (unsigned int i = 0; i < info->dramsize; i++) {
880 if (info->dram_cache[i].dirty) {
881 bool set_interrupt = (i == last && run);
882 scans_add_write32(scans, i, info->dram_cache[i].data,
888 if (run || address < CACHE_NO_READ) {
889 /* Throw away the results of the first read, since it'll contain the
890 * result of the read that happened just before debugint was set. */
891 scans_add_read32(scans, address, false);
893 /* This scan contains the results of the read the caller requested, as
894 * well as an interrupt bit worth looking at. */
895 scans_add_read32(scans, address, false);
898 int retval = scans_execute(scans);
899 if (retval != ERROR_OK) {
901 LOG_ERROR("JTAG execute failed.");
906 for (unsigned int i = 0; i < scans->next_scan; i++) {
907 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
910 case DBUS_STATUS_SUCCESS:
912 case DBUS_STATUS_FAILED:
913 LOG_ERROR("Debug RAM write failed. Hardware error?");
916 case DBUS_STATUS_BUSY:
920 LOG_ERROR("Got invalid bus access status: %d", status);
927 increase_dbus_busy_delay(target);
929 /* Try again, using the slow careful code.
930 * Write all RAM, just to be extra cautious. */
931 for (unsigned int i = 0; i < info->dramsize; i++) {
932 if (i == last && run)
933 dram_write32(target, last, info->dram_cache[last].data, true);
935 dram_write32(target, i, info->dram_cache[i].data, false);
936 info->dram_cache[i].dirty = false;
941 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
942 LOG_ERROR("Debug interrupt didn't clear.");
943 dump_debug_ram(target);
952 for (unsigned int i = 0; i < info->dramsize; i++)
953 info->dram_cache[i].dirty = false;
956 if (run || address < CACHE_NO_READ) {
957 int interrupt = scans_get_u32(scans, scans->next_scan-1,
958 DBUS_DATA_START + 33, 1);
960 increase_interrupt_high_delay(target);
961 /* Slow path wait for it to clear. */
962 if (wait_for_debugint_clear(target, false) != ERROR_OK) {
963 LOG_ERROR("Debug interrupt didn't clear.");
964 dump_debug_ram(target);
969 /* We read a useful value in that last scan. */
970 unsigned int read_addr = scans_get_u32(scans, scans->next_scan-1,
971 DBUS_ADDRESS_START, info->addrbits);
972 if (read_addr != address) {
973 LOG_INFO("Got data from 0x%x but expected it from 0x%x",
976 info->dram_cache[read_addr].data =
977 scans_get_u32(scans, scans->next_scan-1, DBUS_DATA_START, 32);
978 info->dram_cache[read_addr].valid = true;
989 static uint32_t cache_get32(struct target *target, unsigned int address)
991 riscv011_info_t *info = get_info(target);
992 if (!info->dram_cache[address].valid) {
993 info->dram_cache[address].data = dram_read32(target, address);
994 info->dram_cache[address].valid = true;
996 return info->dram_cache[address].data;
999 static uint64_t cache_get(struct target *target, slot_t slot)
1001 unsigned int offset = slot_offset(target, slot);
1002 uint64_t value = cache_get32(target, offset);
1003 if (riscv_xlen(target) > 32)
1004 value |= ((uint64_t) cache_get32(target, offset + 1)) << 32;
1008 /* Write instruction that jumps from the specified word in Debug RAM to resume
1010 static void dram_write_jump(struct target *target, unsigned int index,
1013 dram_write32(target, index,
1014 jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
1018 static int wait_for_state(struct target *target, enum target_state state)
1020 time_t start = time(NULL);
1022 int result = riscv011_poll(target);
1023 if (result != ERROR_OK)
1025 if (target->state == state)
1027 if (time(NULL) - start > riscv_command_timeout_sec) {
1028 LOG_ERROR("Timed out waiting for state %d. "
1029 "Increase timeout with riscv set_command_timeout_sec.", state);
1035 static int read_remote_csr(struct target *target, uint64_t *value, uint32_t csr)
1037 riscv011_info_t *info = get_info(target);
1038 cache_set32(target, 0, csrr(S0, csr));
1039 cache_set_store(target, 1, S0, SLOT0);
1040 cache_set_jump(target, 2);
1041 if (cache_write(target, 4, true) != ERROR_OK)
1043 *value = cache_get(target, SLOT0);
1044 LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
1046 uint32_t exception = cache_get32(target, info->dramsize-1);
1048 LOG_WARNING("Got exception 0x%x when reading %s", exception,
1049 gdb_regno_name(GDB_REGNO_CSR0 + csr));
1057 static int write_remote_csr(struct target *target, uint32_t csr, uint64_t value)
1059 LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
1060 cache_set_load(target, 0, S0, SLOT0);
1061 cache_set32(target, 1, csrw(S0, csr));
1062 cache_set_jump(target, 2);
1063 cache_set(target, SLOT0, value);
1064 if (cache_write(target, 4, true) != ERROR_OK)
1070 static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
1072 cache_set_load(target, 0, gpr, SLOT0);
1073 cache_set_jump(target, 1);
1074 cache_set(target, SLOT0, value);
1075 if (cache_write(target, 4, true) != ERROR_OK)
1080 static int maybe_read_tselect(struct target *target)
1082 riscv011_info_t *info = get_info(target);
1084 if (info->tselect_dirty) {
1085 int result = read_remote_csr(target, &info->tselect, CSR_TSELECT);
1086 if (result != ERROR_OK)
1088 info->tselect_dirty = false;
1094 static int maybe_write_tselect(struct target *target)
1096 riscv011_info_t *info = get_info(target);
1098 if (!info->tselect_dirty) {
1099 int result = write_remote_csr(target, CSR_TSELECT, info->tselect);
1100 if (result != ERROR_OK)
1102 info->tselect_dirty = true;
1108 static int execute_resume(struct target *target, bool step)
1110 riscv011_info_t *info = get_info(target);
1112 LOG_DEBUG("step=%d", step);
1114 maybe_write_tselect(target);
1116 /* TODO: check if dpc is dirty (which also is true if an exception was hit
1118 cache_set_load(target, 0, S0, SLOT0);
1119 cache_set32(target, 1, csrw(S0, CSR_DPC));
1120 cache_set_jump(target, 2);
1121 cache_set(target, SLOT0, info->dpc);
1122 if (cache_write(target, 4, true) != ERROR_OK)
1125 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1126 if (mstatus_reg->valid) {
1127 uint64_t mstatus_user = buf_get_u64(mstatus_reg->value, 0, riscv_xlen(target));
1128 if (mstatus_user != info->mstatus_actual) {
1129 cache_set_load(target, 0, S0, SLOT0);
1130 cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
1131 cache_set_jump(target, 2);
1132 cache_set(target, SLOT0, mstatus_user);
1133 if (cache_write(target, 4, true) != ERROR_OK)
1138 info->dcsr = set_field(info->dcsr, DCSR_EBREAKM, riscv_ebreakm);
1139 info->dcsr = set_field(info->dcsr, DCSR_EBREAKS, riscv_ebreaks);
1140 info->dcsr = set_field(info->dcsr, DCSR_EBREAKU, riscv_ebreaku);
1141 info->dcsr = set_field(info->dcsr, DCSR_EBREAKH, 1);
1142 info->dcsr &= ~DCSR_HALT;
1145 info->dcsr |= DCSR_STEP;
1147 info->dcsr &= ~DCSR_STEP;
1149 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1150 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1151 dram_write32(target, 2, fence_i(), false);
1152 dram_write_jump(target, 3, false);
1154 /* Write DCSR value, set interrupt and clear haltnot. */
1155 uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
1156 dbus_write(target, dram_address(4), dbus_value);
1158 cache_invalidate(target);
1160 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1161 LOG_ERROR("Debug interrupt didn't clear.");
1165 target->state = TARGET_RUNNING;
1166 register_cache_invalidate(target->reg_cache);
1171 /* Execute a step, and wait for reentry into Debug Mode. */
1172 static int full_step(struct target *target, bool announce)
1174 int result = execute_resume(target, true);
1175 if (result != ERROR_OK)
1177 time_t start = time(NULL);
1179 result = poll_target(target, announce);
1180 if (result != ERROR_OK)
1182 if (target->state != TARGET_DEBUG_RUNNING)
1184 if (time(NULL) - start > riscv_command_timeout_sec) {
1185 LOG_ERROR("Timed out waiting for step to complete."
1186 "Increase timeout with riscv set_command_timeout_sec");
1193 static int resume(struct target *target, int debug_execution, bool step)
1195 if (debug_execution) {
1196 LOG_ERROR("TODO: debug_execution is true");
1200 return execute_resume(target, step);
1203 static uint64_t reg_cache_get(struct target *target, unsigned int number)
1205 struct reg *r = &target->reg_cache->reg_list[number];
1207 LOG_ERROR("Register cache entry for %d is invalid!", number);
1210 uint64_t value = buf_get_u64(r->value, 0, r->size);
1211 LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
1215 static void reg_cache_set(struct target *target, unsigned int number,
1218 struct reg *r = &target->reg_cache->reg_list[number];
1219 LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
1221 buf_set_u64(r->value, 0, r->size, value);
1224 static int update_mstatus_actual(struct target *target)
1226 struct reg *mstatus_reg = &target->reg_cache->reg_list[GDB_REGNO_MSTATUS];
1227 if (mstatus_reg->valid) {
1228 /* We previously made it valid. */
1232 /* Force reading the register. In that process mstatus_actual will be
1234 riscv_reg_t mstatus;
1235 return get_register(target, &mstatus, 0, GDB_REGNO_MSTATUS);
1238 /*** OpenOCD target functions. ***/
1240 static int register_read(struct target *target, riscv_reg_t *value, int regnum)
1242 riscv011_info_t *info = get_info(target);
1243 if (regnum >= GDB_REGNO_CSR0 && regnum <= GDB_REGNO_CSR4095) {
1244 cache_set32(target, 0, csrr(S0, regnum - GDB_REGNO_CSR0));
1245 cache_set_store(target, 1, S0, SLOT0);
1246 cache_set_jump(target, 2);
1248 LOG_ERROR("Don't know how to read register %d", regnum);
1252 if (cache_write(target, 4, true) != ERROR_OK)
1255 uint32_t exception = cache_get32(target, info->dramsize-1);
1257 LOG_WARNING("Got exception 0x%x when reading %s", exception, gdb_regno_name(regnum));
1262 *value = cache_get(target, SLOT0);
1263 LOG_DEBUG("reg[%d]=0x%" PRIx64, regnum, *value);
1265 if (regnum == GDB_REGNO_MSTATUS)
1266 info->mstatus_actual = *value;
1271 /* Write the register. No caching or games. */
1272 static int register_write(struct target *target, unsigned int number,
1275 riscv011_info_t *info = get_info(target);
1277 maybe_write_tselect(target);
1280 cache_set_load(target, 0, S0, SLOT0);
1281 cache_set32(target, 1, csrw(S0, CSR_DSCRATCH0));
1282 cache_set_jump(target, 2);
1283 } else if (number == S1) {
1284 cache_set_load(target, 0, S0, SLOT0);
1285 cache_set_store(target, 1, S0, SLOT_LAST);
1286 cache_set_jump(target, 2);
1287 } else if (number <= GDB_REGNO_XPR31) {
1288 cache_set_load(target, 0, number - GDB_REGNO_ZERO, SLOT0);
1289 cache_set_jump(target, 1);
1290 } else if (number == GDB_REGNO_PC) {
1293 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
1294 int result = update_mstatus_actual(target);
1295 if (result != ERROR_OK)
1298 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1299 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1300 cache_set_load(target, i++, S0, SLOT1);
1301 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1302 cache_set(target, SLOT1, info->mstatus_actual);
1305 if (riscv_xlen(target) == 32)
1306 cache_set32(target, i++, flw(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1308 cache_set32(target, i++, fld(number - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1309 cache_set_jump(target, i++);
1310 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
1311 cache_set_load(target, 0, S0, SLOT0);
1312 cache_set32(target, 1, csrw(S0, number - GDB_REGNO_CSR0));
1313 cache_set_jump(target, 2);
1315 if (number == GDB_REGNO_MSTATUS)
1316 info->mstatus_actual = value;
1317 } else if (number == GDB_REGNO_PRIV) {
1318 info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
1321 LOG_ERROR("Don't know how to write register %d", number);
1325 cache_set(target, SLOT0, value);
1326 if (cache_write(target, info->dramsize - 1, true) != ERROR_OK)
1329 uint32_t exception = cache_get32(target, info->dramsize-1);
1331 LOG_WARNING("Got exception 0x%x when writing %s", exception,
1332 gdb_regno_name(number));
1339 static int get_register(struct target *target, riscv_reg_t *value, int hartid,
1342 assert(hartid == 0);
1343 riscv011_info_t *info = get_info(target);
1345 maybe_write_tselect(target);
1347 if (regid <= GDB_REGNO_XPR31) {
1348 *value = reg_cache_get(target, regid);
1349 } else if (regid == GDB_REGNO_PC) {
1351 } else if (regid >= GDB_REGNO_FPR0 && regid <= GDB_REGNO_FPR31) {
1352 int result = update_mstatus_actual(target);
1353 if (result != ERROR_OK)
1356 if ((info->mstatus_actual & MSTATUS_FS) == 0) {
1357 info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
1358 cache_set_load(target, i++, S0, SLOT1);
1359 cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
1360 cache_set(target, SLOT1, info->mstatus_actual);
1363 if (riscv_xlen(target) == 32)
1364 cache_set32(target, i++, fsw(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1366 cache_set32(target, i++, fsd(regid - GDB_REGNO_FPR0, 0, DEBUG_RAM_START + 16));
1367 cache_set_jump(target, i++);
1369 if (cache_write(target, 4, true) != ERROR_OK)
1371 } else if (regid == GDB_REGNO_PRIV) {
1372 *value = get_field(info->dcsr, DCSR_PRV);
1374 int result = register_read(target, value, regid);
1375 if (result != ERROR_OK)
1379 if (regid == GDB_REGNO_MSTATUS)
1380 target->reg_cache->reg_list[regid].valid = true;
1385 static int set_register(struct target *target, int hartid, int regid,
1388 assert(hartid == 0);
1389 return register_write(target, regid, value);
1392 static int halt(struct target *target)
1394 LOG_DEBUG("riscv_halt()");
1395 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1397 cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
1398 cache_set32(target, 1, csrr(S0, CSR_MHARTID));
1399 cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
1400 cache_set_jump(target, 3);
1402 if (cache_write(target, 4, true) != ERROR_OK) {
1403 LOG_ERROR("cache_write() failed.");
1410 static void deinit_target(struct target *target)
1412 LOG_DEBUG("riscv_deinit_target()");
1413 riscv_info_t *info = (riscv_info_t *) target->arch_info;
1414 free(info->version_specific);
1415 info->version_specific = NULL;
1418 static int strict_step(struct target *target, bool announce)
1422 struct watchpoint *watchpoint = target->watchpoints;
1423 while (watchpoint) {
1424 riscv_remove_watchpoint(target, watchpoint);
1425 watchpoint = watchpoint->next;
1428 int result = full_step(target, announce);
1429 if (result != ERROR_OK)
1432 watchpoint = target->watchpoints;
1433 while (watchpoint) {
1434 riscv_add_watchpoint(target, watchpoint);
1435 watchpoint = watchpoint->next;
1441 static int step(struct target *target, int current, target_addr_t address,
1442 int handle_breakpoints)
1444 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1447 if (riscv_xlen(target) > 32) {
1448 LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
1449 riscv_xlen(target));
1451 int result = register_write(target, GDB_REGNO_PC, address);
1452 if (result != ERROR_OK)
1456 if (handle_breakpoints) {
1457 int result = strict_step(target, true);
1458 if (result != ERROR_OK)
1461 return full_step(target, false);
1467 static int examine(struct target *target)
1469 /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1471 uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1472 LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1473 LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
1474 LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
1475 LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
1476 if (dtmcontrol == 0) {
1477 LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
1480 if (get_field(dtmcontrol, DTMCONTROL_VERSION) != 0) {
1481 LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
1482 get_field(dtmcontrol, DTMCONTROL_VERSION), dtmcontrol);
1488 riscv011_info_t *info = get_info(target);
1489 info->addrbits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS);
1490 info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE);
1491 if (info->dtmcontrol_idle == 0) {
1492 /* Some old SiFive cores don't set idle but need it to be 1. */
1493 uint32_t idcode = idcode_scan(target);
1494 if (idcode == 0x10e31913)
1495 info->dtmcontrol_idle = 1;
1498 uint32_t dminfo = dbus_read(target, DMINFO);
1499 LOG_DEBUG("dminfo: 0x%08x", dminfo);
1500 LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
1501 LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
1502 LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
1503 LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
1504 LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
1505 LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
1506 LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
1507 LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
1508 LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
1509 LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
1510 LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
1511 LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
1513 if (get_field(dminfo, DMINFO_VERSION) != 1) {
1514 LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
1515 "(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
1519 info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
1521 if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
1522 LOG_ERROR("Authentication required by RISC-V core but not "
1523 "supported by OpenOCD. dminfo=0x%x", dminfo);
1527 /* Pretend this is a 32-bit system until we have found out the true value. */
1530 /* Figure out XLEN, and test writing all of Debug RAM while we're at it. */
1531 cache_set32(target, 0, xori(S1, ZERO, -1));
1532 /* 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff */
1533 cache_set32(target, 1, srli(S1, S1, 31));
1534 /* 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff */
1535 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
1536 cache_set32(target, 3, srli(S1, S1, 31));
1537 /* 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff */
1538 cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
1539 cache_set_jump(target, 5);
1540 for (unsigned i = 6; i < info->dramsize; i++)
1541 cache_set32(target, i, i * 0x01020304);
1543 cache_write(target, 0, false);
1545 /* Check that we can actually read/write dram. */
1546 if (cache_check(target) != ERROR_OK)
1549 cache_write(target, 0, true);
1550 cache_invalidate(target);
1552 uint32_t word0 = cache_get32(target, 0);
1553 uint32_t word1 = cache_get32(target, 1);
1554 riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
1555 if (word0 == 1 && word1 == 0) {
1556 generic_info->xlen[0] = 32;
1557 } else if (word0 == 0xffffffff && word1 == 3) {
1558 generic_info->xlen[0] = 64;
1559 } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
1560 generic_info->xlen[0] = 128;
1562 uint32_t exception = cache_get32(target, info->dramsize-1);
1563 LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
1564 word0, word1, exception);
1565 dump_debug_ram(target);
1568 LOG_DEBUG("Discovered XLEN is %d", riscv_xlen(target));
1570 if (read_remote_csr(target, &r->misa[0], CSR_MISA) != ERROR_OK) {
1571 const unsigned old_csr_misa = 0xf10;
1572 LOG_WARNING("Failed to read misa at 0x%x; trying 0x%x.", CSR_MISA,
1574 if (read_remote_csr(target, &r->misa[0], old_csr_misa) != ERROR_OK) {
1575 /* Maybe this is an old core that still has $misa at the old
1577 LOG_ERROR("Failed to read misa at 0x%x.", old_csr_misa);
1582 /* Update register list to match discovered XLEN/supported extensions. */
1583 riscv_init_registers(target);
1585 info->never_halted = true;
1587 int result = riscv011_poll(target);
1588 if (result != ERROR_OK)
1591 target_set_examined(target);
1592 riscv_set_current_hartid(target, 0);
1593 for (size_t i = 0; i < 32; ++i)
1594 reg_cache_set(target, i, -1);
1595 LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64,
1596 riscv_xlen(target), r->misa[0]);
1601 static riscv_error_t handle_halt_routine(struct target *target)
1603 riscv011_info_t *info = get_info(target);
1605 scans_t *scans = scans_new(target, 256);
1609 /* Read all GPRs as fast as we can, because gdb is going to ask for them
1610 * anyway. Reading them one at a time is much slower. */
1612 /* Write the jump back to address 1. */
1613 scans_add_write_jump(scans, 1, false);
1614 for (int reg = 1; reg < 32; reg++) {
1615 if (reg == S0 || reg == S1)
1618 /* Write store instruction. */
1619 scans_add_write_store(scans, 0, reg, SLOT0, true);
1622 scans_add_read(scans, SLOT0, false);
1625 /* Write store of s0 at index 1. */
1626 scans_add_write_store(scans, 1, S0, SLOT0, false);
1627 /* Write jump at index 2. */
1628 scans_add_write_jump(scans, 2, false);
1630 /* Read S1 from debug RAM */
1631 scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
1633 scans_add_read(scans, SLOT0, false);
1635 /* Read S0 from dscratch */
1636 unsigned int csr[] = {CSR_DSCRATCH0, CSR_DPC, CSR_DCSR};
1637 for (unsigned int i = 0; i < DIM(csr); i++) {
1638 scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
1639 scans_add_read(scans, SLOT0, false);
1642 /* Final read to get the last value out. */
1643 scans_add_read32(scans, 4, false);
1645 int retval = scans_execute(scans);
1646 if (retval != ERROR_OK) {
1647 LOG_ERROR("JTAG execute failed: %d", retval);
1651 unsigned int dbus_busy = 0;
1652 unsigned int interrupt_set = 0;
1653 unsigned result = 0;
1655 reg_cache_set(target, 0, 0);
1656 /* The first scan result is the result from something old we don't care
1658 for (unsigned int i = 1; i < scans->next_scan && dbus_busy == 0; i++) {
1659 dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
1661 uint64_t data = scans_get_u64(scans, i, DBUS_DATA_START, DBUS_DATA_SIZE);
1662 uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
1665 case DBUS_STATUS_SUCCESS:
1667 case DBUS_STATUS_FAILED:
1668 LOG_ERROR("Debug access failed. Hardware error?");
1670 case DBUS_STATUS_BUSY:
1674 LOG_ERROR("Got invalid bus access status: %d", status);
1677 if (data & DMCONTROL_INTERRUPT) {
1681 if (address == 4 || address == 5) {
1787 LOG_ERROR("Got invalid register result %d", result);
1790 if (riscv_xlen(target) == 32) {
1791 reg_cache_set(target, reg, data & 0xffffffff);
1793 } else if (riscv_xlen(target) == 64) {
1795 value = data & 0xffffffff;
1796 } else if (address == 5) {
1797 reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
1805 scans_delete(scans);
1808 increase_dbus_busy_delay(target);
1811 if (interrupt_set) {
1812 increase_interrupt_high_delay(target);
1816 /* TODO: get rid of those 2 variables and talk to the cache directly. */
1817 info->dpc = reg_cache_get(target, CSR_DPC);
1818 info->dcsr = reg_cache_get(target, CSR_DCSR);
1820 cache_invalidate(target);
1825 scans_delete(scans);
1829 static int handle_halt(struct target *target, bool announce)
1831 riscv011_info_t *info = get_info(target);
1832 target->state = TARGET_HALTED;
1836 re = handle_halt_routine(target);
1837 } while (re == RE_AGAIN);
1839 LOG_ERROR("handle_halt_routine failed");
1843 int cause = get_field(info->dcsr, DCSR_CAUSE);
1845 case DCSR_CAUSE_SWBP:
1846 target->debug_reason = DBG_REASON_BREAKPOINT;
1848 case DCSR_CAUSE_HWBP:
1849 target->debug_reason = DBG_REASON_WATCHPOINT;
1851 case DCSR_CAUSE_DEBUGINT:
1852 target->debug_reason = DBG_REASON_DBGRQ;
1854 case DCSR_CAUSE_STEP:
1855 target->debug_reason = DBG_REASON_SINGLESTEP;
1857 case DCSR_CAUSE_HALT:
1859 LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
1863 if (info->never_halted) {
1864 info->never_halted = false;
1866 int result = maybe_read_tselect(target);
1867 if (result != ERROR_OK)
1869 riscv_enumerate_triggers(target);
1872 if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1874 if (riscv_semihosting(target, &retval) != 0)
1879 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1881 const char *cause_string[] = {
1883 "software breakpoint",
1889 /* This is logged to the user so that gdb will show it when a user types
1890 * 'monitor reset init'. At that time gdb appears to have the pc cached
1891 * still so if a user manually inspects the pc it will still have the old
1893 LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
1898 static int poll_target(struct target *target, bool announce)
1900 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1902 /* Inhibit debug logging during poll(), which isn't usually interesting and
1903 * just fills up the screen/logs with clutter. */
1904 int old_debug_level = debug_level;
1905 if (debug_level >= LOG_LVL_DEBUG)
1906 debug_level = LOG_LVL_INFO;
1907 bits_t bits = read_bits(target);
1908 debug_level = old_debug_level;
1910 if (bits.haltnot && bits.interrupt) {
1911 target->state = TARGET_DEBUG_RUNNING;
1912 LOG_DEBUG("debug running");
1913 } else if (bits.haltnot && !bits.interrupt) {
1914 if (target->state != TARGET_HALTED)
1915 return handle_halt(target, announce);
1916 } else if (!bits.haltnot && bits.interrupt) {
1917 /* Target is halting. There is no state for that, so don't change anything. */
1918 LOG_DEBUG("halting");
1919 } else if (!bits.haltnot && !bits.interrupt) {
1920 target->state = TARGET_RUNNING;
1926 static int riscv011_poll(struct target *target)
1928 return poll_target(target, true);
1931 static int riscv011_resume(struct target *target, int current,
1932 target_addr_t address, int handle_breakpoints, int debug_execution)
1935 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1938 return resume(target, debug_execution, false);
1941 static int assert_reset(struct target *target)
1943 riscv011_info_t *info = get_info(target);
1944 /* TODO: Maybe what I implemented here is more like soft_reset_halt()? */
1946 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1948 /* The only assumption we can make is that the TAP was reset. */
1949 if (wait_for_debugint_clear(target, true) != ERROR_OK) {
1950 LOG_ERROR("Debug interrupt didn't clear.");
1954 /* Not sure what we should do when there are multiple cores.
1955 * Here just reset the single hart we're talking to. */
1956 info->dcsr = set_field(info->dcsr, DCSR_EBREAKM, riscv_ebreakm);
1957 info->dcsr = set_field(info->dcsr, DCSR_EBREAKS, riscv_ebreaks);
1958 info->dcsr = set_field(info->dcsr, DCSR_EBREAKU, riscv_ebreaku);
1959 info->dcsr = set_field(info->dcsr, DCSR_EBREAKH, 1);
1960 info->dcsr |= DCSR_HALT;
1961 if (target->reset_halt)
1962 info->dcsr |= DCSR_NDRESET;
1964 info->dcsr |= DCSR_FULLRESET;
1965 dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
1966 dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
1967 /* We shouldn't actually need the jump because a reset should happen. */
1968 dram_write_jump(target, 2, false);
1969 dram_write32(target, 4, info->dcsr, true);
1970 cache_invalidate(target);
1972 target->state = TARGET_RESET;
1977 static int deassert_reset(struct target *target)
1979 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1980 if (target->reset_halt)
1981 return wait_for_state(target, TARGET_HALTED);
1983 return wait_for_state(target, TARGET_RUNNING);
1986 static int read_memory(struct target *target, target_addr_t address,
1987 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
1989 if (increment != size) {
1990 LOG_ERROR("read_memory with custom increment not implemented");
1991 return ERROR_NOT_IMPLEMENTED;
1994 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
1996 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
1999 cache_set32(target, 1, lb(S1, S0, 0));
2000 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2003 cache_set32(target, 1, lh(S1, S0, 0));
2004 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2007 cache_set32(target, 1, lw(S1, S0, 0));
2008 cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
2011 LOG_ERROR("Unsupported size: %d", size);
2014 cache_set_jump(target, 3);
2015 cache_write(target, CACHE_NO_READ, false);
2017 riscv011_info_t *info = get_info(target);
2018 const unsigned max_batch_size = 256;
2019 scans_t *scans = scans_new(target, max_batch_size);
2023 uint32_t result_value = 0x777;
2025 while (i < count + 3) {
2026 unsigned int batch_size = MIN(count + 3 - i, max_batch_size);
2029 for (unsigned int j = 0; j < batch_size; j++) {
2030 if (i + j == count) {
2031 /* Just insert a read so we can scan out the last value. */
2032 scans_add_read32(scans, 4, false);
2033 } else if (i + j >= count + 1) {
2034 /* And check for errors. */
2035 scans_add_read32(scans, info->dramsize-1, false);
2037 /* Write the next address and set interrupt. */
2038 uint32_t offset = size * (i + j);
2039 scans_add_write32(scans, 4, address + offset, true);
2043 int retval = scans_execute(scans);
2044 if (retval != ERROR_OK) {
2045 LOG_ERROR("JTAG execute failed: %d", retval);
2050 int execute_busy = 0;
2051 for (unsigned int j = 0; j < batch_size; j++) {
2052 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2055 case DBUS_STATUS_SUCCESS:
2057 case DBUS_STATUS_FAILED:
2058 LOG_ERROR("Debug RAM write failed. Hardware error?");
2060 case DBUS_STATUS_BUSY:
2064 LOG_ERROR("Got invalid bus access status: %d", status);
2067 uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
2069 if (data & DMCONTROL_INTERRUPT)
2071 if (i + j == count + 2) {
2072 result_value = data;
2073 } else if (i + j > 1) {
2074 uint32_t offset = size * (i + j - 2);
2077 buffer[offset] = data;
2080 buffer[offset] = data;
2081 buffer[offset+1] = data >> 8;
2084 buffer[offset] = data;
2085 buffer[offset+1] = data >> 8;
2086 buffer[offset+2] = data >> 16;
2087 buffer[offset+3] = data >> 24;
2091 LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
2094 increase_dbus_busy_delay(target);
2096 increase_interrupt_high_delay(target);
2097 if (dbus_busy || execute_busy) {
2098 wait_for_debugint_clear(target, false);
2101 LOG_INFO("Retrying memory read starting from 0x%" TARGET_PRIxADDR
2102 " with more delays", address + size * i);
2108 if (result_value != 0) {
2109 LOG_USER("Core got an exception (0x%x) while reading from 0x%"
2110 TARGET_PRIxADDR, result_value, address + size * (count-1));
2112 LOG_USER("(It may have failed between 0x%" TARGET_PRIxADDR
2113 " and 0x%" TARGET_PRIxADDR " as well, but we "
2114 "didn't check then.)",
2115 address, address + size * (count-2) + size - 1);
2120 scans_delete(scans);
2121 cache_clean(target);
2125 scans_delete(scans);
2126 cache_clean(target);
2130 static int setup_write_memory(struct target *target, uint32_t size)
2134 cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
2135 cache_set32(target, 1, sb(S0, T0, 0));
2138 cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
2139 cache_set32(target, 1, sh(S0, T0, 0));
2142 cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
2143 cache_set32(target, 1, sw(S0, T0, 0));
2146 LOG_ERROR("Unsupported size: %d", size);
2149 cache_set32(target, 2, addi(T0, T0, size));
2150 cache_set_jump(target, 3);
2151 cache_write(target, 4, false);
2156 static int write_memory(struct target *target, target_addr_t address,
2157 uint32_t size, uint32_t count, const uint8_t *buffer)
2159 riscv011_info_t *info = get_info(target);
2160 jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
2162 /* Set up the address. */
2163 cache_set_store(target, 0, T0, SLOT1);
2164 cache_set_load(target, 1, T0, SLOT0);
2165 cache_set_jump(target, 2);
2166 cache_set(target, SLOT0, address);
2167 if (cache_write(target, 5, true) != ERROR_OK)
2170 uint64_t t0 = cache_get(target, SLOT1);
2171 LOG_DEBUG("t0 is 0x%" PRIx64, t0);
2173 if (setup_write_memory(target, size) != ERROR_OK)
2176 const unsigned max_batch_size = 256;
2177 scans_t *scans = scans_new(target, max_batch_size);
2181 uint32_t result_value = 0x777;
2183 while (i < count + 2) {
2184 unsigned int batch_size = MIN(count + 2 - i, max_batch_size);
2187 for (unsigned int j = 0; j < batch_size; j++) {
2188 if (i + j >= count) {
2189 /* Check for an exception. */
2190 scans_add_read32(scans, info->dramsize-1, false);
2192 /* Write the next value and set interrupt. */
2194 uint32_t offset = size * (i + j);
2197 value = buffer[offset];
2200 value = buffer[offset] |
2201 (buffer[offset+1] << 8);
2204 value = buffer[offset] |
2205 ((uint32_t) buffer[offset+1] << 8) |
2206 ((uint32_t) buffer[offset+2] << 16) |
2207 ((uint32_t) buffer[offset+3] << 24);
2213 scans_add_write32(scans, 4, value, true);
2217 int retval = scans_execute(scans);
2218 if (retval != ERROR_OK) {
2219 LOG_ERROR("JTAG execute failed: %d", retval);
2224 int execute_busy = 0;
2225 for (unsigned int j = 0; j < batch_size; j++) {
2226 dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
2229 case DBUS_STATUS_SUCCESS:
2231 case DBUS_STATUS_FAILED:
2232 LOG_ERROR("Debug RAM write failed. Hardware error?");
2234 case DBUS_STATUS_BUSY:
2238 LOG_ERROR("Got invalid bus access status: %d", status);
2241 int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
2244 if (i + j == count + 1)
2245 result_value = scans_get_u32(scans, j, DBUS_DATA_START, 32);
2248 increase_dbus_busy_delay(target);
2250 increase_interrupt_high_delay(target);
2251 if (dbus_busy || execute_busy) {
2252 wait_for_debugint_clear(target, false);
2255 * Set t0 back to what it should have been at the beginning of this
2257 LOG_INFO("Retrying memory write starting from 0x%" TARGET_PRIxADDR
2258 " with more delays", address + size * i);
2260 cache_clean(target);
2262 if (write_gpr(target, T0, address + size * i) != ERROR_OK)
2265 if (setup_write_memory(target, size) != ERROR_OK)
2272 if (result_value != 0) {
2273 LOG_ERROR("Core got an exception (0x%x) while writing to 0x%"
2274 TARGET_PRIxADDR, result_value, address + size * (count-1));
2276 LOG_ERROR("(It may have failed between 0x%" TARGET_PRIxADDR
2277 " and 0x%" TARGET_PRIxADDR " as well, but we "
2278 "didn't check then.)",
2279 address, address + size * (count-2) + size - 1);
2284 scans_delete(scans);
2285 cache_clean(target);
2286 return register_write(target, T0, t0);
2289 scans_delete(scans);
2290 cache_clean(target);
2294 static int arch_state(struct target *target)
2299 static int init_target(struct command_context *cmd_ctx,
2300 struct target *target)
2303 riscv_info_t *generic_info = (riscv_info_t *)target->arch_info;
2304 generic_info->get_register = get_register;
2305 generic_info->set_register = set_register;
2306 generic_info->read_memory = read_memory;
2308 generic_info->version_specific = calloc(1, sizeof(riscv011_info_t));
2309 if (!generic_info->version_specific)
2312 /* Assume 32-bit until we discover the real value in examine(). */
2313 generic_info->xlen[0] = 32;
2314 riscv_init_registers(target);
2319 struct target_type riscv011_target = {
2322 .init_target = init_target,
2323 .deinit_target = deinit_target,
2326 /* poll current target status */
2327 .poll = riscv011_poll,
2330 .resume = riscv011_resume,
2333 .assert_reset = assert_reset,
2334 .deassert_reset = deassert_reset,
2336 .write_memory = write_memory,
2338 .arch_state = arch_state,