2 * This file is auto-generated by running 'make debug_defines.h' in
3 * https://github.com/riscv/riscv-debug-spec/ (30b1a97)
6 #define DTM_IDCODE 0x01
8 * Identifies the release version of this part.
10 #define DTM_IDCODE_VERSION_OFFSET 28
11 #define DTM_IDCODE_VERSION_LENGTH 4
12 #define DTM_IDCODE_VERSION (0xfU << DTM_IDCODE_VERSION_OFFSET)
14 * Identifies the designer's part number of this part.
16 #define DTM_IDCODE_PARTNUMBER_OFFSET 12
17 #define DTM_IDCODE_PARTNUMBER_LENGTH 16
18 #define DTM_IDCODE_PARTNUMBER (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET)
20 * Identifies the designer/manufacturer of this part. Bits 6:0 must be
21 * bits 6:0 of the designer/manufacturer's Identification Code as
22 * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
23 * count of the number of continuation characters (0x7f) in that same
24 * Identification Code.
26 #define DTM_IDCODE_MANUFID_OFFSET 1
27 #define DTM_IDCODE_MANUFID_LENGTH 11
28 #define DTM_IDCODE_MANUFID (0x7ffU << DTM_IDCODE_MANUFID_OFFSET)
29 #define DTM_IDCODE_1_OFFSET 0
30 #define DTM_IDCODE_1_LENGTH 1
31 #define DTM_IDCODE_1 (0x1U << DTM_IDCODE_1_OFFSET)
32 #define DTM_DTMCS 0x10
34 * Writing 1 to this bit does a hard reset of the DTM,
35 * causing the DTM to forget about any outstanding DMI transactions, and
36 * returning all registers and internal state to their reset value.
37 * In general this should only be used when the Debugger has
38 * reason to expect that the outstanding DMI transaction will never
39 * complete (e.g. a reset condition caused an inflight DMI transaction to
42 #define DTM_DTMCS_DMIHARDRESET_OFFSET 17
43 #define DTM_DTMCS_DMIHARDRESET_LENGTH 1
44 #define DTM_DTMCS_DMIHARDRESET (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET)
46 * Writing 1 to this bit clears the sticky error state, but does
47 * not affect outstanding DMI transactions.
49 #define DTM_DTMCS_DMIRESET_OFFSET 16
50 #define DTM_DTMCS_DMIRESET_LENGTH 1
51 #define DTM_DTMCS_DMIRESET (0x1U << DTM_DTMCS_DMIRESET_OFFSET)
53 * This is a hint to the debugger of the minimum number of
54 * cycles a debugger should spend in
55 * Run-Test/Idle after every DMI scan to avoid a `busy'
56 * return code (\FdtmDtmcsDmistat of 3). A debugger must still
57 * check \FdtmDtmcsDmistat when necessary.
59 * 0: It is not necessary to enter Run-Test/Idle at all.
61 * 1: Enter Run-Test/Idle and leave it immediately.
63 * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
67 #define DTM_DTMCS_IDLE_OFFSET 12
68 #define DTM_DTMCS_IDLE_LENGTH 3
69 #define DTM_DTMCS_IDLE (0x7U << DTM_DTMCS_IDLE_OFFSET)
73 * 1: Reserved. Interpret the same as 2.
75 * 2: An operation failed (resulted in \FdtmDmiOp of 2).
77 * 3: An operation was attempted while a DMI access was still in
78 * progress (resulted in \FdtmDmiOp of 3).
80 #define DTM_DTMCS_DMISTAT_OFFSET 10
81 #define DTM_DTMCS_DMISTAT_LENGTH 2
82 #define DTM_DTMCS_DMISTAT (0x3U << DTM_DTMCS_DMISTAT_OFFSET)
84 * The size of \FdmSbaddressZeroAddress in \RdtmDmi.
86 #define DTM_DTMCS_ABITS_OFFSET 4
87 #define DTM_DTMCS_ABITS_LENGTH 6
88 #define DTM_DTMCS_ABITS (0x3fU << DTM_DTMCS_ABITS_OFFSET)
90 * 0: Version described in spec version 0.11.
92 * 1: Version described in spec version 0.13.
94 * 15: Version not described in any available version of this spec.
96 #define DTM_DTMCS_VERSION_OFFSET 0
97 #define DTM_DTMCS_VERSION_LENGTH 4
98 #define DTM_DTMCS_VERSION (0xfU << DTM_DTMCS_VERSION_OFFSET)
101 * Address used for DMI access. In Update-DR this value is used
102 * to access the DM over the DMI.
104 #define DTM_DMI_ADDRESS_OFFSET 34
105 #define DTM_DMI_ADDRESS_LENGTH abits
106 #define DTM_DMI_ADDRESS (((1L << abits) - 1) << DTM_DMI_ADDRESS_OFFSET)
108 * The data to send to the DM over the DMI during Update-DR, and
109 * the data returned from the DM as a result of the previous operation.
111 #define DTM_DMI_DATA_OFFSET 2
112 #define DTM_DMI_DATA_LENGTH 32
113 #define DTM_DMI_DATA (0xffffffffULL << DTM_DMI_DATA_OFFSET)
115 * When the debugger writes this field, it has the following meaning:
117 * 0: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress. (nop)
119 * Don't send anything over the DMI during Update-DR.
120 * This operation should never result in a busy or error response.
121 * The address and data reported in the following Capture-DR
124 * 1: Read from \FdmSbaddressZeroAddress. (read)
126 * 2: Write \FdmSbdataZeroData to \FdmSbaddressZeroAddress. (write)
130 * When the debugger reads this field, it means the following:
132 * 0: The previous operation completed successfully.
136 * 2: A previous operation failed. The data scanned into \RdtmDmi in
137 * this access will be ignored. This status is sticky and can be
138 * cleared by writing \FdtmDtmcsDmireset in \RdtmDtmcs.
140 * This indicates that the DM itself responded with an error.
141 * There are no specified cases in which the DM would
142 * respond with an error, and DMI is not required to support
145 * 3: An operation was attempted while a DMI request is still in
146 * progress. The data scanned into \RdtmDmi in this access will be
147 * ignored. This status is sticky and can be cleared by writing
148 * \FdtmDtmcsDmireset in \RdtmDtmcs. If a debugger sees this status, it
149 * needs to give the target more TCK edges between Update-DR and
150 * Capture-DR. The simplest way to do that is to add extra transitions
153 #define DTM_DMI_OP_OFFSET 0
154 #define DTM_DMI_OP_LENGTH 2
155 #define DTM_DMI_OP (0x3ULL << DTM_DMI_OP_OFFSET)
156 #define CSR_DCSR 0x7b0
158 * 0: There is no external debug support.
160 * 4: External debug support exists as it is described in this document.
162 * 15: There is external debug support, but it does not conform to any
163 * available version of this spec.
165 #define CSR_DCSR_XDEBUGVER_OFFSET 28
166 #define CSR_DCSR_XDEBUGVER_LENGTH 4
167 #define CSR_DCSR_XDEBUGVER (0xfU << CSR_DCSR_XDEBUGVER_OFFSET)
169 * 0: {\tt ebreak} instructions in M-mode behave as described in the
172 * 1: {\tt ebreak} instructions in M-mode enter Debug Mode.
174 #define CSR_DCSR_EBREAKM_OFFSET 15
175 #define CSR_DCSR_EBREAKM_LENGTH 1
176 #define CSR_DCSR_EBREAKM (0x1U << CSR_DCSR_EBREAKM_OFFSET)
178 * 0: {\tt ebreak} instructions in S-mode behave as described in the
181 * 1: {\tt ebreak} instructions in S-mode enter Debug Mode.
183 * This bit is hardwired to 0 if the hart does not support S mode.
185 #define CSR_DCSR_EBREAKS_OFFSET 13
186 #define CSR_DCSR_EBREAKS_LENGTH 1
187 #define CSR_DCSR_EBREAKS (0x1U << CSR_DCSR_EBREAKS_OFFSET)
189 * 0: {\tt ebreak} instructions in U-mode behave as described in the
192 * 1: {\tt ebreak} instructions in U-mode enter Debug Mode.
194 * This bit is hardwired to 0 if the hart does not support U mode.
196 #define CSR_DCSR_EBREAKU_OFFSET 12
197 #define CSR_DCSR_EBREAKU_LENGTH 1
198 #define CSR_DCSR_EBREAKU (0x1U << CSR_DCSR_EBREAKU_OFFSET)
200 * 0: Interrupts (including NMI) are disabled during single stepping.
202 * 1: Interrupts (including NMI) are enabled during single stepping.
204 * Implementations may hard wire this bit to 0.
205 * In that case interrupt behavior can be emulated by the debugger.
207 * The debugger must not change the value of this bit while the hart
210 #define CSR_DCSR_STEPIE_OFFSET 11
211 #define CSR_DCSR_STEPIE_LENGTH 1
212 #define CSR_DCSR_STEPIE (0x1U << CSR_DCSR_STEPIE_OFFSET)
214 * 0: Increment counters as usual.
216 * 1: Don't increment any hart-local counters while in Debug Mode or
217 * on {\tt ebreak} instructions that cause entry into Debug Mode.
218 * These counters include the {\tt instret} CSR. On single-hart cores
219 * {\tt cycle} should be stopped, but on multi-hart cores it must keep
222 * An implementation may hardwire this bit to 0 or 1.
224 #define CSR_DCSR_STOPCOUNT_OFFSET 10
225 #define CSR_DCSR_STOPCOUNT_LENGTH 1
226 #define CSR_DCSR_STOPCOUNT (0x1U << CSR_DCSR_STOPCOUNT_OFFSET)
228 * 0: Increment timers as usual.
230 * 1: Don't increment any hart-local timers while in Debug Mode.
232 * An implementation may hardwire this bit to 0 or 1.
234 #define CSR_DCSR_STOPTIME_OFFSET 9
235 #define CSR_DCSR_STOPTIME_LENGTH 1
236 #define CSR_DCSR_STOPTIME (0x1U << CSR_DCSR_STOPTIME_OFFSET)
238 * Explains why Debug Mode was entered.
240 * When there are multiple reasons to enter Debug Mode in a single
241 * cycle, hardware should set \FcsrDcsrCause to the cause with the highest
244 * 1: An {\tt ebreak} instruction was executed. (priority 3)
246 * 2: The Trigger Module caused a breakpoint exception. (priority 4)
248 * 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
251 * 4: The hart single stepped because \FcsrDcsrStep was set. (priority 0, lowest)
253 * 5: The hart halted directly out of reset due to \Fresethaltreq. It
254 * is also acceptable to report 3 when this happens. (priority 2)
256 * 6: The hart halted because it's part of a halt group. (priority 5,
257 * highest) Harts may report 3 for this cause instead.
259 * Other values are reserved for future use.
261 #define CSR_DCSR_CAUSE_OFFSET 6
262 #define CSR_DCSR_CAUSE_LENGTH 3
263 #define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET)
265 * 0: \FcsrMcontrolMprv in \Rmstatus is ignored in Debug Mode.
267 * 1: \FcsrMcontrolMprv in \Rmstatus takes effect in Debug Mode.
269 * Implementing this bit is optional. It may be tied to either 0 or 1.
271 #define CSR_DCSR_MPRVEN_OFFSET 4
272 #define CSR_DCSR_MPRVEN_LENGTH 1
273 #define CSR_DCSR_MPRVEN (0x1U << CSR_DCSR_MPRVEN_OFFSET)
275 * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
277 * Since an NMI can indicate a hardware error condition,
278 * reliable debugging may no longer be possible once this bit becomes set.
279 * This is implementation-dependent.
281 #define CSR_DCSR_NMIP_OFFSET 3
282 #define CSR_DCSR_NMIP_LENGTH 1
283 #define CSR_DCSR_NMIP (0x1U << CSR_DCSR_NMIP_OFFSET)
285 * When set and not in Debug Mode, the hart will only execute a single
286 * instruction and then enter Debug Mode. See Section~\ref{stepBit}
289 * The debugger must not change the value of this bit while the hart
292 #define CSR_DCSR_STEP_OFFSET 2
293 #define CSR_DCSR_STEP_LENGTH 1
294 #define CSR_DCSR_STEP (0x1U << CSR_DCSR_STEP_OFFSET)
296 * Contains the privilege level the hart was operating in when Debug
297 * Mode was entered. The encoding is described in Table
298 * \ref{tab:privlevel}. A debugger can change this value to change
299 * the hart's privilege level when exiting Debug Mode.
301 * Not all privilege levels are supported on all harts. If the
302 * encoding written is not supported or the debugger is not allowed to
303 * change to it, the hart may change to any supported privilege level.
305 #define CSR_DCSR_PRV_OFFSET 0
306 #define CSR_DCSR_PRV_LENGTH 2
307 #define CSR_DCSR_PRV (0x3U << CSR_DCSR_PRV_OFFSET)
308 #define CSR_DPC 0x7b1
309 #define CSR_DPC_DPC_OFFSET 0
310 #define CSR_DPC_DPC_LENGTH DXLEN
311 #define CSR_DPC_DPC (((1L << DXLEN) - 1) << CSR_DPC_DPC_OFFSET)
312 #define CSR_DSCRATCH0 0x7b2
313 #define CSR_DSCRATCH1 0x7b3
314 #define CSR_TSELECT 0x7a0
315 #define CSR_TSELECT_INDEX_OFFSET 0
316 #define CSR_TSELECT_INDEX_LENGTH XLEN
317 #define CSR_TSELECT_INDEX (((1L << XLEN) - 1) << CSR_TSELECT_INDEX_OFFSET)
318 #define CSR_TDATA1 0x7a1
320 * 0: There is no trigger at this \RcsrTselect.
322 * 1: The trigger is a legacy SiFive address match trigger. These
323 * should not be implemented and aren't further documented here.
325 * 2: The trigger is an address/data match trigger. The remaining bits
326 * in this register act as described in \RcsrMcontrol.
328 * 3: The trigger is an instruction count trigger. The remaining bits
329 * in this register act as described in \RcsrIcount.
331 * 4: The trigger is an interrupt trigger. The remaining bits
332 * in this register act as described in \RcsrItrigger.
334 * 5: The trigger is an exception trigger. The remaining bits
335 * in this register act as described in \RcsrEtrigger.
337 * 12--14: These trigger types are available for non-standard use.
339 * 15: This trigger exists (so enumeration shouldn't terminate), but
340 * is not currently available.
342 * Other values are reserved for future use.
344 #define CSR_TDATA1_TYPE_OFFSET (XLEN-4)
345 #define CSR_TDATA1_TYPE_LENGTH 4
346 #define CSR_TDATA1_TYPE (0xfULL << CSR_TDATA1_TYPE_OFFSET)
348 * If \FcsrTdataOneType is 0, then this bit is hard-wired to 0.
350 * 0: Both Debug and M-mode can write the {\tt tdata} registers at the
351 * selected \RcsrTselect.
353 * 1: Only Debug Mode can write the {\tt tdata} registers at the
354 * selected \RcsrTselect. Writes from other modes are ignored.
356 * This bit is only writable from Debug Mode.
357 * When clearing this bit, the debugger should also clear the action field
358 * (whose location depends on \FcsrTdataOneType).
360 #define CSR_TDATA1_DMODE_OFFSET (XLEN-5)
361 #define CSR_TDATA1_DMODE_LENGTH 1
362 #define CSR_TDATA1_DMODE (0x1ULL << CSR_TDATA1_DMODE_OFFSET)
364 * If \FcsrTdataOneType is 0, then this field is hard-wired to 0.
366 * Trigger-specific data.
368 #define CSR_TDATA1_DATA_OFFSET 0
369 #define CSR_TDATA1_DATA_LENGTH (XLEN - 5)
370 #define CSR_TDATA1_DATA (((1L << XLEN - 5) - 1) << CSR_TDATA1_DATA_OFFSET)
371 #define CSR_TDATA2 0x7a2
372 #define CSR_TDATA2_DATA_OFFSET 0
373 #define CSR_TDATA2_DATA_LENGTH XLEN
374 #define CSR_TDATA2_DATA (((1L << XLEN) - 1) << CSR_TDATA2_DATA_OFFSET)
375 #define CSR_TDATA3 0x7a3
376 #define CSR_TDATA3_DATA_OFFSET 0
377 #define CSR_TDATA3_DATA_LENGTH XLEN
378 #define CSR_TDATA3_DATA (((1L << XLEN) - 1) << CSR_TDATA3_DATA_OFFSET)
379 #define CSR_TINFO 0x7a4
381 * One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N
382 * corresponds to type N. If the bit is set, then that type is
383 * supported by the currently selected trigger.
385 * If the currently selected trigger doesn't exist, this field
388 #define CSR_TINFO_INFO_OFFSET 0
389 #define CSR_TINFO_INFO_LENGTH 16
390 #define CSR_TINFO_INFO (0xffffULL << CSR_TINFO_INFO_OFFSET)
391 #define CSR_TCONTROL 0x7a5
393 * M-mode previous trigger enable field.
395 * When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
398 #define CSR_TCONTROL_MPTE_OFFSET 7
399 #define CSR_TCONTROL_MPTE_LENGTH 1
400 #define CSR_TCONTROL_MPTE (0x1ULL << CSR_TCONTROL_MPTE_OFFSET)
402 * M-mode trigger enable field.
404 * 0: Triggers with action=0 do not match/fire while the hart is in M-mode.
406 * 1: Triggers do match/fire while the hart is in M-mode.
408 * When a trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt
409 * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte.
411 #define CSR_TCONTROL_MTE_OFFSET 3
412 #define CSR_TCONTROL_MTE_LENGTH 1
413 #define CSR_TCONTROL_MTE (0x1ULL << CSR_TCONTROL_MTE_OFFSET)
414 #define CSR_MCONTEXT 0x7a8
416 * Machine mode software can write a context number to this register,
417 * which can be used to set triggers that only fire in that specific
420 * An implementation may tie any number of upper bits in this field to
421 * 0. It's recommended to implement no more than 6 bits on RV32, and
424 #define CSR_MCONTEXT_MCONTEXT_OFFSET 0
425 #define CSR_MCONTEXT_MCONTEXT_LENGTH XLEN
426 #define CSR_MCONTEXT_MCONTEXT (((1L << XLEN) - 1) << CSR_MCONTEXT_MCONTEXT_OFFSET)
427 #define CSR_SCONTEXT 0x7aa
429 * Supervisor mode software can write a context number to this
430 * register, which can be used to set triggers that only fire in that
433 * An implementation may tie any number of high bits in this field to
434 * 0. It's recommended to implement no more than 16 bits on RV32, and
437 #define CSR_SCONTEXT_DATA_OFFSET 0
438 #define CSR_SCONTEXT_DATA_LENGTH XLEN
439 #define CSR_SCONTEXT_DATA (((1L << XLEN) - 1) << CSR_SCONTEXT_DATA_OFFSET)
440 #define CSR_MCONTROL 0x7a1
441 #define CSR_MCONTROL_TYPE_OFFSET (XLEN-4)
442 #define CSR_MCONTROL_TYPE_LENGTH 4
443 #define CSR_MCONTROL_TYPE (0xfULL << CSR_MCONTROL_TYPE_OFFSET)
444 #define CSR_MCONTROL_DMODE_OFFSET (XLEN-5)
445 #define CSR_MCONTROL_DMODE_LENGTH 1
446 #define CSR_MCONTROL_DMODE (0x1ULL << CSR_MCONTROL_DMODE_OFFSET)
448 * Specifies the largest naturally aligned powers-of-two (NAPOT) range
449 * supported by the hardware when \FcsrMcontrolMatch is 1. The value is the
450 * logarithm base 2 of the
451 * number of bytes in that range. A value of 0 indicates that only
452 * exact value matches are supported (one byte range). A value of 63
453 * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in
456 #define CSR_MCONTROL_MASKMAX_OFFSET (XLEN-11)
457 #define CSR_MCONTROL_MASKMAX_LENGTH 6
458 #define CSR_MCONTROL_MASKMAX (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET)
460 * This field only exists when XLEN is at least 64.
461 * It contains the 2 high bits of the access size. The low bits
462 * come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this
465 #define CSR_MCONTROL_SIZEHI_OFFSET 21
466 #define CSR_MCONTROL_SIZEHI_LENGTH 2
467 #define CSR_MCONTROL_SIZEHI (0x3ULL << CSR_MCONTROL_SIZEHI_OFFSET)
469 * If this bit is implemented, the hardware sets it when this
470 * trigger matches. The trigger's user can set or clear it at any
471 * time. It is used to determine which
472 * trigger(s) matched. If the bit is not implemented, it is always 0
473 * and writing it has no effect.
475 #define CSR_MCONTROL_HIT_OFFSET 20
476 #define CSR_MCONTROL_HIT_LENGTH 1
477 #define CSR_MCONTROL_HIT (0x1ULL << CSR_MCONTROL_HIT_OFFSET)
479 * 0: Perform a match on the lowest virtual address of the access. In
480 * addition, it is recommended that the trigger also fires if any of
481 * the other accessed virtual addresses match.
482 * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
483 * and the other addresses are 0x4001, 0x4002, and 0x4003.)
485 * 1: Perform a match on the data value loaded or stored, or the
486 * instruction executed.
488 #define CSR_MCONTROL_SELECT_OFFSET 19
489 #define CSR_MCONTROL_SELECT_LENGTH 1
490 #define CSR_MCONTROL_SELECT (0x1ULL << CSR_MCONTROL_SELECT_OFFSET)
492 * 0: The action for this trigger will be taken just before the
493 * instruction that triggered it is executed, but after all preceding
494 * instructions are committed. \Rmepc or \RcsrDpc (depending on
495 * \FcsrMcontrolAction) must be set to the virtual address of the
496 * instruction that matched.
498 * If this is combined with \FcsrMcontrolLoad then a memory access will be
499 * performed (including any side effects of performing such an access) even
500 * though the load will not update its destination register. Debuggers
501 * should consider this when setting such breakpoints on, for example,
502 * memory-mapped I/O addresses.
504 * 1: The action for this trigger will be taken after the instruction
505 * that triggered it is executed. It should be taken before the next
506 * instruction is executed, but it is better to implement triggers imprecisely
507 * than to not implement them at all.
508 * \Rmepc or \RcsrDpc (depending on \FcsrMcontrolAction) must be set to
509 * the virtual address of the next instruction that must be executed to
510 * preserve the program flow.
512 * Most hardware will only implement one timing or the other, possibly
513 * dependent on \FcsrMcontrolSelect, \FcsrMcontrolExecute,
514 * \FcsrMcontrolLoad, and \FcsrMcontrolStore. This bit
515 * primarily exists for the hardware to communicate to the debugger
516 * what will happen. Hardware may implement the bit fully writable, in
517 * which case the debugger has a little more control.
519 * Data load triggers with \FcsrMcontrolTiming of 0 will result in the same load
520 * happening again when the debugger lets the hart run. For data load
521 * triggers, debuggers must first attempt to set the breakpoint with
522 * \FcsrMcontrolTiming of 1.
524 * If a trigger with \FcsrMcontrolTiming of 0 matches, it is
525 * implementation-dependent whether that prevents a trigger with
526 * \FcsrMcontrolTiming of 1 matching as well.
528 #define CSR_MCONTROL_TIMING_OFFSET 18
529 #define CSR_MCONTROL_TIMING_LENGTH 1
530 #define CSR_MCONTROL_TIMING (0x1ULL << CSR_MCONTROL_TIMING_OFFSET)
532 * This field contains the 2 low bits of the access size. The high bits come
533 * from \FcsrMcontrolSizehi. The combined value is interpreted as follows:
535 * 0: The trigger will attempt to match against an access of any size.
536 * The behavior is only well-defined if $|select|=0$, or if the access
539 * 1: The trigger will only match against 8-bit memory accesses.
541 * 2: The trigger will only match against 16-bit memory accesses or
542 * execution of 16-bit instructions.
544 * 3: The trigger will only match against 32-bit memory accesses or
545 * execution of 32-bit instructions.
547 * 4: The trigger will only match against execution of 48-bit instructions.
549 * 5: The trigger will only match against 64-bit memory accesses or
550 * execution of 64-bit instructions.
552 * 6: The trigger will only match against execution of 80-bit instructions.
554 * 7: The trigger will only match against execution of 96-bit instructions.
556 * 8: The trigger will only match against execution of 112-bit instructions.
558 * 9: The trigger will only match against 128-bit memory accesses or
559 * execution of 128-bit instructions.
561 * An implementation must support the value of 0, but all other values
562 * are optional. It is recommended to support triggers for every
563 * access size the hart supports, as well as for every instruction
564 * size the hart supports.
566 #define CSR_MCONTROL_SIZELO_OFFSET 16
567 #define CSR_MCONTROL_SIZELO_LENGTH 2
568 #define CSR_MCONTROL_SIZELO (0x3ULL << CSR_MCONTROL_SIZELO_OFFSET)
570 * The action to take when the trigger fires. The values are explained
571 * in Table~\ref{tab:action}.
573 #define CSR_MCONTROL_ACTION_OFFSET 12
574 #define CSR_MCONTROL_ACTION_LENGTH 4
575 #define CSR_MCONTROL_ACTION (0xfULL << CSR_MCONTROL_ACTION_OFFSET)
577 * 0: When this trigger matches, the configured action is taken.
579 * 1: While this trigger does not match, it prevents the trigger with
580 * the next index from matching.
582 * A trigger chain starts on the first trigger with $|chain|=1$ after
583 * a trigger with $|chain|=0$, or simply on the first trigger if that
584 * has $|chain|=1$. It ends on the first trigger after that which has
585 * $|chain|=0$. This final trigger is part of the chain. The action
586 * on all but the final trigger is ignored. The action on that final
587 * trigger will be taken if and only if all the triggers in the chain
588 * match at the same time.
590 * Because \FcsrMcontrolChain affects the next trigger, hardware must zero it in
591 * writes to \RcsrMcontrol that set \FcsrTdataOneDmode to 0 if the next trigger has
592 * \FcsrTdataOneDmode of 1.
593 * In addition hardware should ignore writes to \RcsrMcontrol that set
594 * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and
595 * \FcsrMcontrolChain of 1. Debuggers must avoid the latter case by checking
596 * \FcsrMcontrolChain on the previous trigger if they're writing \RcsrMcontrol.
598 * Implementations that wish to limit the maximum length of a trigger
599 * chain (eg. to meet timing requirements) may do so by zeroing
600 * \FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long.
602 #define CSR_MCONTROL_CHAIN_OFFSET 11
603 #define CSR_MCONTROL_CHAIN_LENGTH 1
604 #define CSR_MCONTROL_CHAIN (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET)
606 * 0: Matches when the value equals \RcsrTdataTwo.
608 * 1: Matches when the top M bits of the value match the top M bits of
609 * \RcsrTdataTwo. M is XLEN-1 minus the index of the least-significant
610 * bit containing 0 in \RcsrTdataTwo. Debuggers should only write values
611 * to \RcsrTdataTwo such that M + \FcsrMcontrolMaskmax $\geq$ XLEN, otherwise it's
612 * undefined on what conditions the trigger will fire.
614 * 2: Matches when the value is greater than (unsigned) or equal to
617 * 3: Matches when the value is less than (unsigned) \RcsrTdataTwo.
619 * 4: Matches when the lower half of the value equals the lower half
620 * of \RcsrTdataTwo after the lower half of the value is ANDed with the
621 * upper half of \RcsrTdataTwo.
623 * 5: Matches when the upper half of the value equals the lower half
624 * of \RcsrTdataTwo after the upper half of the value is ANDed with the
625 * upper half of \RcsrTdataTwo.
627 * 8: Matches when \FcsrMcontrolMatch$=0$ would not match.
629 * 9: Matches when \FcsrMcontrolMatch$=1$ would not match.
631 * 12: Matches when \FcsrMcontrolMatch$=4$ would not match.
633 * 13: Matches when \FcsrMcontrolMatch$=5$ would not match.
635 * Other values are reserved for future use.
637 #define CSR_MCONTROL_MATCH_OFFSET 7
638 #define CSR_MCONTROL_MATCH_LENGTH 4
639 #define CSR_MCONTROL_MATCH (0xfULL << CSR_MCONTROL_MATCH_OFFSET)
641 * When set, enable this trigger in M-mode.
643 #define CSR_MCONTROL_M_OFFSET 6
644 #define CSR_MCONTROL_M_LENGTH 1
645 #define CSR_MCONTROL_M (0x1ULL << CSR_MCONTROL_M_OFFSET)
647 * When set, enable this trigger in S-mode.
649 #define CSR_MCONTROL_S_OFFSET 4
650 #define CSR_MCONTROL_S_LENGTH 1
651 #define CSR_MCONTROL_S (0x1ULL << CSR_MCONTROL_S_OFFSET)
653 * When set, enable this trigger in U-mode.
655 #define CSR_MCONTROL_U_OFFSET 3
656 #define CSR_MCONTROL_U_LENGTH 1
657 #define CSR_MCONTROL_U (0x1ULL << CSR_MCONTROL_U_OFFSET)
659 * When set, the trigger fires on the virtual address or opcode of an
660 * instruction that is executed.
662 #define CSR_MCONTROL_EXECUTE_OFFSET 2
663 #define CSR_MCONTROL_EXECUTE_LENGTH 1
664 #define CSR_MCONTROL_EXECUTE (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET)
666 * When set, the trigger fires on the virtual address or data of any
669 #define CSR_MCONTROL_STORE_OFFSET 1
670 #define CSR_MCONTROL_STORE_LENGTH 1
671 #define CSR_MCONTROL_STORE (0x1ULL << CSR_MCONTROL_STORE_OFFSET)
673 * When set, the trigger fires on the virtual address or data of any
676 #define CSR_MCONTROL_LOAD_OFFSET 0
677 #define CSR_MCONTROL_LOAD_LENGTH 1
678 #define CSR_MCONTROL_LOAD (0x1ULL << CSR_MCONTROL_LOAD_OFFSET)
679 #define CSR_ICOUNT 0x7a1
680 #define CSR_ICOUNT_TYPE_OFFSET (XLEN-4)
681 #define CSR_ICOUNT_TYPE_LENGTH 4
682 #define CSR_ICOUNT_TYPE (0xfULL << CSR_ICOUNT_TYPE_OFFSET)
683 #define CSR_ICOUNT_DMODE_OFFSET (XLEN-5)
684 #define CSR_ICOUNT_DMODE_LENGTH 1
685 #define CSR_ICOUNT_DMODE (0x1ULL << CSR_ICOUNT_DMODE_OFFSET)
687 * If this bit is implemented, the hardware sets it when this
688 * trigger matches. The trigger's user can set or clear it at any
689 * time. It is used to determine which
690 * trigger(s) matched. If the bit is not implemented, it is always 0
691 * and writing it has no effect.
693 #define CSR_ICOUNT_HIT_OFFSET 24
694 #define CSR_ICOUNT_HIT_LENGTH 1
695 #define CSR_ICOUNT_HIT (0x1ULL << CSR_ICOUNT_HIT_OFFSET)
697 * When count is decremented to 0, the trigger fires. Instead of
698 * changing \FcsrIcountCount from 1 to 0, it is also acceptable for hardware to
699 * clear \FcsrMcontrolM, \FcsrMcontrolS, and \FcsrMcontrolU. This allows \FcsrIcountCount to be hard-wired
700 * to 1 if this register just exists for single step.
702 #define CSR_ICOUNT_COUNT_OFFSET 10
703 #define CSR_ICOUNT_COUNT_LENGTH 14
704 #define CSR_ICOUNT_COUNT (0x3fffULL << CSR_ICOUNT_COUNT_OFFSET)
706 * When set, every instruction completed in or trap taken from
707 * M-mode decrements \FcsrIcountCount by 1.
709 #define CSR_ICOUNT_M_OFFSET 9
710 #define CSR_ICOUNT_M_LENGTH 1
711 #define CSR_ICOUNT_M (0x1ULL << CSR_ICOUNT_M_OFFSET)
713 * When set, every instruction completed in or trap taken from
714 * S-mode decrements \FcsrIcountCount by 1.
716 #define CSR_ICOUNT_S_OFFSET 7
717 #define CSR_ICOUNT_S_LENGTH 1
718 #define CSR_ICOUNT_S (0x1ULL << CSR_ICOUNT_S_OFFSET)
720 * When set, every instruction completed in or trap taken from
721 * U-mode decrements \FcsrIcountCount by 1.
723 #define CSR_ICOUNT_U_OFFSET 6
724 #define CSR_ICOUNT_U_LENGTH 1
725 #define CSR_ICOUNT_U (0x1ULL << CSR_ICOUNT_U_OFFSET)
727 * The action to take when the trigger fires. The values are explained
728 * in Table~\ref{tab:action}.
730 #define CSR_ICOUNT_ACTION_OFFSET 0
731 #define CSR_ICOUNT_ACTION_LENGTH 6
732 #define CSR_ICOUNT_ACTION (0x3fULL << CSR_ICOUNT_ACTION_OFFSET)
733 #define CSR_ITRIGGER 0x7a1
734 #define CSR_ITRIGGER_TYPE_OFFSET (XLEN-4)
735 #define CSR_ITRIGGER_TYPE_LENGTH 4
736 #define CSR_ITRIGGER_TYPE (0xfULL << CSR_ITRIGGER_TYPE_OFFSET)
737 #define CSR_ITRIGGER_DMODE_OFFSET (XLEN-5)
738 #define CSR_ITRIGGER_DMODE_LENGTH 1
739 #define CSR_ITRIGGER_DMODE (0x1ULL << CSR_ITRIGGER_DMODE_OFFSET)
741 * If this bit is implemented, the hardware sets it when this
742 * trigger matches. The trigger's user can set or clear it at any
743 * time. It is used to determine which
744 * trigger(s) matched. If the bit is not implemented, it is always 0
745 * and writing it has no effect.
747 #define CSR_ITRIGGER_HIT_OFFSET (XLEN-6)
748 #define CSR_ITRIGGER_HIT_LENGTH 1
749 #define CSR_ITRIGGER_HIT (0x1ULL << CSR_ITRIGGER_HIT_OFFSET)
751 * When set, enable this trigger for interrupts that are taken from M
754 #define CSR_ITRIGGER_M_OFFSET 9
755 #define CSR_ITRIGGER_M_LENGTH 1
756 #define CSR_ITRIGGER_M (0x1ULL << CSR_ITRIGGER_M_OFFSET)
758 * When set, enable this trigger for interrupts that are taken from S
761 #define CSR_ITRIGGER_S_OFFSET 7
762 #define CSR_ITRIGGER_S_LENGTH 1
763 #define CSR_ITRIGGER_S (0x1ULL << CSR_ITRIGGER_S_OFFSET)
765 * When set, enable this trigger for interrupts that are taken from U
768 #define CSR_ITRIGGER_U_OFFSET 6
769 #define CSR_ITRIGGER_U_LENGTH 1
770 #define CSR_ITRIGGER_U (0x1ULL << CSR_ITRIGGER_U_OFFSET)
772 * The action to take when the trigger fires. The values are explained
773 * in Table~\ref{tab:action}.
775 #define CSR_ITRIGGER_ACTION_OFFSET 0
776 #define CSR_ITRIGGER_ACTION_LENGTH 6
777 #define CSR_ITRIGGER_ACTION (0x3fULL << CSR_ITRIGGER_ACTION_OFFSET)
778 #define CSR_ETRIGGER 0x7a1
779 #define CSR_ETRIGGER_TYPE_OFFSET (XLEN-4)
780 #define CSR_ETRIGGER_TYPE_LENGTH 4
781 #define CSR_ETRIGGER_TYPE (0xfULL << CSR_ETRIGGER_TYPE_OFFSET)
782 #define CSR_ETRIGGER_DMODE_OFFSET (XLEN-5)
783 #define CSR_ETRIGGER_DMODE_LENGTH 1
784 #define CSR_ETRIGGER_DMODE (0x1ULL << CSR_ETRIGGER_DMODE_OFFSET)
786 * If this bit is implemented, the hardware sets it when this
787 * trigger matches. The trigger's user can set or clear it at any
788 * time. It is used to determine which
789 * trigger(s) matched. If the bit is not implemented, it is always 0
790 * and writing it has no effect.
792 #define CSR_ETRIGGER_HIT_OFFSET (XLEN-6)
793 #define CSR_ETRIGGER_HIT_LENGTH 1
794 #define CSR_ETRIGGER_HIT (0x1ULL << CSR_ETRIGGER_HIT_OFFSET)
796 * When set, non-maskable interrupts cause this
797 * trigger to fire, regardless of the values of \FcsrMcontrolM, \FcsrMcontrolS, and \FcsrMcontrolU.
799 #define CSR_ETRIGGER_NMI_OFFSET 10
800 #define CSR_ETRIGGER_NMI_LENGTH 1
801 #define CSR_ETRIGGER_NMI (0x1ULL << CSR_ETRIGGER_NMI_OFFSET)
803 * When set, enable this trigger for exceptions that are taken from M
806 #define CSR_ETRIGGER_M_OFFSET 9
807 #define CSR_ETRIGGER_M_LENGTH 1
808 #define CSR_ETRIGGER_M (0x1ULL << CSR_ETRIGGER_M_OFFSET)
810 * When set, enable this trigger for exceptions that are taken from S
813 #define CSR_ETRIGGER_S_OFFSET 7
814 #define CSR_ETRIGGER_S_LENGTH 1
815 #define CSR_ETRIGGER_S (0x1ULL << CSR_ETRIGGER_S_OFFSET)
817 * When set, enable this trigger for exceptions that are taken from U
820 #define CSR_ETRIGGER_U_OFFSET 6
821 #define CSR_ETRIGGER_U_LENGTH 1
822 #define CSR_ETRIGGER_U (0x1ULL << CSR_ETRIGGER_U_OFFSET)
824 * The action to take when the trigger fires. The values are explained
825 * in Table~\ref{tab:action}.
827 #define CSR_ETRIGGER_ACTION_OFFSET 0
828 #define CSR_ETRIGGER_ACTION_LENGTH 6
829 #define CSR_ETRIGGER_ACTION (0x3fULL << CSR_ETRIGGER_ACTION_OFFSET)
830 #define CSR_TEXTRA32 0x7a3
832 * Data used together with \FcsrTextraThirtytwoMselect.
834 #define CSR_TEXTRA32_MVALUE_OFFSET 26
835 #define CSR_TEXTRA32_MVALUE_LENGTH 6
836 #define CSR_TEXTRA32_MVALUE (0x3fU << CSR_TEXTRA32_MVALUE_OFFSET)
838 * 0: Ignore \FcsrTextraThirtytwoMvalue.
840 * 1: This trigger will only match if the low bits of
841 * \RcsrMcontext equal \FcsrTextraThirtytwoMvalue.
843 #define CSR_TEXTRA32_MSELECT_OFFSET 25
844 #define CSR_TEXTRA32_MSELECT_LENGTH 1
845 #define CSR_TEXTRA32_MSELECT (0x1U << CSR_TEXTRA32_MSELECT_OFFSET)
847 * Data used together with \FcsrTextraThirtytwoSselect.
849 * This field should be tied to 0 when S-mode is not supported.
851 #define CSR_TEXTRA32_SVALUE_OFFSET 2
852 #define CSR_TEXTRA32_SVALUE_LENGTH 16
853 #define CSR_TEXTRA32_SVALUE (0xffffU << CSR_TEXTRA32_SVALUE_OFFSET)
855 * 0: Ignore \FcsrTextraThirtytwoSvalue.
857 * 1: This trigger will only match if the low bits of
858 * \RcsrScontext equal \FcsrTextraThirtytwoSvalue.
860 * 2: This trigger will only match if \Fasid in \Rsatp
861 * equals the lower ASIDMAX (defined in the Privileged Spec) bits of
862 * \FcsrTextraThirtytwoSvalue.
864 * This field should be tied to 0 when S-mode is not supported.
866 #define CSR_TEXTRA32_SSELECT_OFFSET 0
867 #define CSR_TEXTRA32_SSELECT_LENGTH 2
868 #define CSR_TEXTRA32_SSELECT (0x3U << CSR_TEXTRA32_SSELECT_OFFSET)
869 #define CSR_TEXTRA64 0x7a3
870 #define CSR_TEXTRA64_MVALUE_OFFSET 51
871 #define CSR_TEXTRA64_MVALUE_LENGTH 13
872 #define CSR_TEXTRA64_MVALUE (0x1fffULL << CSR_TEXTRA64_MVALUE_OFFSET)
873 #define CSR_TEXTRA64_MSELECT_OFFSET 50
874 #define CSR_TEXTRA64_MSELECT_LENGTH 1
875 #define CSR_TEXTRA64_MSELECT (0x1ULL << CSR_TEXTRA64_MSELECT_OFFSET)
876 #define CSR_TEXTRA64_SVALUE_OFFSET 2
877 #define CSR_TEXTRA64_SVALUE_LENGTH 34
878 #define CSR_TEXTRA64_SVALUE (0x3ffffffffULL << CSR_TEXTRA64_SVALUE_OFFSET)
879 #define CSR_TEXTRA64_SSELECT_OFFSET 0
880 #define CSR_TEXTRA64_SSELECT_LENGTH 2
881 #define CSR_TEXTRA64_SSELECT (0x3ULL << CSR_TEXTRA64_SSELECT_OFFSET)
882 #define DM_DMSTATUS 0x11
884 * If 1, then there is an implicit {\tt ebreak} instruction at the
885 * non-existent word immediately after the Program Buffer. This saves
886 * the debugger from having to write the {\tt ebreak} itself, and
887 * allows the Program Buffer to be one word smaller.
889 * This must be 1 when \FdmAbstractcsProgbufsize is 1.
891 #define DM_DMSTATUS_IMPEBREAK_OFFSET 22
892 #define DM_DMSTATUS_IMPEBREAK_LENGTH 1
893 #define DM_DMSTATUS_IMPEBREAK (0x1U << DM_DMSTATUS_IMPEBREAK_OFFSET)
895 * This field is 1 when all currently selected harts have been reset
896 * and reset has not been acknowledged for any of them.
898 #define DM_DMSTATUS_ALLHAVERESET_OFFSET 19
899 #define DM_DMSTATUS_ALLHAVERESET_LENGTH 1
900 #define DM_DMSTATUS_ALLHAVERESET (0x1U << DM_DMSTATUS_ALLHAVERESET_OFFSET)
902 * This field is 1 when at least one currently selected hart has been
903 * reset and reset has not been acknowledged for that hart.
905 #define DM_DMSTATUS_ANYHAVERESET_OFFSET 18
906 #define DM_DMSTATUS_ANYHAVERESET_LENGTH 1
907 #define DM_DMSTATUS_ANYHAVERESET (0x1U << DM_DMSTATUS_ANYHAVERESET_OFFSET)
909 * This field is 1 when all currently selected harts have acknowledged
910 * their last resume request.
912 #define DM_DMSTATUS_ALLRESUMEACK_OFFSET 17
913 #define DM_DMSTATUS_ALLRESUMEACK_LENGTH 1
914 #define DM_DMSTATUS_ALLRESUMEACK (0x1U << DM_DMSTATUS_ALLRESUMEACK_OFFSET)
916 * This field is 1 when any currently selected hart has acknowledged
917 * its last resume request.
919 #define DM_DMSTATUS_ANYRESUMEACK_OFFSET 16
920 #define DM_DMSTATUS_ANYRESUMEACK_LENGTH 1
921 #define DM_DMSTATUS_ANYRESUMEACK (0x1U << DM_DMSTATUS_ANYRESUMEACK_OFFSET)
923 * This field is 1 when all currently selected harts do not exist in
926 #define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 15
927 #define DM_DMSTATUS_ALLNONEXISTENT_LENGTH 1
928 #define DM_DMSTATUS_ALLNONEXISTENT (0x1U << DM_DMSTATUS_ALLNONEXISTENT_OFFSET)
930 * This field is 1 when any currently selected hart does not exist in
933 #define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 14
934 #define DM_DMSTATUS_ANYNONEXISTENT_LENGTH 1
935 #define DM_DMSTATUS_ANYNONEXISTENT (0x1U << DM_DMSTATUS_ANYNONEXISTENT_OFFSET)
937 * This field is 1 when all currently selected harts are unavailable.
939 #define DM_DMSTATUS_ALLUNAVAIL_OFFSET 13
940 #define DM_DMSTATUS_ALLUNAVAIL_LENGTH 1
941 #define DM_DMSTATUS_ALLUNAVAIL (0x1U << DM_DMSTATUS_ALLUNAVAIL_OFFSET)
943 * This field is 1 when any currently selected hart is unavailable.
945 #define DM_DMSTATUS_ANYUNAVAIL_OFFSET 12
946 #define DM_DMSTATUS_ANYUNAVAIL_LENGTH 1
947 #define DM_DMSTATUS_ANYUNAVAIL (0x1U << DM_DMSTATUS_ANYUNAVAIL_OFFSET)
949 * This field is 1 when all currently selected harts are running.
951 #define DM_DMSTATUS_ALLRUNNING_OFFSET 11
952 #define DM_DMSTATUS_ALLRUNNING_LENGTH 1
953 #define DM_DMSTATUS_ALLRUNNING (0x1U << DM_DMSTATUS_ALLRUNNING_OFFSET)
955 * This field is 1 when any currently selected hart is running.
957 #define DM_DMSTATUS_ANYRUNNING_OFFSET 10
958 #define DM_DMSTATUS_ANYRUNNING_LENGTH 1
959 #define DM_DMSTATUS_ANYRUNNING (0x1U << DM_DMSTATUS_ANYRUNNING_OFFSET)
961 * This field is 1 when all currently selected harts are halted.
963 #define DM_DMSTATUS_ALLHALTED_OFFSET 9
964 #define DM_DMSTATUS_ALLHALTED_LENGTH 1
965 #define DM_DMSTATUS_ALLHALTED (0x1U << DM_DMSTATUS_ALLHALTED_OFFSET)
967 * This field is 1 when any currently selected hart is halted.
969 #define DM_DMSTATUS_ANYHALTED_OFFSET 8
970 #define DM_DMSTATUS_ANYHALTED_LENGTH 1
971 #define DM_DMSTATUS_ANYHALTED (0x1U << DM_DMSTATUS_ANYHALTED_OFFSET)
973 * 0: Authentication is required before using the DM.
975 * 1: The authentication check has passed.
977 * On components that don't implement authentication, this bit must be
980 #define DM_DMSTATUS_AUTHENTICATED_OFFSET 7
981 #define DM_DMSTATUS_AUTHENTICATED_LENGTH 1
982 #define DM_DMSTATUS_AUTHENTICATED (0x1U << DM_DMSTATUS_AUTHENTICATED_OFFSET)
984 * 0: The authentication module is ready to process the next
985 * read/write to \RdmAuthdata.
987 * 1: The authentication module is busy. Accessing \RdmAuthdata results
988 * in unspecified behavior.
990 * \FdmDmstatusAuthbusy only becomes set in immediate response to an access to
993 #define DM_DMSTATUS_AUTHBUSY_OFFSET 6
994 #define DM_DMSTATUS_AUTHBUSY_LENGTH 1
995 #define DM_DMSTATUS_AUTHBUSY (0x1U << DM_DMSTATUS_AUTHBUSY_OFFSET)
997 * 1 if this Debug Module supports halt-on-reset functionality
998 * controllable by the \FdmDmcontrolSetresethaltreq and \FdmDmcontrolClrresethaltreq bits.
1001 #define DM_DMSTATUS_HASRESETHALTREQ_OFFSET 5
1002 #define DM_DMSTATUS_HASRESETHALTREQ_LENGTH 1
1003 #define DM_DMSTATUS_HASRESETHALTREQ (0x1U << DM_DMSTATUS_HASRESETHALTREQ_OFFSET)
1005 * 0: \RdmConfstrptrZero--\RdmConfstrptrThree hold information which
1006 * is not relevant to the configuration string.
1008 * 1: \RdmConfstrptrZero--\RdmConfstrptrThree hold the address of the
1009 * configuration string.
1011 #define DM_DMSTATUS_CONFSTRPTRVALID_OFFSET 4
1012 #define DM_DMSTATUS_CONFSTRPTRVALID_LENGTH 1
1013 #define DM_DMSTATUS_CONFSTRPTRVALID (0x1U << DM_DMSTATUS_CONFSTRPTRVALID_OFFSET)
1015 * 0: There is no Debug Module present.
1017 * 1: There is a Debug Module and it conforms to version 0.11 of this
1020 * 2: There is a Debug Module and it conforms to version 0.13 of this
1023 * 3: There is a Debug Module and it conforms to version 0.14 of this
1026 * 15: There is a Debug Module but it does not conform to any
1027 * available version of this spec.
1029 #define DM_DMSTATUS_VERSION_OFFSET 0
1030 #define DM_DMSTATUS_VERSION_LENGTH 4
1031 #define DM_DMSTATUS_VERSION (0xfU << DM_DMSTATUS_VERSION_OFFSET)
1032 #define DM_DMCONTROL 0x10
1034 * Writing 0 clears the halt request bit for all currently selected
1035 * harts. This may cancel outstanding halt requests for those harts.
1037 * Writing 1 sets the halt request bit for all currently selected
1038 * harts. Running harts will halt whenever their halt request bit is
1041 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1043 #define DM_DMCONTROL_HALTREQ_OFFSET 31
1044 #define DM_DMCONTROL_HALTREQ_LENGTH 1
1045 #define DM_DMCONTROL_HALTREQ (0x1U << DM_DMCONTROL_HALTREQ_OFFSET)
1047 * Writing 1 causes the currently selected harts to resume once, if
1048 * they are halted when the write occurs. It also clears the resume
1049 * ack bit for those harts.
1051 * \FdmDmcontrolResumereq is ignored if \FdmDmcontrolHaltreq is set.
1053 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1055 #define DM_DMCONTROL_RESUMEREQ_OFFSET 30
1056 #define DM_DMCONTROL_RESUMEREQ_LENGTH 1
1057 #define DM_DMCONTROL_RESUMEREQ (0x1U << DM_DMCONTROL_RESUMEREQ_OFFSET)
1059 * This optional field writes the reset bit for all the currently
1060 * selected harts. To perform a reset the debugger writes 1, and then
1061 * writes 0 to deassert the reset signal.
1063 * While this bit is 1, the debugger must not change which harts are
1066 * If this feature is not implemented, the bit always stays 0, so
1067 * after writing 1 the debugger can read the register back to see if
1068 * the feature is supported.
1070 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1072 #define DM_DMCONTROL_HARTRESET_OFFSET 29
1073 #define DM_DMCONTROL_HARTRESET_LENGTH 1
1074 #define DM_DMCONTROL_HARTRESET (0x1U << DM_DMCONTROL_HARTRESET_OFFSET)
1078 * 1: Clears {\tt havereset} for any selected harts.
1080 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1082 #define DM_DMCONTROL_ACKHAVERESET_OFFSET 28
1083 #define DM_DMCONTROL_ACKHAVERESET_LENGTH 1
1084 #define DM_DMCONTROL_ACKHAVERESET (0x1U << DM_DMCONTROL_ACKHAVERESET_OFFSET)
1086 * Selects the definition of currently selected harts.
1088 * 0: There is a single currently selected hart, that is selected by \Fhartsel.
1090 * 1: There may be multiple currently selected harts -- the hart
1091 * selected by \Fhartsel, plus those selected by the hart array mask
1094 * An implementation which does not implement the hart array mask register
1095 * must tie this field to 0. A debugger which wishes to use the hart array
1096 * mask register feature should set this bit and read back to see if the functionality
1099 #define DM_DMCONTROL_HASEL_OFFSET 26
1100 #define DM_DMCONTROL_HASEL_LENGTH 1
1101 #define DM_DMCONTROL_HASEL (0x1U << DM_DMCONTROL_HASEL_OFFSET)
1103 * The low 10 bits of \Fhartsel: the DM-specific index of the hart to
1104 * select. This hart is always part of the currently selected harts.
1106 #define DM_DMCONTROL_HARTSELLO_OFFSET 16
1107 #define DM_DMCONTROL_HARTSELLO_LENGTH 10
1108 #define DM_DMCONTROL_HARTSELLO (0x3ffU << DM_DMCONTROL_HARTSELLO_OFFSET)
1110 * The high 10 bits of \Fhartsel: the DM-specific index of the hart to
1111 * select. This hart is always part of the currently selected harts.
1113 #define DM_DMCONTROL_HARTSELHI_OFFSET 6
1114 #define DM_DMCONTROL_HARTSELHI_LENGTH 10
1115 #define DM_DMCONTROL_HARTSELHI (0x3ffU << DM_DMCONTROL_HARTSELHI_OFFSET)
1117 * This optional field writes the halt-on-reset request bit for all
1118 * currently selected harts, unless \FdmDmcontrolClrresethaltreq is
1119 * simultaneously set to 1.
1120 * When set to 1, each selected hart will halt upon the next deassertion
1121 * of its reset. The halt-on-reset request bit is not automatically
1122 * cleared. The debugger must write to \FdmDmcontrolClrresethaltreq to clear it.
1124 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1126 * If \FdmDmstatusHasresethaltreq is 0, this field is not implemented.
1128 #define DM_DMCONTROL_SETRESETHALTREQ_OFFSET 3
1129 #define DM_DMCONTROL_SETRESETHALTREQ_LENGTH 1
1130 #define DM_DMCONTROL_SETRESETHALTREQ (0x1U << DM_DMCONTROL_SETRESETHALTREQ_OFFSET)
1132 * This optional field clears the halt-on-reset request bit for all
1133 * currently selected harts.
1135 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1137 #define DM_DMCONTROL_CLRRESETHALTREQ_OFFSET 2
1138 #define DM_DMCONTROL_CLRRESETHALTREQ_LENGTH 1
1139 #define DM_DMCONTROL_CLRRESETHALTREQ (0x1U << DM_DMCONTROL_CLRRESETHALTREQ_OFFSET)
1141 * This bit controls the reset signal from the DM to the rest of the
1142 * system. The signal should reset every part of the system, including
1143 * every hart, except for the DM and any logic required to access the
1145 * To perform a system reset the debugger writes 1,
1147 * to deassert the reset.
1149 #define DM_DMCONTROL_NDMRESET_OFFSET 1
1150 #define DM_DMCONTROL_NDMRESET_LENGTH 1
1151 #define DM_DMCONTROL_NDMRESET (0x1U << DM_DMCONTROL_NDMRESET_OFFSET)
1153 * This bit serves as a reset signal for the Debug Module itself.
1155 * 0: The module's state, including authentication mechanism,
1156 * takes its reset values (the \FdmDmcontrolDmactive bit is the only bit which can
1157 * be written to something other than its reset value). Any accesses
1158 * to the module may fail. Specifically, \FdmDmstatusVersion may not return
1161 * 1: The module functions normally. After writing 1, the debugger should
1162 * poll \RdmDmcontrol until \FdmDmcontrolDmactive is high. Hardware may
1163 * take an arbitrarily long time to initialize and will indicate completion
1164 * by setting dmactive to 1.
1166 * No other mechanism should exist that may result in resetting the
1167 * Debug Module after power up.
1169 * A debugger may pulse this bit low to get the Debug Module into a
1172 * Implementations may pay attention to this bit to further aid
1173 * debugging, for example by preventing the Debug Module from being
1174 * power gated while debugging is active.
1176 #define DM_DMCONTROL_DMACTIVE_OFFSET 0
1177 #define DM_DMCONTROL_DMACTIVE_LENGTH 1
1178 #define DM_DMCONTROL_DMACTIVE (0x1U << DM_DMCONTROL_DMACTIVE_OFFSET)
1179 #define DM_HARTINFO 0x12
1181 * Number of {\tt dscratch} registers available for the debugger
1182 * to use during program buffer execution, starting from \RcsrDscratchZero.
1183 * The debugger can make no assumptions about the contents of these
1184 * registers between commands.
1186 #define DM_HARTINFO_NSCRATCH_OFFSET 20
1187 #define DM_HARTINFO_NSCRATCH_LENGTH 4
1188 #define DM_HARTINFO_NSCRATCH (0xfU << DM_HARTINFO_NSCRATCH_OFFSET)
1190 * 0: The {\tt data} registers are shadowed in the hart by CSRs.
1191 * Each CSR is DXLEN bits in size, and corresponds
1192 * to a single argument, per Table~\ref{tab:datareg}.
1194 * 1: The {\tt data} registers are shadowed in the hart's memory map.
1195 * Each register takes up 4 bytes in the memory map.
1197 #define DM_HARTINFO_DATAACCESS_OFFSET 16
1198 #define DM_HARTINFO_DATAACCESS_LENGTH 1
1199 #define DM_HARTINFO_DATAACCESS (0x1U << DM_HARTINFO_DATAACCESS_OFFSET)
1201 * If \FdmHartinfoDataaccess is 0: Number of CSRs dedicated to
1202 * shadowing the {\tt data} registers.
1204 * If \FdmHartinfoDataaccess is 1: Number of 32-bit words in the memory map
1205 * dedicated to shadowing the {\tt data} registers.
1207 * Since there are at most 12 {\tt data} registers, the value in this
1208 * register must be 12 or smaller.
1210 #define DM_HARTINFO_DATASIZE_OFFSET 12
1211 #define DM_HARTINFO_DATASIZE_LENGTH 4
1212 #define DM_HARTINFO_DATASIZE (0xfU << DM_HARTINFO_DATASIZE_OFFSET)
1214 * If \FdmHartinfoDataaccess is 0: The number of the first CSR dedicated to
1215 * shadowing the {\tt data} registers.
1217 * If \FdmHartinfoDataaccess is 1: Address of RAM where the data
1218 * registers are shadowed. This address is sign extended giving a
1219 * range of -2048 to 2047, easily addressed with a load or store using
1220 * \Xzero as the address register.
1222 #define DM_HARTINFO_DATAADDR_OFFSET 0
1223 #define DM_HARTINFO_DATAADDR_LENGTH 12
1224 #define DM_HARTINFO_DATAADDR (0xfffU << DM_HARTINFO_DATAADDR_OFFSET)
1225 #define DM_HAWINDOWSEL 0x14
1227 * The high bits of this field may be tied to 0, depending on how large
1228 * the array mask register is. E.g.\ on a system with 48 harts only bit 0
1229 * of this field may actually be writable.
1231 #define DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0
1232 #define DM_HAWINDOWSEL_HAWINDOWSEL_LENGTH 15
1233 #define DM_HAWINDOWSEL_HAWINDOWSEL (0x7fffU << DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET)
1234 #define DM_HAWINDOW 0x15
1235 #define DM_HAWINDOW_MASKDATA_OFFSET 0
1236 #define DM_HAWINDOW_MASKDATA_LENGTH 32
1237 #define DM_HAWINDOW_MASKDATA (0xffffffffU << DM_HAWINDOW_MASKDATA_OFFSET)
1238 #define DM_ABSTRACTCS 0x16
1240 * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
1242 #define DM_ABSTRACTCS_PROGBUFSIZE_OFFSET 24
1243 #define DM_ABSTRACTCS_PROGBUFSIZE_LENGTH 5
1244 #define DM_ABSTRACTCS_PROGBUFSIZE (0x1fU << DM_ABSTRACTCS_PROGBUFSIZE_OFFSET)
1246 * 1: An abstract command is currently being executed.
1248 * This bit is set as soon as \RdmCommand is written, and is
1249 * not cleared until that command has completed.
1251 #define DM_ABSTRACTCS_BUSY_OFFSET 12
1252 #define DM_ABSTRACTCS_BUSY_LENGTH 1
1253 #define DM_ABSTRACTCS_BUSY (0x1U << DM_ABSTRACTCS_BUSY_OFFSET)
1255 * This optional bit controls whether program buffer and abstract
1256 * memory accesses are performed with the exact and full set of
1257 * permission checks that apply based on the current architectural
1258 * state of the hart performing the access, or with a relaxed set of
1259 * permission checks (e.g. PMP restrictions are ignored). The
1260 * details of the latter are implementation-specific. When set to 0,
1261 * full permissions apply; when set to 1, relaxed permissions apply.
1263 #define DM_ABSTRACTCS_RELAXEDPRIV_OFFSET 11
1264 #define DM_ABSTRACTCS_RELAXEDPRIV_LENGTH 1
1265 #define DM_ABSTRACTCS_RELAXEDPRIV (0x1U << DM_ABSTRACTCS_RELAXEDPRIV_OFFSET)
1267 * Gets set if an abstract command fails. The bits in this field remain set until
1268 * they are cleared by writing 1 to them. No abstract command is
1269 * started until the value is reset to 0.
1271 * This field only contains a valid value if \FdmAbstractcsBusy is 0.
1273 * 0 (none): No error.
1275 * 1 (busy): An abstract command was executing while \RdmCommand,
1276 * \RdmAbstractcs, or \RdmAbstractauto was written, or when one
1277 * of the {\tt data} or {\tt progbuf} registers was read or written.
1278 * This status is only written if \FdmAbstractcsCmderr contains 0.
1280 * 2 (not supported): The command in \RdmCommand is not supported. It
1281 * may be supported with different options set, but it will not be
1282 * supported at a later time when the hart or system state are
1285 * 3 (exception): An exception occurred while executing the command
1286 * (e.g.\ while executing the Program Buffer).
1288 * 4 (halt/resume): The abstract command couldn't execute because the
1289 * hart wasn't in the required state (running/halted), or unavailable.
1291 * 5 (bus): The abstract command failed due to a bus error (e.g.\
1292 * alignment, access size, or timeout).
1294 * 6: Reserved for future use.
1296 * 7 (other): The command failed for another reason.
1298 #define DM_ABSTRACTCS_CMDERR_OFFSET 8
1299 #define DM_ABSTRACTCS_CMDERR_LENGTH 3
1300 #define DM_ABSTRACTCS_CMDERR (0x7U << DM_ABSTRACTCS_CMDERR_OFFSET)
1302 * Number of {\tt data} registers that are implemented as part of the
1303 * abstract command interface. Valid sizes are 1 -- 12.
1305 #define DM_ABSTRACTCS_DATACOUNT_OFFSET 0
1306 #define DM_ABSTRACTCS_DATACOUNT_LENGTH 4
1307 #define DM_ABSTRACTCS_DATACOUNT (0xfU << DM_ABSTRACTCS_DATACOUNT_OFFSET)
1308 #define DM_COMMAND 0x17
1310 * The type determines the overall functionality of this
1313 #define DM_COMMAND_CMDTYPE_OFFSET 24
1314 #define DM_COMMAND_CMDTYPE_LENGTH 8
1315 #define DM_COMMAND_CMDTYPE (0xffU << DM_COMMAND_CMDTYPE_OFFSET)
1317 * This field is interpreted in a command-specific manner,
1318 * described for each abstract command.
1320 #define DM_COMMAND_CONTROL_OFFSET 0
1321 #define DM_COMMAND_CONTROL_LENGTH 24
1322 #define DM_COMMAND_CONTROL (0xffffffU << DM_COMMAND_CONTROL_OFFSET)
1323 #define DM_ABSTRACTAUTO 0x18
1325 * When a bit in this field is 1, read or write accesses to the
1326 * corresponding {\tt progbuf} word cause the command in \RdmCommand to
1327 * be executed again.
1329 #define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16
1330 #define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16
1331 #define DM_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffffU << DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET)
1333 * When a bit in this field is 1, read or write accesses to the
1334 * corresponding {\tt data} word cause the command in \RdmCommand to be
1337 #define DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0
1338 #define DM_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12
1339 #define DM_ABSTRACTAUTO_AUTOEXECDATA (0xfffU << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET)
1340 #define DM_CONFSTRPTR0 0x19
1341 #define DM_CONFSTRPTR0_ADDR_OFFSET 0
1342 #define DM_CONFSTRPTR0_ADDR_LENGTH 32
1343 #define DM_CONFSTRPTR0_ADDR (0xffffffffU << DM_CONFSTRPTR0_ADDR_OFFSET)
1344 #define DM_CONFSTRPTR1 0x1a
1345 #define DM_CONFSTRPTR1_ADDR_OFFSET 0
1346 #define DM_CONFSTRPTR1_ADDR_LENGTH 32
1347 #define DM_CONFSTRPTR1_ADDR (0xffffffffU << DM_CONFSTRPTR1_ADDR_OFFSET)
1348 #define DM_CONFSTRPTR2 0x1b
1349 #define DM_CONFSTRPTR2_ADDR_OFFSET 0
1350 #define DM_CONFSTRPTR2_ADDR_LENGTH 32
1351 #define DM_CONFSTRPTR2_ADDR (0xffffffffU << DM_CONFSTRPTR2_ADDR_OFFSET)
1352 #define DM_CONFSTRPTR3 0x1c
1353 #define DM_CONFSTRPTR3_ADDR_OFFSET 0
1354 #define DM_CONFSTRPTR3_ADDR_LENGTH 32
1355 #define DM_CONFSTRPTR3_ADDR (0xffffffffU << DM_CONFSTRPTR3_ADDR_OFFSET)
1356 #define DM_NEXTDM 0x1d
1357 #define DM_NEXTDM_ADDR_OFFSET 0
1358 #define DM_NEXTDM_ADDR_LENGTH 32
1359 #define DM_NEXTDM_ADDR (0xffffffffU << DM_NEXTDM_ADDR_OFFSET)
1360 #define DM_DATA0 0x04
1361 #define DM_DATA0_DATA_OFFSET 0
1362 #define DM_DATA0_DATA_LENGTH 32
1363 #define DM_DATA0_DATA (0xffffffffU << DM_DATA0_DATA_OFFSET)
1364 #define DM_DATA11 0x0f
1365 #define DM_PROGBUF0 0x20
1366 #define DM_PROGBUF0_DATA_OFFSET 0
1367 #define DM_PROGBUF0_DATA_LENGTH 32
1368 #define DM_PROGBUF0_DATA (0xffffffffU << DM_PROGBUF0_DATA_OFFSET)
1369 #define DM_PROGBUF15 0x2f
1370 #define DM_AUTHDATA 0x30
1371 #define DM_AUTHDATA_DATA_OFFSET 0
1372 #define DM_AUTHDATA_DATA_LENGTH 32
1373 #define DM_AUTHDATA_DATA (0xffffffffU << DM_AUTHDATA_DATA_OFFSET)
1374 #define DM_DMCS2 0x32
1376 * 0: The remaining fields in this register configure halt groups.
1378 * 1: The remaining fields in this register configure resume groups.
1380 #define DM_DMCS2_GROUPTYPE_OFFSET 11
1381 #define DM_DMCS2_GROUPTYPE_LENGTH 1
1382 #define DM_DMCS2_GROUPTYPE (0x1U << DM_DMCS2_GROUPTYPE_OFFSET)
1384 * This field contains the currently selected external trigger.
1386 * If a non-existent trigger value is written here, the hardware will
1387 * change it to a valid one or 0 if no external triggers exist.
1389 #define DM_DMCS2_EXTTRIGGER_OFFSET 7
1390 #define DM_DMCS2_EXTTRIGGER_LENGTH 4
1391 #define DM_DMCS2_EXTTRIGGER (0xfU << DM_DMCS2_EXTTRIGGER_OFFSET)
1393 * When \FdmDmcsTwoHgselect is 0, contains the group of the hart
1394 * specified by \Fhartsel.
1396 * When \FdmDmcsTwoHgselect is 1, contains the group of the external
1397 * trigger selected by \FdmDmcsTwoExttrigger.
1399 * Writes only have an effect if \FdmDmcsTwoHgwrite is also written 1.
1401 * Group numbers are contiguous starting at 0, with the highest number
1402 * being implementation-dependent, and possibly different between
1403 * different group types. Debuggers should read back this field after
1404 * writing to confirm they are using a hart group that is supported.
1406 * If groups aren't implemented, then this entire field is 0.
1408 #define DM_DMCS2_GROUP_OFFSET 2
1409 #define DM_DMCS2_GROUP_LENGTH 5
1410 #define DM_DMCS2_GROUP (0x1fU << DM_DMCS2_GROUP_OFFSET)
1412 * When \FdmDmcsTwoHgselect is 0, writing 1 changes the group of all
1413 * selected harts to the value written to \FdmDmcsTwoGroup.
1415 * When 1 is written and \FdmDmcsTwoHgselect is 0, for every selected
1416 * hart the DM will change its group to the value written to \FdmDmcsTwoGroup,
1417 * if the hardware supports that group for that hart.
1419 * When 1 is written and \FdmDmcsTwoHgselect is 1, the DM will change
1420 * the group of the external trigger selected by \FdmDmcsTwoExttrigger
1421 * to the value written to \FdmDmcsTwoGroup, if the hardware supports
1422 * that group for that trigger.
1424 * Writing 0 has no effect.
1426 #define DM_DMCS2_HGWRITE_OFFSET 1
1427 #define DM_DMCS2_HGWRITE_LENGTH 1
1428 #define DM_DMCS2_HGWRITE (0x1U << DM_DMCS2_HGWRITE_OFFSET)
1430 * 0: Operate on harts.
1432 * 1: Operate on external triggers.
1434 * If there are no external triggers, this field must be tied to 0.
1436 #define DM_DMCS2_HGSELECT_OFFSET 0
1437 #define DM_DMCS2_HGSELECT_LENGTH 1
1438 #define DM_DMCS2_HGSELECT (0x1U << DM_DMCS2_HGSELECT_OFFSET)
1439 #define DM_HALTSUM0 0x40
1440 #define DM_HALTSUM0_HALTSUM0_OFFSET 0
1441 #define DM_HALTSUM0_HALTSUM0_LENGTH 32
1442 #define DM_HALTSUM0_HALTSUM0 (0xffffffffU << DM_HALTSUM0_HALTSUM0_OFFSET)
1443 #define DM_HALTSUM1 0x13
1444 #define DM_HALTSUM1_HALTSUM1_OFFSET 0
1445 #define DM_HALTSUM1_HALTSUM1_LENGTH 32
1446 #define DM_HALTSUM1_HALTSUM1 (0xffffffffU << DM_HALTSUM1_HALTSUM1_OFFSET)
1447 #define DM_HALTSUM2 0x34
1448 #define DM_HALTSUM2_HALTSUM2_OFFSET 0
1449 #define DM_HALTSUM2_HALTSUM2_LENGTH 32
1450 #define DM_HALTSUM2_HALTSUM2 (0xffffffffU << DM_HALTSUM2_HALTSUM2_OFFSET)
1451 #define DM_HALTSUM3 0x35
1452 #define DM_HALTSUM3_HALTSUM3_OFFSET 0
1453 #define DM_HALTSUM3_HALTSUM3_LENGTH 32
1454 #define DM_HALTSUM3_HALTSUM3 (0xffffffffU << DM_HALTSUM3_HALTSUM3_OFFSET)
1455 #define DM_SBCS 0x38
1457 * 0: The System Bus interface conforms to mainline drafts of this
1458 * spec older than 1 January, 2018.
1460 * 1: The System Bus interface conforms to this version of the spec.
1462 * Other values are reserved for future versions.
1464 #define DM_SBCS_SBVERSION_OFFSET 29
1465 #define DM_SBCS_SBVERSION_LENGTH 3
1466 #define DM_SBCS_SBVERSION (0x7U << DM_SBCS_SBVERSION_OFFSET)
1468 * Set when the debugger attempts to read data while a read is in
1469 * progress, or when the debugger initiates a new access while one is
1470 * already in progress (while \FdmSbcsSbbusy is set). It remains set until
1471 * it's explicitly cleared by the debugger.
1473 * While this field is set, no more system bus accesses can be
1474 * initiated by the Debug Module.
1476 #define DM_SBCS_SBBUSYERROR_OFFSET 22
1477 #define DM_SBCS_SBBUSYERROR_LENGTH 1
1478 #define DM_SBCS_SBBUSYERROR (0x1U << DM_SBCS_SBBUSYERROR_OFFSET)
1480 * When 1, indicates the system bus master is busy. (Whether the
1481 * system bus itself is busy is related, but not the same thing.) This
1482 * bit goes high immediately when a read or write is requested for any
1483 * reason, and does not go low until the access is fully completed.
1485 * Writes to \RdmSbcs while \FdmSbcsSbbusy is high result in undefined
1486 * behavior. A debugger must not write to \RdmSbcs until it reads
1487 * \FdmSbcsSbbusy as 0.
1489 #define DM_SBCS_SBBUSY_OFFSET 21
1490 #define DM_SBCS_SBBUSY_LENGTH 1
1491 #define DM_SBCS_SBBUSY (0x1U << DM_SBCS_SBBUSY_OFFSET)
1493 * When 1, every write to \RdmSbaddressZero automatically triggers a
1494 * system bus read at the new address.
1496 #define DM_SBCS_SBREADONADDR_OFFSET 20
1497 #define DM_SBCS_SBREADONADDR_LENGTH 1
1498 #define DM_SBCS_SBREADONADDR (0x1U << DM_SBCS_SBREADONADDR_OFFSET)
1500 * Select the access size to use for system bus accesses.
1512 * If \FdmSbcsSbaccess has an unsupported value when the DM starts a bus
1513 * access, the access is not performed and \FdmSbcsSberror is set to 4.
1515 #define DM_SBCS_SBACCESS_OFFSET 17
1516 #define DM_SBCS_SBACCESS_LENGTH 3
1517 #define DM_SBCS_SBACCESS (0x7U << DM_SBCS_SBACCESS_OFFSET)
1519 * When 1, {\tt sbaddress} is incremented by the access size (in
1520 * bytes) selected in \FdmSbcsSbaccess after every system bus access.
1522 #define DM_SBCS_SBAUTOINCREMENT_OFFSET 16
1523 #define DM_SBCS_SBAUTOINCREMENT_LENGTH 1
1524 #define DM_SBCS_SBAUTOINCREMENT (0x1U << DM_SBCS_SBAUTOINCREMENT_OFFSET)
1526 * When 1, every read from \RdmSbdataZero automatically triggers a
1527 * system bus read at the (possibly auto-incremented) address.
1529 #define DM_SBCS_SBREADONDATA_OFFSET 15
1530 #define DM_SBCS_SBREADONDATA_LENGTH 1
1531 #define DM_SBCS_SBREADONDATA (0x1U << DM_SBCS_SBREADONDATA_OFFSET)
1533 * When the Debug Module's system bus
1534 * master encounters an error, this field gets set. The bits in this
1535 * field remain set until they are cleared by writing 1 to them.
1536 * While this field is non-zero, no more system bus accesses can be
1537 * initiated by the Debug Module.
1539 * An implementation may report ``Other'' (7) for any error condition.
1541 * 0: There was no bus error.
1543 * 1: There was a timeout.
1545 * 2: A bad address was accessed.
1547 * 3: There was an alignment error.
1549 * 4: An access of unsupported size was requested.
1553 #define DM_SBCS_SBERROR_OFFSET 12
1554 #define DM_SBCS_SBERROR_LENGTH 3
1555 #define DM_SBCS_SBERROR (0x7U << DM_SBCS_SBERROR_OFFSET)
1557 * Width of system bus addresses in bits. (0 indicates there is no bus
1560 #define DM_SBCS_SBASIZE_OFFSET 5
1561 #define DM_SBCS_SBASIZE_LENGTH 7
1562 #define DM_SBCS_SBASIZE (0x7fU << DM_SBCS_SBASIZE_OFFSET)
1564 * 1 when 128-bit system bus accesses are supported.
1566 #define DM_SBCS_SBACCESS128_OFFSET 4
1567 #define DM_SBCS_SBACCESS128_LENGTH 1
1568 #define DM_SBCS_SBACCESS128 (0x1U << DM_SBCS_SBACCESS128_OFFSET)
1570 * 1 when 64-bit system bus accesses are supported.
1572 #define DM_SBCS_SBACCESS64_OFFSET 3
1573 #define DM_SBCS_SBACCESS64_LENGTH 1
1574 #define DM_SBCS_SBACCESS64 (0x1U << DM_SBCS_SBACCESS64_OFFSET)
1576 * 1 when 32-bit system bus accesses are supported.
1578 #define DM_SBCS_SBACCESS32_OFFSET 2
1579 #define DM_SBCS_SBACCESS32_LENGTH 1
1580 #define DM_SBCS_SBACCESS32 (0x1U << DM_SBCS_SBACCESS32_OFFSET)
1582 * 1 when 16-bit system bus accesses are supported.
1584 #define DM_SBCS_SBACCESS16_OFFSET 1
1585 #define DM_SBCS_SBACCESS16_LENGTH 1
1586 #define DM_SBCS_SBACCESS16 (0x1U << DM_SBCS_SBACCESS16_OFFSET)
1588 * 1 when 8-bit system bus accesses are supported.
1590 #define DM_SBCS_SBACCESS8_OFFSET 0
1591 #define DM_SBCS_SBACCESS8_LENGTH 1
1592 #define DM_SBCS_SBACCESS8 (0x1U << DM_SBCS_SBACCESS8_OFFSET)
1593 #define DM_SBADDRESS0 0x39
1595 * Accesses bits 31:0 of the physical address in {\tt sbaddress}.
1597 #define DM_SBADDRESS0_ADDRESS_OFFSET 0
1598 #define DM_SBADDRESS0_ADDRESS_LENGTH 32
1599 #define DM_SBADDRESS0_ADDRESS (0xffffffffU << DM_SBADDRESS0_ADDRESS_OFFSET)
1600 #define DM_SBADDRESS1 0x3a
1602 * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if
1603 * the system address bus is that wide).
1605 #define DM_SBADDRESS1_ADDRESS_OFFSET 0
1606 #define DM_SBADDRESS1_ADDRESS_LENGTH 32
1607 #define DM_SBADDRESS1_ADDRESS (0xffffffffU << DM_SBADDRESS1_ADDRESS_OFFSET)
1608 #define DM_SBADDRESS2 0x3b
1610 * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if
1611 * the system address bus is that wide).
1613 #define DM_SBADDRESS2_ADDRESS_OFFSET 0
1614 #define DM_SBADDRESS2_ADDRESS_LENGTH 32
1615 #define DM_SBADDRESS2_ADDRESS (0xffffffffU << DM_SBADDRESS2_ADDRESS_OFFSET)
1616 #define DM_SBADDRESS3 0x37
1618 * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if
1619 * the system address bus is that wide).
1621 #define DM_SBADDRESS3_ADDRESS_OFFSET 0
1622 #define DM_SBADDRESS3_ADDRESS_LENGTH 32
1623 #define DM_SBADDRESS3_ADDRESS (0xffffffffU << DM_SBADDRESS3_ADDRESS_OFFSET)
1624 #define DM_SBDATA0 0x3c
1626 * Accesses bits 31:0 of {\tt sbdata}.
1628 #define DM_SBDATA0_DATA_OFFSET 0
1629 #define DM_SBDATA0_DATA_LENGTH 32
1630 #define DM_SBDATA0_DATA (0xffffffffU << DM_SBDATA0_DATA_OFFSET)
1631 #define DM_SBDATA1 0x3d
1633 * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that
1636 #define DM_SBDATA1_DATA_OFFSET 0
1637 #define DM_SBDATA1_DATA_LENGTH 32
1638 #define DM_SBDATA1_DATA (0xffffffffU << DM_SBDATA1_DATA_OFFSET)
1639 #define DM_SBDATA2 0x3e
1641 * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that
1644 #define DM_SBDATA2_DATA_OFFSET 0
1645 #define DM_SBDATA2_DATA_LENGTH 32
1646 #define DM_SBDATA2_DATA (0xffffffffU << DM_SBDATA2_DATA_OFFSET)
1647 #define DM_SBDATA3 0x3f
1649 * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that
1652 #define DM_SBDATA3_DATA_OFFSET 0
1653 #define DM_SBDATA3_DATA_LENGTH 32
1654 #define DM_SBDATA3_DATA (0xffffffffU << DM_SBDATA3_DATA_OFFSET)
1655 #define DM_CUSTOM 0x1f
1656 #define DM_CUSTOM0 0x70
1657 #define DM_CUSTOM15 0x7f
1658 #define SHORTNAME 0x123
1660 * Description of what this field is used for.
1662 #define SHORTNAME_FIELD_OFFSET 0
1663 #define SHORTNAME_FIELD_LENGTH 8
1664 #define SHORTNAME_FIELD (0xffU << SHORTNAME_FIELD_OFFSET)
1666 * This is 0 to indicate Access Register Command.
1668 #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 24
1669 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8
1670 #define AC_ACCESS_REGISTER_CMDTYPE (0xffU << AC_ACCESS_REGISTER_CMDTYPE_OFFSET)
1672 * 2: Access the lowest 32 bits of the register.
1674 * 3: Access the lowest 64 bits of the register.
1676 * 4: Access the lowest 128 bits of the register.
1678 * If \FacAccessregisterAarsize specifies a size larger than the register's actual size,
1679 * then the access must fail. If a register is accessible, then reads of \FacAccessregisterAarsize
1680 * less than or equal to the register's actual size must be supported.
1682 * This field controls the Argument Width as referenced in
1683 * Table~\ref{tab:datareg}.
1685 #define AC_ACCESS_REGISTER_AARSIZE_OFFSET 20
1686 #define AC_ACCESS_REGISTER_AARSIZE_LENGTH 3
1687 #define AC_ACCESS_REGISTER_AARSIZE (0x7U << AC_ACCESS_REGISTER_AARSIZE_OFFSET)
1689 * 0: No effect. This variant must be supported.
1691 * 1: After a successful register access, \FacAccessregisterRegno is
1692 * incremented (wrapping around to 0). Supporting this variant is
1693 * optional. It is undefined whether the increment happens when
1694 * \FacAccessregisterTransfer is 0.
1696 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 19
1697 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1
1698 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT (0x1U << AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET)
1700 * 0: No effect. This variant must be supported, and is the only
1701 * supported one if \FdmAbstractcsProgbufsize is 0.
1703 * 1: Execute the program in the Program Buffer exactly once after
1704 * performing the transfer, if any. Supporting this variant is
1707 #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 18
1708 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1
1709 #define AC_ACCESS_REGISTER_POSTEXEC (0x1U << AC_ACCESS_REGISTER_POSTEXEC_OFFSET)
1711 * 0: Don't do the operation specified by \FacAccessregisterWrite.
1713 * 1: Do the operation specified by \FacAccessregisterWrite.
1715 * This bit can be used to just execute the Program Buffer without
1716 * having to worry about placing valid values into \FacAccessregisterAarsize or \FacAccessregisterRegno.
1718 #define AC_ACCESS_REGISTER_TRANSFER_OFFSET 17
1719 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1
1720 #define AC_ACCESS_REGISTER_TRANSFER (0x1U << AC_ACCESS_REGISTER_TRANSFER_OFFSET)
1722 * When \FacAccessregisterTransfer is set:
1723 * 0: Copy data from the specified register into {\tt arg0} portion
1726 * 1: Copy data from {\tt arg0} portion of {\tt data} into the
1727 * specified register.
1729 #define AC_ACCESS_REGISTER_WRITE_OFFSET 16
1730 #define AC_ACCESS_REGISTER_WRITE_LENGTH 1
1731 #define AC_ACCESS_REGISTER_WRITE (0x1U << AC_ACCESS_REGISTER_WRITE_OFFSET)
1733 * Number of the register to access, as described in
1734 * Table~\ref{tab:regno}.
1735 * \RcsrDpc may be used as an alias for PC if this command is
1736 * supported on a non-halted hart.
1738 #define AC_ACCESS_REGISTER_REGNO_OFFSET 0
1739 #define AC_ACCESS_REGISTER_REGNO_LENGTH 16
1740 #define AC_ACCESS_REGISTER_REGNO (0xffffU << AC_ACCESS_REGISTER_REGNO_OFFSET)
1742 * This is 1 to indicate Quick Access command.
1744 #define AC_QUICK_ACCESS_CMDTYPE_OFFSET 24
1745 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8
1746 #define AC_QUICK_ACCESS_CMDTYPE (0xffU << AC_QUICK_ACCESS_CMDTYPE_OFFSET)
1748 * This is 2 to indicate Access Memory Command.
1750 #define AC_ACCESS_MEMORY_CMDTYPE_OFFSET 24
1751 #define AC_ACCESS_MEMORY_CMDTYPE_LENGTH 8
1752 #define AC_ACCESS_MEMORY_CMDTYPE (0xffU << AC_ACCESS_MEMORY_CMDTYPE_OFFSET)
1754 * An implementation does not have to implement both virtual and
1755 * physical accesses, but it must fail accesses that it doesn't
1758 * 0: Addresses are physical (to the hart they are performed on).
1760 * 1: Addresses are virtual, and translated the way they would be from
1761 * M-mode, with \FcsrMcontrolMprv set.
1763 #define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 23
1764 #define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1
1765 #define AC_ACCESS_MEMORY_AAMVIRTUAL (0x1U << AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET)
1767 * 0: Access the lowest 8 bits of the memory location.
1769 * 1: Access the lowest 16 bits of the memory location.
1771 * 2: Access the lowest 32 bits of the memory location.
1773 * 3: Access the lowest 64 bits of the memory location.
1775 * 4: Access the lowest 128 bits of the memory location.
1777 #define AC_ACCESS_MEMORY_AAMSIZE_OFFSET 20
1778 #define AC_ACCESS_MEMORY_AAMSIZE_LENGTH 3
1779 #define AC_ACCESS_MEMORY_AAMSIZE (0x7U << AC_ACCESS_MEMORY_AAMSIZE_OFFSET)
1781 * After a memory access has completed, if this bit is 1, increment
1782 * {\tt arg1} (which contains the address used) by the number of bytes
1783 * encoded in \FacAccessmemoryAamsize.
1785 * Supporting this variant is optional, but highly recommended for
1786 * performance reasons.
1788 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET 19
1789 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_LENGTH 1
1790 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT (0x1U << AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET)
1792 * 0: Copy data from the memory location specified in {\tt arg1} into
1793 * the low bits of {\tt arg0}. Any remaining bits of {\tt arg0} now
1794 * have an undefined value.
1796 * 1: Copy data from the low bits of {\tt arg0} into the memory
1797 * location specified in {\tt arg1}.
1799 #define AC_ACCESS_MEMORY_WRITE_OFFSET 16
1800 #define AC_ACCESS_MEMORY_WRITE_LENGTH 1
1801 #define AC_ACCESS_MEMORY_WRITE (0x1U << AC_ACCESS_MEMORY_WRITE_OFFSET)
1803 * These bits are reserved for target-specific uses.
1805 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET 14
1806 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC_LENGTH 2
1807 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC (0x3U << AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET)
1808 #define VIRT_PRIV virtual
1810 * Contains the privilege level the hart was operating in when Debug
1811 * Mode was entered. The encoding is described in Table
1812 * \ref{tab:privlevel}, and matches the privilege level encoding from
1813 * the Privileged Spec. A user can write this
1814 * value to change the hart's privilege level when exiting Debug Mode.
1816 #define VIRT_PRIV_PRV_OFFSET 0
1817 #define VIRT_PRIV_PRV_LENGTH 2
1818 #define VIRT_PRIV_PRV (0x3U << VIRT_PRIV_PRV_OFFSET)
1819 #define DMI_SERCS 0x34
1821 * Number of supported serial ports.
1823 #define DMI_SERCS_SERIALCOUNT_OFFSET 28
1824 #define DMI_SERCS_SERIALCOUNT_LENGTH 4
1825 #define DMI_SERCS_SERIALCOUNT (0xfU << DMI_SERCS_SERIALCOUNT_OFFSET)
1827 * Select which serial port is accessed by \RdmiSerrx and \RdmiSertx.
1829 #define DMI_SERCS_SERIAL_OFFSET 24
1830 #define DMI_SERCS_SERIAL_LENGTH 3
1831 #define DMI_SERCS_SERIAL (0x7U << DMI_SERCS_SERIAL_OFFSET)
1832 #define DMI_SERCS_ERROR7_OFFSET 23
1833 #define DMI_SERCS_ERROR7_LENGTH 1
1834 #define DMI_SERCS_ERROR7 (0x1U << DMI_SERCS_ERROR7_OFFSET)
1835 #define DMI_SERCS_VALID7_OFFSET 22
1836 #define DMI_SERCS_VALID7_LENGTH 1
1837 #define DMI_SERCS_VALID7 (0x1U << DMI_SERCS_VALID7_OFFSET)
1838 #define DMI_SERCS_FULL7_OFFSET 21
1839 #define DMI_SERCS_FULL7_LENGTH 1
1840 #define DMI_SERCS_FULL7 (0x1U << DMI_SERCS_FULL7_OFFSET)
1841 #define DMI_SERCS_ERROR6_OFFSET 20
1842 #define DMI_SERCS_ERROR6_LENGTH 1
1843 #define DMI_SERCS_ERROR6 (0x1U << DMI_SERCS_ERROR6_OFFSET)
1844 #define DMI_SERCS_VALID6_OFFSET 19
1845 #define DMI_SERCS_VALID6_LENGTH 1
1846 #define DMI_SERCS_VALID6 (0x1U << DMI_SERCS_VALID6_OFFSET)
1847 #define DMI_SERCS_FULL6_OFFSET 18
1848 #define DMI_SERCS_FULL6_LENGTH 1
1849 #define DMI_SERCS_FULL6 (0x1U << DMI_SERCS_FULL6_OFFSET)
1850 #define DMI_SERCS_ERROR5_OFFSET 17
1851 #define DMI_SERCS_ERROR5_LENGTH 1
1852 #define DMI_SERCS_ERROR5 (0x1U << DMI_SERCS_ERROR5_OFFSET)
1853 #define DMI_SERCS_VALID5_OFFSET 16
1854 #define DMI_SERCS_VALID5_LENGTH 1
1855 #define DMI_SERCS_VALID5 (0x1U << DMI_SERCS_VALID5_OFFSET)
1856 #define DMI_SERCS_FULL5_OFFSET 15
1857 #define DMI_SERCS_FULL5_LENGTH 1
1858 #define DMI_SERCS_FULL5 (0x1U << DMI_SERCS_FULL5_OFFSET)
1859 #define DMI_SERCS_ERROR4_OFFSET 14
1860 #define DMI_SERCS_ERROR4_LENGTH 1
1861 #define DMI_SERCS_ERROR4 (0x1U << DMI_SERCS_ERROR4_OFFSET)
1862 #define DMI_SERCS_VALID4_OFFSET 13
1863 #define DMI_SERCS_VALID4_LENGTH 1
1864 #define DMI_SERCS_VALID4 (0x1U << DMI_SERCS_VALID4_OFFSET)
1865 #define DMI_SERCS_FULL4_OFFSET 12
1866 #define DMI_SERCS_FULL4_LENGTH 1
1867 #define DMI_SERCS_FULL4 (0x1U << DMI_SERCS_FULL4_OFFSET)
1868 #define DMI_SERCS_ERROR3_OFFSET 11
1869 #define DMI_SERCS_ERROR3_LENGTH 1
1870 #define DMI_SERCS_ERROR3 (0x1U << DMI_SERCS_ERROR3_OFFSET)
1871 #define DMI_SERCS_VALID3_OFFSET 10
1872 #define DMI_SERCS_VALID3_LENGTH 1
1873 #define DMI_SERCS_VALID3 (0x1U << DMI_SERCS_VALID3_OFFSET)
1874 #define DMI_SERCS_FULL3_OFFSET 9
1875 #define DMI_SERCS_FULL3_LENGTH 1
1876 #define DMI_SERCS_FULL3 (0x1U << DMI_SERCS_FULL3_OFFSET)
1877 #define DMI_SERCS_ERROR2_OFFSET 8
1878 #define DMI_SERCS_ERROR2_LENGTH 1
1879 #define DMI_SERCS_ERROR2 (0x1U << DMI_SERCS_ERROR2_OFFSET)
1880 #define DMI_SERCS_VALID2_OFFSET 7
1881 #define DMI_SERCS_VALID2_LENGTH 1
1882 #define DMI_SERCS_VALID2 (0x1U << DMI_SERCS_VALID2_OFFSET)
1883 #define DMI_SERCS_FULL2_OFFSET 6
1884 #define DMI_SERCS_FULL2_LENGTH 1
1885 #define DMI_SERCS_FULL2 (0x1U << DMI_SERCS_FULL2_OFFSET)
1886 #define DMI_SERCS_ERROR1_OFFSET 5
1887 #define DMI_SERCS_ERROR1_LENGTH 1
1888 #define DMI_SERCS_ERROR1 (0x1U << DMI_SERCS_ERROR1_OFFSET)
1889 #define DMI_SERCS_VALID1_OFFSET 4
1890 #define DMI_SERCS_VALID1_LENGTH 1
1891 #define DMI_SERCS_VALID1 (0x1U << DMI_SERCS_VALID1_OFFSET)
1892 #define DMI_SERCS_FULL1_OFFSET 3
1893 #define DMI_SERCS_FULL1_LENGTH 1
1894 #define DMI_SERCS_FULL1 (0x1U << DMI_SERCS_FULL1_OFFSET)
1896 * 1 when the debugger-to-core queue for serial port 0 has
1897 * over or underflowed. This bit will remain set until it is reset by
1898 * writing 1 to this bit.
1900 #define DMI_SERCS_ERROR0_OFFSET 2
1901 #define DMI_SERCS_ERROR0_LENGTH 1
1902 #define DMI_SERCS_ERROR0 (0x1U << DMI_SERCS_ERROR0_OFFSET)
1904 * 1 when the core-to-debugger queue for serial port 0 is not empty.
1906 #define DMI_SERCS_VALID0_OFFSET 1
1907 #define DMI_SERCS_VALID0_LENGTH 1
1908 #define DMI_SERCS_VALID0 (0x1U << DMI_SERCS_VALID0_OFFSET)
1910 * 1 when the debugger-to-core queue for serial port 0 is full.
1912 #define DMI_SERCS_FULL0_OFFSET 0
1913 #define DMI_SERCS_FULL0_LENGTH 1
1914 #define DMI_SERCS_FULL0 (0x1U << DMI_SERCS_FULL0_OFFSET)
1915 #define DMI_SERTX 0x35
1916 #define DMI_SERTX_DATA_OFFSET 0
1917 #define DMI_SERTX_DATA_LENGTH 32
1918 #define DMI_SERTX_DATA (0xffffffffU << DMI_SERTX_DATA_OFFSET)
1919 #define DMI_SERRX 0x36
1920 #define DMI_SERRX_DATA_OFFSET 0
1921 #define DMI_SERRX_DATA_LENGTH 32
1922 #define DMI_SERRX_DATA (0xffffffffU << DMI_SERRX_DATA_OFFSET)