2 * This file is auto-generated by running 'make debug_defines.h' in
3 * https://github.com/riscv/riscv-debug-spec/ (d749752)
6 #define DTM_IDCODE 0x01
8 * Identifies the release version of this part.
10 #define DTM_IDCODE_VERSION_OFFSET 0x1c
11 #define DTM_IDCODE_VERSION_LENGTH 4
12 #define DTM_IDCODE_VERSION 0xf0000000U
14 * Identifies the designer's part number of this part.
16 #define DTM_IDCODE_PARTNUMBER_OFFSET 0xc
17 #define DTM_IDCODE_PARTNUMBER_LENGTH 0x10
18 #define DTM_IDCODE_PARTNUMBER 0xffff000
20 * Identifies the designer/manufacturer of this part. Bits 6:0 must be
21 * bits 6:0 of the designer/manufacturer's Identification Code as
22 * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
23 * count of the number of continuation characters (0x7f) in that same
24 * Identification Code.
26 #define DTM_IDCODE_MANUFID_OFFSET 1
27 #define DTM_IDCODE_MANUFID_LENGTH 0xb
28 #define DTM_IDCODE_MANUFID 0xffe
29 #define DTM_IDCODE_1_OFFSET 0
30 #define DTM_IDCODE_1_LENGTH 1
31 #define DTM_IDCODE_1 1
32 #define DTM_DTMCS 0x10
34 * Writing 1 to this bit does a hard reset of the DTM,
35 * causing the DTM to forget about any outstanding DMI transactions, and
36 * returning all registers and internal state to their reset value.
37 * In general this should only be used when the Debugger has
38 * reason to expect that the outstanding DMI transaction will never
39 * complete (e.g. a reset condition caused an inflight DMI transaction to
42 #define DTM_DTMCS_DMIHARDRESET_OFFSET 0x11
43 #define DTM_DTMCS_DMIHARDRESET_LENGTH 1
44 #define DTM_DTMCS_DMIHARDRESET 0x20000
46 * Writing 1 to this bit clears the sticky error state, but does
47 * not affect outstanding DMI transactions.
49 #define DTM_DTMCS_DMIRESET_OFFSET 0x10
50 #define DTM_DTMCS_DMIRESET_LENGTH 1
51 #define DTM_DTMCS_DMIRESET 0x10000
53 * This is a hint to the debugger of the minimum number of
54 * cycles a debugger should spend in
55 * Run-Test/Idle after every DMI scan to avoid a `busy'
56 * return code (\FdtmDtmcsDmistat of 3). A debugger must still
57 * check \FdtmDtmcsDmistat when necessary.
59 * 0: It is not necessary to enter Run-Test/Idle at all.
61 * 1: Enter Run-Test/Idle and leave it immediately.
63 * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
67 #define DTM_DTMCS_IDLE_OFFSET 0xc
68 #define DTM_DTMCS_IDLE_LENGTH 3
69 #define DTM_DTMCS_IDLE 0x7000
71 * Read-only alias of \FdtmDmiOp.
73 #define DTM_DTMCS_DMISTAT_OFFSET 0xa
74 #define DTM_DTMCS_DMISTAT_LENGTH 2
75 #define DTM_DTMCS_DMISTAT 0xc00
77 * The size of \FdmSbaddressZeroAddress in \RdtmDmi.
79 #define DTM_DTMCS_ABITS_OFFSET 4
80 #define DTM_DTMCS_ABITS_LENGTH 6
81 #define DTM_DTMCS_ABITS 0x3f0
82 #define DTM_DTMCS_VERSION_OFFSET 0
83 #define DTM_DTMCS_VERSION_LENGTH 4
84 #define DTM_DTMCS_VERSION 0xf
86 * 0.11: Version described in spec version 0.11.
88 #define DTM_DTMCS_VERSION_0_11 0
90 * 1.0: Version described in spec versions 0.13 and 1.0.
92 #define DTM_DTMCS_VERSION_1_0 1
94 * custom: Version not described in any available version of this spec.
96 #define DTM_DTMCS_VERSION_CUSTOM 15
99 * Address used for DMI access. In Update-DR this value is used
100 * to access the DM over the DMI.
102 #define DTM_DMI_ADDRESS_OFFSET 0x22
103 #define DTM_DMI_ADDRESS_LENGTH(abits) abits
104 #define DTM_DMI_ADDRESS(abits) ((0x400000000ULL * (1ULL<<abits)) + -0x400000000ULL)
106 * The data to send to the DM over the DMI during Update-DR, and
107 * the data returned from the DM as a result of the previous operation.
109 #define DTM_DMI_DATA_OFFSET 2
110 #define DTM_DMI_DATA_LENGTH 0x20
111 #define DTM_DMI_DATA 0x3fffffffcULL
113 * When the debugger writes this field, it has the following meaning:
115 #define DTM_DMI_OP_OFFSET 0
116 #define DTM_DMI_OP_LENGTH 2
119 * nop: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress.
121 * Don't send anything over the DMI during Update-DR.
122 * This operation should never result in a busy or error response.
123 * The address and data reported in the following Capture-DR
126 #define DTM_DMI_OP_NOP 0
128 * read: Read from \FdmSbaddressZeroAddress.
130 #define DTM_DMI_OP_READ 1
132 * write: Write \FdmSbdataZeroData to \FdmSbaddressZeroAddress.
134 #define DTM_DMI_OP_WRITE 2
136 * reserved: Reserved.
139 * When the debugger reads this field, it means the following:
142 * success: The previous operation completed successfully.
144 #define DTM_DMI_OP_SUCCESS 0
146 * reserved: Reserved.
149 * failed: A previous operation failed. The data scanned into \RdtmDmi in
150 * this access will be ignored. This status is sticky and can be
151 * cleared by writing \FdtmDtmcsDmireset in \RdtmDtmcs.
153 * This indicates that the DM itself responded with an error.
154 * There are no specified cases in which the DM would
155 * respond with an error, and DMI is not required to support
158 #define DTM_DMI_OP_FAILED 2
160 * busy: An operation was attempted while a DMI request is still in
161 * progress. The data scanned into \RdtmDmi in this access will be
162 * ignored. This status is sticky and can be cleared by writing
163 * \FdtmDtmcsDmireset in \RdtmDtmcs. If a debugger sees this status, it
164 * needs to give the target more TCK edges between Update-DR and
165 * Capture-DR. The simplest way to do that is to add extra transitions
168 #define DTM_DMI_OP_BUSY 3
169 #define CSR_DCSR 0x7b0
170 #define CSR_DCSR_DEBUGVER_OFFSET 0x1c
171 #define CSR_DCSR_DEBUGVER_LENGTH 4
172 #define CSR_DCSR_DEBUGVER 0xf0000000U
174 * none: There is no debug support.
176 #define CSR_DCSR_DEBUGVER_NONE 0
178 * 1.0: Debug support exists as it is described in this document.
180 #define CSR_DCSR_DEBUGVER_1_0 4
182 * custom: There is debug support, but it does not conform to any
183 * available version of this spec.
185 #define CSR_DCSR_DEBUGVER_CUSTOM 15
186 #define CSR_DCSR_EBREAKVS_OFFSET 0x11
187 #define CSR_DCSR_EBREAKVS_LENGTH 1
188 #define CSR_DCSR_EBREAKVS 0x20000
190 * exception: {\tt ebreak} instructions in VS-mode behave as described in the
193 #define CSR_DCSR_EBREAKVS_EXCEPTION 0
195 * debug mode: {\tt ebreak} instructions in VS-mode enter Debug Mode.
197 #define CSR_DCSR_EBREAKVS_DEBUG_MODE 1
199 * This bit is hardwired to 0 if the hart does not support virtualization mode.
201 #define CSR_DCSR_EBREAKVU_OFFSET 0x10
202 #define CSR_DCSR_EBREAKVU_LENGTH 1
203 #define CSR_DCSR_EBREAKVU 0x10000
205 * exception: {\tt ebreak} instructions in VU-mode behave as described in the
208 #define CSR_DCSR_EBREAKVU_EXCEPTION 0
210 * debug mode: {\tt ebreak} instructions in VU-mode enter Debug Mode.
212 #define CSR_DCSR_EBREAKVU_DEBUG_MODE 1
214 * This bit is hardwired to 0 if the hart does not support virtualization mode.
216 #define CSR_DCSR_EBREAKM_OFFSET 0xf
217 #define CSR_DCSR_EBREAKM_LENGTH 1
218 #define CSR_DCSR_EBREAKM 0x8000
220 * exception: {\tt ebreak} instructions in M-mode behave as described in the
223 #define CSR_DCSR_EBREAKM_EXCEPTION 0
225 * debug mode: {\tt ebreak} instructions in M-mode enter Debug Mode.
227 #define CSR_DCSR_EBREAKM_DEBUG_MODE 1
228 #define CSR_DCSR_EBREAKS_OFFSET 0xd
229 #define CSR_DCSR_EBREAKS_LENGTH 1
230 #define CSR_DCSR_EBREAKS 0x2000
232 * exception: {\tt ebreak} instructions in S-mode behave as described in the
235 #define CSR_DCSR_EBREAKS_EXCEPTION 0
237 * debug mode: {\tt ebreak} instructions in S-mode enter Debug Mode.
239 #define CSR_DCSR_EBREAKS_DEBUG_MODE 1
241 * This bit is hardwired to 0 if the hart does not support S-mode.
243 #define CSR_DCSR_EBREAKU_OFFSET 0xc
244 #define CSR_DCSR_EBREAKU_LENGTH 1
245 #define CSR_DCSR_EBREAKU 0x1000
247 * exception: {\tt ebreak} instructions in U-mode behave as described in the
250 #define CSR_DCSR_EBREAKU_EXCEPTION 0
252 * debug mode: {\tt ebreak} instructions in U-mode enter Debug Mode.
254 #define CSR_DCSR_EBREAKU_DEBUG_MODE 1
256 * This bit is hardwired to 0 if the hart does not support U-mode.
258 #define CSR_DCSR_STEPIE_OFFSET 0xb
259 #define CSR_DCSR_STEPIE_LENGTH 1
260 #define CSR_DCSR_STEPIE 0x800
262 * interrupts disabled: Interrupts (including NMI) are disabled during single stepping.
264 #define CSR_DCSR_STEPIE_INTERRUPTS_DISABLED 0
266 * interrupts enabled: Interrupts (including NMI) are enabled during single stepping.
268 #define CSR_DCSR_STEPIE_INTERRUPTS_ENABLED 1
270 * Implementations may hard wire this bit to 0.
271 * In that case interrupt behavior can be emulated by the debugger.
273 * The debugger must not change the value of this bit while the hart
276 #define CSR_DCSR_STOPCOUNT_OFFSET 0xa
277 #define CSR_DCSR_STOPCOUNT_LENGTH 1
278 #define CSR_DCSR_STOPCOUNT 0x400
280 * normal: Increment counters as usual.
282 #define CSR_DCSR_STOPCOUNT_NORMAL 0
284 * freeze: Don't increment any hart-local counters while in Debug Mode or
285 * on {\tt ebreak} instructions that cause entry into Debug Mode.
286 * These counters include the {\tt instret} CSR. On single-hart cores
287 * {\tt cycle} should be stopped, but on multi-hart cores it must keep
290 #define CSR_DCSR_STOPCOUNT_FREEZE 1
292 * An implementation may hardwire this bit to 0 or 1.
294 #define CSR_DCSR_STOPTIME_OFFSET 9
295 #define CSR_DCSR_STOPTIME_LENGTH 1
296 #define CSR_DCSR_STOPTIME 0x200
298 * normal: Increment \Rtime as usual.
300 #define CSR_DCSR_STOPTIME_NORMAL 0
302 * freeze: Don't increment \Rtime while in Debug Mode. If all harts
303 * have \FcsrDcsrStoptime=1 and are in Debug Mode then \Rmtime
304 * is also allowed to stop incrementing.
306 #define CSR_DCSR_STOPTIME_FREEZE 1
308 * An implementation may hardwire this bit to 0 or 1.
311 * Explains why Debug Mode was entered.
313 * When there are multiple reasons to enter Debug Mode in a single
314 * cycle, hardware should set \FcsrDcsrCause to the cause with the highest
315 * priority. See table~\ref{tab:dcsrcausepriority} for priorities.
317 #define CSR_DCSR_CAUSE_OFFSET 6
318 #define CSR_DCSR_CAUSE_LENGTH 3
319 #define CSR_DCSR_CAUSE 0x1c0
321 * ebreak: An {\tt ebreak} instruction was executed.
323 #define CSR_DCSR_CAUSE_EBREAK 1
325 * trigger: A Trigger Module trigger fired with action=1.
327 #define CSR_DCSR_CAUSE_TRIGGER 2
329 * haltreq: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
331 #define CSR_DCSR_CAUSE_HALTREQ 3
333 * step: The hart single stepped because \FcsrDcsrStep was set.
335 #define CSR_DCSR_CAUSE_STEP 4
337 * resethaltreq: The hart halted directly out of reset due to \Fresethaltreq. It
338 * is also acceptable to report 3 when this happens.
340 #define CSR_DCSR_CAUSE_RESETHALTREQ 5
342 * group: The hart halted because it's part of a halt group.
343 * Harts may report 3 for this cause instead.
345 #define CSR_DCSR_CAUSE_GROUP 6
347 * Other values are reserved for future use.
350 * Extends the prv field with the virtualization mode the hart was operating
351 * in when Debug Mode was entered. The encoding is described in Table
352 * \ref{tab:privmode}.
353 * A debugger can change this value to change the hart's virtualization mode
354 * when exiting Debug Mode.
355 * This bit is hardwired to 0 on harts that do not support virtualization mode.
357 #define CSR_DCSR_V_OFFSET 5
358 #define CSR_DCSR_V_LENGTH 1
359 #define CSR_DCSR_V 0x20
360 #define CSR_DCSR_MPRVEN_OFFSET 4
361 #define CSR_DCSR_MPRVEN_LENGTH 1
362 #define CSR_DCSR_MPRVEN 0x10
364 * disabled: \FcsrMstatusMprv in \Rmstatus is ignored in Debug Mode.
366 #define CSR_DCSR_MPRVEN_DISABLED 0
368 * enabled: \FcsrMstatusMprv in \Rmstatus takes effect in Debug Mode.
370 #define CSR_DCSR_MPRVEN_ENABLED 1
372 * Implementing this bit is optional. It may be tied to either 0 or 1.
375 * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
377 * Since an NMI can indicate a hardware error condition,
378 * reliable debugging may no longer be possible once this bit becomes set.
379 * This is implementation-dependent.
381 #define CSR_DCSR_NMIP_OFFSET 3
382 #define CSR_DCSR_NMIP_LENGTH 1
383 #define CSR_DCSR_NMIP 8
385 * When set and not in Debug Mode, the hart will only execute a single
386 * instruction and then enter Debug Mode. See Section~\ref{stepBit}
389 * The debugger must not change the value of this bit while the hart
392 #define CSR_DCSR_STEP_OFFSET 2
393 #define CSR_DCSR_STEP_LENGTH 1
394 #define CSR_DCSR_STEP 4
396 * Contains the privilege mode the hart was operating in when Debug
397 * Mode was entered. The encoding is described in Table
398 * \ref{tab:privmode}. A debugger can change this value to change
399 * the hart's privilege mode when exiting Debug Mode.
401 * Not all privilege modes are supported on all harts. If the
402 * encoding written is not supported or the debugger is not allowed to
403 * change to it, the hart may change to any supported privilege mode.
405 #define CSR_DCSR_PRV_OFFSET 0
406 #define CSR_DCSR_PRV_LENGTH 2
407 #define CSR_DCSR_PRV 3
408 #define CSR_DPC 0x7b1
409 #define CSR_DPC_DPC_OFFSET 0
410 #define CSR_DPC_DPC_LENGTH(DXLEN) DXLEN
411 #define CSR_DPC_DPC(DXLEN) ((1ULL<<DXLEN) + -1)
412 #define CSR_DSCRATCH0 0x7b2
413 #define CSR_DSCRATCH1 0x7b3
414 #define CSR_TSELECT 0x7a0
415 #define CSR_TSELECT_INDEX_OFFSET 0
416 #define CSR_TSELECT_INDEX_LENGTH(XLEN) XLEN
417 #define CSR_TSELECT_INDEX(XLEN) ((1ULL<<XLEN) + -1)
418 #define CSR_TDATA1 0x7a1
419 #define CSR_TDATA1_TYPE_OFFSET(XLEN) (XLEN + -4)
420 #define CSR_TDATA1_TYPE_LENGTH 4
421 #define CSR_TDATA1_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
423 * none: There is no trigger at this \RcsrTselect.
425 #define CSR_TDATA1_TYPE_NONE 0
427 * legacy: The trigger is a legacy SiFive address match trigger. These
428 * should not be implemented and aren't further documented here.
430 #define CSR_TDATA1_TYPE_LEGACY 1
432 * mcontrol: The trigger is an address/data match trigger. The remaining bits
433 * in this register act as described in \RcsrMcontrol.
435 #define CSR_TDATA1_TYPE_MCONTROL 2
437 * icount: The trigger is an instruction count trigger. The remaining bits
438 * in this register act as described in \RcsrIcount.
440 #define CSR_TDATA1_TYPE_ICOUNT 3
442 * itrigger: The trigger is an interrupt trigger. The remaining bits
443 * in this register act as described in \RcsrItrigger.
445 #define CSR_TDATA1_TYPE_ITRIGGER 4
447 * etrigger: The trigger is an exception trigger. The remaining bits
448 * in this register act as described in \RcsrEtrigger.
450 #define CSR_TDATA1_TYPE_ETRIGGER 5
452 * mcontrol6: The trigger is an address/data match trigger. The remaining bits
453 * in this register act as described in \RcsrMcontrolSix. This is similar
454 * to a type 2 trigger, but provides additional functionality and
455 * should be used instead of type 2 in newer implementations.
457 #define CSR_TDATA1_TYPE_MCONTROL6 6
459 * tmexttrigger: The trigger is a trigger source external to the TM. The
460 * remaining bits in this register act as described in \RcsrTmexttrigger.
462 #define CSR_TDATA1_TYPE_TMEXTTRIGGER 7
464 * custom: These trigger types are available for non-standard use.
466 #define CSR_TDATA1_TYPE_CUSTOM_LOW 12
467 #define CSR_TDATA1_TYPE_CUSTOM_HIGH 14
469 * disabled: This trigger is disabled. In this state, \RcsrTdataTwo and
470 * \RcsrTdataThree can be written with any value that is supported for
471 * any of the types this trigger implements. The remaining bits in this
472 * register are ignored.
474 #define CSR_TDATA1_TYPE_DISABLED 15
476 * Other values are reserved for future use.
479 * If \FcsrTdataOneType is 0, then this bit is hard-wired to 0.
481 #define CSR_TDATA1_DMODE_OFFSET(XLEN) (XLEN + -5)
482 #define CSR_TDATA1_DMODE_LENGTH 1
483 #define CSR_TDATA1_DMODE(XLEN) (1ULL<<(XLEN + -5))
485 * both: Both Debug and M-mode can write the {\tt tdata} registers at the
486 * selected \RcsrTselect.
488 #define CSR_TDATA1_DMODE_BOTH 0
490 * dmode: Only Debug Mode can write the {\tt tdata} registers at the
491 * selected \RcsrTselect. Writes from other modes are ignored.
493 #define CSR_TDATA1_DMODE_DMODE 1
495 * This bit is only writable from Debug Mode.
496 * In ordinary use, external debuggers will always set this bit when
497 * configuring a trigger.
498 * When clearing this bit, debuggers should also set the action field
499 * (whose location depends on \FcsrTdataOneType) to something other
503 * If \FcsrTdataOneType is 0, then this field is hard-wired to 0.
505 * Trigger-specific data.
507 #define CSR_TDATA1_DATA_OFFSET 0
508 #define CSR_TDATA1_DATA_LENGTH(XLEN) (XLEN + -5)
509 #define CSR_TDATA1_DATA(XLEN) ((1ULL<<(XLEN + -5)) + -1)
510 #define CSR_TDATA2 0x7a2
511 #define CSR_TDATA2_DATA_OFFSET 0
512 #define CSR_TDATA2_DATA_LENGTH(XLEN) XLEN
513 #define CSR_TDATA2_DATA(XLEN) ((1ULL<<XLEN) + -1)
514 #define CSR_TDATA3 0x7a3
515 #define CSR_TDATA3_DATA_OFFSET 0
516 #define CSR_TDATA3_DATA_LENGTH(XLEN) XLEN
517 #define CSR_TDATA3_DATA(XLEN) ((1ULL<<XLEN) + -1)
518 #define CSR_TINFO 0x7a4
520 * One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N
521 * corresponds to type N. If the bit is set, then that type is
522 * supported by the currently selected trigger.
524 * If the currently selected trigger doesn't exist, this field
527 #define CSR_TINFO_INFO_OFFSET 0
528 #define CSR_TINFO_INFO_LENGTH 0x10
529 #define CSR_TINFO_INFO 0xffff
530 #define CSR_TCONTROL 0x7a5
532 * M-mode previous trigger enable field.
534 * \FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem
535 * regarding triggers with action=0 firing in M-mode trap handlers. See
536 * Section~\ref{sec:nativetrigger} for more details.
538 * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
541 #define CSR_TCONTROL_MPTE_OFFSET 7
542 #define CSR_TCONTROL_MPTE_LENGTH 1
543 #define CSR_TCONTROL_MPTE 0x80
545 * M-mode trigger enable field.
547 #define CSR_TCONTROL_MTE_OFFSET 3
548 #define CSR_TCONTROL_MTE_LENGTH 1
549 #define CSR_TCONTROL_MTE 8
551 * disabled: Triggers with action=0 do not match/fire while the hart is in M-mode.
553 #define CSR_TCONTROL_MTE_DISABLED 0
555 * enabled: Triggers do match/fire while the hart is in M-mode.
557 #define CSR_TCONTROL_MTE_ENABLED 1
559 * When a breakpoint trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt
560 * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte.
562 #define CSR_HCONTEXT 0x6a8
564 * Hypervisor mode software can write a context number to this register,
565 * which can be used to set triggers that only fire in that specific
568 * An implementation may tie any number of upper bits in this field to
569 * 0. If the H extension is not implemented, it's recommended to implement
570 * no more than 6 bits on RV32 and 13 on RV64 (as visible through the
571 * \RcsrMcontext register). If the H extension is implemented,
572 * it's recommended to implement no more than 7 bits on RV32
575 #define CSR_HCONTEXT_HCONTEXT_OFFSET 0
576 #define CSR_HCONTEXT_HCONTEXT_LENGTH(XLEN) XLEN
577 #define CSR_HCONTEXT_HCONTEXT(XLEN) ((1ULL<<XLEN) + -1)
578 #define CSR_SCONTEXT 0x5a8
580 * Supervisor mode software can write a context number to this
581 * register, which can be used to set triggers that only fire in that
584 * An implementation may tie any number of high bits in this field to
585 * 0. It's recommended to implement no more than 16 bits on RV32, and
588 #define CSR_SCONTEXT_DATA_OFFSET 0
589 #define CSR_SCONTEXT_DATA_LENGTH(XLEN) XLEN
590 #define CSR_SCONTEXT_DATA(XLEN) ((1ULL<<XLEN) + -1)
591 #define CSR_MCONTEXT 0x7a8
592 #define CSR_MSCONTEXT 0x7aa
593 #define CSR_MCONTROL 0x7a1
594 #define CSR_MCONTROL_TYPE_OFFSET(XLEN) (XLEN + -4)
595 #define CSR_MCONTROL_TYPE_LENGTH 4
596 #define CSR_MCONTROL_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
597 #define CSR_MCONTROL_DMODE_OFFSET(XLEN) (XLEN + -5)
598 #define CSR_MCONTROL_DMODE_LENGTH 1
599 #define CSR_MCONTROL_DMODE(XLEN) (1ULL<<(XLEN + -5))
601 * Specifies the largest naturally aligned powers-of-two (NAPOT) range
602 * supported by the hardware when \FcsrMcontrolMatch is 1. The value is the
603 * logarithm base 2 of the number of bytes in that range.
604 * A value of 0 indicates \FcsrMcontrolMatch 1 is not supported.
605 * A value of 63 corresponds to the maximum NAPOT range, which is
606 * $2^{63}$ bytes in size.
608 #define CSR_MCONTROL_MASKMAX_OFFSET(XLEN) (XLEN + -0xb)
609 #define CSR_MCONTROL_MASKMAX_LENGTH 6
610 #define CSR_MCONTROL_MASKMAX(XLEN) (0x3f * (1ULL<<(XLEN + -0xb)))
612 * This field only exists when XLEN is at least 64.
613 * It contains the 2 high bits of the access size. The low bits
614 * come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this
617 #define CSR_MCONTROL_SIZEHI_OFFSET 0x15
618 #define CSR_MCONTROL_SIZEHI_LENGTH 2
619 #define CSR_MCONTROL_SIZEHI 0x600000
621 * If this bit is implemented then it must become set when this
622 * trigger fires and may become set when this trigger matches.
623 * The trigger's user can set or clear it at any
624 * time. It is used to determine which
625 * trigger(s) matched. If the bit is not implemented, it is always 0
626 * and writing it has no effect.
628 #define CSR_MCONTROL_HIT_OFFSET 0x14
629 #define CSR_MCONTROL_HIT_LENGTH 1
630 #define CSR_MCONTROL_HIT 0x100000
632 * This bit determines the contents of the XLEN-bit compare values.
634 #define CSR_MCONTROL_SELECT_OFFSET 0x13
635 #define CSR_MCONTROL_SELECT_LENGTH 1
636 #define CSR_MCONTROL_SELECT 0x80000
638 * address: There is at least one compare value and it contains the lowest
639 * virtual address of the access.
640 * It is recommended that there are additional compare values for
641 * the other accessed virtual addresses.
642 * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
643 * and the other addresses are 0x4001, 0x4002, and 0x4003.)
645 #define CSR_MCONTROL_SELECT_ADDRESS 0
647 * data: There is exactly one compare value and it contains the data
648 * value loaded or stored, or the instruction executed.
649 * Any bits beyond the size of the data access will contain 0.
651 #define CSR_MCONTROL_SELECT_DATA 1
652 #define CSR_MCONTROL_TIMING_OFFSET 0x12
653 #define CSR_MCONTROL_TIMING_LENGTH 1
654 #define CSR_MCONTROL_TIMING 0x40000
656 * before: The action for this trigger will be taken just before the
657 * instruction that triggered it is committed, but after all preceding
658 * instructions are committed. \Rxepc or \RcsrDpc (depending
659 * on \FcsrMcontrolAction) must be set to the virtual address of the
660 * instruction that matched.
662 * If this is combined with \FcsrMcontrolLoad and
663 * \FcsrMcontrolSelect=1 then a memory access will be
664 * performed (including any side effects of performing such an access) even
665 * though the load will not update its destination register. Debuggers
666 * should consider this when setting such breakpoints on, for example,
667 * memory-mapped I/O addresses.
669 #define CSR_MCONTROL_TIMING_BEFORE 0
671 * after: The action for this trigger will be taken after the instruction
672 * that triggered it is committed. It should be taken before the next
673 * instruction is committed, but it is better to implement triggers imprecisely
674 * than to not implement them at all. \Rxepc or
675 * \RcsrDpc (depending on \FcsrMcontrolAction) must be set to
676 * the virtual address of the next instruction that must be executed to
677 * preserve the program flow.
679 #define CSR_MCONTROL_TIMING_AFTER 1
681 * Most hardware will only implement one timing or the other, possibly
682 * dependent on \FcsrMcontrolSelect, \FcsrMcontrolExecute,
683 * \FcsrMcontrolLoad, and \FcsrMcontrolStore. This bit
684 * primarily exists for the hardware to communicate to the debugger
685 * what will happen. Hardware may implement the bit fully writable, in
686 * which case the debugger has a little more control.
688 * Data load triggers with \FcsrMcontrolTiming of 0 will result in the same load
689 * happening again when the debugger lets the hart run. For data load
690 * triggers, debuggers must first attempt to set the breakpoint with
691 * \FcsrMcontrolTiming of 1.
693 * If a trigger with \FcsrMcontrolTiming of 0 matches, it is
694 * implementation-dependent whether that prevents a trigger with
695 * \FcsrMcontrolTiming of 1 matching as well.
698 * This field contains the 2 low bits of the access size. The high bits come
699 * from \FcsrMcontrolSizehi. The combined value is interpreted as follows:
701 #define CSR_MCONTROL_SIZELO_OFFSET 0x10
702 #define CSR_MCONTROL_SIZELO_LENGTH 2
703 #define CSR_MCONTROL_SIZELO 0x30000
705 * any: The trigger will attempt to match against an access of any size.
706 * The behavior is only well-defined if $|select|=0$, or if the access
709 #define CSR_MCONTROL_SIZELO_ANY 0
711 * 8bit: The trigger will only match against 8-bit memory accesses.
713 #define CSR_MCONTROL_SIZELO_8BIT 1
715 * 16bit: The trigger will only match against 16-bit memory accesses or
716 * execution of 16-bit instructions.
718 #define CSR_MCONTROL_SIZELO_16BIT 2
720 * 32bit: The trigger will only match against 32-bit memory accesses or
721 * execution of 32-bit instructions.
723 #define CSR_MCONTROL_SIZELO_32BIT 3
725 * 48bit: The trigger will only match against execution of 48-bit instructions.
727 #define CSR_MCONTROL_SIZELO_48BIT 4
729 * 64bit: The trigger will only match against 64-bit memory accesses or
730 * execution of 64-bit instructions.
732 #define CSR_MCONTROL_SIZELO_64BIT 5
734 * 80bit: The trigger will only match against execution of 80-bit instructions.
736 #define CSR_MCONTROL_SIZELO_80BIT 6
738 * 96bit: The trigger will only match against execution of 96-bit instructions.
740 #define CSR_MCONTROL_SIZELO_96BIT 7
742 * 112bit: The trigger will only match against execution of 112-bit instructions.
744 #define CSR_MCONTROL_SIZELO_112BIT 8
746 * 128bit: The trigger will only match against 128-bit memory accesses or
747 * execution of 128-bit instructions.
749 #define CSR_MCONTROL_SIZELO_128BIT 9
751 * An implementation must support the value of 0, but all other values
752 * are optional. When an implementation supports address triggers
753 * (\FcsrMcontrolSelect=0), it is recommended that those triggers
754 * support every access size that the hart supports, as well as for
755 * every instruction size that the hart supports.
757 * Implementations such as RV32D or RV64V are able to perform loads
758 * and stores that are wider than XLEN. Custom extensions may also
759 * support instructions that are wider than XLEN. Because
760 * \RcsrTdataTwo is of size XLEN, there is a known limitation that
761 * data value triggers (\FcsrMcontrolSelect=1) can only be supported
762 * for access sizes up to XLEN bits. When an implementation supports
763 * data value triggers (\FcsrMcontrolSelect=1), it is recommended
764 * that those triggers support every access size up to XLEN that the
765 * hart supports, as well as for every instruction length up to XLEN
766 * that the hart supports.
769 * The action to take when the trigger fires. The values are explained
770 * in Table~\ref{tab:action}.
772 #define CSR_MCONTROL_ACTION_OFFSET 0xc
773 #define CSR_MCONTROL_ACTION_LENGTH 4
774 #define CSR_MCONTROL_ACTION 0xf000
778 #define CSR_MCONTROL_ACTION_BREAKPOINT 0
782 #define CSR_MCONTROL_ACTION_DEBUG_MODE 1
786 #define CSR_MCONTROL_ACTION_TRACE_ON 2
790 #define CSR_MCONTROL_ACTION_TRACE_OFF 3
794 #define CSR_MCONTROL_ACTION_TRACE_NOTIFY 4
798 #define CSR_MCONTROL_ACTION_EXTERNAL0 8
802 #define CSR_MCONTROL_ACTION_EXTERNAL1 9
803 #define CSR_MCONTROL_CHAIN_OFFSET 0xb
804 #define CSR_MCONTROL_CHAIN_LENGTH 1
805 #define CSR_MCONTROL_CHAIN 0x800
807 * disabled: When this trigger matches, the configured action is taken.
809 #define CSR_MCONTROL_CHAIN_DISABLED 0
811 * enabled: While this trigger does not match, it prevents the trigger with
812 * the next index from matching.
814 #define CSR_MCONTROL_CHAIN_ENABLED 1
816 * A trigger chain starts on the first trigger with $|chain|=1$ after
817 * a trigger with $|chain|=0$, or simply on the first trigger if that
818 * has $|chain|=1$. It ends on the first trigger after that which has
819 * $|chain|=0$. This final trigger is part of the chain. The action
820 * on all but the final trigger is ignored. The action on that final
821 * trigger will be taken if and only if all the triggers in the chain
822 * match at the same time.
824 * Debuggers should not terminate a chain with a trigger with a
825 * different type. It is undefined when exactly such a chain fires.
827 * Because \FcsrMcontrolChain affects the next trigger, hardware must zero it in
828 * writes to \RcsrMcontrol that set \FcsrTdataOneDmode to 0 if the next trigger has
829 * \FcsrTdataOneDmode of 1.
830 * In addition hardware should ignore writes to \RcsrMcontrol that set
831 * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and
832 * \FcsrMcontrolChain of 1. Debuggers must avoid the latter case by checking
833 * \FcsrMcontrolChain on the previous trigger if they're writing \RcsrMcontrol.
835 * Implementations that wish to limit the maximum length of a trigger
836 * chain (eg. to meet timing requirements) may do so by zeroing
837 * \FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long.
839 #define CSR_MCONTROL_MATCH_OFFSET 7
840 #define CSR_MCONTROL_MATCH_LENGTH 4
841 #define CSR_MCONTROL_MATCH 0x780
843 * equal: Matches when any compare value equals \RcsrTdataTwo.
845 #define CSR_MCONTROL_MATCH_EQUAL 0
847 * napot: Matches when the top $M$ bits of any compare value match the top
848 * $M$ bits of \RcsrTdataTwo.
849 * $M$ is $|XLEN|-1$ minus the index of the least-significant
850 * bit containing 0 in \RcsrTdataTwo. Debuggers should only write values
851 * to \RcsrTdataTwo such that $M + $\FcsrMcontrolMaskmax$ \geq |XLEN|$
852 * and $M\gt0$ , otherwise it's undefined on what conditions the
853 * trigger will match.
855 #define CSR_MCONTROL_MATCH_NAPOT 1
857 * ge: Matches when any compare value is greater than (unsigned) or
858 * equal to \RcsrTdataTwo.
860 #define CSR_MCONTROL_MATCH_GE 2
862 * lt: Matches when any compare value is less than (unsigned)
865 #define CSR_MCONTROL_MATCH_LT 3
867 * mask low: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
868 * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
869 * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with
870 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
872 #define CSR_MCONTROL_MATCH_MASK_LOW 4
874 * mask high: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare
875 * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
876 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with
877 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
879 #define CSR_MCONTROL_MATCH_MASK_HIGH 5
881 * not equal: Matches when \FcsrMcontrolMatch$=0$ would not match.
883 #define CSR_MCONTROL_MATCH_NOT_EQUAL 8
885 * not napot: Matches when \FcsrMcontrolMatch$=1$ would not match.
887 #define CSR_MCONTROL_MATCH_NOT_NAPOT 9
889 * not mask low: Matches when \FcsrMcontrolMatch$=4$ would not match.
891 #define CSR_MCONTROL_MATCH_NOT_MASK_LOW 12
893 * not mask high: Matches when \FcsrMcontrolMatch$=5$ would not match.
895 #define CSR_MCONTROL_MATCH_NOT_MASK_HIGH 13
897 * Other values are reserved for future use.
899 * All comparisons only look at the lower XLEN (in the current mode)
900 * bits of the compare values and of \RcsrTdataTwo.
901 * When \FcsrMcontrolSelect=1 and access size is N, this is further
902 * reduced, and comparisons only look at the lower N bits of the
903 * compare values and of \RcsrTdataTwo.
906 * When set, enable this trigger in M-mode.
908 #define CSR_MCONTROL_M_OFFSET 6
909 #define CSR_MCONTROL_M_LENGTH 1
910 #define CSR_MCONTROL_M 0x40
912 * When set, enable this trigger in S/HS-mode.
913 * This bit is hard-wired to 0 if the hart does not support
916 #define CSR_MCONTROL_S_OFFSET 4
917 #define CSR_MCONTROL_S_LENGTH 1
918 #define CSR_MCONTROL_S 0x10
920 * When set, enable this trigger in U-mode.
921 * This bit is hard-wired to 0 if the hart does not support
924 #define CSR_MCONTROL_U_OFFSET 3
925 #define CSR_MCONTROL_U_LENGTH 1
926 #define CSR_MCONTROL_U 8
928 * When set, the trigger fires on the virtual address or opcode of an
929 * instruction that is executed.
931 #define CSR_MCONTROL_EXECUTE_OFFSET 2
932 #define CSR_MCONTROL_EXECUTE_LENGTH 1
933 #define CSR_MCONTROL_EXECUTE 4
935 * When set, the trigger fires on the virtual address or data of any
938 #define CSR_MCONTROL_STORE_OFFSET 1
939 #define CSR_MCONTROL_STORE_LENGTH 1
940 #define CSR_MCONTROL_STORE 2
942 * When set, the trigger fires on the virtual address or data of any
945 #define CSR_MCONTROL_LOAD_OFFSET 0
946 #define CSR_MCONTROL_LOAD_LENGTH 1
947 #define CSR_MCONTROL_LOAD 1
948 #define CSR_MCONTROL6 0x7a1
949 #define CSR_MCONTROL6_TYPE_OFFSET(XLEN) (XLEN + -4)
950 #define CSR_MCONTROL6_TYPE_LENGTH 4
951 #define CSR_MCONTROL6_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
952 #define CSR_MCONTROL6_DMODE_OFFSET(XLEN) (XLEN + -5)
953 #define CSR_MCONTROL6_DMODE_LENGTH 1
954 #define CSR_MCONTROL6_DMODE(XLEN) (1ULL<<(XLEN + -5))
956 * When set, enable this trigger in VS-mode.
957 * This bit is hard-wired to 0 if the hart does not support
958 * virtualization mode.
960 #define CSR_MCONTROL6_VS_OFFSET 0x18
961 #define CSR_MCONTROL6_VS_LENGTH 1
962 #define CSR_MCONTROL6_VS 0x1000000
964 * When set, enable this trigger in VU-mode.
965 * This bit is hard-wired to 0 if the hart does not support
966 * virtualization mode.
968 #define CSR_MCONTROL6_VU_OFFSET 0x17
969 #define CSR_MCONTROL6_VU_LENGTH 1
970 #define CSR_MCONTROL6_VU 0x800000
972 * If this bit is implemented then it must become set when this
973 * trigger fires and may become set when this trigger matches.
974 * The trigger's user can set or clear it at any
975 * time. It is used to determine which
976 * trigger(s) matched. If the bit is not implemented, it is always 0
977 * and writing it has no effect.
979 #define CSR_MCONTROL6_HIT_OFFSET 0x16
980 #define CSR_MCONTROL6_HIT_LENGTH 1
981 #define CSR_MCONTROL6_HIT 0x400000
983 * This bit determines the contents of the XLEN-bit compare values.
985 #define CSR_MCONTROL6_SELECT_OFFSET 0x15
986 #define CSR_MCONTROL6_SELECT_LENGTH 1
987 #define CSR_MCONTROL6_SELECT 0x200000
989 * address: There is at least one compare value and it contains the lowest
990 * virtual address of the access.
991 * In addition, it is recommended that there are additional compare
992 * values for the other accessed virtual addresses match.
993 * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
994 * and the other addresses are 0x4001, 0x4002, and 0x4003.)
996 #define CSR_MCONTROL6_SELECT_ADDRESS 0
998 * data: There is exactly one compare value and it contains the data
999 * value loaded or stored, or the instruction executed.
1000 * Any bits beyond the size of the data access will contain 0.
1002 #define CSR_MCONTROL6_SELECT_DATA 1
1003 #define CSR_MCONTROL6_TIMING_OFFSET 0x14
1004 #define CSR_MCONTROL6_TIMING_LENGTH 1
1005 #define CSR_MCONTROL6_TIMING 0x100000
1007 * before: The action for this trigger will be taken just before the
1008 * instruction that triggered it is committed, but after all preceding
1009 * instructions are committed. \Rxepc or \RcsrDpc (depending
1010 * on \FcsrMcontrolSixAction) must be set to the virtual address of the
1011 * instruction that matched.
1013 * If this is combined with \FcsrMcontrolSixLoad and
1014 * \FcsrMcontrolSixSelect=1 then a memory access will be
1015 * performed (including any side effects of performing such an access) even
1016 * though the load will not update its destination register. Debuggers
1017 * should consider this when setting such breakpoints on, for example,
1018 * memory-mapped I/O addresses.
1020 #define CSR_MCONTROL6_TIMING_BEFORE 0
1022 * after: The action for this trigger will be taken after the instruction
1023 * that triggered it is committed. It should be taken before the next
1024 * instruction is committed, but it is better to implement triggers imprecisely
1025 * than to not implement them at all. \Rxepc or
1026 * \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to
1027 * the virtual address of the next instruction that must be executed to
1028 * preserve the program flow.
1030 #define CSR_MCONTROL6_TIMING_AFTER 1
1032 * Most hardware will only implement one timing or the other, possibly
1033 * dependent on \FcsrMcontrolSixSelect, \FcsrMcontrolSixExecute,
1034 * \FcsrMcontrolSixLoad, and \FcsrMcontrolSixStore. This bit
1035 * primarily exists for the hardware to communicate to the debugger
1036 * what will happen. Hardware may implement the bit fully writable, in
1037 * which case the debugger has a little more control.
1039 * Data load triggers with \FcsrMcontrolSixTiming of 0 will result in the same load
1040 * happening again when the debugger lets the hart run. For data load
1041 * triggers, debuggers must first attempt to set the breakpoint with
1042 * \FcsrMcontrolSixTiming of 1.
1044 * If a trigger with \FcsrMcontrolSixTiming of 0 matches, it is
1045 * implementation-dependent whether that prevents a trigger with
1046 * \FcsrMcontrolSixTiming of 1 matching as well.
1048 #define CSR_MCONTROL6_SIZE_OFFSET 0x10
1049 #define CSR_MCONTROL6_SIZE_LENGTH 4
1050 #define CSR_MCONTROL6_SIZE 0xf0000
1052 * any: The trigger will attempt to match against an access of any size.
1053 * The behavior is only well-defined if $|select|=0$, or if the access
1056 #define CSR_MCONTROL6_SIZE_ANY 0
1058 * 8bit: The trigger will only match against 8-bit memory accesses.
1060 #define CSR_MCONTROL6_SIZE_8BIT 1
1062 * 16bit: The trigger will only match against 16-bit memory accesses or
1063 * execution of 16-bit instructions.
1065 #define CSR_MCONTROL6_SIZE_16BIT 2
1067 * 32bit: The trigger will only match against 32-bit memory accesses or
1068 * execution of 32-bit instructions.
1070 #define CSR_MCONTROL6_SIZE_32BIT 3
1072 * 48bit: The trigger will only match against execution of 48-bit instructions.
1074 #define CSR_MCONTROL6_SIZE_48BIT 4
1076 * 64bit: The trigger will only match against 64-bit memory accesses or
1077 * execution of 64-bit instructions.
1079 #define CSR_MCONTROL6_SIZE_64BIT 5
1081 * 80bit: The trigger will only match against execution of 80-bit instructions.
1083 #define CSR_MCONTROL6_SIZE_80BIT 6
1085 * 96bit: The trigger will only match against execution of 96-bit instructions.
1087 #define CSR_MCONTROL6_SIZE_96BIT 7
1089 * 112bit: The trigger will only match against execution of 112-bit instructions.
1091 #define CSR_MCONTROL6_SIZE_112BIT 8
1093 * 128bit: The trigger will only match against 128-bit memory accesses or
1094 * execution of 128-bit instructions.
1096 #define CSR_MCONTROL6_SIZE_128BIT 9
1098 * An implementation must support the value of 0, but all other values
1099 * are optional. When an implementation supports address triggers
1100 * (\FcsrMcontrolSixSelect=0), it is recommended that those triggers
1101 * support every access size that the hart supports, as well as for
1102 * every instruction size that the hart supports.
1104 * Implementations such as RV32D or RV64V are able to perform loads
1105 * and stores that are wider than XLEN. Custom extensions may also
1106 * support instructions that are wider than XLEN. Because
1107 * \RcsrTdataTwo is of size XLEN, there is a known limitation that
1108 * data value triggers (\FcsrMcontrolSixSelect=1) can only be supported
1109 * for access sizes up to XLEN bits. When an implementation supports
1110 * data value triggers (\FcsrMcontrolSixSelect=1), it is recommended
1111 * that those triggers support every access size up to XLEN that the
1112 * hart supports, as well as for every instruction length up to XLEN
1113 * that the hart supports.
1116 * The action to take when the trigger fires. The values are explained
1117 * in Table~\ref{tab:action}.
1119 #define CSR_MCONTROL6_ACTION_OFFSET 0xc
1120 #define CSR_MCONTROL6_ACTION_LENGTH 4
1121 #define CSR_MCONTROL6_ACTION 0xf000
1125 #define CSR_MCONTROL6_ACTION_BREAKPOINT 0
1129 #define CSR_MCONTROL6_ACTION_DEBUG_MODE 1
1133 #define CSR_MCONTROL6_ACTION_TRACE_ON 2
1137 #define CSR_MCONTROL6_ACTION_TRACE_OFF 3
1141 #define CSR_MCONTROL6_ACTION_TRACE_NOTIFY 4
1145 #define CSR_MCONTROL6_ACTION_EXTERNAL0 8
1149 #define CSR_MCONTROL6_ACTION_EXTERNAL1 9
1150 #define CSR_MCONTROL6_CHAIN_OFFSET 0xb
1151 #define CSR_MCONTROL6_CHAIN_LENGTH 1
1152 #define CSR_MCONTROL6_CHAIN 0x800
1154 * disabled: When this trigger matches, the configured action is taken.
1156 #define CSR_MCONTROL6_CHAIN_DISABLED 0
1158 * enabled: While this trigger does not match, it prevents the trigger with
1159 * the next index from matching.
1161 #define CSR_MCONTROL6_CHAIN_ENABLED 1
1163 * A trigger chain starts on the first trigger with $|chain|=1$ after
1164 * a trigger with $|chain|=0$, or simply on the first trigger if that
1165 * has $|chain|=1$. It ends on the first trigger after that which has
1166 * $|chain|=0$. This final trigger is part of the chain. The action
1167 * on all but the final trigger is ignored. The action on that final
1168 * trigger will be taken if and only if all the triggers in the chain
1169 * match at the same time.
1171 * Debuggers should not terminate a chain with a trigger with a
1172 * different type. It is undefined when exactly such a chain fires.
1174 * Because \FcsrMcontrolSixChain affects the next trigger, hardware must zero it in
1175 * writes to \RcsrMcontrolSix that set \FcsrTdataOneDmode to 0 if the next trigger has
1176 * \FcsrTdataOneDmode of 1.
1177 * In addition hardware should ignore writes to \RcsrMcontrolSix that set
1178 * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and
1179 * \FcsrMcontrolSixChain of 1. Debuggers must avoid the latter case by checking
1180 * \FcsrMcontrolSixChain on the previous trigger if they're writing \RcsrMcontrolSix.
1182 * Implementations that wish to limit the maximum length of a trigger
1183 * chain (eg. to meet timing requirements) may do so by zeroing
1184 * \FcsrMcontrolSixChain in writes to \RcsrMcontrolSix that would make the chain too long.
1186 #define CSR_MCONTROL6_MATCH_OFFSET 7
1187 #define CSR_MCONTROL6_MATCH_LENGTH 4
1188 #define CSR_MCONTROL6_MATCH 0x780
1190 * equal: Matches when any compare value equals \RcsrTdataTwo.
1192 #define CSR_MCONTROL6_MATCH_EQUAL 0
1194 * napot: Matches when the top $M$ bits of any compare value match the top
1195 * $M$ bits of \RcsrTdataTwo.
1196 * $M$ is $|XLEN|-1$ minus the index of the least-significant bit
1197 * containing 0 in \RcsrTdataTwo.
1198 * \RcsrTdataTwo is WARL and if bits $|maskmax6|-1$:0 are written with all
1199 * ones then bit $|maskmax6|-1$ will be set to 0 while the values of bits $|maskmax6|-2$:0
1201 * Legal values for \RcsrTdataTwo require $M + |maskmax6| \geq |XLEN|$ and $M\gt0$.
1202 * See above for how to determine maskmax6.
1204 #define CSR_MCONTROL6_MATCH_NAPOT 1
1206 * ge: Matches when any compare value is greater than (unsigned) or
1207 * equal to \RcsrTdataTwo.
1209 #define CSR_MCONTROL6_MATCH_GE 2
1211 * lt: Matches when any compare value is less than (unsigned)
1214 #define CSR_MCONTROL6_MATCH_LT 3
1216 * mask low: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
1217 * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
1218 * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with
1219 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
1221 #define CSR_MCONTROL6_MATCH_MASK_LOW 4
1223 * mask high: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare
1224 * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
1225 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with
1226 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
1228 #define CSR_MCONTROL6_MATCH_MASK_HIGH 5
1230 * not equal: Matches when \FcsrMcontrolSixMatch$=0$ would not match.
1232 #define CSR_MCONTROL6_MATCH_NOT_EQUAL 8
1234 * not napot: Matches when \FcsrMcontrolSixMatch$=1$ would not match.
1236 #define CSR_MCONTROL6_MATCH_NOT_NAPOT 9
1238 * not mask low: Matches when \FcsrMcontrolSixMatch$=4$ would not match.
1240 #define CSR_MCONTROL6_MATCH_NOT_MASK_LOW 12
1242 * not mask high: Matches when \FcsrMcontrolSixMatch$=5$ would not match.
1244 #define CSR_MCONTROL6_MATCH_NOT_MASK_HIGH 13
1246 * Other values are reserved for future use.
1248 * All comparisons only look at the lower XLEN (in the current mode)
1249 * bits of the compare values and of \RcsrTdataTwo.
1250 * When \FcsrMcontrolSelect=1 and access size is N, this is further
1251 * reduced, and comparisons only look at the lower N bits of the
1252 * compare values and of \RcsrTdataTwo.
1255 * When set, enable this trigger in M-mode.
1257 #define CSR_MCONTROL6_M_OFFSET 6
1258 #define CSR_MCONTROL6_M_LENGTH 1
1259 #define CSR_MCONTROL6_M 0x40
1261 * When set, enable this trigger in S/HS-mode.
1262 * This bit is hard-wired to 0 if the hart does not support
1265 #define CSR_MCONTROL6_S_OFFSET 4
1266 #define CSR_MCONTROL6_S_LENGTH 1
1267 #define CSR_MCONTROL6_S 0x10
1269 * When set, enable this trigger in U-mode.
1270 * This bit is hard-wired to 0 if the hart does not support
1273 #define CSR_MCONTROL6_U_OFFSET 3
1274 #define CSR_MCONTROL6_U_LENGTH 1
1275 #define CSR_MCONTROL6_U 8
1277 * When set, the trigger fires on the virtual address or opcode of an
1278 * instruction that is executed.
1280 #define CSR_MCONTROL6_EXECUTE_OFFSET 2
1281 #define CSR_MCONTROL6_EXECUTE_LENGTH 1
1282 #define CSR_MCONTROL6_EXECUTE 4
1284 * When set, the trigger fires on the virtual address or data of any
1287 #define CSR_MCONTROL6_STORE_OFFSET 1
1288 #define CSR_MCONTROL6_STORE_LENGTH 1
1289 #define CSR_MCONTROL6_STORE 2
1291 * When set, the trigger fires on the virtual address or data of any
1294 #define CSR_MCONTROL6_LOAD_OFFSET 0
1295 #define CSR_MCONTROL6_LOAD_LENGTH 1
1296 #define CSR_MCONTROL6_LOAD 1
1297 #define CSR_ICOUNT 0x7a1
1298 #define CSR_ICOUNT_TYPE_OFFSET(XLEN) (XLEN + -4)
1299 #define CSR_ICOUNT_TYPE_LENGTH 4
1300 #define CSR_ICOUNT_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
1301 #define CSR_ICOUNT_DMODE_OFFSET(XLEN) (XLEN + -5)
1302 #define CSR_ICOUNT_DMODE_LENGTH 1
1303 #define CSR_ICOUNT_DMODE(XLEN) (1ULL<<(XLEN + -5))
1305 * When set, enable this trigger in VS-mode.
1306 * This bit is hard-wired to 0 if the hart does not support
1307 * virtualization mode.
1309 #define CSR_ICOUNT_VS_OFFSET 0x1a
1310 #define CSR_ICOUNT_VS_LENGTH 1
1311 #define CSR_ICOUNT_VS 0x4000000
1313 * When set, enable this trigger in VU-mode.
1314 * This bit is hard-wired to 0 if the hart does not support
1315 * virtualization mode.
1317 #define CSR_ICOUNT_VU_OFFSET 0x19
1318 #define CSR_ICOUNT_VU_LENGTH 1
1319 #define CSR_ICOUNT_VU 0x2000000
1321 * If this bit is implemented, the hardware sets it when this
1322 * trigger fires. The trigger's user can set or clear it at any
1323 * time. It is used to determine which
1324 * trigger(s) fires. If the bit is not implemented, it is always 0
1325 * and writing it has no effect.
1327 #define CSR_ICOUNT_HIT_OFFSET 0x18
1328 #define CSR_ICOUNT_HIT_LENGTH 1
1329 #define CSR_ICOUNT_HIT 0x1000000
1331 * The trigger will generally fire after \FcsrIcountCount instructions
1332 * in enabled modes have been executed. See above for the precise behavior.
1334 #define CSR_ICOUNT_COUNT_OFFSET 0xa
1335 #define CSR_ICOUNT_COUNT_LENGTH 0xe
1336 #define CSR_ICOUNT_COUNT 0xfffc00
1338 * When set, enable this trigger in M-mode.
1340 #define CSR_ICOUNT_M_OFFSET 9
1341 #define CSR_ICOUNT_M_LENGTH 1
1342 #define CSR_ICOUNT_M 0x200
1344 * This bit becomes set when \FcsrIcountCount is decremented from 1
1345 * to 0. It is cleared when the trigger fires, which will happen just
1346 * before executing the next instruction in one of the enabled modes.
1348 #define CSR_ICOUNT_PENDING_OFFSET 8
1349 #define CSR_ICOUNT_PENDING_LENGTH 1
1350 #define CSR_ICOUNT_PENDING 0x100
1352 * When set, enable this trigger in S/HS-mode.
1353 * This bit is hard-wired to 0 if the hart does not support
1356 #define CSR_ICOUNT_S_OFFSET 7
1357 #define CSR_ICOUNT_S_LENGTH 1
1358 #define CSR_ICOUNT_S 0x80
1360 * When set, enable this trigger in U-mode.
1361 * This bit is hard-wired to 0 if the hart does not support
1364 #define CSR_ICOUNT_U_OFFSET 6
1365 #define CSR_ICOUNT_U_LENGTH 1
1366 #define CSR_ICOUNT_U 0x40
1368 * The action to take when the trigger fires. The values are explained
1369 * in Table~\ref{tab:action}.
1371 #define CSR_ICOUNT_ACTION_OFFSET 0
1372 #define CSR_ICOUNT_ACTION_LENGTH 6
1373 #define CSR_ICOUNT_ACTION 0x3f
1377 #define CSR_ICOUNT_ACTION_BREAKPOINT 0
1381 #define CSR_ICOUNT_ACTION_DEBUG_MODE 1
1385 #define CSR_ICOUNT_ACTION_TRACE_ON 2
1389 #define CSR_ICOUNT_ACTION_TRACE_OFF 3
1393 #define CSR_ICOUNT_ACTION_TRACE_NOTIFY 4
1397 #define CSR_ICOUNT_ACTION_EXTERNAL0 8
1401 #define CSR_ICOUNT_ACTION_EXTERNAL1 9
1402 #define CSR_ITRIGGER 0x7a1
1403 #define CSR_ITRIGGER_TYPE_OFFSET(XLEN) (XLEN + -4)
1404 #define CSR_ITRIGGER_TYPE_LENGTH 4
1405 #define CSR_ITRIGGER_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
1406 #define CSR_ITRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5)
1407 #define CSR_ITRIGGER_DMODE_LENGTH 1
1408 #define CSR_ITRIGGER_DMODE(XLEN) (1ULL<<(XLEN + -5))
1410 * If this bit is implemented, the hardware sets it when this
1411 * trigger matches. The trigger's user can set or clear it at any
1412 * time. It is used to determine which
1413 * trigger(s) matched. If the bit is not implemented, it is always 0
1414 * and writing it has no effect.
1416 #define CSR_ITRIGGER_HIT_OFFSET(XLEN) (XLEN + -6)
1417 #define CSR_ITRIGGER_HIT_LENGTH 1
1418 #define CSR_ITRIGGER_HIT(XLEN) (1ULL<<(XLEN + -6))
1420 * When set, enable this trigger for interrupts that are taken from VS
1422 * This bit is hard-wired to 0 if the hart does not support
1423 * virtualization mode.
1425 #define CSR_ITRIGGER_VS_OFFSET 0xc
1426 #define CSR_ITRIGGER_VS_LENGTH 1
1427 #define CSR_ITRIGGER_VS 0x1000
1429 * When set, enable this trigger for interrupts that are taken from VU
1431 * This bit is hard-wired to 0 if the hart does not support
1432 * virtualization mode.
1434 #define CSR_ITRIGGER_VU_OFFSET 0xb
1435 #define CSR_ITRIGGER_VU_LENGTH 1
1436 #define CSR_ITRIGGER_VU 0x800
1438 * When set, non-maskable interrupts cause this
1439 * trigger to fire if the trigger is enabled for the current mode.
1441 #define CSR_ITRIGGER_NMI_OFFSET 0xa
1442 #define CSR_ITRIGGER_NMI_LENGTH 1
1443 #define CSR_ITRIGGER_NMI 0x400
1445 * When set, enable this trigger for interrupts that are taken from M
1448 #define CSR_ITRIGGER_M_OFFSET 9
1449 #define CSR_ITRIGGER_M_LENGTH 1
1450 #define CSR_ITRIGGER_M 0x200
1452 * When set, enable this trigger for interrupts that are taken from S/HS
1454 * This bit is hard-wired to 0 if the hart does not support
1457 #define CSR_ITRIGGER_S_OFFSET 7
1458 #define CSR_ITRIGGER_S_LENGTH 1
1459 #define CSR_ITRIGGER_S 0x80
1461 * When set, enable this trigger for interrupts that are taken from U
1463 * This bit is hard-wired to 0 if the hart does not support
1466 #define CSR_ITRIGGER_U_OFFSET 6
1467 #define CSR_ITRIGGER_U_LENGTH 1
1468 #define CSR_ITRIGGER_U 0x40
1470 * The action to take when the trigger fires. The values are explained
1471 * in Table~\ref{tab:action}.
1473 #define CSR_ITRIGGER_ACTION_OFFSET 0
1474 #define CSR_ITRIGGER_ACTION_LENGTH 6
1475 #define CSR_ITRIGGER_ACTION 0x3f
1479 #define CSR_ITRIGGER_ACTION_BREAKPOINT 0
1483 #define CSR_ITRIGGER_ACTION_DEBUG_MODE 1
1487 #define CSR_ITRIGGER_ACTION_TRACE_ON 2
1491 #define CSR_ITRIGGER_ACTION_TRACE_OFF 3
1495 #define CSR_ITRIGGER_ACTION_TRACE_NOTIFY 4
1499 #define CSR_ITRIGGER_ACTION_EXTERNAL0 8
1503 #define CSR_ITRIGGER_ACTION_EXTERNAL1 9
1504 #define CSR_ETRIGGER 0x7a1
1505 #define CSR_ETRIGGER_TYPE_OFFSET(XLEN) (XLEN + -4)
1506 #define CSR_ETRIGGER_TYPE_LENGTH 4
1507 #define CSR_ETRIGGER_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
1508 #define CSR_ETRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5)
1509 #define CSR_ETRIGGER_DMODE_LENGTH 1
1510 #define CSR_ETRIGGER_DMODE(XLEN) (1ULL<<(XLEN + -5))
1512 * If this bit is implemented, the hardware sets it when this
1513 * trigger matches. The trigger's user can set or clear it at any
1514 * time. It is used to determine which
1515 * trigger(s) matched. If the bit is not implemented, it is always 0
1516 * and writing it has no effect.
1518 #define CSR_ETRIGGER_HIT_OFFSET(XLEN) (XLEN + -6)
1519 #define CSR_ETRIGGER_HIT_LENGTH 1
1520 #define CSR_ETRIGGER_HIT(XLEN) (1ULL<<(XLEN + -6))
1522 * When set, enable this trigger for exceptions that are taken from VS
1524 * This bit is hard-wired to 0 if the hart does not support
1525 * virtualization mode.
1527 #define CSR_ETRIGGER_VS_OFFSET 0xc
1528 #define CSR_ETRIGGER_VS_LENGTH 1
1529 #define CSR_ETRIGGER_VS 0x1000
1531 * When set, enable this trigger for exceptions that are taken from VU
1533 * This bit is hard-wired to 0 if the hart does not support
1534 * virtualization mode.
1536 #define CSR_ETRIGGER_VU_OFFSET 0xb
1537 #define CSR_ETRIGGER_VU_LENGTH 1
1538 #define CSR_ETRIGGER_VU 0x800
1540 * When set, enable this trigger for exceptions that are taken from M
1543 #define CSR_ETRIGGER_M_OFFSET 9
1544 #define CSR_ETRIGGER_M_LENGTH 1
1545 #define CSR_ETRIGGER_M 0x200
1547 * When set, enable this trigger for exceptions that are taken from S/HS
1549 * This bit is hard-wired to 0 if the hart does not support
1552 #define CSR_ETRIGGER_S_OFFSET 7
1553 #define CSR_ETRIGGER_S_LENGTH 1
1554 #define CSR_ETRIGGER_S 0x80
1556 * When set, enable this trigger for exceptions that are taken from U
1558 * This bit is hard-wired to 0 if the hart does not support
1561 #define CSR_ETRIGGER_U_OFFSET 6
1562 #define CSR_ETRIGGER_U_LENGTH 1
1563 #define CSR_ETRIGGER_U 0x40
1565 * The action to take when the trigger fires. The values are explained
1566 * in Table~\ref{tab:action}.
1568 #define CSR_ETRIGGER_ACTION_OFFSET 0
1569 #define CSR_ETRIGGER_ACTION_LENGTH 6
1570 #define CSR_ETRIGGER_ACTION 0x3f
1574 #define CSR_ETRIGGER_ACTION_BREAKPOINT 0
1578 #define CSR_ETRIGGER_ACTION_DEBUG_MODE 1
1582 #define CSR_ETRIGGER_ACTION_TRACE_ON 2
1586 #define CSR_ETRIGGER_ACTION_TRACE_OFF 3
1590 #define CSR_ETRIGGER_ACTION_TRACE_NOTIFY 4
1594 #define CSR_ETRIGGER_ACTION_EXTERNAL0 8
1598 #define CSR_ETRIGGER_ACTION_EXTERNAL1 9
1599 #define CSR_TMEXTTRIGGER 0x7a1
1600 #define CSR_TMEXTTRIGGER_TYPE_OFFSET(XLEN) (XLEN + -4)
1601 #define CSR_TMEXTTRIGGER_TYPE_LENGTH 4
1602 #define CSR_TMEXTTRIGGER_TYPE(XLEN) (0xf * (1ULL<<(XLEN + -4)))
1603 #define CSR_TMEXTTRIGGER_DMODE_OFFSET(XLEN) (XLEN + -5)
1604 #define CSR_TMEXTTRIGGER_DMODE_LENGTH 1
1605 #define CSR_TMEXTTRIGGER_DMODE(XLEN) (1ULL<<(XLEN + -5))
1607 * If this bit is implemented, the hardware sets it when this
1608 * trigger matches. The trigger's user can set or clear it at any
1609 * time. It is used to determine which
1610 * trigger(s) matched. If the bit is not implemented, it is always 0
1611 * and writing it has no effect.
1613 #define CSR_TMEXTTRIGGER_HIT_OFFSET(XLEN) (XLEN + -6)
1614 #define CSR_TMEXTTRIGGER_HIT_LENGTH 1
1615 #define CSR_TMEXTTRIGGER_HIT(XLEN) (1ULL<<(XLEN + -6))
1617 * This optional bit, when set, causes this trigger to fire whenever an attached
1618 * interrupt controller signals a trigger.
1620 #define CSR_TMEXTTRIGGER_INTCTL_OFFSET 0x16
1621 #define CSR_TMEXTTRIGGER_INTCTL_LENGTH 1
1622 #define CSR_TMEXTTRIGGER_INTCTL 0x400000
1624 * Selects any combination of up to 16 external debug trigger inputs
1625 * that cause this trigger to fire.
1627 #define CSR_TMEXTTRIGGER_SELECT_OFFSET 6
1628 #define CSR_TMEXTTRIGGER_SELECT_LENGTH 0x10
1629 #define CSR_TMEXTTRIGGER_SELECT 0x3fffc0
1631 * The action to take when the trigger fires. The values are explained
1632 * in Table~\ref{tab:action}.
1634 #define CSR_TMEXTTRIGGER_ACTION_OFFSET 0
1635 #define CSR_TMEXTTRIGGER_ACTION_LENGTH 6
1636 #define CSR_TMEXTTRIGGER_ACTION 0x3f
1640 #define CSR_TMEXTTRIGGER_ACTION_BREAKPOINT 0
1644 #define CSR_TMEXTTRIGGER_ACTION_DEBUG_MODE 1
1648 #define CSR_TMEXTTRIGGER_ACTION_TRACE_ON 2
1652 #define CSR_TMEXTTRIGGER_ACTION_TRACE_OFF 3
1656 #define CSR_TMEXTTRIGGER_ACTION_TRACE_NOTIFY 4
1660 #define CSR_TMEXTTRIGGER_ACTION_EXTERNAL0 8
1664 #define CSR_TMEXTTRIGGER_ACTION_EXTERNAL1 9
1665 #define CSR_TEXTRA32 0x7a3
1667 * Data used together with \FcsrTextraThirtytwoMhselect.
1669 #define CSR_TEXTRA32_MHVALUE_OFFSET 0x1a
1670 #define CSR_TEXTRA32_MHVALUE_LENGTH 6
1671 #define CSR_TEXTRA32_MHVALUE 0xfc000000U
1672 #define CSR_TEXTRA32_MHSELECT_OFFSET 0x17
1673 #define CSR_TEXTRA32_MHSELECT_LENGTH 3
1674 #define CSR_TEXTRA32_MHSELECT 0x3800000
1676 * ignore: Ignore \FcsrTextraThirtytwoMhvalue.
1678 #define CSR_TEXTRA32_MHSELECT_IGNORE 0
1680 * mcontext: This trigger will only match if the low bits of
1681 * \RcsrMcontext/\RcsrHcontext equal \FcsrTextraThirtytwoMhvalue.
1683 #define CSR_TEXTRA32_MHSELECT_MCONTEXT 4
1685 * 1, 5 (mcontext\_select): This trigger will only match if the low bits of
1686 * \RcsrMcontext/\RcsrHcontext equal \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}.
1688 * 2, 6 (vmid\_select): This trigger will only match if VMID in hgatp equals the lower VMIDMAX
1689 * (defined in the Privileged Spec) bits of \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}.
1691 * 3, 7 (reserved): Reserved.
1693 * If the H extension is not supported, the only legal values are 0 and 4.
1696 * When the least significant bit of this field is 1, it causes bits 7:0
1697 * in the comparison to be ignored, when \FcsrTextraThirtytwoSselect=1.
1698 * When the next most significant bit of this field is 1, it causes bits 15:8
1699 * to be ignored in the comparison, when \FcsrTextraThirtytwoSselect=1.
1701 #define CSR_TEXTRA32_SBYTEMASK_OFFSET 0x12
1702 #define CSR_TEXTRA32_SBYTEMASK_LENGTH 2
1703 #define CSR_TEXTRA32_SBYTEMASK 0xc0000
1705 * Data used together with \FcsrTextraThirtytwoSselect.
1707 * This field should be tied to 0 when S-mode is not supported.
1709 #define CSR_TEXTRA32_SVALUE_OFFSET 2
1710 #define CSR_TEXTRA32_SVALUE_LENGTH 0x10
1711 #define CSR_TEXTRA32_SVALUE 0x3fffc
1712 #define CSR_TEXTRA32_SSELECT_OFFSET 0
1713 #define CSR_TEXTRA32_SSELECT_LENGTH 2
1714 #define CSR_TEXTRA32_SSELECT 3
1716 * ignore: Ignore \FcsrTextraThirtytwoSvalue.
1718 #define CSR_TEXTRA32_SSELECT_IGNORE 0
1720 * scontext: This trigger will only match if the low bits of
1721 * \RcsrScontext equal \FcsrTextraThirtytwoSvalue.
1723 #define CSR_TEXTRA32_SSELECT_SCONTEXT 1
1725 * asid: This trigger will only match if:
1726 * \begin{itemize}[noitemsep,nolistsep]
1727 * \item the mode is VS-mode or VU-mode and ASID in \Rvsatp
1728 * equals the lower ASIDMAX (defined in the Privileged Spec) bits
1729 * of \FcsrTextraThirtytwoSvalue.
1730 * \item in all other modes, ASID in \Rsatp equals the lower
1731 * ASIDMAX (defined in the Privileged Spec) bits of
1732 * \FcsrTextraThirtytwoSvalue.
1735 #define CSR_TEXTRA32_SSELECT_ASID 2
1737 * This field should be tied to 0 when S-mode is not supported.
1739 #define CSR_TEXTRA64 0x7a3
1740 #define CSR_TEXTRA64_MHVALUE_OFFSET 0x33
1741 #define CSR_TEXTRA64_MHVALUE_LENGTH 0xd
1742 #define CSR_TEXTRA64_MHVALUE 0xfff8000000000000ULL
1743 #define CSR_TEXTRA64_MHSELECT_OFFSET 0x30
1744 #define CSR_TEXTRA64_MHSELECT_LENGTH 3
1745 #define CSR_TEXTRA64_MHSELECT 0x7000000000000ULL
1747 * When the least significant bit of this field is 1, it causes bits 7:0
1748 * in the comparison to be ignored, when \FcsrTextraSixtyfourSselect=1.
1749 * Likewise, the second bit controls the comparison of bits 15:8,
1750 * third bit controls the comparison of bits 23:16,
1751 * fourth bit controls the comparison of bits 31:24, and
1752 * fifth bit controls the comparison of bits 33:32.
1754 #define CSR_TEXTRA64_SBYTEMASK_OFFSET 0x24
1755 #define CSR_TEXTRA64_SBYTEMASK_LENGTH 5
1756 #define CSR_TEXTRA64_SBYTEMASK 0x1f000000000ULL
1757 #define CSR_TEXTRA64_SVALUE_OFFSET 2
1758 #define CSR_TEXTRA64_SVALUE_LENGTH 0x22
1759 #define CSR_TEXTRA64_SVALUE 0xffffffffcULL
1760 #define CSR_TEXTRA64_SSELECT_OFFSET 0
1761 #define CSR_TEXTRA64_SSELECT_LENGTH 2
1762 #define CSR_TEXTRA64_SSELECT 3
1763 #define DM_DMSTATUS 0x11
1764 #define DM_DMSTATUS_NDMRESETPENDING_OFFSET 0x18
1765 #define DM_DMSTATUS_NDMRESETPENDING_LENGTH 1
1766 #define DM_DMSTATUS_NDMRESETPENDING 0x1000000
1768 * false: Unimplemented, or \FdmDmcontrolNdmreset is zero and no ndmreset is currently
1771 #define DM_DMSTATUS_NDMRESETPENDING_FALSE 0
1773 * true: \FdmDmcontrolNdmreset is currently nonzero, or there is an ndmreset in progress.
1775 #define DM_DMSTATUS_NDMRESETPENDING_TRUE 1
1776 #define DM_DMSTATUS_STICKYUNAVAIL_OFFSET 0x17
1777 #define DM_DMSTATUS_STICKYUNAVAIL_LENGTH 1
1778 #define DM_DMSTATUS_STICKYUNAVAIL 0x800000
1780 * current: The per-hart {\tt unavail} bits reflect the current state of the hart.
1782 #define DM_DMSTATUS_STICKYUNAVAIL_CURRENT 0
1784 * sticky: The per-hart {\tt unavail} bits are sticky. Once they are set, they will
1785 * not clear until the debugger acknowledges them using \FdmDmcontrolAckunavail.
1787 #define DM_DMSTATUS_STICKYUNAVAIL_STICKY 1
1789 * If 1, then there is an implicit {\tt ebreak} instruction at the
1790 * non-existent word immediately after the Program Buffer. This saves
1791 * the debugger from having to write the {\tt ebreak} itself, and
1792 * allows the Program Buffer to be one word smaller.
1794 * This must be 1 when \FdmAbstractcsProgbufsize is 1.
1796 #define DM_DMSTATUS_IMPEBREAK_OFFSET 0x16
1797 #define DM_DMSTATUS_IMPEBREAK_LENGTH 1
1798 #define DM_DMSTATUS_IMPEBREAK 0x400000
1800 * This field is 1 when all currently selected harts have been reset
1801 * and reset has not been acknowledged for any of them.
1803 #define DM_DMSTATUS_ALLHAVERESET_OFFSET 0x13
1804 #define DM_DMSTATUS_ALLHAVERESET_LENGTH 1
1805 #define DM_DMSTATUS_ALLHAVERESET 0x80000
1807 * This field is 1 when at least one currently selected hart has been
1808 * reset and reset has not been acknowledged for that hart.
1810 #define DM_DMSTATUS_ANYHAVERESET_OFFSET 0x12
1811 #define DM_DMSTATUS_ANYHAVERESET_LENGTH 1
1812 #define DM_DMSTATUS_ANYHAVERESET 0x40000
1814 * This field is 1 when all currently selected harts have their
1815 * resume ack bit\index{resume ack bit} set.
1817 #define DM_DMSTATUS_ALLRESUMEACK_OFFSET 0x11
1818 #define DM_DMSTATUS_ALLRESUMEACK_LENGTH 1
1819 #define DM_DMSTATUS_ALLRESUMEACK 0x20000
1821 * This field is 1 when any currently selected hart has its
1822 * resume ack bit\index{resume ack bit} set.
1824 #define DM_DMSTATUS_ANYRESUMEACK_OFFSET 0x10
1825 #define DM_DMSTATUS_ANYRESUMEACK_LENGTH 1
1826 #define DM_DMSTATUS_ANYRESUMEACK 0x10000
1828 * This field is 1 when all currently selected harts do not exist in
1829 * this hardware platform.
1831 #define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 0xf
1832 #define DM_DMSTATUS_ALLNONEXISTENT_LENGTH 1
1833 #define DM_DMSTATUS_ALLNONEXISTENT 0x8000
1835 * This field is 1 when any currently selected hart does not exist in
1836 * this hardware platform.
1838 #define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 0xe
1839 #define DM_DMSTATUS_ANYNONEXISTENT_LENGTH 1
1840 #define DM_DMSTATUS_ANYNONEXISTENT 0x4000
1842 * This field is 1 when all currently selected harts are
1843 * unavailable, or (if \FdmDmstatusStickyunavail is 1) were
1844 * unavailable without that being acknowledged.
1846 #define DM_DMSTATUS_ALLUNAVAIL_OFFSET 0xd
1847 #define DM_DMSTATUS_ALLUNAVAIL_LENGTH 1
1848 #define DM_DMSTATUS_ALLUNAVAIL 0x2000
1850 * This field is 1 when any currently selected hart is unavailable,
1851 * or (if \FdmDmstatusStickyunavail is 1) was unavailable without
1852 * that being acknowledged.
1854 #define DM_DMSTATUS_ANYUNAVAIL_OFFSET 0xc
1855 #define DM_DMSTATUS_ANYUNAVAIL_LENGTH 1
1856 #define DM_DMSTATUS_ANYUNAVAIL 0x1000
1858 * This field is 1 when all currently selected harts are running.
1860 #define DM_DMSTATUS_ALLRUNNING_OFFSET 0xb
1861 #define DM_DMSTATUS_ALLRUNNING_LENGTH 1
1862 #define DM_DMSTATUS_ALLRUNNING 0x800
1864 * This field is 1 when any currently selected hart is running.
1866 #define DM_DMSTATUS_ANYRUNNING_OFFSET 0xa
1867 #define DM_DMSTATUS_ANYRUNNING_LENGTH 1
1868 #define DM_DMSTATUS_ANYRUNNING 0x400
1870 * This field is 1 when all currently selected harts are halted.
1872 #define DM_DMSTATUS_ALLHALTED_OFFSET 9
1873 #define DM_DMSTATUS_ALLHALTED_LENGTH 1
1874 #define DM_DMSTATUS_ALLHALTED 0x200
1876 * This field is 1 when any currently selected hart is halted.
1878 #define DM_DMSTATUS_ANYHALTED_OFFSET 8
1879 #define DM_DMSTATUS_ANYHALTED_LENGTH 1
1880 #define DM_DMSTATUS_ANYHALTED 0x100
1881 #define DM_DMSTATUS_AUTHENTICATED_OFFSET 7
1882 #define DM_DMSTATUS_AUTHENTICATED_LENGTH 1
1883 #define DM_DMSTATUS_AUTHENTICATED 0x80
1885 * false: Authentication is required before using the DM.
1887 #define DM_DMSTATUS_AUTHENTICATED_FALSE 0
1889 * true: The authentication check has passed.
1891 #define DM_DMSTATUS_AUTHENTICATED_TRUE 1
1893 * On components that don't implement authentication, this bit must be
1896 #define DM_DMSTATUS_AUTHBUSY_OFFSET 6
1897 #define DM_DMSTATUS_AUTHBUSY_LENGTH 1
1898 #define DM_DMSTATUS_AUTHBUSY 0x40
1900 * ready: The authentication module is ready to process the next
1901 * read/write to \RdmAuthdata.
1903 #define DM_DMSTATUS_AUTHBUSY_READY 0
1905 * busy: The authentication module is busy. Accessing \RdmAuthdata results
1906 * in unspecified behavior.
1908 #define DM_DMSTATUS_AUTHBUSY_BUSY 1
1910 * \FdmDmstatusAuthbusy only becomes set in immediate response to an access to
1914 * 1 if this Debug Module supports halt-on-reset functionality
1915 * controllable by the \FdmDmcontrolSetresethaltreq and \FdmDmcontrolClrresethaltreq bits.
1918 #define DM_DMSTATUS_HASRESETHALTREQ_OFFSET 5
1919 #define DM_DMSTATUS_HASRESETHALTREQ_LENGTH 1
1920 #define DM_DMSTATUS_HASRESETHALTREQ 0x20
1921 #define DM_DMSTATUS_CONFSTRPTRVALID_OFFSET 4
1922 #define DM_DMSTATUS_CONFSTRPTRVALID_LENGTH 1
1923 #define DM_DMSTATUS_CONFSTRPTRVALID 0x10
1925 * invalid: \RdmConfstrptrZero--\RdmConfstrptrThree hold information which
1926 * is not relevant to the configuration structure.
1928 #define DM_DMSTATUS_CONFSTRPTRVALID_INVALID 0
1930 * valid: \RdmConfstrptrZero--\RdmConfstrptrThree hold the address of the
1931 * configuration structure.
1933 #define DM_DMSTATUS_CONFSTRPTRVALID_VALID 1
1934 #define DM_DMSTATUS_VERSION_OFFSET 0
1935 #define DM_DMSTATUS_VERSION_LENGTH 4
1936 #define DM_DMSTATUS_VERSION 0xf
1938 * none: There is no Debug Module present.
1940 #define DM_DMSTATUS_VERSION_NONE 0
1942 * 0.11: There is a Debug Module and it conforms to version 0.11 of this
1945 #define DM_DMSTATUS_VERSION_0_11 1
1947 * 0.13: There is a Debug Module and it conforms to version 0.13 of this
1950 #define DM_DMSTATUS_VERSION_0_13 2
1952 * 1.0: There is a Debug Module and it conforms to version 1.0 of this
1955 #define DM_DMSTATUS_VERSION_1_0 3
1957 * custom: There is a Debug Module but it does not conform to any
1958 * available version of this spec.
1960 #define DM_DMSTATUS_VERSION_CUSTOM 15
1961 #define DM_DMCONTROL 0x10
1963 * Writing 0 clears the halt request bit for all currently selected
1964 * harts. This may cancel outstanding halt requests for those harts.
1966 * Writing 1 sets the halt request bit for all currently selected
1967 * harts. Running harts will halt whenever their halt request bit is
1970 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1972 #define DM_DMCONTROL_HALTREQ_OFFSET 0x1f
1973 #define DM_DMCONTROL_HALTREQ_LENGTH 1
1974 #define DM_DMCONTROL_HALTREQ 0x80000000U
1976 * Writing 1 causes the currently selected harts to resume once, if
1977 * they are halted when the write occurs. It also clears the resume
1978 * ack bit for those harts.
1980 * \FdmDmcontrolResumereq is ignored if \FdmDmcontrolHaltreq is set.
1982 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1984 #define DM_DMCONTROL_RESUMEREQ_OFFSET 0x1e
1985 #define DM_DMCONTROL_RESUMEREQ_LENGTH 1
1986 #define DM_DMCONTROL_RESUMEREQ 0x40000000
1988 * This optional field writes the reset bit for all the currently
1989 * selected harts. To perform a reset the debugger writes 1, and then
1990 * writes 0 to deassert the reset signal.
1992 * While this bit is 1, the debugger must not change which harts are
1995 * If this feature is not implemented, the bit always stays 0, so
1996 * after writing 1 the debugger can read the register back to see if
1997 * the feature is supported.
1999 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
2001 #define DM_DMCONTROL_HARTRESET_OFFSET 0x1d
2002 #define DM_DMCONTROL_HARTRESET_LENGTH 1
2003 #define DM_DMCONTROL_HARTRESET 0x20000000
2004 #define DM_DMCONTROL_ACKHAVERESET_OFFSET 0x1c
2005 #define DM_DMCONTROL_ACKHAVERESET_LENGTH 1
2006 #define DM_DMCONTROL_ACKHAVERESET 0x10000000
2010 #define DM_DMCONTROL_ACKHAVERESET_NOP 0
2012 * ack: Clears {\tt havereset} for any selected harts.
2014 #define DM_DMCONTROL_ACKHAVERESET_ACK 1
2016 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
2018 #define DM_DMCONTROL_ACKUNAVAIL_OFFSET 0x1b
2019 #define DM_DMCONTROL_ACKUNAVAIL_LENGTH 1
2020 #define DM_DMCONTROL_ACKUNAVAIL 0x8000000
2024 #define DM_DMCONTROL_ACKUNAVAIL_NOP 0
2026 * ack: Clears {\tt unavail} for any selected harts that are currently available.
2028 #define DM_DMCONTROL_ACKUNAVAIL_ACK 1
2030 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
2033 * Selects the definition of currently selected harts.
2035 #define DM_DMCONTROL_HASEL_OFFSET 0x1a
2036 #define DM_DMCONTROL_HASEL_LENGTH 1
2037 #define DM_DMCONTROL_HASEL 0x4000000
2039 * single: There is a single currently selected hart, that is selected by \Fhartsel.
2041 #define DM_DMCONTROL_HASEL_SINGLE 0
2043 * multiple: There may be multiple currently selected harts -- the hart
2044 * selected by \Fhartsel, plus those selected by the hart array mask
2047 #define DM_DMCONTROL_HASEL_MULTIPLE 1
2049 * An implementation which does not implement the hart array mask register
2050 * must tie this field to 0. A debugger which wishes to use the hart array
2051 * mask register feature should set this bit and read back to see if the functionality
2055 * The low 10 bits of \Fhartsel: the DM-specific index of the hart to
2056 * select. This hart is always part of the currently selected harts.
2058 #define DM_DMCONTROL_HARTSELLO_OFFSET 0x10
2059 #define DM_DMCONTROL_HARTSELLO_LENGTH 0xa
2060 #define DM_DMCONTROL_HARTSELLO 0x3ff0000
2062 * The high 10 bits of \Fhartsel: the DM-specific index of the hart to
2063 * select. This hart is always part of the currently selected harts.
2065 #define DM_DMCONTROL_HARTSELHI_OFFSET 6
2066 #define DM_DMCONTROL_HARTSELHI_LENGTH 0xa
2067 #define DM_DMCONTROL_HARTSELHI 0xffc0
2069 * This optional field sets \Fkeepalive for all currently selected
2070 * harts, unless \FdmDmcontrolClrkeepalive is simultaneously set to
2073 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
2075 #define DM_DMCONTROL_SETKEEPALIVE_OFFSET 5
2076 #define DM_DMCONTROL_SETKEEPALIVE_LENGTH 1
2077 #define DM_DMCONTROL_SETKEEPALIVE 0x20
2079 * This optional field clears \Fkeepalive for all currently selected
2082 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
2084 #define DM_DMCONTROL_CLRKEEPALIVE_OFFSET 4
2085 #define DM_DMCONTROL_CLRKEEPALIVE_LENGTH 1
2086 #define DM_DMCONTROL_CLRKEEPALIVE 0x10
2088 * This optional field writes the halt-on-reset request bit for all
2089 * currently selected harts, unless \FdmDmcontrolClrresethaltreq is
2090 * simultaneously set to 1.
2091 * When set to 1, each selected hart will halt upon the next deassertion
2092 * of its reset. The halt-on-reset request bit is not automatically
2093 * cleared. The debugger must write to \FdmDmcontrolClrresethaltreq to clear it.
2095 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
2097 * If \FdmDmstatusHasresethaltreq is 0, this field is not implemented.
2099 #define DM_DMCONTROL_SETRESETHALTREQ_OFFSET 3
2100 #define DM_DMCONTROL_SETRESETHALTREQ_LENGTH 1
2101 #define DM_DMCONTROL_SETRESETHALTREQ 8
2103 * This optional field clears the halt-on-reset request bit for all
2104 * currently selected harts.
2106 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
2108 #define DM_DMCONTROL_CLRRESETHALTREQ_OFFSET 2
2109 #define DM_DMCONTROL_CLRRESETHALTREQ_LENGTH 1
2110 #define DM_DMCONTROL_CLRRESETHALTREQ 4
2112 * This bit controls the reset signal from the DM to the rest of the
2113 * hardware platform. The signal should reset every part of the hardware platform, including
2114 * every hart, except for the DM and any logic required to access the
2116 * To perform a hardware platform reset the debugger writes 1,
2118 * to deassert the reset.
2120 #define DM_DMCONTROL_NDMRESET_OFFSET 1
2121 #define DM_DMCONTROL_NDMRESET_LENGTH 1
2122 #define DM_DMCONTROL_NDMRESET 2
2124 * This bit serves as a reset signal for the Debug Module itself.
2125 * After changing the value of this bit, the debugger must poll
2126 * \RdmDmcontrol until \FdmDmcontrolDmactive has taken the requested value
2127 * before performing any action that assumes the requested \FdmDmcontrolDmactive
2128 * state change has completed. Hardware may
2129 * take an arbitrarily long time to complete activation or deactivation and will
2130 * indicate completion by setting \FdmDmcontrolDmactive to the requested value.
2132 #define DM_DMCONTROL_DMACTIVE_OFFSET 0
2133 #define DM_DMCONTROL_DMACTIVE_LENGTH 1
2134 #define DM_DMCONTROL_DMACTIVE 1
2136 * inactive: The module's state, including authentication mechanism,
2137 * takes its reset values (the \FdmDmcontrolDmactive bit is the only bit which can
2138 * be written to something other than its reset value). Any accesses
2139 * to the module may fail. Specifically, \FdmDmstatusVersion might not return
2142 #define DM_DMCONTROL_DMACTIVE_INACTIVE 0
2144 * active: The module functions normally.
2146 #define DM_DMCONTROL_DMACTIVE_ACTIVE 1
2148 * No other mechanism should exist that may result in resetting the
2149 * Debug Module after power up.
2151 * To place the Debug Module into a known state, a debugger may write 0 to \FdmDmcontrolDmactive,
2152 * poll until \FdmDmcontrolDmactive is observed 0, write 1 to \FdmDmcontrolDmactive, and
2153 * poll until \FdmDmcontrolDmactive is observed 1.
2155 * Implementations may pay attention to this bit to further aid
2156 * debugging, for example by preventing the Debug Module from being
2157 * power gated while debugging is active.
2159 #define DM_HARTINFO 0x12
2161 * Number of {\tt dscratch} registers available for the debugger
2162 * to use during program buffer execution, starting from \RcsrDscratchZero.
2163 * The debugger can make no assumptions about the contents of these
2164 * registers between commands.
2166 #define DM_HARTINFO_NSCRATCH_OFFSET 0x14
2167 #define DM_HARTINFO_NSCRATCH_LENGTH 4
2168 #define DM_HARTINFO_NSCRATCH 0xf00000
2169 #define DM_HARTINFO_DATAACCESS_OFFSET 0x10
2170 #define DM_HARTINFO_DATAACCESS_LENGTH 1
2171 #define DM_HARTINFO_DATAACCESS 0x10000
2173 * csr: The {\tt data} registers are shadowed in the hart by CSRs.
2174 * Each CSR is DXLEN bits in size, and corresponds
2175 * to a single argument, per Table~\ref{tab:datareg}.
2177 #define DM_HARTINFO_DATAACCESS_CSR 0
2179 * memory: The {\tt data} registers are shadowed in the hart's memory map.
2180 * Each register takes up 4 bytes in the memory map.
2182 #define DM_HARTINFO_DATAACCESS_MEMORY 1
2184 * If \FdmHartinfoDataaccess is 0: Number of CSRs dedicated to
2185 * shadowing the {\tt data} registers.
2187 * If \FdmHartinfoDataaccess is 1: Number of 32-bit words in the memory map
2188 * dedicated to shadowing the {\tt data} registers.
2190 * If this value is non-zero, then the {tt data} registers must go
2191 * beyond being MRs and guarantee they each store a single value, that is
2192 * readable/writable by either side.
2194 * Since there are at most 12 {\tt data} registers, the value in this
2195 * register must be 12 or smaller.
2197 #define DM_HARTINFO_DATASIZE_OFFSET 0xc
2198 #define DM_HARTINFO_DATASIZE_LENGTH 4
2199 #define DM_HARTINFO_DATASIZE 0xf000
2201 * If \FdmHartinfoDataaccess is 0: The number of the first CSR dedicated to
2202 * shadowing the {\tt data} registers.
2204 * If \FdmHartinfoDataaccess is 1: Address of RAM where the data
2205 * registers are shadowed. This address is sign extended giving a
2206 * range of -2048 to 2047, easily addressed with a load or store using
2207 * \Xzero as the address register.
2209 #define DM_HARTINFO_DATAADDR_OFFSET 0
2210 #define DM_HARTINFO_DATAADDR_LENGTH 0xc
2211 #define DM_HARTINFO_DATAADDR 0xfff
2212 #define DM_HAWINDOWSEL 0x14
2214 * The high bits of this field may be tied to 0, depending on how large
2215 * the array mask register is. E.g.\ on a hardware platform with 48 harts only bit 0
2216 * of this field may actually be writable.
2218 #define DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0
2219 #define DM_HAWINDOWSEL_HAWINDOWSEL_LENGTH 0xf
2220 #define DM_HAWINDOWSEL_HAWINDOWSEL 0x7fff
2221 #define DM_HAWINDOW 0x15
2222 #define DM_HAWINDOW_MASKDATA_OFFSET 0
2223 #define DM_HAWINDOW_MASKDATA_LENGTH 0x20
2224 #define DM_HAWINDOW_MASKDATA 0xffffffffU
2225 #define DM_ABSTRACTCS 0x16
2227 * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
2229 #define DM_ABSTRACTCS_PROGBUFSIZE_OFFSET 0x18
2230 #define DM_ABSTRACTCS_PROGBUFSIZE_LENGTH 5
2231 #define DM_ABSTRACTCS_PROGBUFSIZE 0x1f000000
2232 #define DM_ABSTRACTCS_BUSY_OFFSET 0xc
2233 #define DM_ABSTRACTCS_BUSY_LENGTH 1
2234 #define DM_ABSTRACTCS_BUSY 0x1000
2236 * ready: There is no abstract command currently being executed.
2238 #define DM_ABSTRACTCS_BUSY_READY 0
2240 * busy: An abstract command is currently being executed.
2242 #define DM_ABSTRACTCS_BUSY_BUSY 1
2244 * This bit is set as soon as \RdmCommand is written, and is
2245 * not cleared until that command has completed.
2248 * This optional bit controls whether program buffer and abstract
2249 * memory accesses are performed with the exact and full set of
2250 * permission checks that apply based on the current architectural
2251 * state of the hart performing the access, or with a relaxed set of
2252 * permission checks (e.g. PMP restrictions are ignored). The
2253 * details of the latter are implementation-specific. When set to 0,
2254 * full permissions apply; when set to 1, relaxed permissions apply.
2256 #define DM_ABSTRACTCS_RELAXEDPRIV_OFFSET 0xb
2257 #define DM_ABSTRACTCS_RELAXEDPRIV_LENGTH 1
2258 #define DM_ABSTRACTCS_RELAXEDPRIV 0x800
2260 * Gets set if an abstract command fails. The bits in this field remain set until
2261 * they are cleared by writing 1 to them. No abstract command is
2262 * started until the value is reset to 0.
2264 * This field only contains a valid value if \FdmAbstractcsBusy is 0.
2266 #define DM_ABSTRACTCS_CMDERR_OFFSET 8
2267 #define DM_ABSTRACTCS_CMDERR_LENGTH 3
2268 #define DM_ABSTRACTCS_CMDERR 0x700
2272 #define DM_ABSTRACTCS_CMDERR_NONE 0
2274 * busy: An abstract command was executing while \RdmCommand,
2275 * \RdmAbstractcs, or \RdmAbstractauto was written, or when one
2276 * of the {\tt data} or {\tt progbuf} registers was read or written.
2277 * This status is only written if \FdmAbstractcsCmderr contains 0.
2279 #define DM_ABSTRACTCS_CMDERR_BUSY 1
2281 * not supported: The command in \RdmCommand is not supported. It
2282 * may be supported with different options set, but it will not be
2283 * supported at a later time when the hart or system state are
2286 #define DM_ABSTRACTCS_CMDERR_NOT_SUPPORTED 2
2288 * exception: An exception occurred while executing the command
2289 * (e.g.\ while executing the Program Buffer).
2291 #define DM_ABSTRACTCS_CMDERR_EXCEPTION 3
2293 * halt/resume: The abstract command couldn't execute because the
2294 * hart wasn't in the required state (running/halted), or unavailable.
2296 #define DM_ABSTRACTCS_CMDERR_HALT_RESUME 4
2298 * bus: The abstract command failed due to a bus error (e.g.\
2299 * alignment, access size, or timeout).
2301 #define DM_ABSTRACTCS_CMDERR_BUS 5
2303 * reserved: Reserved for future use.
2305 #define DM_ABSTRACTCS_CMDERR_RESERVED 6
2307 * other: The command failed for another reason.
2309 #define DM_ABSTRACTCS_CMDERR_OTHER 7
2311 * Number of {\tt data} registers that are implemented as part of the
2312 * abstract command interface. Valid sizes are 1 -- 12.
2314 #define DM_ABSTRACTCS_DATACOUNT_OFFSET 0
2315 #define DM_ABSTRACTCS_DATACOUNT_LENGTH 4
2316 #define DM_ABSTRACTCS_DATACOUNT 0xf
2317 #define DM_COMMAND 0x17
2319 * The type determines the overall functionality of this
2322 #define DM_COMMAND_CMDTYPE_OFFSET 0x18
2323 #define DM_COMMAND_CMDTYPE_LENGTH 8
2324 #define DM_COMMAND_CMDTYPE 0xff000000U
2326 * This field is interpreted in a command-specific manner,
2327 * described for each abstract command.
2329 #define DM_COMMAND_CONTROL_OFFSET 0
2330 #define DM_COMMAND_CONTROL_LENGTH 0x18
2331 #define DM_COMMAND_CONTROL 0xffffff
2332 #define DM_ABSTRACTAUTO 0x18
2334 * When a bit in this field is 1, read or write accesses to the
2335 * corresponding {\tt progbuf} word cause the DM to act as if the
2336 * current value in \RdmCommand was written there again after the
2337 * access to {\tt progbuf} completes.
2339 #define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 0x10
2340 #define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 0x10
2341 #define DM_ABSTRACTAUTO_AUTOEXECPROGBUF 0xffff0000U
2343 * When a bit in this field is 1, read or write accesses to the
2344 * corresponding {\tt data} word cause the DM to act as if the current
2345 * value in \RdmCommand was written there again after the
2346 * access to {\tt data} completes.
2348 #define DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0
2349 #define DM_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 0xc
2350 #define DM_ABSTRACTAUTO_AUTOEXECDATA 0xfff
2351 #define DM_CONFSTRPTR0 0x19
2352 #define DM_CONFSTRPTR0_ADDR_OFFSET 0
2353 #define DM_CONFSTRPTR0_ADDR_LENGTH 0x20
2354 #define DM_CONFSTRPTR0_ADDR 0xffffffffU
2355 #define DM_CONFSTRPTR1 0x1a
2356 #define DM_CONFSTRPTR1_ADDR_OFFSET 0
2357 #define DM_CONFSTRPTR1_ADDR_LENGTH 0x20
2358 #define DM_CONFSTRPTR1_ADDR 0xffffffffU
2359 #define DM_CONFSTRPTR2 0x1b
2360 #define DM_CONFSTRPTR2_ADDR_OFFSET 0
2361 #define DM_CONFSTRPTR2_ADDR_LENGTH 0x20
2362 #define DM_CONFSTRPTR2_ADDR 0xffffffffU
2363 #define DM_CONFSTRPTR3 0x1c
2364 #define DM_CONFSTRPTR3_ADDR_OFFSET 0
2365 #define DM_CONFSTRPTR3_ADDR_LENGTH 0x20
2366 #define DM_CONFSTRPTR3_ADDR 0xffffffffU
2367 #define DM_NEXTDM 0x1d
2368 #define DM_NEXTDM_ADDR_OFFSET 0
2369 #define DM_NEXTDM_ADDR_LENGTH 0x20
2370 #define DM_NEXTDM_ADDR 0xffffffffU
2371 #define DM_DATA0 0x04
2372 #define DM_DATA0_DATA_OFFSET 0
2373 #define DM_DATA0_DATA_LENGTH 0x20
2374 #define DM_DATA0_DATA 0xffffffffU
2375 #define DM_DATA1 0x05
2376 #define DM_DATA2 0x06
2377 #define DM_DATA3 0x07
2378 #define DM_DATA4 0x08
2379 #define DM_DATA5 0x09
2380 #define DM_DATA6 0x0a
2381 #define DM_DATA7 0x0b
2382 #define DM_DATA8 0x0c
2383 #define DM_DATA9 0x0d
2384 #define DM_DATA10 0x0e
2385 #define DM_DATA11 0x0f
2386 #define DM_PROGBUF0 0x20
2387 #define DM_PROGBUF0_DATA_OFFSET 0
2388 #define DM_PROGBUF0_DATA_LENGTH 0x20
2389 #define DM_PROGBUF0_DATA 0xffffffffU
2390 #define DM_PROGBUF1 0x21
2391 #define DM_PROGBUF2 0x22
2392 #define DM_PROGBUF3 0x23
2393 #define DM_PROGBUF4 0x24
2394 #define DM_PROGBUF5 0x25
2395 #define DM_PROGBUF6 0x26
2396 #define DM_PROGBUF7 0x27
2397 #define DM_PROGBUF8 0x28
2398 #define DM_PROGBUF9 0x29
2399 #define DM_PROGBUF10 0x2a
2400 #define DM_PROGBUF11 0x2b
2401 #define DM_PROGBUF12 0x2c
2402 #define DM_PROGBUF13 0x2d
2403 #define DM_PROGBUF14 0x2e
2404 #define DM_PROGBUF15 0x2f
2405 #define DM_AUTHDATA 0x30
2406 #define DM_AUTHDATA_DATA_OFFSET 0
2407 #define DM_AUTHDATA_DATA_LENGTH 0x20
2408 #define DM_AUTHDATA_DATA 0xffffffffU
2409 #define DM_DMCS2 0x32
2410 #define DM_DMCS2_GROUPTYPE_OFFSET 0xb
2411 #define DM_DMCS2_GROUPTYPE_LENGTH 1
2412 #define DM_DMCS2_GROUPTYPE 0x800
2414 * halt: The remaining fields in this register configure halt groups.
2416 #define DM_DMCS2_GROUPTYPE_HALT 0
2418 * resume: The remaining fields in this register configure resume groups.
2420 #define DM_DMCS2_GROUPTYPE_RESUME 1
2422 * This field contains the currently selected DM external trigger.
2424 * If a non-existent trigger value is written here, the hardware will
2425 * change it to a valid one or 0 if no DM external triggers exist.
2427 #define DM_DMCS2_DMEXTTRIGGER_OFFSET 7
2428 #define DM_DMCS2_DMEXTTRIGGER_LENGTH 4
2429 #define DM_DMCS2_DMEXTTRIGGER 0x780
2431 * When \FdmDmcsTwoHgselect is 0, contains the group of the hart
2432 * specified by \Fhartsel.
2434 * When \FdmDmcsTwoHgselect is 1, contains the group of the DM external
2435 * trigger selected by \FdmDmcsTwoDmexttrigger.
2437 * The value written to this field is ignored unless \FdmDmcsTwoHgwrite
2438 * is also written 1.
2440 * Group numbers are contiguous starting at 0, with the highest number
2441 * being implementation-dependent, and possibly different between
2442 * different group types. Debuggers should read back this field after
2443 * writing to confirm they are using a hart group that is supported.
2445 * If groups aren't implemented, then this entire field is 0.
2447 #define DM_DMCS2_GROUP_OFFSET 2
2448 #define DM_DMCS2_GROUP_LENGTH 5
2449 #define DM_DMCS2_GROUP 0x7c
2451 * When 1 is written and \FdmDmcsTwoHgselect is 0, for every selected
2452 * hart the DM will change its group to the value written to \FdmDmcsTwoGroup,
2453 * if the hardware supports that group for that hart.
2454 * Implementations may also change the group of a minimal set of
2455 * unselected harts in the same way, if that is necessary due to
2456 * a hardware limitation.
2458 * When 1 is written and \FdmDmcsTwoHgselect is 1, the DM will change
2459 * the group of the DM external trigger selected by \FdmDmcsTwoDmexttrigger
2460 * to the value written to \FdmDmcsTwoGroup, if the hardware supports
2461 * that group for that trigger.
2463 * Writing 0 has no effect.
2465 #define DM_DMCS2_HGWRITE_OFFSET 1
2466 #define DM_DMCS2_HGWRITE_LENGTH 1
2467 #define DM_DMCS2_HGWRITE 2
2468 #define DM_DMCS2_HGSELECT_OFFSET 0
2469 #define DM_DMCS2_HGSELECT_LENGTH 1
2470 #define DM_DMCS2_HGSELECT 1
2472 * harts: Operate on harts.
2474 #define DM_DMCS2_HGSELECT_HARTS 0
2476 * triggers: Operate on DM external triggers.
2478 #define DM_DMCS2_HGSELECT_TRIGGERS 1
2480 * If there are no DM external triggers, this field must be tied to 0.
2482 #define DM_HALTSUM0 0x40
2483 #define DM_HALTSUM0_HALTSUM0_OFFSET 0
2484 #define DM_HALTSUM0_HALTSUM0_LENGTH 0x20
2485 #define DM_HALTSUM0_HALTSUM0 0xffffffffU
2486 #define DM_HALTSUM1 0x13
2487 #define DM_HALTSUM1_HALTSUM1_OFFSET 0
2488 #define DM_HALTSUM1_HALTSUM1_LENGTH 0x20
2489 #define DM_HALTSUM1_HALTSUM1 0xffffffffU
2490 #define DM_HALTSUM2 0x34
2491 #define DM_HALTSUM2_HALTSUM2_OFFSET 0
2492 #define DM_HALTSUM2_HALTSUM2_LENGTH 0x20
2493 #define DM_HALTSUM2_HALTSUM2 0xffffffffU
2494 #define DM_HALTSUM3 0x35
2495 #define DM_HALTSUM3_HALTSUM3_OFFSET 0
2496 #define DM_HALTSUM3_HALTSUM3_LENGTH 0x20
2497 #define DM_HALTSUM3_HALTSUM3 0xffffffffU
2498 #define DM_SBCS 0x38
2499 #define DM_SBCS_SBVERSION_OFFSET 0x1d
2500 #define DM_SBCS_SBVERSION_LENGTH 3
2501 #define DM_SBCS_SBVERSION 0xe0000000U
2503 * legacy: The System Bus interface conforms to mainline drafts of this
2504 * spec older than 1 January, 2018.
2506 #define DM_SBCS_SBVERSION_LEGACY 0
2508 * 1.0: The System Bus interface conforms to this version of the spec.
2510 #define DM_SBCS_SBVERSION_1_0 1
2512 * Other values are reserved for future versions.
2515 * Set when the debugger attempts to read data while a read is in
2516 * progress, or when the debugger initiates a new access while one is
2517 * already in progress (while \FdmSbcsSbbusy is set). It remains set until
2518 * it's explicitly cleared by the debugger.
2520 * While this field is set, no more system bus accesses can be
2521 * initiated by the Debug Module.
2523 #define DM_SBCS_SBBUSYERROR_OFFSET 0x16
2524 #define DM_SBCS_SBBUSYERROR_LENGTH 1
2525 #define DM_SBCS_SBBUSYERROR 0x400000
2527 * When 1, indicates the system bus master is busy. (Whether the
2528 * system bus itself is busy is related, but not the same thing.) This
2529 * bit goes high immediately when a read or write is requested for any
2530 * reason, and does not go low until the access is fully completed.
2532 * Writes to \RdmSbcs while \FdmSbcsSbbusy is high result in undefined
2533 * behavior. A debugger must not write to \RdmSbcs until it reads
2534 * \FdmSbcsSbbusy as 0.
2536 #define DM_SBCS_SBBUSY_OFFSET 0x15
2537 #define DM_SBCS_SBBUSY_LENGTH 1
2538 #define DM_SBCS_SBBUSY 0x200000
2540 * When 1, every write to \RdmSbaddressZero automatically triggers a
2541 * system bus read at the new address.
2543 #define DM_SBCS_SBREADONADDR_OFFSET 0x14
2544 #define DM_SBCS_SBREADONADDR_LENGTH 1
2545 #define DM_SBCS_SBREADONADDR 0x100000
2547 * Select the access size to use for system bus accesses.
2549 #define DM_SBCS_SBACCESS_OFFSET 0x11
2550 #define DM_SBCS_SBACCESS_LENGTH 3
2551 #define DM_SBCS_SBACCESS 0xe0000
2555 #define DM_SBCS_SBACCESS_8BIT 0
2559 #define DM_SBCS_SBACCESS_16BIT 1
2563 #define DM_SBCS_SBACCESS_32BIT 2
2567 #define DM_SBCS_SBACCESS_64BIT 3
2571 #define DM_SBCS_SBACCESS_128BIT 4
2573 * If \FdmSbcsSbaccess has an unsupported value when the DM starts a bus
2574 * access, the access is not performed and \FdmSbcsSberror is set to 4.
2577 * When 1, {\tt sbaddress} is incremented by the access size (in
2578 * bytes) selected in \FdmSbcsSbaccess after every system bus access.
2580 #define DM_SBCS_SBAUTOINCREMENT_OFFSET 0x10
2581 #define DM_SBCS_SBAUTOINCREMENT_LENGTH 1
2582 #define DM_SBCS_SBAUTOINCREMENT 0x10000
2584 * When 1, every read from \RdmSbdataZero automatically triggers a
2585 * system bus read at the (possibly auto-incremented) address.
2587 #define DM_SBCS_SBREADONDATA_OFFSET 0xf
2588 #define DM_SBCS_SBREADONDATA_LENGTH 1
2589 #define DM_SBCS_SBREADONDATA 0x8000
2591 * When the Debug Module's system bus
2592 * master encounters an error, this field gets set. The bits in this
2593 * field remain set until they are cleared by writing 1 to them.
2594 * While this field is non-zero, no more system bus accesses can be
2595 * initiated by the Debug Module.
2597 * An implementation may report ``Other'' (7) for any error condition.
2599 #define DM_SBCS_SBERROR_OFFSET 0xc
2600 #define DM_SBCS_SBERROR_LENGTH 3
2601 #define DM_SBCS_SBERROR 0x7000
2603 * none: There was no bus error.
2605 #define DM_SBCS_SBERROR_NONE 0
2607 * timeout: There was a timeout.
2609 #define DM_SBCS_SBERROR_TIMEOUT 1
2611 * address: A bad address was accessed.
2613 #define DM_SBCS_SBERROR_ADDRESS 2
2615 * alignment: There was an alignment error.
2617 #define DM_SBCS_SBERROR_ALIGNMENT 3
2619 * size: An access of unsupported size was requested.
2621 #define DM_SBCS_SBERROR_SIZE 4
2625 #define DM_SBCS_SBERROR_OTHER 7
2627 * Width of system bus addresses in bits. (0 indicates there is no bus
2630 #define DM_SBCS_SBASIZE_OFFSET 5
2631 #define DM_SBCS_SBASIZE_LENGTH 7
2632 #define DM_SBCS_SBASIZE 0xfe0
2634 * 1 when 128-bit system bus accesses are supported.
2636 #define DM_SBCS_SBACCESS128_OFFSET 4
2637 #define DM_SBCS_SBACCESS128_LENGTH 1
2638 #define DM_SBCS_SBACCESS128 0x10
2640 * 1 when 64-bit system bus accesses are supported.
2642 #define DM_SBCS_SBACCESS64_OFFSET 3
2643 #define DM_SBCS_SBACCESS64_LENGTH 1
2644 #define DM_SBCS_SBACCESS64 8
2646 * 1 when 32-bit system bus accesses are supported.
2648 #define DM_SBCS_SBACCESS32_OFFSET 2
2649 #define DM_SBCS_SBACCESS32_LENGTH 1
2650 #define DM_SBCS_SBACCESS32 4
2652 * 1 when 16-bit system bus accesses are supported.
2654 #define DM_SBCS_SBACCESS16_OFFSET 1
2655 #define DM_SBCS_SBACCESS16_LENGTH 1
2656 #define DM_SBCS_SBACCESS16 2
2658 * 1 when 8-bit system bus accesses are supported.
2660 #define DM_SBCS_SBACCESS8_OFFSET 0
2661 #define DM_SBCS_SBACCESS8_LENGTH 1
2662 #define DM_SBCS_SBACCESS8 1
2663 #define DM_SBADDRESS0 0x39
2665 * Accesses bits 31:0 of the physical address in {\tt sbaddress}.
2667 #define DM_SBADDRESS0_ADDRESS_OFFSET 0
2668 #define DM_SBADDRESS0_ADDRESS_LENGTH 0x20
2669 #define DM_SBADDRESS0_ADDRESS 0xffffffffU
2670 #define DM_SBADDRESS1 0x3a
2672 * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if
2673 * the system address bus is that wide).
2675 #define DM_SBADDRESS1_ADDRESS_OFFSET 0
2676 #define DM_SBADDRESS1_ADDRESS_LENGTH 0x20
2677 #define DM_SBADDRESS1_ADDRESS 0xffffffffU
2678 #define DM_SBADDRESS2 0x3b
2680 * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if
2681 * the system address bus is that wide).
2683 #define DM_SBADDRESS2_ADDRESS_OFFSET 0
2684 #define DM_SBADDRESS2_ADDRESS_LENGTH 0x20
2685 #define DM_SBADDRESS2_ADDRESS 0xffffffffU
2686 #define DM_SBADDRESS3 0x37
2688 * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if
2689 * the system address bus is that wide).
2691 #define DM_SBADDRESS3_ADDRESS_OFFSET 0
2692 #define DM_SBADDRESS3_ADDRESS_LENGTH 0x20
2693 #define DM_SBADDRESS3_ADDRESS 0xffffffffU
2694 #define DM_SBDATA0 0x3c
2696 * Accesses bits 31:0 of {\tt sbdata}.
2698 #define DM_SBDATA0_DATA_OFFSET 0
2699 #define DM_SBDATA0_DATA_LENGTH 0x20
2700 #define DM_SBDATA0_DATA 0xffffffffU
2701 #define DM_SBDATA1 0x3d
2703 * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that
2706 #define DM_SBDATA1_DATA_OFFSET 0
2707 #define DM_SBDATA1_DATA_LENGTH 0x20
2708 #define DM_SBDATA1_DATA 0xffffffffU
2709 #define DM_SBDATA2 0x3e
2711 * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that
2714 #define DM_SBDATA2_DATA_OFFSET 0
2715 #define DM_SBDATA2_DATA_LENGTH 0x20
2716 #define DM_SBDATA2_DATA 0xffffffffU
2717 #define DM_SBDATA3 0x3f
2719 * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that
2722 #define DM_SBDATA3_DATA_OFFSET 0
2723 #define DM_SBDATA3_DATA_LENGTH 0x20
2724 #define DM_SBDATA3_DATA 0xffffffffU
2725 #define DM_CUSTOM 0x1f
2726 #define DM_CUSTOM0 0x70
2727 #define DM_CUSTOM1 0x71
2728 #define DM_CUSTOM2 0x72
2729 #define DM_CUSTOM3 0x73
2730 #define DM_CUSTOM4 0x74
2731 #define DM_CUSTOM5 0x75
2732 #define DM_CUSTOM6 0x76
2733 #define DM_CUSTOM7 0x77
2734 #define DM_CUSTOM8 0x78
2735 #define DM_CUSTOM9 0x79
2736 #define DM_CUSTOM10 0x7a
2737 #define DM_CUSTOM11 0x7b
2738 #define DM_CUSTOM12 0x7c
2739 #define DM_CUSTOM13 0x7d
2740 #define DM_CUSTOM14 0x7e
2741 #define DM_CUSTOM15 0x7f
2742 #define SHORTNAME 0x123
2744 * Description of what this field is used for.
2746 #define SHORTNAME_FIELD_OFFSET 0
2747 #define SHORTNAME_FIELD_LENGTH 8
2748 #define SHORTNAME_FIELD 0xff
2750 * This is 0 to indicate Access Register Command.
2752 #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 0x18
2753 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8
2754 #define AC_ACCESS_REGISTER_CMDTYPE 0xff000000U
2755 #define AC_ACCESS_REGISTER_AARSIZE_OFFSET 0x14
2756 #define AC_ACCESS_REGISTER_AARSIZE_LENGTH 3
2757 #define AC_ACCESS_REGISTER_AARSIZE 0x700000
2759 * 32bit: Access the lowest 32 bits of the register.
2761 #define AC_ACCESS_REGISTER_AARSIZE_32BIT 2
2763 * 64bit: Access the lowest 64 bits of the register.
2765 #define AC_ACCESS_REGISTER_AARSIZE_64BIT 3
2767 * 128bit: Access the lowest 128 bits of the register.
2769 #define AC_ACCESS_REGISTER_AARSIZE_128BIT 4
2771 * If \FacAccessregisterAarsize specifies a size larger than the register's actual size,
2772 * then the access must fail. If a register is accessible, then reads of \FacAccessregisterAarsize
2773 * less than or equal to the register's actual size must be supported.
2774 * Writing less than the full register may be supported, but what
2775 * happens to the high bits in that case is \unspecified.
2777 * This field controls the Argument Width as referenced in
2778 * Table~\ref{tab:datareg}.
2780 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 0x13
2781 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1
2782 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT 0x80000
2784 * disabled: No effect. This variant must be supported.
2786 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_DISABLED 0
2788 * enabled: After a successful register access, \FacAccessregisterRegno is
2789 * incremented. Incrementing past the highest supported value
2790 * causes \FacAccessregisterRegno to become \unspecified. Supporting
2791 * this variant is optional. It is undefined whether the increment
2792 * happens when \FacAccessregisterTransfer is 0.
2794 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_ENABLED 1
2795 #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 0x12
2796 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1
2797 #define AC_ACCESS_REGISTER_POSTEXEC 0x40000
2799 * disabled: No effect. This variant must be supported, and is the only
2800 * supported one if \FdmAbstractcsProgbufsize is 0.
2802 #define AC_ACCESS_REGISTER_POSTEXEC_DISABLED 0
2804 * enabled: Execute the program in the Program Buffer exactly once after
2805 * performing the transfer, if any. Supporting this variant is
2808 #define AC_ACCESS_REGISTER_POSTEXEC_ENABLED 1
2809 #define AC_ACCESS_REGISTER_TRANSFER_OFFSET 0x11
2810 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1
2811 #define AC_ACCESS_REGISTER_TRANSFER 0x20000
2813 * disabled: Don't do the operation specified by \FacAccessregisterWrite.
2815 #define AC_ACCESS_REGISTER_TRANSFER_DISABLED 0
2817 * enabled: Do the operation specified by \FacAccessregisterWrite.
2819 #define AC_ACCESS_REGISTER_TRANSFER_ENABLED 1
2821 * This bit can be used to just execute the Program Buffer without
2822 * having to worry about placing valid values into \FacAccessregisterAarsize or \FacAccessregisterRegno.
2825 * When \FacAccessregisterTransfer is set:
2827 #define AC_ACCESS_REGISTER_WRITE_OFFSET 0x10
2828 #define AC_ACCESS_REGISTER_WRITE_LENGTH 1
2829 #define AC_ACCESS_REGISTER_WRITE 0x10000
2831 * arg0: Copy data from the specified register into {\tt arg0} portion
2834 #define AC_ACCESS_REGISTER_WRITE_ARG0 0
2836 * register: Copy data from {\tt arg0} portion of {\tt data} into the
2837 * specified register.
2839 #define AC_ACCESS_REGISTER_WRITE_REGISTER 1
2841 * Number of the register to access, as described in
2842 * Table~\ref{tab:regno}.
2843 * \RcsrDpc may be used as an alias for PC if this command is
2844 * supported on a non-halted hart.
2846 #define AC_ACCESS_REGISTER_REGNO_OFFSET 0
2847 #define AC_ACCESS_REGISTER_REGNO_LENGTH 0x10
2848 #define AC_ACCESS_REGISTER_REGNO 0xffff
2850 * This is 1 to indicate Quick Access command.
2852 #define AC_QUICK_ACCESS_CMDTYPE_OFFSET 0x18
2853 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8
2854 #define AC_QUICK_ACCESS_CMDTYPE 0xff000000U
2856 * This is 2 to indicate Access Memory Command.
2858 #define AC_ACCESS_MEMORY_CMDTYPE_OFFSET 0x18
2859 #define AC_ACCESS_MEMORY_CMDTYPE_LENGTH 8
2860 #define AC_ACCESS_MEMORY_CMDTYPE 0xff000000U
2862 * An implementation does not have to implement both virtual and
2863 * physical accesses, but it must fail accesses that it doesn't
2866 #define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 0x17
2867 #define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1
2868 #define AC_ACCESS_MEMORY_AAMVIRTUAL 0x800000
2870 * physical: Addresses are physical (to the hart they are performed on).
2872 #define AC_ACCESS_MEMORY_AAMVIRTUAL_PHYSICAL 0
2874 * virtual: Addresses are virtual, and translated the way they would be from
2875 * M-mode, with \FcsrMstatusMprv set.
2877 #define AC_ACCESS_MEMORY_AAMVIRTUAL_VIRTUAL 1
2879 * Debug Modules on systems without address translation (i.e. virtual addresses equal physical)
2880 * may optionally allow \FacAccessmemoryAamvirtual set to 1, which would produce the same result as
2881 * that same abstract command with \FacAccessmemoryAamvirtual cleared.
2883 #define AC_ACCESS_MEMORY_AAMSIZE_OFFSET 0x14
2884 #define AC_ACCESS_MEMORY_AAMSIZE_LENGTH 3
2885 #define AC_ACCESS_MEMORY_AAMSIZE 0x700000
2887 * 8bit: Access the lowest 8 bits of the memory location.
2889 #define AC_ACCESS_MEMORY_AAMSIZE_8BIT 0
2891 * 16bit: Access the lowest 16 bits of the memory location.
2893 #define AC_ACCESS_MEMORY_AAMSIZE_16BIT 1
2895 * 32bit: Access the lowest 32 bits of the memory location.
2897 #define AC_ACCESS_MEMORY_AAMSIZE_32BIT 2
2899 * 64bit: Access the lowest 64 bits of the memory location.
2901 #define AC_ACCESS_MEMORY_AAMSIZE_64BIT 3
2903 * 128bit: Access the lowest 128 bits of the memory location.
2905 #define AC_ACCESS_MEMORY_AAMSIZE_128BIT 4
2907 * After a memory access has completed, if this bit is 1, increment
2908 * {\tt arg1} (which contains the address used) by the number of bytes
2909 * encoded in \FacAccessmemoryAamsize.
2911 * Supporting this variant is optional, but highly recommended for
2912 * performance reasons.
2914 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET 0x13
2915 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_LENGTH 1
2916 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT 0x80000
2917 #define AC_ACCESS_MEMORY_WRITE_OFFSET 0x10
2918 #define AC_ACCESS_MEMORY_WRITE_LENGTH 1
2919 #define AC_ACCESS_MEMORY_WRITE 0x10000
2921 * arg0: Copy data from the memory location specified in {\tt arg1} into
2922 * the low bits of {\tt arg0}. The value of the remaining bits of
2923 * {\tt arg0} are \unspecified.
2925 #define AC_ACCESS_MEMORY_WRITE_ARG0 0
2927 * memory: Copy data from the low bits of {\tt arg0} into the memory
2928 * location specified in {\tt arg1}.
2930 #define AC_ACCESS_MEMORY_WRITE_MEMORY 1
2932 * These bits are reserved for target-specific uses.
2934 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET 0xe
2935 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC_LENGTH 2
2936 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC 0xc000
2937 #define VIRT_PRIV virtual
2939 * Contains the virtualization mode the hart was operating in when Debug
2940 * Mode was entered. The encoding is described in Table \ref{tab:privmode},
2941 * and matches the virtualization mode encoding from the Privileged Spec.
2942 * A user can write this value to change the hart's virtualization mode
2943 * when exiting Debug Mode.
2945 #define VIRT_PRIV_V_OFFSET 2
2946 #define VIRT_PRIV_V_LENGTH 1
2947 #define VIRT_PRIV_V 4
2949 * Contains the privilege mode the hart was operating in when Debug
2950 * Mode was entered. The encoding is described in Table
2951 * \ref{tab:privmode}, and matches the privilege mode encoding from
2952 * the Privileged Spec. A user can write this
2953 * value to change the hart's privilege mode when exiting Debug Mode.
2955 #define VIRT_PRIV_PRV_OFFSET 0
2956 #define VIRT_PRIV_PRV_LENGTH 2
2957 #define VIRT_PRIV_PRV 3
2958 #define DMI_SERCS 0x34
2960 * Number of supported serial ports.
2962 #define DMI_SERCS_SERIALCOUNT_OFFSET 0x1c
2963 #define DMI_SERCS_SERIALCOUNT_LENGTH 4
2964 #define DMI_SERCS_SERIALCOUNT 0xf0000000U
2966 * Select which serial port is accessed by \RdmiSerrx and \RdmiSertx.
2968 #define DMI_SERCS_SERIAL_OFFSET 0x18
2969 #define DMI_SERCS_SERIAL_LENGTH 3
2970 #define DMI_SERCS_SERIAL 0x7000000
2971 #define DMI_SERCS_ERROR7_OFFSET 0x17
2972 #define DMI_SERCS_ERROR7_LENGTH 1
2973 #define DMI_SERCS_ERROR7 0x800000
2974 #define DMI_SERCS_VALID7_OFFSET 0x16
2975 #define DMI_SERCS_VALID7_LENGTH 1
2976 #define DMI_SERCS_VALID7 0x400000
2977 #define DMI_SERCS_FULL7_OFFSET 0x15
2978 #define DMI_SERCS_FULL7_LENGTH 1
2979 #define DMI_SERCS_FULL7 0x200000
2980 #define DMI_SERCS_ERROR6_OFFSET 0x14
2981 #define DMI_SERCS_ERROR6_LENGTH 1
2982 #define DMI_SERCS_ERROR6 0x100000
2983 #define DMI_SERCS_VALID6_OFFSET 0x13
2984 #define DMI_SERCS_VALID6_LENGTH 1
2985 #define DMI_SERCS_VALID6 0x80000
2986 #define DMI_SERCS_FULL6_OFFSET 0x12
2987 #define DMI_SERCS_FULL6_LENGTH 1
2988 #define DMI_SERCS_FULL6 0x40000
2989 #define DMI_SERCS_ERROR5_OFFSET 0x11
2990 #define DMI_SERCS_ERROR5_LENGTH 1
2991 #define DMI_SERCS_ERROR5 0x20000
2992 #define DMI_SERCS_VALID5_OFFSET 0x10
2993 #define DMI_SERCS_VALID5_LENGTH 1
2994 #define DMI_SERCS_VALID5 0x10000
2995 #define DMI_SERCS_FULL5_OFFSET 0xf
2996 #define DMI_SERCS_FULL5_LENGTH 1
2997 #define DMI_SERCS_FULL5 0x8000
2998 #define DMI_SERCS_ERROR4_OFFSET 0xe
2999 #define DMI_SERCS_ERROR4_LENGTH 1
3000 #define DMI_SERCS_ERROR4 0x4000
3001 #define DMI_SERCS_VALID4_OFFSET 0xd
3002 #define DMI_SERCS_VALID4_LENGTH 1
3003 #define DMI_SERCS_VALID4 0x2000
3004 #define DMI_SERCS_FULL4_OFFSET 0xc
3005 #define DMI_SERCS_FULL4_LENGTH 1
3006 #define DMI_SERCS_FULL4 0x1000
3007 #define DMI_SERCS_ERROR3_OFFSET 0xb
3008 #define DMI_SERCS_ERROR3_LENGTH 1
3009 #define DMI_SERCS_ERROR3 0x800
3010 #define DMI_SERCS_VALID3_OFFSET 0xa
3011 #define DMI_SERCS_VALID3_LENGTH 1
3012 #define DMI_SERCS_VALID3 0x400
3013 #define DMI_SERCS_FULL3_OFFSET 9
3014 #define DMI_SERCS_FULL3_LENGTH 1
3015 #define DMI_SERCS_FULL3 0x200
3016 #define DMI_SERCS_ERROR2_OFFSET 8
3017 #define DMI_SERCS_ERROR2_LENGTH 1
3018 #define DMI_SERCS_ERROR2 0x100
3019 #define DMI_SERCS_VALID2_OFFSET 7
3020 #define DMI_SERCS_VALID2_LENGTH 1
3021 #define DMI_SERCS_VALID2 0x80
3022 #define DMI_SERCS_FULL2_OFFSET 6
3023 #define DMI_SERCS_FULL2_LENGTH 1
3024 #define DMI_SERCS_FULL2 0x40
3025 #define DMI_SERCS_ERROR1_OFFSET 5
3026 #define DMI_SERCS_ERROR1_LENGTH 1
3027 #define DMI_SERCS_ERROR1 0x20
3028 #define DMI_SERCS_VALID1_OFFSET 4
3029 #define DMI_SERCS_VALID1_LENGTH 1
3030 #define DMI_SERCS_VALID1 0x10
3031 #define DMI_SERCS_FULL1_OFFSET 3
3032 #define DMI_SERCS_FULL1_LENGTH 1
3033 #define DMI_SERCS_FULL1 8
3035 * 1 when the debugger-to-core queue for serial port 0 has
3036 * over or underflowed. This bit will remain set until it is reset by
3037 * writing 1 to this bit.
3039 #define DMI_SERCS_ERROR0_OFFSET 2
3040 #define DMI_SERCS_ERROR0_LENGTH 1
3041 #define DMI_SERCS_ERROR0 4
3043 * 1 when the core-to-debugger queue for serial port 0 is not empty.
3045 #define DMI_SERCS_VALID0_OFFSET 1
3046 #define DMI_SERCS_VALID0_LENGTH 1
3047 #define DMI_SERCS_VALID0 2
3049 * 1 when the debugger-to-core queue for serial port 0 is full.
3051 #define DMI_SERCS_FULL0_OFFSET 0
3052 #define DMI_SERCS_FULL0_LENGTH 1
3053 #define DMI_SERCS_FULL0 1
3054 #define DMI_SERTX 0x35
3055 #define DMI_SERTX_DATA_OFFSET 0
3056 #define DMI_SERTX_DATA_LENGTH 0x20
3057 #define DMI_SERTX_DATA 0xffffffffU
3058 #define DMI_SERRX 0x36
3059 #define DMI_SERRX_DATA_OFFSET 0
3060 #define DMI_SERRX_DATA_LENGTH 0x20
3061 #define DMI_SERRX_DATA 0xffffffffU