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   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Julius Baxter                                   *
   3  *   julius@opencores.org                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2013 by Marek Czerski                                   *
   6  *   ma.czerski@gmail.com                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2013 by Franck Jullien                                  *
   9  *   elec4fun@gmail.com                                                    *
  10  *                                                                         *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  26  ***************************************************************************/
  27
  28 #ifndef OR1K_H
  29 #define OR1K_H
  30
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #include <target/target.h>
  36
  37 /* SPR groups start address */
  38 #define GROUP0          (0  << 11)
  39 #define GROUP1          (1  << 11)
  40 #define GROUP2          (2  << 11)
  41 #define GROUP3          (3  << 11)
  42 #define GROUP4          (4  << 11)
  43 #define GROUP5          (5  << 11)
  44 #define GROUP6          (6  << 11)
  45 #define GROUP7          (7  << 11)
  46 #define GROUP8          (8  << 11)
  47 #define GROUP9          (9  << 11)
  48 #define GROUP10         (10 << 11)
  49
  50 /* OR1K registers */
  51 enum or1k_reg_nums {
  52         OR1K_REG_R0 = 0,
  53         OR1K_REG_R1,
  54         OR1K_REG_R2,
  55         OR1K_REG_R3,
  56         OR1K_REG_R4,
  57         OR1K_REG_R5,
  58         OR1K_REG_R6,
  59         OR1K_REG_R7,
  60         OR1K_REG_R8,
  61         OR1K_REG_R9,
  62         OR1K_REG_R10,
  63         OR1K_REG_R11,
  64         OR1K_REG_R12,
  65         OR1K_REG_R13,
  66         OR1K_REG_R14,
  67         OR1K_REG_R15,
  68         OR1K_REG_R16,
  69         OR1K_REG_R17,
  70         OR1K_REG_R18,
  71         OR1K_REG_R19,
  72         OR1K_REG_R20,
  73         OR1K_REG_R21,
  74         OR1K_REG_R22,
  75         OR1K_REG_R23,
  76         OR1K_REG_R24,
  77         OR1K_REG_R25,
  78         OR1K_REG_R26,
  79         OR1K_REG_R27,
  80         OR1K_REG_R28,
  81         OR1K_REG_R29,
  82         OR1K_REG_R30,
  83         OR1K_REG_R31,
  84         OR1K_REG_PPC,
  85         OR1K_REG_NPC,
  86         OR1K_REG_SR,
  87         OR1KNUMCOREREGS
  88 };
  89
  90 struct or1k_jtag {
  91         struct jtag_tap *tap;
  92         int or1k_jtag_inited;
  93         int or1k_jtag_module_selected;
  94         uint8_t *current_reg_idx;
  95         struct or1k_tap_ip *tap_ip;
  96         struct or1k_du *du_core;
  97         struct target *target;
  98 };
  99
 100 struct or1k_common {
 101         struct or1k_jtag jtag;
 102         struct reg_cache *core_cache;
 103         uint32_t core_regs[OR1KNUMCOREREGS];
 104         int nb_regs;
 105         struct or1k_core_reg *arch_info;
 106 };
 107
 108 static inline struct or1k_common *
 109 target_to_or1k(struct target *target)
 110 {
 111         return (struct or1k_common *)target->arch_info;
 112 }
 113
 114 struct or1k_core_reg {
 115         const char *name;
 116         uint32_t list_num;   /* Index in register cache */
 117         uint32_t spr_num;    /* Number in architecture's SPR space */
 118         struct target *target;
 119         struct or1k_common *or1k_common;
 120         const char *feature; /* feature name in XML tdesc file */
 121         const char *group;   /* register group in XML tdesc file */
 122 };
 123
 124 struct or1k_core_reg_init {
 125         const char *name;
 126         uint32_t spr_num;    /* Number in architecture's SPR space */
 127         const char *feature; /* feature name in XML tdesc file */
 128         const char *group;   /* register group in XML tdesc file */
 129 };
 130
 131 /* ORBIS32 Trap instruction */
 132 #define OR1K_TRAP_INSTR  0x21000001
 133
 134 enum or1k_debug_reg_nums {
 135         OR1K_DEBUG_REG_DMR1 = 0,
 136         OR1K_DEBUG_REG_DMR2,
 137         OR1K_DEBUG_REG_DCWR0,
 138         OR1K_DEBUG_REG_DCWR1,
 139         OR1K_DEBUG_REG_DSR,
 140         OR1K_DEBUG_REG_DRR,
 141         OR1K_DEBUG_REG_NUM
 142 };
 143
 144 #define NO_SINGLE_STEP          0
 145 #define SINGLE_STEP             1
 146
 147 /* OR1K Debug registers and bits needed for resuming */
 148 #define OR1K_DEBUG_REG_BASE     GROUP6                     /* Debug registers Base address */
 149 #define OR1K_DMR1_CPU_REG_ADD   (OR1K_DEBUG_REG_BASE + 16) /* Debug Mode Register 1 0x3010 */
 150 #define OR1K_DMR1_ST            0x00400000                 /* Single-step trace */
 151 #define OR1K_DMR1_BT            0x00800000                 /* Branch trace */
 152 #define OR1K_DMR2_WGB           0x003ff000                 /* Watchpoints generating breakpoint */
 153 #define OR1K_DSR_TE             0x00002000                 /* Trap exception */
 154
 155 /* OR1K Instruction cache registers needed for invalidating instruction
 156  * memory during adding and removing breakpoints.
 157  */
 158 #define OR1K_ICBIR_CPU_REG_ADD ((4 << 11) + 2)             /* IC Block Invalidate Register 0x2002 */
 159
 160 #endif