git.gag.com Git - fw/openocd/blob - src/target/openrisc/or1k.c

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Julius Baxter                                   *
   3  *   julius@opencores.org                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2013 by Marek Czerski                                   *
   6  *   ma.czerski@gmail.com                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2013 by Franck Jullien                                  *
   9  *   elec4fun@gmail.com                                                    *
  10  *                                                                         *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  ***************************************************************************/
  22
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include <jtag/jtag.h>
  28 #include <target/register.h>
  29 #include <target/target.h>
  30 #include <target/breakpoints.h>
  31 #include <target/target_type.h>
  32 #include <helper/fileio.h>
  33 #include "or1k_tap.h"
  34 #include "or1k.h"
  35 #include "or1k_du.h"
  36
  37 LIST_HEAD(tap_list);
  38 LIST_HEAD(du_list);
  39
  40 static int or1k_remove_breakpoint(struct target *target,
  41                                   struct breakpoint *breakpoint);
  42
  43 static int or1k_read_core_reg(struct target *target, int num);
  44 static int or1k_write_core_reg(struct target *target, int num);
  45
  46 static struct or1k_core_reg *or1k_core_reg_list_arch_info;
  47
  48 static const struct or1k_core_reg_init or1k_init_reg_list[] = {
  49         {"r0"       , GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
  50         {"r1"       , GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
  51         {"r2"       , GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
  52         {"r3"       , GROUP0 + 1027, "org.gnu.gdb.or1k.group0", NULL},
  53         {"r4"       , GROUP0 + 1028, "org.gnu.gdb.or1k.group0", NULL},
  54         {"r5"       , GROUP0 + 1029, "org.gnu.gdb.or1k.group0", NULL},
  55         {"r6"       , GROUP0 + 1030, "org.gnu.gdb.or1k.group0", NULL},
  56         {"r7"       , GROUP0 + 1031, "org.gnu.gdb.or1k.group0", NULL},
  57         {"r8"       , GROUP0 + 1032, "org.gnu.gdb.or1k.group0", NULL},
  58         {"r9"       , GROUP0 + 1033, "org.gnu.gdb.or1k.group0", NULL},
  59         {"r10"      , GROUP0 + 1034, "org.gnu.gdb.or1k.group0", NULL},
  60         {"r11"      , GROUP0 + 1035, "org.gnu.gdb.or1k.group0", NULL},
  61         {"r12"      , GROUP0 + 1036, "org.gnu.gdb.or1k.group0", NULL},
  62         {"r13"      , GROUP0 + 1037, "org.gnu.gdb.or1k.group0", NULL},
  63         {"r14"      , GROUP0 + 1038, "org.gnu.gdb.or1k.group0", NULL},
  64         {"r15"      , GROUP0 + 1039, "org.gnu.gdb.or1k.group0", NULL},
  65         {"r16"      , GROUP0 + 1040, "org.gnu.gdb.or1k.group0", NULL},
  66         {"r17"      , GROUP0 + 1041, "org.gnu.gdb.or1k.group0", NULL},
  67         {"r18"      , GROUP0 + 1042, "org.gnu.gdb.or1k.group0", NULL},
  68         {"r19"      , GROUP0 + 1043, "org.gnu.gdb.or1k.group0", NULL},
  69         {"r20"      , GROUP0 + 1044, "org.gnu.gdb.or1k.group0", NULL},
  70         {"r21"      , GROUP0 + 1045, "org.gnu.gdb.or1k.group0", NULL},
  71         {"r22"      , GROUP0 + 1046, "org.gnu.gdb.or1k.group0", NULL},
  72         {"r23"      , GROUP0 + 1047, "org.gnu.gdb.or1k.group0", NULL},
  73         {"r24"      , GROUP0 + 1048, "org.gnu.gdb.or1k.group0", NULL},
  74         {"r25"      , GROUP0 + 1049, "org.gnu.gdb.or1k.group0", NULL},
  75         {"r26"      , GROUP0 + 1050, "org.gnu.gdb.or1k.group0", NULL},
  76         {"r27"      , GROUP0 + 1051, "org.gnu.gdb.or1k.group0", NULL},
  77         {"r28"      , GROUP0 + 1052, "org.gnu.gdb.or1k.group0", NULL},
  78         {"r29"      , GROUP0 + 1053, "org.gnu.gdb.or1k.group0", NULL},
  79         {"r30"      , GROUP0 + 1054, "org.gnu.gdb.or1k.group0", NULL},
  80         {"r31"      , GROUP0 + 1055, "org.gnu.gdb.or1k.group0", NULL},
  81         {"ppc"      , GROUP0 + 18,   "org.gnu.gdb.or1k.group0", NULL},
  82         {"npc"      , GROUP0 + 16,   "org.gnu.gdb.or1k.group0", NULL},
  83         {"sr"       , GROUP0 + 17,   "org.gnu.gdb.or1k.group0", NULL},
  84         {"vr"       , GROUP0 + 0,    "org.gnu.gdb.or1k.group0", "system"},
  85         {"upr"      , GROUP0 + 1,    "org.gnu.gdb.or1k.group0", "system"},
  86         {"cpucfgr"  , GROUP0 + 2,    "org.gnu.gdb.or1k.group0", "system"},
  87         {"dmmucfgr" , GROUP0 + 3,    "org.gnu.gdb.or1k.group0", "system"},
  88         {"immucfgr" , GROUP0 + 4,    "org.gnu.gdb.or1k.group0", "system"},
  89         {"dccfgr"   , GROUP0 + 5,    "org.gnu.gdb.or1k.group0", "system"},
  90         {"iccfgr"   , GROUP0 + 6,    "org.gnu.gdb.or1k.group0", "system"},
  91         {"dcfgr"    , GROUP0 + 7,    "org.gnu.gdb.or1k.group0", "system"},
  92         {"pccfgr"   , GROUP0 + 8,    "org.gnu.gdb.or1k.group0", "system"},
  93         {"fpcsr"    , GROUP0 + 20,   "org.gnu.gdb.or1k.group0", "system"},
  94         {"epcr0"    , GROUP0 + 32,   "org.gnu.gdb.or1k.group0", "system"},
  95         {"epcr1"    , GROUP0 + 33,   "org.gnu.gdb.or1k.group0", "system"},
  96         {"epcr2"    , GROUP0 + 34,   "org.gnu.gdb.or1k.group0", "system"},
  97         {"epcr3"    , GROUP0 + 35,   "org.gnu.gdb.or1k.group0", "system"},
  98         {"epcr4"    , GROUP0 + 36,   "org.gnu.gdb.or1k.group0", "system"},
  99         {"epcr5"    , GROUP0 + 37,   "org.gnu.gdb.or1k.group0", "system"},
 100         {"epcr6"    , GROUP0 + 38,   "org.gnu.gdb.or1k.group0", "system"},
 101         {"epcr7"    , GROUP0 + 39,   "org.gnu.gdb.or1k.group0", "system"},
 102         {"epcr8"    , GROUP0 + 40,   "org.gnu.gdb.or1k.group0", "system"},
 103         {"epcr9"    , GROUP0 + 41,   "org.gnu.gdb.or1k.group0", "system"},
 104         {"epcr10"   , GROUP0 + 42,   "org.gnu.gdb.or1k.group0", "system"},
 105         {"epcr11"   , GROUP0 + 43,   "org.gnu.gdb.or1k.group0", "system"},
 106         {"epcr12"   , GROUP0 + 44,   "org.gnu.gdb.or1k.group0", "system"},
 107         {"epcr13"   , GROUP0 + 45,   "org.gnu.gdb.or1k.group0", "system"},
 108         {"epcr14"   , GROUP0 + 46,   "org.gnu.gdb.or1k.group0", "system"},
 109         {"epcr15"   , GROUP0 + 47,   "org.gnu.gdb.or1k.group0", "system"},
 110         {"eear0"    , GROUP0 + 48,   "org.gnu.gdb.or1k.group0", "system"},
 111         {"eear1"    , GROUP0 + 49,   "org.gnu.gdb.or1k.group0", "system"},
 112         {"eear2"    , GROUP0 + 50,   "org.gnu.gdb.or1k.group0", "system"},
 113         {"eear3"    , GROUP0 + 51,   "org.gnu.gdb.or1k.group0", "system"},
 114         {"eear4"    , GROUP0 + 52,   "org.gnu.gdb.or1k.group0", "system"},
 115         {"eear5"    , GROUP0 + 53,   "org.gnu.gdb.or1k.group0", "system"},
 116         {"eear6"    , GROUP0 + 54,   "org.gnu.gdb.or1k.group0", "system"},
 117         {"eear7"    , GROUP0 + 55,   "org.gnu.gdb.or1k.group0", "system"},
 118         {"eear8"    , GROUP0 + 56,   "org.gnu.gdb.or1k.group0", "system"},
 119         {"eear9"    , GROUP0 + 57,   "org.gnu.gdb.or1k.group0", "system"},
 120         {"eear10"   , GROUP0 + 58,   "org.gnu.gdb.or1k.group0", "system"},
 121         {"eear11"   , GROUP0 + 59,   "org.gnu.gdb.or1k.group0", "system"},
 122         {"eear12"   , GROUP0 + 60,   "org.gnu.gdb.or1k.group0", "system"},
 123         {"eear13"   , GROUP0 + 61,   "org.gnu.gdb.or1k.group0", "system"},
 124         {"eear14"   , GROUP0 + 62,   "org.gnu.gdb.or1k.group0", "system"},
 125         {"eear15"   , GROUP0 + 63,   "org.gnu.gdb.or1k.group0", "system"},
 126         {"esr0"     , GROUP0 + 64,   "org.gnu.gdb.or1k.group0", "system"},
 127         {"esr1"     , GROUP0 + 65,   "org.gnu.gdb.or1k.group0", "system"},
 128         {"esr2"     , GROUP0 + 66,   "org.gnu.gdb.or1k.group0", "system"},
 129         {"esr3"     , GROUP0 + 67,   "org.gnu.gdb.or1k.group0", "system"},
 130         {"esr4"     , GROUP0 + 68,   "org.gnu.gdb.or1k.group0", "system"},
 131         {"esr5"     , GROUP0 + 69,   "org.gnu.gdb.or1k.group0", "system"},
 132         {"esr6"     , GROUP0 + 70,   "org.gnu.gdb.or1k.group0", "system"},
 133         {"esr7"     , GROUP0 + 71,   "org.gnu.gdb.or1k.group0", "system"},
 134         {"esr8"     , GROUP0 + 72,   "org.gnu.gdb.or1k.group0", "system"},
 135         {"esr9"     , GROUP0 + 73,   "org.gnu.gdb.or1k.group0", "system"},
 136         {"esr10"    , GROUP0 + 74,   "org.gnu.gdb.or1k.group0", "system"},
 137         {"esr11"    , GROUP0 + 75,   "org.gnu.gdb.or1k.group0", "system"},
 138         {"esr12"    , GROUP0 + 76,   "org.gnu.gdb.or1k.group0", "system"},
 139         {"esr13"    , GROUP0 + 77,   "org.gnu.gdb.or1k.group0", "system"},
 140         {"esr14"    , GROUP0 + 78,   "org.gnu.gdb.or1k.group0", "system"},
 141         {"esr15"    , GROUP0 + 79,   "org.gnu.gdb.or1k.group0", "system"},
 142
 143         {"dmmuucr"  , GROUP1 + 0,    "org.gnu.gdb.or1k.group1", "dmmu"},
 144         {"dmmuupr"  , GROUP1 + 1,    "org.gnu.gdb.or1k.group1", "dmmu"},
 145         {"dtlbeir"  , GROUP1 + 2,    "org.gnu.gdb.or1k.group1", "dmmu"},
 146         {"datbmr0"  , GROUP1 + 4,    "org.gnu.gdb.or1k.group1", "dmmu"},
 147         {"datbmr1"  , GROUP1 + 5,    "org.gnu.gdb.or1k.group1", "dmmu"},
 148         {"datbmr2"  , GROUP1 + 6,    "org.gnu.gdb.or1k.group1", "dmmu"},
 149         {"datbmr3"  , GROUP1 + 7,    "org.gnu.gdb.or1k.group1", "dmmu"},
 150         {"datbtr0"  , GROUP1 + 8,    "org.gnu.gdb.or1k.group1", "dmmu"},
 151         {"datbtr1"  , GROUP1 + 9,    "org.gnu.gdb.or1k.group1", "dmmu"},
 152         {"datbtr2"  , GROUP1 + 10,   "org.gnu.gdb.or1k.group1", "dmmu"},
 153         {"datbtr3"  , GROUP1 + 11,   "org.gnu.gdb.or1k.group1", "dmmu"},
 154
 155         {"immucr"   , GROUP2 + 0,    "org.gnu.gdb.or1k.group2", "immu"},
 156         {"immupr"   , GROUP2 + 1,    "org.gnu.gdb.or1k.group2", "immu"},
 157         {"itlbeir"  , GROUP2 + 2,    "org.gnu.gdb.or1k.group2", "immu"},
 158         {"iatbmr0"  , GROUP2 + 4,    "org.gnu.gdb.or1k.group2", "immu"},
 159         {"iatbmr1"  , GROUP2 + 5,    "org.gnu.gdb.or1k.group2", "immu"},
 160         {"iatbmr2"  , GROUP2 + 6,    "org.gnu.gdb.or1k.group2", "immu"},
 161         {"iatbmr3"  , GROUP2 + 7,    "org.gnu.gdb.or1k.group2", "immu"},
 162         {"iatbtr0"  , GROUP2 + 8,    "org.gnu.gdb.or1k.group2", "immu"},
 163         {"iatbtr1"  , GROUP2 + 9,    "org.gnu.gdb.or1k.group2", "immu"},
 164         {"iatbtr2"  , GROUP2 + 10,   "org.gnu.gdb.or1k.group2", "immu"},
 165         {"iatbtr3"  , GROUP2 + 11,   "org.gnu.gdb.or1k.group2", "immu"},
 166
 167         {"dccr"     , GROUP3 + 0,    "org.gnu.gdb.or1k.group3", "dcache"},
 168         {"dcbpr"    , GROUP3 + 1,    "org.gnu.gdb.or1k.group3", "dcache"},
 169         {"dcbfr"    , GROUP3 + 2,    "org.gnu.gdb.or1k.group3", "dcache"},
 170         {"dcbir"    , GROUP3 + 3,    "org.gnu.gdb.or1k.group3", "dcache"},
 171         {"dcbwr"    , GROUP3 + 4,    "org.gnu.gdb.or1k.group3", "dcache"},
 172         {"dcblr"    , GROUP3 + 5,    "org.gnu.gdb.or1k.group3", "dcache"},
 173
 174         {"iccr"     , GROUP4 + 0,    "org.gnu.gdb.or1k.group4", "icache"},
 175         {"icbpr"    , GROUP4 + 1,    "org.gnu.gdb.or1k.group4", "icache"},
 176         {"icbir"    , GROUP4 + 2,    "org.gnu.gdb.or1k.group4", "icache"},
 177         {"icblr"    , GROUP4 + 3,    "org.gnu.gdb.or1k.group4", "icache"},
 178
 179         {"maclo"    , GROUP5 + 0,    "org.gnu.gdb.or1k.group5", "mac"},
 180         {"machi"    , GROUP5 + 1,    "org.gnu.gdb.or1k.group5", "mac"},
 181
 182         {"dvr0"     , GROUP6 + 0,    "org.gnu.gdb.or1k.group6", "debug"},
 183         {"dvr1"     , GROUP6 + 1,    "org.gnu.gdb.or1k.group6", "debug"},
 184         {"dvr2"     , GROUP6 + 2,    "org.gnu.gdb.or1k.group6", "debug"},
 185         {"dvr3"     , GROUP6 + 3,    "org.gnu.gdb.or1k.group6", "debug"},
 186         {"dvr4"     , GROUP6 + 4,    "org.gnu.gdb.or1k.group6", "debug"},
 187         {"dvr5"     , GROUP6 + 5,    "org.gnu.gdb.or1k.group6", "debug"},
 188         {"dvr6"     , GROUP6 + 6,    "org.gnu.gdb.or1k.group6", "debug"},
 189         {"dvr7"     , GROUP6 + 7,    "org.gnu.gdb.or1k.group6", "debug"},
 190         {"dcr0"     , GROUP6 + 8,    "org.gnu.gdb.or1k.group6", "debug"},
 191         {"dcr1"     , GROUP6 + 9,    "org.gnu.gdb.or1k.group6", "debug"},
 192         {"dcr2"     , GROUP6 + 10,   "org.gnu.gdb.or1k.group6", "debug"},
 193         {"dcr3"     , GROUP6 + 11,   "org.gnu.gdb.or1k.group6", "debug"},
 194         {"dcr4"     , GROUP6 + 12,   "org.gnu.gdb.or1k.group6", "debug"},
 195         {"dcr5"     , GROUP6 + 13,   "org.gnu.gdb.or1k.group6", "debug"},
 196         {"dcr6"     , GROUP6 + 14,   "org.gnu.gdb.or1k.group6", "debug"},
 197         {"dcr7"     , GROUP6 + 15,   "org.gnu.gdb.or1k.group6", "debug"},
 198         {"dmr1"     , GROUP6 + 16,   "org.gnu.gdb.or1k.group6", "debug"},
 199         {"dmr2"     , GROUP6 + 17,   "org.gnu.gdb.or1k.group6", "debug"},
 200         {"dcwr0"    , GROUP6 + 18,   "org.gnu.gdb.or1k.group6", "debug"},
 201         {"dcwr1"    , GROUP6 + 19,   "org.gnu.gdb.or1k.group6", "debug"},
 202         {"dsr"      , GROUP6 + 20,   "org.gnu.gdb.or1k.group6", "debug"},
 203         {"drr"      , GROUP6 + 21,   "org.gnu.gdb.or1k.group6", "debug"},
 204
 205         {"pccr0"    , GROUP7 + 0,    "org.gnu.gdb.or1k.group7", "perf"},
 206         {"pccr1"    , GROUP7 + 1,    "org.gnu.gdb.or1k.group7", "perf"},
 207         {"pccr2"    , GROUP7 + 2,    "org.gnu.gdb.or1k.group7", "perf"},
 208         {"pccr3"    , GROUP7 + 3,    "org.gnu.gdb.or1k.group7", "perf"},
 209         {"pccr4"    , GROUP7 + 4,    "org.gnu.gdb.or1k.group7", "perf"},
 210         {"pccr5"    , GROUP7 + 5,    "org.gnu.gdb.or1k.group7", "perf"},
 211         {"pccr6"    , GROUP7 + 6,    "org.gnu.gdb.or1k.group7", "perf"},
 212         {"pccr7"    , GROUP7 + 7,    "org.gnu.gdb.or1k.group7", "perf"},
 213         {"pcmr0"    , GROUP7 + 8,    "org.gnu.gdb.or1k.group7", "perf"},
 214         {"pcmr1"    , GROUP7 + 9,    "org.gnu.gdb.or1k.group7", "perf"},
 215         {"pcmr2"    , GROUP7 + 10,   "org.gnu.gdb.or1k.group7", "perf"},
 216         {"pcmr3"    , GROUP7 + 11,   "org.gnu.gdb.or1k.group7", "perf"},
 217         {"pcmr4"    , GROUP7 + 12,   "org.gnu.gdb.or1k.group7", "perf"},
 218         {"pcmr5"    , GROUP7 + 13,   "org.gnu.gdb.or1k.group7", "perf"},
 219         {"pcmr6"    , GROUP7 + 14,   "org.gnu.gdb.or1k.group7", "perf"},
 220         {"pcmr7"    , GROUP7 + 15,   "org.gnu.gdb.or1k.group7", "perf"},
 221
 222         {"pmr"      , GROUP8 + 0,    "org.gnu.gdb.or1k.group8", "power"},
 223
 224         {"picmr"    , GROUP9 + 0,    "org.gnu.gdb.or1k.group9", "pic"},
 225         {"picsr"    , GROUP9 + 2,    "org.gnu.gdb.or1k.group9", "pic"},
 226
 227         {"ttmr"     , GROUP10 + 0,   "org.gnu.gdb.or1k.group10", "timer"},
 228         {"ttcr"     , GROUP10 + 1,   "org.gnu.gdb.or1k.group10", "timer"},
 229 };
 230
 231 static int or1k_add_reg(struct target *target, struct or1k_core_reg *new_reg)
 232 {
 233         struct or1k_common *or1k = target_to_or1k(target);
 234         int reg_list_size = or1k->nb_regs * sizeof(struct or1k_core_reg);
 235
 236         or1k_core_reg_list_arch_info = realloc(or1k_core_reg_list_arch_info,
 237                                 reg_list_size + sizeof(struct or1k_core_reg));
 238
 239         memcpy(&or1k_core_reg_list_arch_info[or1k->nb_regs], new_reg,
 240                 sizeof(struct or1k_core_reg));
 241
 242         or1k_core_reg_list_arch_info[or1k->nb_regs].list_num = or1k->nb_regs;
 243
 244         or1k->nb_regs++;
 245
 246         return ERROR_OK;
 247 }
 248
 249 static int or1k_create_reg_list(struct target *target)
 250 {
 251         struct or1k_common *or1k = target_to_or1k(target);
 252
 253         LOG_DEBUG("-");
 254
 255         or1k_core_reg_list_arch_info = malloc(ARRAY_SIZE(or1k_init_reg_list) *
 256                                        sizeof(struct or1k_core_reg));
 257
 258         for (int i = 0; i < (int)ARRAY_SIZE(or1k_init_reg_list); i++) {
 259                 or1k_core_reg_list_arch_info[i].name = or1k_init_reg_list[i].name;
 260                 or1k_core_reg_list_arch_info[i].spr_num = or1k_init_reg_list[i].spr_num;
 261                 or1k_core_reg_list_arch_info[i].group = or1k_init_reg_list[i].group;
 262                 or1k_core_reg_list_arch_info[i].feature = or1k_init_reg_list[i].feature;
 263                 or1k_core_reg_list_arch_info[i].list_num = i;
 264                 or1k_core_reg_list_arch_info[i].target = NULL;
 265                 or1k_core_reg_list_arch_info[i].or1k_common = NULL;
 266         }
 267
 268         or1k->nb_regs = ARRAY_SIZE(or1k_init_reg_list);
 269
 270         struct or1k_core_reg new_reg;
 271         new_reg.target = NULL;
 272         new_reg.or1k_common = NULL;
 273
 274         char name[32];
 275         for (int way = 0; way < 4; way++) {
 276                 for (int i = 0; i < 128; i++) {
 277
 278                         sprintf(name, "dtlbw%dmr%d", way, i);
 279                         new_reg.name = strdup(name);
 280                         new_reg.spr_num = GROUP1 + 512 + i + (way * 256);
 281                         new_reg.feature = "org.gnu.gdb.or1k.group1";
 282                         new_reg.group = "dmmu";
 283                         or1k_add_reg(target, &new_reg);
 284
 285                         sprintf(name, "dtlbw%dtr%d", way, i);
 286                         new_reg.name = strdup(name);
 287                         new_reg.spr_num = GROUP1 + 640 + i + (way * 256);
 288                         new_reg.feature = "org.gnu.gdb.or1k.group1";
 289                         new_reg.group = "dmmu";
 290                         or1k_add_reg(target, &new_reg);
 291
 292
 293                         sprintf(name, "itlbw%dmr%d", way, i);
 294                         new_reg.name = strdup(name);
 295                         new_reg.spr_num = GROUP2 + 512 + i + (way * 256);
 296                         new_reg.feature = "org.gnu.gdb.or1k.group2";
 297                         new_reg.group = "immu";
 298                         or1k_add_reg(target, &new_reg);
 299
 300
 301                         sprintf(name, "itlbw%dtr%d", way, i);
 302                         new_reg.name = strdup(name);
 303                         new_reg.spr_num = GROUP2 + 640 + i + (way * 256);
 304                         new_reg.feature = "org.gnu.gdb.or1k.group2";
 305                         new_reg.group = "immu";
 306                         or1k_add_reg(target, &new_reg);
 307
 308                 }
 309         }
 310
 311         return ERROR_OK;
 312 }
 313
 314 static int or1k_jtag_read_regs(struct or1k_common *or1k, uint32_t *regs)
 315 {
 316         struct or1k_du *du_core = or1k_jtag_to_du(&or1k->jtag);
 317
 318         LOG_DEBUG("-");
 319
 320         return du_core->or1k_jtag_read_cpu(&or1k->jtag,
 321                         or1k->arch_info[OR1K_REG_R0].spr_num, OR1K_REG_R31 + 1,
 322                         regs + OR1K_REG_R0);
 323 }
 324
 325 static int or1k_jtag_write_regs(struct or1k_common *or1k, uint32_t *regs)
 326 {
 327         struct or1k_du *du_core = or1k_jtag_to_du(&or1k->jtag);
 328
 329         LOG_DEBUG("-");
 330
 331         return du_core->or1k_jtag_write_cpu(&or1k->jtag,
 332                         or1k->arch_info[OR1K_REG_R0].spr_num, OR1K_REG_R31 + 1,
 333                         &regs[OR1K_REG_R0]);
 334 }
 335
 336 static int or1k_save_context(struct target *target)
 337 {
 338         struct or1k_common *or1k = target_to_or1k(target);
 339         struct or1k_du *du_core = or1k_to_du(or1k);
 340         int regs_read = 0;
 341         int retval;
 342
 343         LOG_DEBUG("-");
 344
 345         for (int i = 0; i < OR1KNUMCOREREGS; i++) {
 346                 if (!or1k->core_cache->reg_list[i].valid) {
 347                         if (i == OR1K_REG_PPC || i == OR1K_REG_NPC || i == OR1K_REG_SR) {
 348                                 retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
 349                                                 or1k->arch_info[i].spr_num, 1,
 350                                                 &or1k->core_regs[i]);
 351                                 if (retval != ERROR_OK)
 352                                         return retval;
 353                         } else if (!regs_read) {
 354                                 /* read gpr registers at once (but only one time in this loop) */
 355                                 retval = or1k_jtag_read_regs(or1k, or1k->core_regs);
 356                                 if (retval != ERROR_OK)
 357                                         return retval;
 358                                 /* prevent next reads in this loop */
 359                                 regs_read = 1;
 360                         }
 361                         /* We've just updated the core_reg[i], now update
 362                            the core cache */
 363                         or1k_read_core_reg(target, i);
 364                 }
 365         }
 366
 367         return ERROR_OK;
 368 }
 369
 370 static int or1k_restore_context(struct target *target)
 371 {
 372         struct or1k_common *or1k = target_to_or1k(target);
 373         struct or1k_du *du_core = or1k_to_du(or1k);
 374         int reg_write = 0;
 375         int retval;
 376
 377         LOG_DEBUG("-");
 378
 379         for (int i = 0; i < OR1KNUMCOREREGS; i++) {
 380                 if (or1k->core_cache->reg_list[i].dirty) {
 381                         or1k_write_core_reg(target, i);
 382
 383                         if (i == OR1K_REG_PPC || i == OR1K_REG_NPC || i == OR1K_REG_SR) {
 384                                 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
 385                                                 or1k->arch_info[i].spr_num, 1,
 386                                                 &or1k->core_regs[i]);
 387                                 if (retval != ERROR_OK) {
 388                                         LOG_ERROR("Error while restoring context");
 389                                         return retval;
 390                                 }
 391                         } else
 392                                 reg_write = 1;
 393                 }
 394         }
 395
 396         if (reg_write) {
 397                 /* read gpr registers at once (but only one time in this loop) */
 398                 retval = or1k_jtag_write_regs(or1k, or1k->core_regs);
 399                 if (retval != ERROR_OK) {
 400                         LOG_ERROR("Error while restoring context");
 401                         return retval;
 402                 }
 403         }
 404
 405         return ERROR_OK;
 406 }
 407
 408 static int or1k_read_core_reg(struct target *target, int num)
 409 {
 410         struct or1k_common *or1k = target_to_or1k(target);
 411         struct or1k_du *du_core = or1k_to_du(or1k);
 412         uint32_t reg_value;
 413
 414         LOG_DEBUG("-");
 415
 416         if ((num < 0) || (num >= or1k->nb_regs))
 417                 return ERROR_COMMAND_SYNTAX_ERROR;
 418
 419         if ((num >= 0) && (num < OR1KNUMCOREREGS)) {
 420                 reg_value = or1k->core_regs[num];
 421                 buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
 422                 LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value);
 423                 or1k->core_cache->reg_list[num].valid = 1;
 424                 or1k->core_cache->reg_list[num].dirty = 0;
 425         } else {
 426                 /* This is an spr, always read value from HW */
 427                 int retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
 428                                                          or1k->arch_info[num].spr_num, 1, &reg_value);
 429                 if (retval != ERROR_OK) {
 430                         LOG_ERROR("Error while reading spr 0x%08" PRIx32, or1k->arch_info[num].spr_num);
 431                         return retval;
 432                 }
 433                 buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
 434                 LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num , reg_value);
 435         }
 436
 437         return ERROR_OK;
 438 }
 439
 440 static int or1k_write_core_reg(struct target *target, int num)
 441 {
 442         struct or1k_common *or1k = target_to_or1k(target);
 443
 444         LOG_DEBUG("-");
 445
 446         if ((num < 0) || (num >= OR1KNUMCOREREGS))
 447                 return ERROR_COMMAND_SYNTAX_ERROR;
 448
 449         uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
 450         or1k->core_regs[num] = reg_value;
 451         LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value);
 452         or1k->core_cache->reg_list[num].valid = 1;
 453         or1k->core_cache->reg_list[num].dirty = 0;
 454
 455         return ERROR_OK;
 456 }
 457
 458 static int or1k_get_core_reg(struct reg *reg)
 459 {
 460         struct or1k_core_reg *or1k_reg = reg->arch_info;
 461         struct target *target = or1k_reg->target;
 462
 463         LOG_DEBUG("-");
 464
 465         if (target->state != TARGET_HALTED)
 466                 return ERROR_TARGET_NOT_HALTED;
 467
 468         return or1k_read_core_reg(target, or1k_reg->list_num);
 469 }
 470
 471 static int or1k_set_core_reg(struct reg *reg, uint8_t *buf)
 472 {
 473         struct or1k_core_reg *or1k_reg = reg->arch_info;
 474         struct target *target = or1k_reg->target;
 475         struct or1k_common *or1k = target_to_or1k(target);
 476         struct or1k_du *du_core = or1k_to_du(or1k);
 477         uint32_t value = buf_get_u32(buf, 0, 32);
 478
 479         LOG_DEBUG("-");
 480
 481         if (target->state != TARGET_HALTED)
 482                 return ERROR_TARGET_NOT_HALTED;
 483
 484         if (or1k_reg->list_num < OR1KNUMCOREREGS) {
 485                 buf_set_u32(reg->value, 0, 32, value);
 486                 reg->dirty = 1;
 487                 reg->valid = 1;
 488         } else {
 489                 /* This is an spr, write it to the HW */
 490                 int retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
 491                                                           or1k_reg->spr_num, 1, &value);
 492                 if (retval != ERROR_OK) {
 493                         LOG_ERROR("Error while writing spr 0x%08" PRIx32, or1k_reg->spr_num);
 494                         return retval;
 495                 }
 496         }
 497
 498         return ERROR_OK;
 499 }
 500
 501 static const struct reg_arch_type or1k_reg_type = {
 502         .get = or1k_get_core_reg,
 503         .set = or1k_set_core_reg,
 504 };
 505
 506 static struct reg_cache *or1k_build_reg_cache(struct target *target)
 507 {
 508         struct or1k_common *or1k = target_to_or1k(target);
 509         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 510         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 511         struct reg *reg_list = calloc(or1k->nb_regs, sizeof(struct reg));
 512         struct or1k_core_reg *arch_info =
 513                 malloc((or1k->nb_regs) * sizeof(struct or1k_core_reg));
 514         struct reg_feature *feature;
 515
 516         LOG_DEBUG("-");
 517
 518         /* Build the process context cache */
 519         cache->name = "OpenRISC 1000 registers";
 520         cache->next = NULL;
 521         cache->reg_list = reg_list;
 522         cache->num_regs = or1k->nb_regs;
 523         (*cache_p) = cache;
 524         or1k->core_cache = cache;
 525         or1k->arch_info = arch_info;
 526
 527         for (int i = 0; i < or1k->nb_regs; i++) {
 528                 arch_info[i] = or1k_core_reg_list_arch_info[i];
 529                 arch_info[i].target = target;
 530                 arch_info[i].or1k_common = or1k;
 531                 reg_list[i].name = or1k_core_reg_list_arch_info[i].name;
 532
 533                 feature = malloc(sizeof(struct reg_feature));
 534                 feature->name = or1k_core_reg_list_arch_info[i].feature;
 535                 reg_list[i].feature = feature;
 536
 537                 reg_list[i].group = or1k_core_reg_list_arch_info[i].group;
 538                 reg_list[i].size = 32;
 539                 reg_list[i].value = calloc(1, 4);
 540                 reg_list[i].dirty = 0;
 541                 reg_list[i].valid = 0;
 542                 reg_list[i].type = &or1k_reg_type;
 543                 reg_list[i].arch_info = &arch_info[i];
 544                 reg_list[i].number = i;
 545                 reg_list[i].exist = true;
 546         }
 547
 548         return cache;
 549 }
 550
 551 static int or1k_debug_entry(struct target *target)
 552 {
 553         LOG_DEBUG("-");
 554
 555         int retval = or1k_save_context(target);
 556         if (retval != ERROR_OK) {
 557                 LOG_ERROR("Error while calling or1k_save_context");
 558                 return retval;
 559         }
 560
 561         struct or1k_common *or1k = target_to_or1k(target);
 562         uint32_t addr = or1k->core_regs[OR1K_REG_NPC];
 563
 564         if (breakpoint_find(target, addr))
 565                 /* Halted on a breakpoint, step back to permit executing the instruction there */
 566                 retval = or1k_set_core_reg(&or1k->core_cache->reg_list[OR1K_REG_NPC],
 567                                            (uint8_t *)&addr);
 568
 569         return retval;
 570 }
 571
 572 static int or1k_halt(struct target *target)
 573 {
 574         struct or1k_common *or1k = target_to_or1k(target);
 575         struct or1k_du *du_core = or1k_to_du(or1k);
 576
 577         LOG_DEBUG("target->state: %s",
 578                   target_state_name(target));
 579
 580         if (target->state == TARGET_HALTED) {
 581                 LOG_DEBUG("Target was already halted");
 582                 return ERROR_OK;
 583         }
 584
 585         if (target->state == TARGET_UNKNOWN)
 586                 LOG_WARNING("Target was in unknown state when halt was requested");
 587
 588         if (target->state == TARGET_RESET) {
 589                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) &&
 590                     jtag_get_srst()) {
 591                         LOG_ERROR("Can't request a halt while in reset if nSRST pulls nTRST");
 592                         return ERROR_TARGET_FAILURE;
 593                 } else {
 594                         target->debug_reason = DBG_REASON_DBGRQ;
 595                         return ERROR_OK;
 596                 }
 597         }
 598
 599         int retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_STALL);
 600         if (retval != ERROR_OK) {
 601                 LOG_ERROR("Impossible to stall the CPU");
 602                 return retval;
 603         }
 604
 605         target->debug_reason = DBG_REASON_DBGRQ;
 606
 607         return ERROR_OK;
 608 }
 609
 610 static int or1k_is_cpu_running(struct target *target, int *running)
 611 {
 612         struct or1k_common *or1k = target_to_or1k(target);
 613         struct or1k_du *du_core = or1k_to_du(or1k);
 614         int retval;
 615         int tries = 0;
 616         const int RETRIES_MAX = 5;
 617
 618         /* Have a retry loop to determine of the CPU is running.
 619            If target has been hard reset for any reason, it might take a couple
 620            of goes before it's ready again.
 621         */
 622         while (tries < RETRIES_MAX) {
 623
 624                 tries++;
 625
 626                 retval = du_core->or1k_is_cpu_running(&or1k->jtag, running);
 627                 if (retval != ERROR_OK) {
 628                         LOG_WARNING("Debug IF CPU control reg read failure.");
 629                         /* Try once to restart the JTAG infrastructure -
 630                            quite possibly the board has just been reset. */
 631                         LOG_WARNING("Resetting JTAG TAP state and reconnectiong to debug IF.");
 632                         du_core->or1k_jtag_init(&or1k->jtag);
 633
 634                         LOG_WARNING("...attempt %d of %d", tries, RETRIES_MAX);
 635
 636                         alive_sleep(2);
 637
 638                         continue;
 639                 } else
 640                         return ERROR_OK;
 641         }
 642
 643         LOG_ERROR("Could not re-establish communication with target");
 644         return retval;
 645 }
 646
 647 static int or1k_poll(struct target *target)
 648 {
 649         int retval;
 650         int running;
 651
 652         retval = or1k_is_cpu_running(target, &running);
 653         if (retval != ERROR_OK) {
 654                 LOG_ERROR("Error while calling or1k_is_cpu_running");
 655                 return retval;
 656         }
 657
 658         /* check for processor halted */
 659         if (!running) {
 660                 /* It's actually stalled, so update our software's state */
 661                 if ((target->state == TARGET_RUNNING) ||
 662                     (target->state == TARGET_RESET)) {
 663
 664                         target->state = TARGET_HALTED;
 665
 666                         retval = or1k_debug_entry(target);
 667                         if (retval != ERROR_OK) {
 668                                 LOG_ERROR("Error while calling or1k_debug_entry");
 669                                 return retval;
 670                         }
 671
 672                         target_call_event_callbacks(target,
 673                                                     TARGET_EVENT_HALTED);
 674                 } else if (target->state == TARGET_DEBUG_RUNNING) {
 675                         target->state = TARGET_HALTED;
 676
 677                         retval = or1k_debug_entry(target);
 678                         if (retval != ERROR_OK) {
 679                                 LOG_ERROR("Error while calling or1k_debug_entry");
 680                                 return retval;
 681                         }
 682
 683                         target_call_event_callbacks(target,
 684                                                     TARGET_EVENT_DEBUG_HALTED);
 685                 }
 686         } else { /* ... target is running */
 687
 688                 /* If target was supposed to be stalled, stall it again */
 689                 if  (target->state == TARGET_HALTED) {
 690
 691                         target->state = TARGET_RUNNING;
 692
 693                         retval = or1k_halt(target);
 694                         if (retval != ERROR_OK) {
 695                                 LOG_ERROR("Error while calling or1k_halt");
 696                                 return retval;
 697                         }
 698
 699                         retval = or1k_debug_entry(target);
 700                         if (retval != ERROR_OK) {
 701                                 LOG_ERROR("Error while calling or1k_debug_entry");
 702                                 return retval;
 703                         }
 704
 705                         target_call_event_callbacks(target,
 706                                                     TARGET_EVENT_DEBUG_HALTED);
 707                 }
 708
 709                 target->state = TARGET_RUNNING;
 710
 711         }
 712
 713         return ERROR_OK;
 714 }
 715
 716 static int or1k_assert_reset(struct target *target)
 717 {
 718         struct or1k_common *or1k = target_to_or1k(target);
 719         struct or1k_du *du_core = or1k_to_du(or1k);
 720
 721         LOG_DEBUG("-");
 722
 723         int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_RESET);
 724         if (retval != ERROR_OK) {
 725                 LOG_ERROR("Error while asserting RESET");
 726                 return retval;
 727         }
 728
 729         return ERROR_OK;
 730 }
 731
 732 static int or1k_deassert_reset(struct target *target)
 733 {
 734         struct or1k_common *or1k = target_to_or1k(target);
 735         struct or1k_du *du_core = or1k_to_du(or1k);
 736
 737         LOG_DEBUG("-");
 738
 739         int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_NOT_RESET);
 740         if (retval != ERROR_OK) {
 741                 LOG_ERROR("Error while desasserting RESET");
 742                 return retval;
 743         }
 744
 745         return ERROR_OK;
 746 }
 747
 748 static int or1k_soft_reset_halt(struct target *target)
 749 {
 750         struct or1k_common *or1k = target_to_or1k(target);
 751         struct or1k_du *du_core = or1k_to_du(or1k);
 752
 753         LOG_DEBUG("-");
 754
 755         int retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_STALL);
 756         if (retval != ERROR_OK) {
 757                 LOG_ERROR("Error while stalling the CPU");
 758                 return retval;
 759         }
 760
 761         retval = or1k_assert_reset(target);
 762         if (retval != ERROR_OK)
 763                 return retval;
 764
 765         retval = or1k_deassert_reset(target);
 766         if (retval != ERROR_OK)
 767                 return retval;
 768
 769         return ERROR_OK;
 770 }
 771
 772 static bool is_any_soft_breakpoint(struct target *target)
 773 {
 774         struct breakpoint *breakpoint = target->breakpoints;
 775
 776         LOG_DEBUG("-");
 777
 778         while (breakpoint)
 779                 if (breakpoint->type == BKPT_SOFT)
 780                         return true;
 781
 782         return false;
 783 }
 784
 785 static int or1k_resume_or_step(struct target *target, int current,
 786                                uint32_t address, int handle_breakpoints,
 787                                int debug_execution, int step)
 788 {
 789         struct or1k_common *or1k = target_to_or1k(target);
 790         struct or1k_du *du_core = or1k_to_du(or1k);
 791         struct breakpoint *breakpoint = NULL;
 792         uint32_t resume_pc;
 793         uint32_t debug_reg_list[OR1K_DEBUG_REG_NUM];
 794
 795         LOG_DEBUG("Addr: 0x%" PRIx32 ", stepping: %s, handle breakpoints %s\n",
 796                   address, step ? "yes" : "no", handle_breakpoints ? "yes" : "no");
 797
 798         if (target->state != TARGET_HALTED) {
 799                 LOG_ERROR("Target not halted");
 800                 return ERROR_TARGET_NOT_HALTED;
 801         }
 802
 803         if (!debug_execution)
 804                 target_free_all_working_areas(target);
 805
 806         /* current ? continue on current pc : continue at <address> */
 807         if (!current)
 808                 buf_set_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value, 0,
 809                             32, address);
 810
 811         int retval = or1k_restore_context(target);
 812         if (retval != ERROR_OK) {
 813                 LOG_ERROR("Error while calling or1k_restore_context");
 814                 return retval;
 815         }
 816
 817         /* read debug registers (starting from DMR1 register) */
 818         retval = du_core->or1k_jtag_read_cpu(&or1k->jtag, OR1K_DMR1_CPU_REG_ADD,
 819                                              OR1K_DEBUG_REG_NUM, debug_reg_list);
 820         if (retval != ERROR_OK) {
 821                 LOG_ERROR("Error while reading debug registers");
 822                 return retval;
 823         }
 824
 825         /* Clear Debug Reason Register (DRR) */
 826         debug_reg_list[OR1K_DEBUG_REG_DRR] = 0;
 827
 828         /* Clear watchpoint break generation in Debug Mode Register 2 (DMR2) */
 829         debug_reg_list[OR1K_DEBUG_REG_DMR2] &= ~OR1K_DMR2_WGB;
 830         if (step)
 831                 /* Set the single step trigger in Debug Mode Register 1 (DMR1) */
 832                 debug_reg_list[OR1K_DEBUG_REG_DMR1] |= OR1K_DMR1_ST | OR1K_DMR1_BT;
 833         else
 834                 /* Clear the single step trigger in Debug Mode Register 1 (DMR1) */
 835                 debug_reg_list[OR1K_DEBUG_REG_DMR1] &= ~(OR1K_DMR1_ST | OR1K_DMR1_BT);
 836
 837         /* Set traps to be handled by the debug unit in the Debug Stop
 838            Register (DSR). Check if we have any software breakpoints in
 839            place before setting this value - the kernel, for instance,
 840            relies on l.trap instructions not stalling the processor ! */
 841         if (is_any_soft_breakpoint(target) == true)
 842                 debug_reg_list[OR1K_DEBUG_REG_DSR] |= OR1K_DSR_TE;
 843
 844         /* Write debug registers (starting from DMR1 register) */
 845         retval = du_core->or1k_jtag_write_cpu(&or1k->jtag, OR1K_DMR1_CPU_REG_ADD,
 846                                               OR1K_DEBUG_REG_NUM, debug_reg_list);
 847         if (retval != ERROR_OK) {
 848                 LOG_ERROR("Error while writing back debug registers");
 849                 return retval;
 850         }
 851
 852         resume_pc = buf_get_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value,
 853                                 0, 32);
 854
 855         /* The front-end may request us not to handle breakpoints */
 856         if (handle_breakpoints) {
 857                 /* Single step past breakpoint at current address */
 858                 breakpoint = breakpoint_find(target, resume_pc);
 859                 if (breakpoint) {
 860                         LOG_DEBUG("Unset breakpoint at 0x%08" PRIx32, breakpoint->address);
 861                         retval = or1k_remove_breakpoint(target, breakpoint);
 862                         if (retval != ERROR_OK)
 863                                 return retval;
 864                 }
 865         }
 866
 867         /* Unstall time */
 868         retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_UNSTALL);
 869         if (retval != ERROR_OK) {
 870                 LOG_ERROR("Error while unstalling the CPU");
 871                 return retval;
 872         }
 873
 874         if (step)
 875                 target->debug_reason = DBG_REASON_SINGLESTEP;
 876         else
 877                 target->debug_reason = DBG_REASON_NOTHALTED;
 878
 879         /* Registers are now invalid */
 880         register_cache_invalidate(or1k->core_cache);
 881
 882         if (!debug_execution) {
 883                 target->state = TARGET_RUNNING;
 884                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 885                 LOG_DEBUG("Target resumed at 0x%08" PRIx32, resume_pc);
 886         } else {
 887                 target->state = TARGET_DEBUG_RUNNING;
 888                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 889                 LOG_DEBUG("Target debug resumed at 0x%08" PRIx32, resume_pc);
 890         }
 891
 892         return ERROR_OK;
 893 }
 894
 895 static int or1k_resume(struct target *target, int current,
 896                 uint32_t address, int handle_breakpoints, int debug_execution)
 897 {
 898         return or1k_resume_or_step(target, current, address,
 899                                    handle_breakpoints,
 900                                    debug_execution,
 901                                    NO_SINGLE_STEP);
 902 }
 903
 904 static int or1k_step(struct target *target, int current,
 905                      uint32_t address, int handle_breakpoints)
 906 {
 907         return or1k_resume_or_step(target, current, address,
 908                                    handle_breakpoints,
 909                                    0,
 910                                    SINGLE_STEP);
 911
 912 }
 913
 914 static int or1k_add_breakpoint(struct target *target,
 915                                struct breakpoint *breakpoint)
 916 {
 917         struct or1k_common *or1k = target_to_or1k(target);
 918         struct or1k_du *du_core = or1k_to_du(or1k);
 919         uint8_t data;
 920
 921         LOG_DEBUG("Adding breakpoint: addr 0x%08" PRIx32 ", len %d, type %d, set: %d, id: %" PRId32,
 922                   breakpoint->address, breakpoint->length, breakpoint->type,
 923                   breakpoint->set, breakpoint->unique_id);
 924
 925         /* Only support SW breakpoints for now. */
 926         if (breakpoint->type == BKPT_HARD)
 927                 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
 928
 929         /* Read and save the instruction */
 930         int retval = du_core->or1k_jtag_read_memory(&or1k->jtag,
 931                                          breakpoint->address,
 932                                          4,
 933                                          1,
 934                                          &data);
 935         if (retval != ERROR_OK) {
 936                 LOG_ERROR("Error while reading the instruction at 0x%08" PRIx32,
 937                            breakpoint->address);
 938                 return retval;
 939         }
 940
 941         if (breakpoint->orig_instr != NULL)
 942                 free(breakpoint->orig_instr);
 943
 944         breakpoint->orig_instr = malloc(breakpoint->length);
 945         memcpy(breakpoint->orig_instr, &data, breakpoint->length);
 946
 947         /* Sub in the OR1K trap instruction */
 948         uint8_t or1k_trap_insn[4];
 949         target_buffer_set_u32(target, or1k_trap_insn, OR1K_TRAP_INSTR);
 950         retval = du_core->or1k_jtag_write_memory(&or1k->jtag,
 951                                           breakpoint->address,
 952                                           4,
 953                                           1,
 954                                           or1k_trap_insn);
 955
 956         if (retval != ERROR_OK) {
 957                 LOG_ERROR("Error while writing OR1K_TRAP_INSTR at 0x%08" PRIx32,
 958                            breakpoint->address);
 959                 return retval;
 960         }
 961
 962         /* invalidate instruction cache */
 963         retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
 964                         OR1K_ICBIR_CPU_REG_ADD, 1, &breakpoint->address);
 965         if (retval != ERROR_OK) {
 966                 LOG_ERROR("Error while invalidating the ICACHE");
 967                 return retval;
 968         }
 969
 970         return ERROR_OK;
 971 }
 972
 973 static int or1k_remove_breakpoint(struct target *target,
 974                                   struct breakpoint *breakpoint)
 975 {
 976         struct or1k_common *or1k = target_to_or1k(target);
 977         struct or1k_du *du_core = or1k_to_du(or1k);
 978
 979         LOG_DEBUG("Removing breakpoint: addr 0x%08" PRIx32 ", len %d, type %d, set: %d, id: %" PRId32,
 980                   breakpoint->address, breakpoint->length, breakpoint->type,
 981                   breakpoint->set, breakpoint->unique_id);
 982
 983         /* Only support SW breakpoints for now. */
 984         if (breakpoint->type == BKPT_HARD)
 985                 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
 986
 987         /* Replace the removed instruction */
 988         int retval = du_core->or1k_jtag_write_memory(&or1k->jtag,
 989                                           breakpoint->address,
 990                                           4,
 991                                           1,
 992                                           breakpoint->orig_instr);
 993
 994         if (retval != ERROR_OK) {
 995                 LOG_ERROR("Error while writing back the instruction at 0x%08" PRIx32,
 996                            breakpoint->address);
 997                 return retval;
 998         }
 999
1000         /* invalidate instruction cache */
1001         retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
1002                         OR1K_ICBIR_CPU_REG_ADD, 1, &breakpoint->address);
1003         if (retval != ERROR_OK) {
1004                 LOG_ERROR("Error while invalidating the ICACHE");
1005                 return retval;
1006         }
1007
1008         return ERROR_OK;
1009 }
1010
1011 static int or1k_add_watchpoint(struct target *target,
1012                                struct watchpoint *watchpoint)
1013 {
1014         LOG_ERROR("%s: implement me", __func__);
1015         return ERROR_OK;
1016 }
1017
1018 static int or1k_remove_watchpoint(struct target *target,
1019                                   struct watchpoint *watchpoint)
1020 {
1021         LOG_ERROR("%s: implement me", __func__);
1022         return ERROR_OK;
1023 }
1024
1025 static int or1k_read_memory(struct target *target, uint32_t address,
1026                 uint32_t size, uint32_t count, uint8_t *buffer)
1027 {
1028         struct or1k_common *or1k = target_to_or1k(target);
1029         struct or1k_du *du_core = or1k_to_du(or1k);
1030
1031         LOG_DEBUG("Read memory at 0x%08" PRIx32 ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
1032
1033         if (target->state != TARGET_HALTED) {
1034                 LOG_ERROR("Target not halted");
1035                 return ERROR_TARGET_NOT_HALTED;
1036         }
1037
1038         /* Sanitize arguments */
1039         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !buffer) {
1040                 LOG_ERROR("Bad arguments");
1041                 return ERROR_COMMAND_SYNTAX_ERROR;
1042         }
1043
1044         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) {
1045                 LOG_ERROR("Can't handle unaligned memory access");
1046                 return ERROR_TARGET_UNALIGNED_ACCESS;
1047         }
1048
1049         return du_core->or1k_jtag_read_memory(&or1k->jtag, address, size, count, buffer);
1050 }
1051
1052 static int or1k_write_memory(struct target *target, uint32_t address,
1053                 uint32_t size, uint32_t count, const uint8_t *buffer)
1054 {
1055         struct or1k_common *or1k = target_to_or1k(target);
1056         struct or1k_du *du_core = or1k_to_du(or1k);
1057
1058         LOG_DEBUG("Write memory at 0x%08" PRIx32 ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
1059
1060         if (target->state != TARGET_HALTED) {
1061                 LOG_WARNING("Target not halted");
1062                 return ERROR_TARGET_NOT_HALTED;
1063         }
1064
1065         /* Sanitize arguments */
1066         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !buffer) {
1067                 LOG_ERROR("Bad arguments");
1068                 return ERROR_COMMAND_SYNTAX_ERROR;
1069         }
1070
1071         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) {
1072                 LOG_ERROR("Can't handle unaligned memory access");
1073                 return ERROR_TARGET_UNALIGNED_ACCESS;
1074         }
1075
1076         return du_core->or1k_jtag_write_memory(&or1k->jtag, address, size, count, buffer);
1077 }
1078
1079 static int or1k_init_target(struct command_context *cmd_ctx,
1080                 struct target *target)
1081 {
1082         struct or1k_common *or1k = target_to_or1k(target);
1083         struct or1k_du *du_core = or1k_to_du(or1k);
1084         struct or1k_jtag *jtag = &or1k->jtag;
1085
1086         if (du_core == NULL) {
1087                 LOG_ERROR("No debug unit selected");
1088                 return ERROR_FAIL;
1089         }
1090
1091         if (jtag->tap_ip == NULL) {
1092                 LOG_ERROR("No tap selected");
1093                 return ERROR_FAIL;
1094         }
1095
1096         or1k->jtag.tap = target->tap;
1097         or1k->jtag.or1k_jtag_inited = 0;
1098         or1k->jtag.or1k_jtag_module_selected = -1;
1099         or1k->jtag.target = target;
1100
1101         or1k_build_reg_cache(target);
1102
1103         return ERROR_OK;
1104 }
1105
1106 static int or1k_target_create(struct target *target, Jim_Interp *interp)
1107 {
1108         if (target->tap == NULL)
1109                 return ERROR_FAIL;
1110
1111         struct or1k_common *or1k = calloc(1, sizeof(struct or1k_common));
1112
1113         target->arch_info = or1k;
1114
1115         or1k_create_reg_list(target);
1116
1117         or1k_tap_vjtag_register();
1118         or1k_tap_xilinx_bscan_register();
1119         or1k_tap_mohor_register();
1120
1121         or1k_du_adv_register();
1122
1123         return ERROR_OK;
1124 }
1125
1126 static int or1k_examine(struct target *target)
1127 {
1128         struct or1k_common *or1k = target_to_or1k(target);
1129         struct or1k_du *du_core = or1k_to_du(or1k);
1130
1131         if (!target_was_examined(target)) {
1132
1133                 target_set_examined(target);
1134
1135                 int running;
1136
1137                 int retval = du_core->or1k_is_cpu_running(&or1k->jtag, &running);
1138                 if (retval != ERROR_OK) {
1139                         LOG_ERROR("Couldn't read the CPU state");
1140                         return retval;
1141                 } else {
1142                         if (running)
1143                                 target->state = TARGET_RUNNING;
1144                         else {
1145                                 LOG_DEBUG("Target is halted");
1146
1147                                 /* This is the first time we examine the target,
1148                                  * it is stalled and we don't know why. Let's
1149                                  * assume this is because of a debug reason.
1150                                  */
1151                                 if (target->state == TARGET_UNKNOWN)
1152                                         target->debug_reason = DBG_REASON_DBGRQ;
1153
1154                                 target->state = TARGET_HALTED;
1155                         }
1156                 }
1157         }
1158
1159         return ERROR_OK;
1160 }
1161
1162 static int or1k_arch_state(struct target *target)
1163 {
1164         return ERROR_OK;
1165 }
1166
1167 static int or1k_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
1168                           int *reg_list_size, enum target_register_class reg_class)
1169 {
1170         struct or1k_common *or1k = target_to_or1k(target);
1171
1172         if (reg_class == REG_CLASS_GENERAL) {
1173                 /* We will have this called whenever GDB connects. */
1174                 int retval = or1k_save_context(target);
1175                 if (retval != ERROR_OK) {
1176                         LOG_ERROR("Error while calling or1k_save_context");
1177                         return retval;
1178                 }
1179                 *reg_list_size = OR1KNUMCOREREGS;
1180                 /* this is free()'d back in gdb_server.c's gdb_get_register_packet() */
1181                 *reg_list = malloc((*reg_list_size) * sizeof(struct reg *));
1182
1183                 for (int i = 0; i < OR1KNUMCOREREGS; i++)
1184                         (*reg_list)[i] = &or1k->core_cache->reg_list[i];
1185         } else {
1186                 *reg_list_size = or1k->nb_regs;
1187                 *reg_list = malloc((*reg_list_size) * sizeof(struct reg *));
1188
1189                 for (int i = 0; i < or1k->nb_regs; i++)
1190                         (*reg_list)[i] = &or1k->core_cache->reg_list[i];
1191         }
1192
1193         return ERROR_OK;
1194
1195 }
1196
1197 int or1k_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info)
1198 {
1199         return ERROR_FAIL;
1200 }
1201
1202 static int or1k_checksum_memory(struct target *target, uint32_t address,
1203                 uint32_t count, uint32_t *checksum) {
1204
1205         return ERROR_FAIL;
1206 }
1207
1208 COMMAND_HANDLER(or1k_tap_select_command_handler)
1209 {
1210         struct target *target = get_current_target(CMD_CTX);
1211         struct or1k_common *or1k = target_to_or1k(target);
1212         struct or1k_jtag *jtag = &or1k->jtag;
1213         struct or1k_tap_ip *or1k_tap;
1214
1215         if (CMD_ARGC != 1)
1216                 return ERROR_COMMAND_SYNTAX_ERROR;
1217
1218         list_for_each_entry(or1k_tap, &tap_list, list) {
1219                 if (or1k_tap->name) {
1220                         if (!strcmp(CMD_ARGV[0], or1k_tap->name)) {
1221                                 jtag->tap_ip = or1k_tap;
1222                                 LOG_INFO("%s tap selected", or1k_tap->name);
1223                                 return ERROR_OK;
1224                         }
1225                 }
1226         }
1227
1228         LOG_ERROR("%s unknown, no tap selected", CMD_ARGV[0]);
1229         return ERROR_COMMAND_SYNTAX_ERROR;
1230 }
1231
1232 COMMAND_HANDLER(or1k_tap_list_command_handler)
1233 {
1234         struct or1k_tap_ip *or1k_tap;
1235
1236         if (CMD_ARGC != 0)
1237                 return ERROR_COMMAND_SYNTAX_ERROR;
1238
1239         list_for_each_entry(or1k_tap, &tap_list, list) {
1240                 if (or1k_tap->name)
1241                         command_print(CMD_CTX, "%s", or1k_tap->name);
1242         }
1243
1244         return ERROR_OK;
1245 }
1246
1247 COMMAND_HANDLER(or1k_du_select_command_handler)
1248 {
1249         struct target *target = get_current_target(CMD_CTX);
1250         struct or1k_common *or1k = target_to_or1k(target);
1251         struct or1k_jtag *jtag = &or1k->jtag;
1252         struct or1k_du *or1k_du;
1253
1254         if (CMD_ARGC > 2)
1255                 return ERROR_COMMAND_SYNTAX_ERROR;
1256
1257         list_for_each_entry(or1k_du, &du_list, list) {
1258                 if (or1k_du->name) {
1259                         if (!strcmp(CMD_ARGV[0], or1k_du->name)) {
1260                                 jtag->du_core = or1k_du;
1261                                 LOG_INFO("%s debug unit selected", or1k_du->name);
1262
1263                                 if (CMD_ARGC == 2) {
1264                                         int options;
1265                                         COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], options);
1266                                         or1k_du->options = options;
1267                                         LOG_INFO("Option %x is passed to %s debug unit"
1268                                                  , options, or1k_du->name);
1269                                 }
1270
1271                                 return ERROR_OK;
1272                         }
1273                 }
1274         }
1275
1276         LOG_ERROR("%s unknown, no debug unit selected", CMD_ARGV[0]);
1277         return ERROR_COMMAND_SYNTAX_ERROR;
1278 }
1279
1280 COMMAND_HANDLER(or1k_du_list_command_handler)
1281 {
1282         struct or1k_du *or1k_du;
1283
1284         if (CMD_ARGC != 0)
1285                 return ERROR_COMMAND_SYNTAX_ERROR;
1286
1287         list_for_each_entry(or1k_du, &du_list, list) {
1288                 if (or1k_du->name)
1289                         command_print(CMD_CTX, "%s", or1k_du->name);
1290         }
1291
1292         return ERROR_OK;
1293 }
1294
1295 COMMAND_HANDLER(or1k_addreg_command_handler)
1296 {
1297         struct target *target = get_current_target(CMD_CTX);
1298         struct or1k_core_reg new_reg;
1299
1300         if (CMD_ARGC != 4)
1301                 return ERROR_COMMAND_SYNTAX_ERROR;
1302
1303         new_reg.target = NULL;
1304         new_reg.or1k_common = NULL;
1305
1306         uint32_t addr;
1307         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], addr);
1308
1309         new_reg.name = strdup(CMD_ARGV[0]);
1310         new_reg.spr_num = addr;
1311         new_reg.feature = strdup(CMD_ARGV[2]);
1312         new_reg.group = strdup(CMD_ARGV[3]);
1313
1314         or1k_add_reg(target, &new_reg);
1315
1316         LOG_DEBUG("Add reg \"%s\" @ 0x%08" PRIx32 ", group \"%s\", feature \"%s\"",
1317                   new_reg.name, addr, new_reg.group, new_reg.feature);
1318
1319         return ERROR_OK;
1320 }
1321
1322 static const struct command_registration or1k_hw_ip_command_handlers[] = {
1323         {
1324                 "tap_select",
1325                 .handler = or1k_tap_select_command_handler,
1326                 .mode = COMMAND_ANY,
1327                 .usage = "tap_select name",
1328                 .help = "Select the TAP core to use",
1329         },
1330         {
1331                 "tap_list",
1332                 .handler = or1k_tap_list_command_handler,
1333                 .mode = COMMAND_ANY,
1334                 .usage = "tap_list",
1335                 .help = "Display available TAP core",
1336         },
1337         {
1338                 "du_select",
1339                 .handler = or1k_du_select_command_handler,
1340                 .mode = COMMAND_ANY,
1341                 .usage = "du_select name",
1342                 .help = "Select the Debug Unit core to use",
1343         },
1344         {
1345                 "du_list",
1346                 .handler = or1k_du_list_command_handler,
1347                 .mode = COMMAND_ANY,
1348                 .usage = "select_tap name",
1349                 .help = "Display available Debug Unit core",
1350         },
1351         COMMAND_REGISTRATION_DONE
1352 };
1353
1354 static const struct command_registration or1k_reg_command_handlers[] = {
1355         {
1356                 "addreg",
1357                 .handler = or1k_addreg_command_handler,
1358                 .mode = COMMAND_ANY,
1359                 .usage = "addreg name addr feature group",
1360                 .help = "Add a register to the register list",
1361         },
1362         COMMAND_REGISTRATION_DONE
1363 };
1364
1365 static const struct command_registration or1k_command_handlers[] = {
1366         {
1367                 .chain = or1k_reg_command_handlers,
1368         },
1369         {
1370                 .chain = or1k_hw_ip_command_handlers,
1371         },
1372         COMMAND_REGISTRATION_DONE
1373 };
1374
1375
1376 struct target_type or1k_target = {
1377         .name = "or1k",
1378
1379         .poll = or1k_poll,
1380         .arch_state = or1k_arch_state,
1381
1382         .target_request_data = NULL,
1383
1384         .halt = or1k_halt,
1385         .resume = or1k_resume,
1386         .step = or1k_step,
1387
1388         .assert_reset = or1k_assert_reset,
1389         .deassert_reset = or1k_deassert_reset,
1390         .soft_reset_halt = or1k_soft_reset_halt,
1391
1392         .get_gdb_reg_list = or1k_get_gdb_reg_list,
1393
1394         .read_memory = or1k_read_memory,
1395         .write_memory = or1k_write_memory,
1396         .checksum_memory = or1k_checksum_memory,
1397
1398         .commands = or1k_command_handlers,
1399         .add_breakpoint = or1k_add_breakpoint,
1400         .remove_breakpoint = or1k_remove_breakpoint,
1401         .add_watchpoint = or1k_add_watchpoint,
1402         .remove_watchpoint = or1k_remove_watchpoint,
1403
1404         .target_create = or1k_target_create,
1405         .init_target = or1k_init_target,
1406         .examine = or1k_examine,
1407
1408         .get_gdb_fileio_info = or1k_get_gdb_fileio_info,
1409 };