1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
25 #include <helper/time_support.h>
26 #include <helper/binarybuffer.h>
27 #include "breakpoints.h"
28 #include "nds32_insn.h"
29 #include "nds32_reg.h"
30 #include "nds32_edm.h"
31 #include "nds32_cmd.h"
33 #include "nds32_aice.h"
34 #include "target_type.h"
36 static int nds32_v2_register_mapping(struct nds32 *nds32, int reg_no)
38 uint32_t max_level = nds32->max_interrupt_level;
39 uint32_t cur_level = nds32->current_interrupt_level;
41 if ((1 <= cur_level) && (cur_level < max_level)) {
43 LOG_DEBUG("Map PSW to IPSW");
45 } else if (PC == reg_no) {
46 LOG_DEBUG("Map PC to IPC");
49 } else if ((2 <= cur_level) && (cur_level < max_level)) {
51 LOG_DEBUG("Mapping P0 to P_P0");
53 } else if (R27 == reg_no) {
54 LOG_DEBUG("Mapping P1 to P_P1");
56 } else if (IR1 == reg_no) {
57 LOG_DEBUG("Mapping IPSW to P_IPSW");
59 } else if (IR4 == reg_no) {
60 LOG_DEBUG("Mapping EVA to P_EVA");
62 } else if (IR6 == reg_no) {
63 LOG_DEBUG("Mapping ITYPE to P_ITYPE");
65 } else if (IR9 == reg_no) {
66 LOG_DEBUG("Mapping IPC to P_IPC");
69 } else if (cur_level == max_level) {
71 LOG_DEBUG("Mapping PC to O_IPC");
79 static int nds32_v2_get_debug_reason(struct nds32 *nds32, uint32_t *reason)
82 struct aice_port_s *aice = target_to_aice(nds32->target);
84 aice_read_register(aice, IR6, &val_itype);
86 *reason = val_itype & 0x0F;
91 static int nds32_v2_activate_hardware_breakpoint(struct target *target)
93 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
94 struct aice_port_s *aice = target_to_aice(target);
95 struct breakpoint *bp;
96 int32_t hbr_index = 0;
98 for (bp = target->breakpoints; bp; bp = bp->next) {
99 if (bp->type == BKPT_SOFT) {
100 /* already set at nds32_v2_add_breakpoint() */
102 } else if (bp->type == BKPT_HARD) {
104 aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + hbr_index, bp->address);
106 aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + hbr_index, 0);
108 aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + hbr_index, 0);
110 if (nds32_v2->nds32.memory.address_translation)
111 /* enable breakpoint (virtual address) */
112 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x2);
114 /* enable breakpoint (physical address) */
115 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
117 LOG_DEBUG("Add hardware BP %d at %08" PRIx32, hbr_index,
129 static int nds32_v2_deactivate_hardware_breakpoint(struct target *target)
131 struct aice_port_s *aice = target_to_aice(target);
132 struct breakpoint *bp;
133 int32_t hbr_index = 0;
135 for (bp = target->breakpoints; bp; bp = bp->next) {
136 if (bp->type == BKPT_SOFT)
138 else if (bp->type == BKPT_HARD)
139 /* disable breakpoint */
140 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x0);
144 LOG_DEBUG("Remove hardware BP %d at %08" PRIx32, hbr_index,
153 static int nds32_v2_activate_hardware_watchpoint(struct target *target)
155 struct aice_port_s *aice = target_to_aice(target);
156 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
157 struct watchpoint *wp;
158 int32_t wp_num = nds32_v2->next_hbr_index;
159 uint32_t wp_config = 0;
161 for (wp = target->watchpoints; wp; wp = wp->next) {
164 wp->mask = wp->length - 1;
165 if ((wp->address % wp->length) != 0)
166 wp->mask = (wp->mask << 1) + 1;
168 if (wp->rw == WPT_READ)
170 else if (wp->rw == WPT_WRITE)
172 else if (wp->rw == WPT_ACCESS)
175 /* set/unset physical address bit of BPCn according to PSW.DT */
176 if (nds32_v2->nds32.memory.address_translation == false)
180 aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num,
181 wp->address - (wp->address % wp->length));
183 aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask);
184 /* enable watchpoint */
185 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config);
187 aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
189 LOG_DEBUG("Add hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32, wp_num,
190 wp->address, wp->mask);
197 static int nds32_v2_deactivate_hardware_watchpoint(struct target *target)
199 struct aice_port_s *aice = target_to_aice(target);
200 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
201 int32_t wp_num = nds32_v2->next_hbr_index;
202 struct watchpoint *wp;
204 for (wp = target->watchpoints; wp; wp = wp->next) {
206 /* disable watchpoint */
207 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
209 LOG_DEBUG("Remove hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32,
210 wp_num, wp->address, wp->mask);
216 static int nds32_v2_check_interrupt_stack(struct nds32_v2_common *nds32_v2)
218 struct nds32 *nds32 = &(nds32_v2->nds32);
219 struct aice_port_s *aice = target_to_aice(nds32->target);
223 uint32_t modified_psw;
225 /* Save interrupt level */
226 aice_read_register(aice, IR0, &val_ir0); /* get $IR0 directly */
229 nds32_v2->backup_ir0 = val_ir0;
231 nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
233 if (nds32_reach_max_interrupt_level(nds32)) {
234 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %d. -->",
235 nds32->current_interrupt_level);
237 /* decrease interrupt level */
238 modified_psw = val_ir0 - 0x2;
240 /* disable GIE, IT, DT, HSS */
241 modified_psw &= (~0x8C1);
243 aice_write_register(aice, IR0, modified_psw);
248 /* There is a case that single step also trigger another interrupt,
249 then HSS bit in psw(ir0) will push to ipsw(ir1).
250 Then hit debug interrupt HSS bit in ipsw(ir1) will push to (p_ipsw)ir2
251 Therefore, HSS bit in p_ipsw(ir2) also need clear.
253 Only update $ir2 as current interrupt level is 2, because $ir2 will be random
254 value if the target never reaches interrupt level 2. */
255 if ((nds32->max_interrupt_level == 3) && (nds32->current_interrupt_level == 2)) {
256 aice_read_register(aice, IR2, &val_ir2); /* get $IR2 directly */
257 val_ir2 &= ~(0x01 << 11);
258 aice_write_register(aice, IR2, val_ir2);
261 /* get origianl DT bit and set to current state let debugger has same memory view
262 PSW.IT MUST be turned off. Otherwise, DIM could not operate normally. */
263 aice_read_register(aice, IR1, &val_ir1);
264 modified_psw = val_ir0 | (val_ir1 & 0x80);
265 aice_write_register(aice, IR0, modified_psw);
270 static int nds32_v2_restore_interrupt_stack(struct nds32_v2_common *nds32_v2)
272 struct nds32 *nds32 = &(nds32_v2->nds32);
273 struct aice_port_s *aice = target_to_aice(nds32->target);
275 /* restore origin $IR0 */
276 aice_write_register(aice, IR0, nds32_v2->backup_ir0);
282 * Save processor state. This is called after a HALT instruction
283 * succeeds, and on other occasions the processor enters debug mode
284 * (breakpoint, watchpoint, etc).
286 static int nds32_v2_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
288 LOG_DEBUG("nds32_v2_debug_entry");
290 jtag_poll_set_enabled(false);
292 if (nds32->virtual_hosting)
293 LOG_WARNING("<-- TARGET WARNING! Virtual hosting is not supported "
294 "under V1/V2 architecture. -->");
296 enum target_state backup_state = nds32->target->state;
297 nds32->target->state = TARGET_HALTED;
299 if (nds32->init_arch_info_after_halted == false) {
300 /* init architecture info according to config registers */
301 CHECK_RETVAL(nds32_config(nds32));
303 nds32->init_arch_info_after_halted = true;
306 /* REVISIT entire cache should already be invalid !!! */
307 register_cache_invalidate(nds32->core_cache);
309 /* deactivate all hardware breakpoints */
310 CHECK_RETVAL(nds32_v2_deactivate_hardware_breakpoint(nds32->target));
312 if (enable_watchpoint)
313 CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target));
315 if (ERROR_OK != nds32_examine_debug_reason(nds32)) {
316 nds32->target->state = backup_state;
318 /* re-activate all hardware breakpoints & watchpoints */
319 CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
321 if (enable_watchpoint) {
322 /* activate all watchpoints */
323 CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target));
329 /* check interrupt level before .full_context(), because
330 * get_mapped_reg() in nds32_full_context() needs current_interrupt_level
332 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
333 nds32_v2_check_interrupt_stack(nds32_v2);
335 /* Save registers. */
336 nds32_full_context(nds32);
341 /* target request support */
342 static int nds32_v2_target_request_data(struct target *target,
343 uint32_t size, uint8_t *buffer)
345 /* AndesCore could use DTR register to communicate with OpenOCD
347 * Target data will be put in buffer
348 * The format of DTR is as follow
349 * DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd
350 * target_req_cmd has three possible values:
351 * TARGET_REQ_TRACEMSG
352 * TARGET_REQ_DEBUGMSG
353 * TARGET_REQ_DEBUGCHAR
354 * if size == 0, target will call target_asciimsg(),
355 * else call target_hexmsg()
357 LOG_WARNING("Not implemented: %s", __func__);
363 * Restore processor state.
365 static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
367 LOG_DEBUG("nds32_v2_leave_debug_state");
369 struct target *target = nds32->target;
371 /* activate all hardware breakpoints */
372 CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
374 if (enable_watchpoint) {
375 /* activate all watchpoints */
376 CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target));
379 /* restore interrupt stack */
380 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
381 nds32_v2_restore_interrupt_stack(nds32_v2);
383 /* restore PSW, PC, and R0 ... after flushing any modified
386 CHECK_RETVAL(nds32_restore_context(target));
388 register_cache_invalidate(nds32->core_cache);
390 jtag_poll_set_enabled(true);
395 static int nds32_v2_soft_reset_halt(struct target *target)
398 struct nds32 *nds32 = target_to_nds32(target);
399 struct aice_port_s *aice = target_to_aice(target);
401 aice_assert_srst(aice, AICE_SRST);
403 /* halt core and set pc to 0x0 */
404 int retval = target_halt(target);
405 if (retval != ERROR_OK)
408 /* start fetching from IVB */
410 nds32_get_mapped_reg(nds32, IR3, &value_ir3);
411 nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
416 static int nds32_v2_deassert_reset(struct target *target)
420 CHECK_RETVAL(nds32_poll(target));
422 if (target->state != TARGET_HALTED) {
424 LOG_WARNING("%s: ran after reset and before halt ...",
425 target_name(target));
426 retval = target_halt(target);
427 if (retval != ERROR_OK)
429 /* call target_poll() to avoid "Halt timed out" */
430 CHECK_RETVAL(target_poll(target));
432 jtag_poll_set_enabled(false);
438 static int nds32_v2_checksum_memory(struct target *target,
439 uint32_t address, uint32_t count, uint32_t *checksum)
441 LOG_WARNING("Not implemented: %s", __func__);
446 static int nds32_v2_add_breakpoint(struct target *target,
447 struct breakpoint *breakpoint)
449 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
450 struct nds32 *nds32 = &(nds32_v2->nds32);
453 if (breakpoint->type == BKPT_HARD) {
454 /* check hardware resource */
455 if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
456 LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
457 "breakpoints/watchpoints! The limit of "
458 "combined hardware breakpoints/watchpoints "
459 "is %d. -->", nds32_v2->n_hbr);
460 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
463 /* update next place to put hardware breakpoint */
464 nds32_v2->next_hbr_index++;
466 /* hardware breakpoint insertion occurs before 'continue' actually */
468 } else if (breakpoint->type == BKPT_SOFT) {
469 result = nds32_add_software_breakpoint(target, breakpoint);
470 if (ERROR_OK != result) {
471 /* auto convert to hardware breakpoint if failed */
472 if (nds32->auto_convert_hw_bp) {
473 /* convert to hardware breakpoint */
474 breakpoint->type = BKPT_HARD;
476 return nds32_v2_add_breakpoint(target, breakpoint);
481 } else /* unrecognized breakpoint type */
487 static int nds32_v2_remove_breakpoint(struct target *target,
488 struct breakpoint *breakpoint)
490 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
492 if (breakpoint->type == BKPT_HARD) {
493 if (nds32_v2->next_hbr_index <= 0)
496 /* update next place to put hardware breakpoint */
497 nds32_v2->next_hbr_index--;
499 /* hardware breakpoint removal occurs after 'halted' actually */
501 } else if (breakpoint->type == BKPT_SOFT) {
502 return nds32_remove_software_breakpoint(target, breakpoint);
503 } else /* unrecognized breakpoint type */
509 static int nds32_v2_add_watchpoint(struct target *target,
510 struct watchpoint *watchpoint)
512 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
514 /* check hardware resource */
515 if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
516 LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
517 "breakpoints/watchpoints! The limit of "
518 "combined hardware breakpoints/watchpoints is %d. -->", nds32_v2->n_hbr);
519 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
522 /* update next place to put hardware watchpoint */
523 nds32_v2->next_hbr_index++;
528 static int nds32_v2_remove_watchpoint(struct target *target,
529 struct watchpoint *watchpoint)
531 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
533 if (nds32_v2->next_hbr_index <= 0)
536 /* update next place to put hardware breakpoint */
537 nds32_v2->next_hbr_index--;
542 static int nds32_v2_get_exception_address(struct nds32 *nds32,
543 uint32_t *address, uint32_t reason)
545 struct aice_port_s *aice = target_to_aice(nds32->target);
547 aice_read_register(aice, IR4, address); /* read $EVA directly */
549 /* TODO: hit multiple watchpoints */
555 * find out which watchpoint hits
556 * get exception address and compare the address to watchpoints
558 static int nds32_v2_hit_watchpoint(struct target *target,
559 struct watchpoint **hit_watchpoint)
561 uint32_t exception_address;
562 struct watchpoint *wp;
563 static struct watchpoint scan_all_watchpoint;
564 struct nds32 *nds32 = target_to_nds32(target);
566 scan_all_watchpoint.address = 0;
567 scan_all_watchpoint.rw = WPT_WRITE;
568 scan_all_watchpoint.next = 0;
569 scan_all_watchpoint.unique_id = 0x5CA8;
571 exception_address = nds32->watched_address;
573 if (exception_address == 0) {
574 /* send watch:0 to tell GDB to do software scan for hitting multiple watchpoints */
575 *hit_watchpoint = &scan_all_watchpoint;
579 for (wp = target->watchpoints; wp; wp = wp->next) {
580 if (((exception_address ^ wp->address) & (~wp->mask)) == 0) {
581 /* TODO: dispel false match */
582 *hit_watchpoint = wp;
590 static int nds32_v2_run_algorithm(struct target *target,
592 struct mem_param *mem_params,
594 struct reg_param *reg_params,
595 uint32_t entry_point,
600 LOG_WARNING("Not implemented: %s", __func__);
605 static int nds32_v2_target_create(struct target *target, Jim_Interp *interp)
607 struct nds32_v2_common *nds32_v2;
609 nds32_v2 = calloc(1, sizeof(*nds32_v2));
613 nds32_v2->nds32.register_map = nds32_v2_register_mapping;
614 nds32_v2->nds32.get_debug_reason = nds32_v2_get_debug_reason;
615 nds32_v2->nds32.enter_debug_state = nds32_v2_debug_entry;
616 nds32_v2->nds32.leave_debug_state = nds32_v2_leave_debug_state;
617 nds32_v2->nds32.get_watched_address = nds32_v2_get_exception_address;
619 nds32_init_arch_info(target, &(nds32_v2->nds32));
624 static int nds32_v2_init_target(struct command_context *cmd_ctx,
625 struct target *target)
627 /* Initialize anything we can set up without talking to the target */
629 struct nds32 *nds32 = target_to_nds32(target);
636 /* talk to the target and set things up */
637 static int nds32_v2_examine(struct target *target)
639 struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
640 struct nds32 *nds32 = &(nds32_v2->nds32);
641 struct aice_port_s *aice = target_to_aice(target);
643 if (!target_was_examined(target)) {
644 CHECK_RETVAL(nds32_edm_config(nds32));
646 if (nds32->reset_halt_as_examine)
647 CHECK_RETVAL(nds32_reset_halt(nds32));
651 aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
653 /* get the number of hardware breakpoints */
654 nds32_v2->n_hbr = (edm_cfg & 0x7) + 1;
656 nds32_v2->next_hbr_index = 0;
658 LOG_INFO("%s: total hardware breakpoint %d", target_name(target),
661 nds32->target->state = TARGET_RUNNING;
662 nds32->target->debug_reason = DBG_REASON_NOTHALTED;
664 target_set_examined(target);
669 static int nds32_v2_translate_address(struct target *target, uint32_t *address)
671 struct nds32 *nds32 = target_to_nds32(target);
672 struct nds32_memory *memory = &(nds32->memory);
673 uint32_t physical_address;
675 /* Following conditions need to do address translation
677 * 2. CPU mode under maximum interrupt level */
678 if ((NDS_MEMORY_ACC_BUS == memory->access_channel) ||
679 ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
680 nds32_reach_max_interrupt_level(nds32))) {
681 if (ERROR_OK == target->type->virt2phys(target, *address, &physical_address))
682 *address = physical_address;
690 static int nds32_v2_read_buffer(struct target *target, uint32_t address,
691 uint32_t size, uint8_t *buffer)
693 struct nds32 *nds32 = target_to_nds32(target);
694 struct nds32_memory *memory = &(nds32->memory);
696 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
697 (target->state != TARGET_HALTED)) {
698 LOG_WARNING("target was not halted");
699 return ERROR_TARGET_NOT_HALTED;
702 /* BUG: If access range crosses multiple pages, the translation will not correct
703 * for second page or so. */
705 nds32_v2_translate_address(target, &address);
707 return nds32_read_buffer(target, address, size, buffer);
710 static int nds32_v2_write_buffer(struct target *target, uint32_t address,
711 uint32_t size, const uint8_t *buffer)
713 struct nds32 *nds32 = target_to_nds32(target);
714 struct nds32_memory *memory = &(nds32->memory);
716 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
717 (target->state != TARGET_HALTED)) {
718 LOG_WARNING("target was not halted");
719 return ERROR_TARGET_NOT_HALTED;
722 /* BUG: If access range crosses multiple pages, the translation will not correct
723 * for second page or so. */
725 nds32_v2_translate_address(target, &address);
727 return nds32_write_buffer(target, address, size, buffer);
730 static int nds32_v2_read_memory(struct target *target, uint32_t address,
731 uint32_t size, uint32_t count, uint8_t *buffer)
733 struct nds32 *nds32 = target_to_nds32(target);
734 struct nds32_memory *memory = &(nds32->memory);
736 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
737 (target->state != TARGET_HALTED)) {
738 LOG_WARNING("target was not halted");
739 return ERROR_TARGET_NOT_HALTED;
742 /* BUG: If access range crosses multiple pages, the translation will not correct
743 * for second page or so. */
745 nds32_v2_translate_address(target, &address);
747 return nds32_read_memory(target, address, size, count, buffer);
750 static int nds32_v2_write_memory(struct target *target, uint32_t address,
751 uint32_t size, uint32_t count, const uint8_t *buffer)
753 struct nds32 *nds32 = target_to_nds32(target);
754 struct nds32_memory *memory = &(nds32->memory);
756 if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
757 (target->state != TARGET_HALTED)) {
758 LOG_WARNING("target was not halted");
759 return ERROR_TARGET_NOT_HALTED;
762 /* BUG: If access range crosses multiple pages, the translation will not correct
763 * for second page or so. */
765 nds32_v2_translate_address(target, &address);
767 return nds32_write_memory(target, address, size, count, buffer);
770 /** Holds methods for V2 targets. */
771 struct target_type nds32_v2_target = {
775 .arch_state = nds32_arch_state,
777 .target_request_data = nds32_v2_target_request_data,
780 .resume = nds32_resume,
783 .assert_reset = nds32_assert_reset,
784 .deassert_reset = nds32_v2_deassert_reset,
785 .soft_reset_halt = nds32_v2_soft_reset_halt,
787 /* register access */
788 .get_gdb_reg_list = nds32_get_gdb_reg_list,
791 .read_buffer = nds32_v2_read_buffer,
792 .write_buffer = nds32_v2_write_buffer,
793 .read_memory = nds32_v2_read_memory,
794 .write_memory = nds32_v2_write_memory,
796 .checksum_memory = nds32_v2_checksum_memory,
798 /* breakpoint/watchpoint */
799 .add_breakpoint = nds32_v2_add_breakpoint,
800 .remove_breakpoint = nds32_v2_remove_breakpoint,
801 .add_watchpoint = nds32_v2_add_watchpoint,
802 .remove_watchpoint = nds32_v2_remove_watchpoint,
803 .hit_watchpoint = nds32_v2_hit_watchpoint,
807 .virt2phys = nds32_virtual_to_physical,
808 .read_phys_memory = nds32_read_phys_memory,
809 .write_phys_memory = nds32_write_phys_memory,
811 .run_algorithm = nds32_v2_run_algorithm,
813 .commands = nds32_command_handlers,
814 .target_create = nds32_v2_target_create,
815 .init_target = nds32_v2_init_target,
816 .examine = nds32_v2_examine,