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   1 /***************************************************************************
   2  *   Copyright (C) 2013 Andes Technology                                   *
   3  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include <helper/time_support.h>
  26 #include <helper/binarybuffer.h>
  27 #include "breakpoints.h"
  28 #include "nds32_insn.h"
  29 #include "nds32_reg.h"
  30 #include "nds32_edm.h"
  31 #include "nds32_cmd.h"
  32 #include "nds32_v2.h"
  33 #include "nds32_aice.h"
  34 #include "target_type.h"
  35
  36 static int nds32_v2_register_mapping(struct nds32 *nds32, int reg_no)
  37 {
  38         uint32_t max_level = nds32->max_interrupt_level;
  39         uint32_t cur_level = nds32->current_interrupt_level;
  40
  41         if ((1 <= cur_level) && (cur_level < max_level)) {
  42                 if (IR0 == reg_no) {
  43                         LOG_DEBUG("Map PSW to IPSW");
  44                         return IR1;
  45                 } else if (PC == reg_no) {
  46                         LOG_DEBUG("Map PC to IPC");
  47                         return IR9;
  48                 }
  49         } else if ((2 <= cur_level) && (cur_level < max_level)) {
  50                 if (R26 == reg_no) {
  51                         LOG_DEBUG("Mapping P0 to P_P0");
  52                         return IR12;
  53                 } else if (R27 == reg_no) {
  54                         LOG_DEBUG("Mapping P1 to P_P1");
  55                         return IR13;
  56                 } else if (IR1 == reg_no) {
  57                         LOG_DEBUG("Mapping IPSW to P_IPSW");
  58                         return IR2;
  59                 } else if (IR4 == reg_no) {
  60                         LOG_DEBUG("Mapping EVA to P_EVA");
  61                         return IR5;
  62                 } else if (IR6 == reg_no) {
  63                         LOG_DEBUG("Mapping ITYPE to P_ITYPE");
  64                         return IR7;
  65                 } else if (IR9 == reg_no) {
  66                         LOG_DEBUG("Mapping IPC to P_IPC");
  67                         return IR10;
  68                 }
  69         } else if (cur_level == max_level) {
  70                 if (PC == reg_no) {
  71                         LOG_DEBUG("Mapping PC to O_IPC");
  72                         return IR11;
  73                 }
  74         }
  75
  76         return reg_no;
  77 }
  78
  79 static int nds32_v2_get_debug_reason(struct nds32 *nds32, uint32_t *reason)
  80 {
  81         uint32_t val_itype;
  82         struct aice_port_s *aice = target_to_aice(nds32->target);
  83
  84         aice_read_register(aice, IR6, &val_itype);
  85
  86         *reason = val_itype & 0x0F;
  87
  88         return ERROR_OK;
  89 }
  90
  91 static int nds32_v2_activate_hardware_breakpoint(struct target *target)
  92 {
  93         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
  94         struct aice_port_s *aice = target_to_aice(target);
  95         struct breakpoint *bp;
  96         int32_t hbr_index = 0;
  97
  98         for (bp = target->breakpoints; bp; bp = bp->next) {
  99                 if (bp->type == BKPT_SOFT) {
 100                         /* already set at nds32_v2_add_breakpoint() */
 101                         continue;
 102                 } else if (bp->type == BKPT_HARD) {
 103                         /* set address */
 104                         aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + hbr_index, bp->address);
 105                         /* set mask */
 106                         aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + hbr_index, 0);
 107                         /* set value */
 108                         aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + hbr_index, 0);
 109
 110                         if (nds32_v2->nds32.memory.address_translation)
 111                                 /* enable breakpoint (virtual address) */
 112                                 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x2);
 113                         else
 114                                 /* enable breakpoint (physical address) */
 115                                 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
 116
 117                         LOG_DEBUG("Add hardware BP %d at %08" PRIx32, hbr_index,
 118                                         bp->address);
 119
 120                         hbr_index++;
 121                 } else {
 122                         return ERROR_FAIL;
 123                 }
 124         }
 125
 126         return ERROR_OK;
 127 }
 128
 129 static int nds32_v2_deactivate_hardware_breakpoint(struct target *target)
 130 {
 131         struct aice_port_s *aice = target_to_aice(target);
 132         struct breakpoint *bp;
 133         int32_t hbr_index = 0;
 134
 135         for (bp = target->breakpoints; bp; bp = bp->next) {
 136                 if (bp->type == BKPT_SOFT)
 137                         continue;
 138                 else if (bp->type == BKPT_HARD)
 139                         /* disable breakpoint */
 140                         aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x0);
 141                 else
 142                         return ERROR_FAIL;
 143
 144                 LOG_DEBUG("Remove hardware BP %d at %08" PRIx32, hbr_index,
 145                                 bp->address);
 146
 147                 hbr_index++;
 148         }
 149
 150         return ERROR_OK;
 151 }
 152
 153 static int nds32_v2_activate_hardware_watchpoint(struct target *target)
 154 {
 155         struct aice_port_s *aice = target_to_aice(target);
 156         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
 157         struct watchpoint *wp;
 158         int32_t wp_num = nds32_v2->next_hbr_index;
 159         uint32_t wp_config = 0;
 160
 161         for (wp = target->watchpoints; wp; wp = wp->next) {
 162
 163                 wp_num--;
 164                 wp->mask = wp->length - 1;
 165                 if ((wp->address % wp->length) != 0)
 166                         wp->mask = (wp->mask << 1) + 1;
 167
 168                 if (wp->rw == WPT_READ)
 169                         wp_config = 0x3;
 170                 else if (wp->rw == WPT_WRITE)
 171                         wp_config = 0x5;
 172                 else if (wp->rw == WPT_ACCESS)
 173                         wp_config = 0x7;
 174
 175                 /* set/unset physical address bit of BPCn according to PSW.DT */
 176                 if (nds32_v2->nds32.memory.address_translation == false)
 177                         wp_config |= 0x8;
 178
 179                 /* set address */
 180                 aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num,
 181                                 wp->address - (wp->address % wp->length));
 182                 /* set mask */
 183                 aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask);
 184                 /* enable watchpoint */
 185                 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config);
 186                 /* set value */
 187                 aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
 188
 189                 LOG_DEBUG("Add hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32, wp_num,
 190                                 wp->address, wp->mask);
 191
 192         }
 193
 194         return ERROR_OK;
 195 }
 196
 197 static int nds32_v2_deactivate_hardware_watchpoint(struct target *target)
 198 {
 199         struct aice_port_s *aice = target_to_aice(target);
 200         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
 201         int32_t wp_num = nds32_v2->next_hbr_index;
 202         struct watchpoint *wp;
 203
 204         for (wp = target->watchpoints; wp; wp = wp->next) {
 205                 wp_num--;
 206                 /* disable watchpoint */
 207                 aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
 208
 209                 LOG_DEBUG("Remove hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32,
 210                                 wp_num, wp->address, wp->mask);
 211         }
 212
 213         return ERROR_OK;
 214 }
 215
 216 static int nds32_v2_check_interrupt_stack(struct nds32_v2_common *nds32_v2)
 217 {
 218         struct nds32 *nds32 = &(nds32_v2->nds32);
 219         struct aice_port_s *aice = target_to_aice(nds32->target);
 220         uint32_t val_ir0;
 221         uint32_t val_ir1;
 222         uint32_t val_ir2;
 223         uint32_t modified_psw;
 224
 225         /* Save interrupt level */
 226         aice_read_register(aice, IR0, &val_ir0); /* get $IR0 directly */
 227
 228         /* backup $IR0 */
 229         nds32_v2->backup_ir0 = val_ir0;
 230
 231         nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
 232
 233         if (nds32_reach_max_interrupt_level(nds32)) {
 234                 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %d. -->",
 235                                 nds32->current_interrupt_level);
 236
 237                 /* decrease interrupt level */
 238                 modified_psw = val_ir0 - 0x2;
 239
 240                 /* disable GIE, IT, DT, HSS */
 241                 modified_psw &= (~0x8C1);
 242
 243                 aice_write_register(aice, IR0, modified_psw);
 244
 245                 return ERROR_OK;
 246         }
 247
 248         /* There is a case that single step also trigger another interrupt,
 249            then HSS bit in psw(ir0) will push to ipsw(ir1).
 250            Then hit debug interrupt HSS bit in ipsw(ir1) will push to (p_ipsw)ir2
 251            Therefore, HSS bit in p_ipsw(ir2) also need clear.
 252
 253            Only update $ir2 as current interrupt level is 2, because $ir2 will be random
 254            value if the target never reaches interrupt level 2. */
 255         if ((nds32->max_interrupt_level == 3) && (nds32->current_interrupt_level == 2)) {
 256                 aice_read_register(aice, IR2, &val_ir2); /* get $IR2 directly */
 257                 val_ir2 &= ~(0x01 << 11);
 258                 aice_write_register(aice, IR2, val_ir2);
 259         }
 260
 261         /* get origianl DT bit and set to current state let debugger has same memory view
 262            PSW.IT MUST be turned off.  Otherwise, DIM could not operate normally. */
 263         aice_read_register(aice, IR1, &val_ir1);
 264         modified_psw = val_ir0 | (val_ir1 & 0x80);
 265         aice_write_register(aice, IR0, modified_psw);
 266
 267         return ERROR_OK;
 268 }
 269
 270 static int nds32_v2_restore_interrupt_stack(struct nds32_v2_common *nds32_v2)
 271 {
 272         struct nds32 *nds32 = &(nds32_v2->nds32);
 273         struct aice_port_s *aice = target_to_aice(nds32->target);
 274
 275         /* restore origin $IR0 */
 276         aice_write_register(aice, IR0, nds32_v2->backup_ir0);
 277
 278         return ERROR_OK;
 279 }
 280
 281 /**
 282  * Save processor state.  This is called after a HALT instruction
 283  * succeeds, and on other occasions the processor enters debug mode
 284  * (breakpoint, watchpoint, etc).
 285  */
 286 static int nds32_v2_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
 287 {
 288         LOG_DEBUG("nds32_v2_debug_entry");
 289
 290         if (nds32->virtual_hosting)
 291                 LOG_WARNING("<-- TARGET WARNING! Virtual hosting is not supported "
 292                                 "under V1/V2 architecture. -->");
 293
 294         enum target_state backup_state = nds32->target->state;
 295         nds32->target->state = TARGET_HALTED;
 296
 297         if (nds32->init_arch_info_after_halted == false) {
 298                 /* init architecture info according to config registers */
 299                 CHECK_RETVAL(nds32_config(nds32));
 300
 301                 nds32->init_arch_info_after_halted = true;
 302         }
 303
 304         /* REVISIT entire cache should already be invalid !!! */
 305         register_cache_invalidate(nds32->core_cache);
 306
 307         /* deactivate all hardware breakpoints */
 308         CHECK_RETVAL(nds32_v2_deactivate_hardware_breakpoint(nds32->target));
 309
 310         if (enable_watchpoint)
 311                 CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target));
 312
 313         if (ERROR_OK != nds32_examine_debug_reason(nds32)) {
 314                 nds32->target->state = backup_state;
 315
 316                 /* re-activate all hardware breakpoints & watchpoints */
 317                 CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
 318
 319                 if (enable_watchpoint) {
 320                         /* activate all watchpoints */
 321                         CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target));
 322                 }
 323
 324                 return ERROR_FAIL;
 325         }
 326
 327         /* check interrupt level before .full_context(), because
 328          * get_mapped_reg() in nds32_full_context() needs current_interrupt_level
 329          * information */
 330         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
 331         nds32_v2_check_interrupt_stack(nds32_v2);
 332
 333         /* Save registers. */
 334         nds32_full_context(nds32);
 335
 336         return ERROR_OK;
 337 }
 338
 339 /* target request support */
 340 static int nds32_v2_target_request_data(struct target *target,
 341                 uint32_t size, uint8_t *buffer)
 342 {
 343         /* AndesCore could use DTR register to communicate with OpenOCD
 344          * to output messages
 345          * Target data will be put in buffer
 346          * The format of DTR is as follow
 347          * DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd
 348          * target_req_cmd has three possible values:
 349          *   TARGET_REQ_TRACEMSG
 350          *   TARGET_REQ_DEBUGMSG
 351          *   TARGET_REQ_DEBUGCHAR
 352          * if size == 0, target will call target_asciimsg(),
 353          * else call target_hexmsg()
 354          */
 355         LOG_WARNING("Not implemented: %s", __func__);
 356
 357         return ERROR_OK;
 358 }
 359
 360 /**
 361  * Restore processor state.
 362  */
 363 static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
 364 {
 365         LOG_DEBUG("nds32_v2_leave_debug_state");
 366
 367         struct target *target = nds32->target;
 368
 369         /* activate all hardware breakpoints */
 370         CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
 371
 372         if (enable_watchpoint) {
 373                 /* activate all watchpoints */
 374                 CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target));
 375         }
 376
 377         /* restore interrupt stack */
 378         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
 379         nds32_v2_restore_interrupt_stack(nds32_v2);
 380
 381         /* restore PSW, PC, and R0 ... after flushing any modified
 382          * registers.
 383          */
 384         CHECK_RETVAL(nds32_restore_context(target));
 385
 386         register_cache_invalidate(nds32->core_cache);
 387
 388         return ERROR_OK;
 389 }
 390
 391 static int nds32_v2_soft_reset_halt(struct target *target)
 392 {
 393         /* TODO: test it */
 394         struct nds32 *nds32 = target_to_nds32(target);
 395         struct aice_port_s *aice = target_to_aice(target);
 396
 397         aice_assert_srst(aice, AICE_SRST);
 398
 399         /* halt core and set pc to 0x0 */
 400         int retval = target_halt(target);
 401         if (retval != ERROR_OK)
 402                 return retval;
 403
 404         /* start fetching from IVB */
 405         uint32_t value_ir3;
 406         nds32_get_mapped_reg(nds32, IR3, &value_ir3);
 407         nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
 408
 409         return ERROR_OK;
 410 }
 411
 412 static int nds32_v2_deassert_reset(struct target *target)
 413 {
 414         int retval;
 415
 416         CHECK_RETVAL(nds32_poll(target));
 417
 418         if (target->state != TARGET_HALTED) {
 419                 /* reset only */
 420                 LOG_WARNING("%s: ran after reset and before halt ...",
 421                                 target_name(target));
 422                 retval = target_halt(target);
 423                 if (retval != ERROR_OK)
 424                         return retval;
 425         }
 426
 427         return ERROR_OK;
 428 }
 429
 430 static int nds32_v2_checksum_memory(struct target *target,
 431                 uint32_t address, uint32_t count, uint32_t *checksum)
 432 {
 433         LOG_WARNING("Not implemented: %s", __func__);
 434
 435         return ERROR_FAIL;
 436 }
 437
 438 static int nds32_v2_add_breakpoint(struct target *target,
 439                 struct breakpoint *breakpoint)
 440 {
 441         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
 442         struct nds32 *nds32 = &(nds32_v2->nds32);
 443         int result;
 444
 445         if (breakpoint->type == BKPT_HARD) {
 446                 /* check hardware resource */
 447                 if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
 448                         LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
 449                                         "breakpoints/watchpoints!  The limit of "
 450                                         "combined hardware breakpoints/watchpoints "
 451                                         "is %d. -->", nds32_v2->n_hbr);
 452                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 453                 }
 454
 455                 /* update next place to put hardware breakpoint */
 456                 nds32_v2->next_hbr_index++;
 457
 458                 /* hardware breakpoint insertion occurs before 'continue' actually */
 459                 return ERROR_OK;
 460         } else if (breakpoint->type == BKPT_SOFT) {
 461                 result = nds32_add_software_breakpoint(target, breakpoint);
 462                 if (ERROR_OK != result) {
 463                         /* auto convert to hardware breakpoint if failed */
 464                         if (nds32->auto_convert_hw_bp) {
 465                                 /* convert to hardware breakpoint */
 466                                 breakpoint->type = BKPT_HARD;
 467
 468                                 return nds32_v2_add_breakpoint(target, breakpoint);
 469                         }
 470                 }
 471
 472                 return result;
 473         } else /* unrecognized breakpoint type */
 474                 return ERROR_FAIL;
 475
 476         return ERROR_OK;
 477 }
 478
 479 static int nds32_v2_remove_breakpoint(struct target *target,
 480                 struct breakpoint *breakpoint)
 481 {
 482         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
 483
 484         if (breakpoint->type == BKPT_HARD) {
 485                 if (nds32_v2->next_hbr_index <= 0)
 486                         return ERROR_FAIL;
 487
 488                 /* update next place to put hardware breakpoint */
 489                 nds32_v2->next_hbr_index--;
 490
 491                 /* hardware breakpoint removal occurs after 'halted' actually */
 492                 return ERROR_OK;
 493         } else if (breakpoint->type == BKPT_SOFT) {
 494                 return nds32_remove_software_breakpoint(target, breakpoint);
 495         } else /* unrecognized breakpoint type */
 496                 return ERROR_FAIL;
 497
 498         return ERROR_OK;
 499 }
 500
 501 static int nds32_v2_add_watchpoint(struct target *target,
 502                 struct watchpoint *watchpoint)
 503 {
 504         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
 505
 506         /* check hardware resource */
 507         if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
 508                 LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
 509                                 "breakpoints/watchpoints!  The limit of "
 510                                 "combined hardware breakpoints/watchpoints is %d. -->", nds32_v2->n_hbr);
 511                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 512         }
 513
 514         /* update next place to put hardware watchpoint */
 515         nds32_v2->next_hbr_index++;
 516
 517         return ERROR_OK;
 518 }
 519
 520 static int nds32_v2_remove_watchpoint(struct target *target,
 521                 struct watchpoint *watchpoint)
 522 {
 523         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
 524
 525         if (nds32_v2->next_hbr_index <= 0)
 526                 return ERROR_FAIL;
 527
 528         /* update next place to put hardware breakpoint */
 529         nds32_v2->next_hbr_index--;
 530
 531         return ERROR_OK;
 532 }
 533
 534 static int nds32_v2_get_exception_address(struct nds32 *nds32,
 535                 uint32_t *address, uint32_t reason)
 536 {
 537         struct aice_port_s *aice = target_to_aice(nds32->target);
 538
 539         aice_read_register(aice, IR4, address); /* read $EVA directly */
 540
 541         /* TODO: hit multiple watchpoints */
 542
 543         return ERROR_OK;
 544 }
 545
 546 /**
 547  * find out which watchpoint hits
 548  * get exception address and compare the address to watchpoints
 549  */
 550 static int nds32_v2_hit_watchpoint(struct target *target,
 551                 struct watchpoint **hit_watchpoint)
 552 {
 553         uint32_t exception_address;
 554         struct watchpoint *wp;
 555         static struct watchpoint scan_all_watchpoint;
 556         struct nds32 *nds32 = target_to_nds32(target);
 557
 558         scan_all_watchpoint.address = 0;
 559         scan_all_watchpoint.rw = WPT_WRITE;
 560         scan_all_watchpoint.next = 0;
 561         scan_all_watchpoint.unique_id = 0x5CA8;
 562
 563         exception_address = nds32->watched_address;
 564
 565         if (exception_address == 0) {
 566                 /* send watch:0 to tell GDB to do software scan for hitting multiple watchpoints */
 567                 *hit_watchpoint = &scan_all_watchpoint;
 568                 return ERROR_OK;
 569         }
 570
 571         for (wp = target->watchpoints; wp; wp = wp->next) {
 572                 if (((exception_address ^ wp->address) & (~wp->mask)) == 0) {
 573                         /* TODO: dispel false match */
 574                         *hit_watchpoint = wp;
 575                         return ERROR_OK;
 576                 }
 577         }
 578
 579         return ERROR_FAIL;
 580 }
 581
 582 static int nds32_v2_run_algorithm(struct target *target,
 583                 int num_mem_params,
 584                 struct mem_param *mem_params,
 585                 int num_reg_params,
 586                 struct reg_param *reg_params,
 587                 uint32_t entry_point,
 588                 uint32_t exit_point,
 589                 int timeout_ms,
 590                 void *arch_info)
 591 {
 592         LOG_WARNING("Not implemented: %s", __func__);
 593
 594         return ERROR_FAIL;
 595 }
 596
 597 static int nds32_v2_target_create(struct target *target, Jim_Interp *interp)
 598 {
 599         struct nds32_v2_common *nds32_v2;
 600
 601         nds32_v2 = calloc(1, sizeof(*nds32_v2));
 602         if (!nds32_v2)
 603                 return ERROR_FAIL;
 604
 605         nds32_v2->nds32.register_map = nds32_v2_register_mapping;
 606         nds32_v2->nds32.get_debug_reason = nds32_v2_get_debug_reason;
 607         nds32_v2->nds32.enter_debug_state = nds32_v2_debug_entry;
 608         nds32_v2->nds32.leave_debug_state = nds32_v2_leave_debug_state;
 609         nds32_v2->nds32.get_watched_address = nds32_v2_get_exception_address;
 610
 611         nds32_init_arch_info(target, &(nds32_v2->nds32));
 612
 613         return ERROR_OK;
 614 }
 615
 616 static int nds32_v2_init_target(struct command_context *cmd_ctx,
 617                 struct target *target)
 618 {
 619         /* Initialize anything we can set up without talking to the target */
 620
 621         struct nds32 *nds32 = target_to_nds32(target);
 622
 623         nds32_init(nds32);
 624
 625         return ERROR_OK;
 626 }
 627
 628 /* talk to the target and set things up */
 629 static int nds32_v2_examine(struct target *target)
 630 {
 631         struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
 632         struct nds32 *nds32 = &(nds32_v2->nds32);
 633         struct aice_port_s *aice = target_to_aice(target);
 634
 635         if (!target_was_examined(target)) {
 636                 CHECK_RETVAL(nds32_edm_config(nds32));
 637
 638                 if (nds32->reset_halt_as_examine)
 639                         CHECK_RETVAL(nds32_reset_halt(nds32));
 640         }
 641
 642         uint32_t edm_cfg;
 643         aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
 644
 645         /* get the number of hardware breakpoints */
 646         nds32_v2->n_hbr = (edm_cfg & 0x7) + 1;
 647
 648         nds32_v2->next_hbr_index = 0;
 649
 650         LOG_INFO("%s: total hardware breakpoint %d", target_name(target),
 651                         nds32_v2->n_hbr);
 652
 653         nds32->target->state = TARGET_RUNNING;
 654         nds32->target->debug_reason = DBG_REASON_NOTHALTED;
 655
 656         target_set_examined(target);
 657
 658         return ERROR_OK;
 659 }
 660
 661 static int nds32_v2_translate_address(struct target *target, uint32_t *address)
 662 {
 663         struct nds32 *nds32 = target_to_nds32(target);
 664         struct nds32_memory *memory = &(nds32->memory);
 665         uint32_t physical_address;
 666
 667         /* Following conditions need to do address translation
 668          * 1. BUS mode
 669          * 2. CPU mode under maximum interrupt level */
 670         if ((NDS_MEMORY_ACC_BUS == memory->access_channel) ||
 671                         ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
 672                          nds32_reach_max_interrupt_level(nds32))) {
 673                 if (ERROR_OK == target->type->virt2phys(target, *address, &physical_address))
 674                         *address = physical_address;
 675                 else
 676                         return ERROR_FAIL;
 677         }
 678
 679         return ERROR_OK;
 680 }
 681
 682 static int nds32_v2_read_buffer(struct target *target, uint32_t address,
 683                 uint32_t size, uint8_t *buffer)
 684 {
 685         struct nds32 *nds32 = target_to_nds32(target);
 686         struct nds32_memory *memory = &(nds32->memory);
 687
 688         if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
 689                         (target->state != TARGET_HALTED)) {
 690                 LOG_WARNING("target was not halted");
 691                 return ERROR_TARGET_NOT_HALTED;
 692         }
 693
 694         /* BUG: If access range crosses multiple pages, the translation will not correct
 695          * for second page or so. */
 696
 697         nds32_v2_translate_address(target, &address);
 698
 699         return nds32_read_buffer(target, address, size, buffer);
 700 }
 701
 702 static int nds32_v2_write_buffer(struct target *target, uint32_t address,
 703                 uint32_t size, const uint8_t *buffer)
 704 {
 705         struct nds32 *nds32 = target_to_nds32(target);
 706         struct nds32_memory *memory = &(nds32->memory);
 707
 708         if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
 709                         (target->state != TARGET_HALTED)) {
 710                 LOG_WARNING("target was not halted");
 711                 return ERROR_TARGET_NOT_HALTED;
 712         }
 713
 714         /* BUG: If access range crosses multiple pages, the translation will not correct
 715          * for second page or so. */
 716
 717         nds32_v2_translate_address(target, &address);
 718
 719         return nds32_write_buffer(target, address, size, buffer);
 720 }
 721
 722 static int nds32_v2_read_memory(struct target *target, uint32_t address,
 723                 uint32_t size, uint32_t count, uint8_t *buffer)
 724 {
 725         struct nds32 *nds32 = target_to_nds32(target);
 726         struct nds32_memory *memory = &(nds32->memory);
 727
 728         if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
 729                         (target->state != TARGET_HALTED)) {
 730                 LOG_WARNING("target was not halted");
 731                 return ERROR_TARGET_NOT_HALTED;
 732         }
 733
 734         /* BUG: If access range crosses multiple pages, the translation will not correct
 735          * for second page or so. */
 736
 737         nds32_v2_translate_address(target, &address);
 738
 739         return nds32_read_memory(target, address, size, count, buffer);
 740 }
 741
 742 static int nds32_v2_write_memory(struct target *target, uint32_t address,
 743                 uint32_t size, uint32_t count, const uint8_t *buffer)
 744 {
 745         struct nds32 *nds32 = target_to_nds32(target);
 746         struct nds32_memory *memory = &(nds32->memory);
 747
 748         if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
 749                         (target->state != TARGET_HALTED)) {
 750                 LOG_WARNING("target was not halted");
 751                 return ERROR_TARGET_NOT_HALTED;
 752         }
 753
 754         /* BUG: If access range crosses multiple pages, the translation will not correct
 755          * for second page or so. */
 756
 757         nds32_v2_translate_address(target, &address);
 758
 759         return nds32_write_memory(target, address, size, count, buffer);
 760 }
 761
 762 /** Holds methods for V2 targets. */
 763 struct target_type nds32_v2_target = {
 764         .name = "nds32_v2",
 765
 766         .poll = nds32_poll,
 767         .arch_state = nds32_arch_state,
 768
 769         .target_request_data = nds32_v2_target_request_data,
 770
 771         .halt = nds32_halt,
 772         .resume = nds32_resume,
 773         .step = nds32_step,
 774
 775         .assert_reset = nds32_assert_reset,
 776         .deassert_reset = nds32_v2_deassert_reset,
 777         .soft_reset_halt = nds32_v2_soft_reset_halt,
 778
 779         /* register access */
 780         .get_gdb_reg_list = nds32_get_gdb_reg_list,
 781
 782         /* memory access */
 783         .read_buffer = nds32_v2_read_buffer,
 784         .write_buffer = nds32_v2_write_buffer,
 785         .read_memory = nds32_v2_read_memory,
 786         .write_memory = nds32_v2_write_memory,
 787
 788         .checksum_memory = nds32_v2_checksum_memory,
 789
 790         /* breakpoint/watchpoint */
 791         .add_breakpoint = nds32_v2_add_breakpoint,
 792         .remove_breakpoint = nds32_v2_remove_breakpoint,
 793         .add_watchpoint = nds32_v2_add_watchpoint,
 794         .remove_watchpoint = nds32_v2_remove_watchpoint,
 795         .hit_watchpoint = nds32_v2_hit_watchpoint,
 796
 797         /* MMU */
 798         .mmu = nds32_mmu,
 799         .virt2phys = nds32_virtual_to_physical,
 800         .read_phys_memory = nds32_read_phys_memory,
 801         .write_phys_memory = nds32_write_phys_memory,
 802
 803         .run_algorithm = nds32_v2_run_algorithm,
 804
 805         .commands = nds32_command_handlers,
 806         .target_create = nds32_v2_target_create,
 807         .init_target = nds32_v2_init_target,
 808         .examine = nds32_v2_examine,
 809 };