1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2013 Andes Technology *
5 * Hsiangkai Wang <hkwang@andestech.com> *
6 ***************************************************************************/
8 #ifndef OPENOCD_TARGET_NDS32_REG_H
9 #define OPENOCD_TARGET_NDS32_REG_H
11 #define SRIDX(a, b, c) ((a << 7) | (b << 3) | c)
12 #define NDS32_REGISTER_DISABLE (0x0)
14 enum nds32_reg_number_s {
15 R0 = 0, /* general registers */
54 CR0, /* system registers */
173 D0L24, /* audio registers */
275 enum nds32_reg_type_s {
276 NDS32_REG_TYPE_GPR = 0,
287 NDS32_REG_TYPE_SECURE,
292 const char *simple_mnemonic;
293 const char *symbolic_mnemonic;
295 enum nds32_reg_type_s type;
299 struct nds32_reg_exception_s {
301 uint32_t ex_value_bit_pos;
302 uint32_t ex_value_mask;
306 void nds32_reg_init(void);
307 uint32_t nds32_reg_sr_index(uint32_t number);
308 enum nds32_reg_type_s nds32_reg_type(uint32_t number);
309 uint8_t nds32_reg_size(uint32_t number);
310 const char *nds32_reg_simple_name(uint32_t number);
311 const char *nds32_reg_symbolic_name(uint32_t number);
312 bool nds32_reg_exception(uint32_t number, uint32_t value);
314 #endif /* OPENOCD_TARGET_NDS32_REG_H */