1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2013 Andes Technology *
5 * Hsiangkai Wang <hkwang@andestech.com> *
6 ***************************************************************************/
8 #ifndef OPENOCD_TARGET_NDS32_EDM_H
9 #define OPENOCD_TARGET_NDS32_EDM_H
11 #include "helper/types.h"
15 * This is the interface to the Embedded Debug Module for Andes cores.
18 /* EDM misc registers */
19 enum nds_edm_misc_reg {
20 NDS_EDM_MISC_DIMIR = 0x0,
22 NDS_EDM_MISC_EDM_CMDR,
25 NDS_EDM_MISC_EDM_PROBE,
26 NDS_EDM_MISC_GEN_PORT0,
27 NDS_EDM_MISC_GEN_PORT1,
30 /* EDM system registers */
31 enum nds_edm_system_reg {
32 NDS_EDM_SR_BPC0 = 0x00,
40 NDS_EDM_SR_BPA0 = 0x08,
48 NDS_EDM_SR_BPAM0 = 0x10,
56 NDS_EDM_SR_BPV0 = 0x18,
64 NDS_EDM_SR_BPCID0 = 0x20,
72 NDS_EDM_SR_EDM_CFG = 0x28,
73 NDS_EDM_SR_EDMSW = 0x30,
74 NDS_EDM_SR_EDM_CTL = 0x38,
75 NDS_EDM_SR_EDM_DTR = 0x40,
76 NDS_EDM_SR_BPMTV = 0x48,
77 NDS_EDM_SR_DIMBR = 0x50,
78 NDS_EDM_SR_TECR0 = 0x70,
79 NDS_EDM_SR_TECR1 = 0x71,
82 enum nds_memory_access {
83 NDS_MEMORY_ACC_BUS = 0,
87 enum nds_memory_select {
88 NDS_MEMORY_SELECT_AUTO = 0,
89 NDS_MEMORY_SELECT_MEM = 1,
90 NDS_MEMORY_SELECT_ILM = 2,
91 NDS_MEMORY_SELECT_DLM = 3,
94 #define NDS_DBGER_DEX (0x1)
95 #define NDS_DBGER_DPED (0x2)
96 #define NDS_DBGER_CRST (0x4)
97 #define NDS_DBGER_AT_MAX (0x8)
98 #define NDS_DBGER_ILL_SEC_ACC (0x10)
99 #define NDS_DBGER_ALL_SUPRS_EX (0x40000000)
100 #define NDS_DBGER_RESACC (0x80000000)
101 #define NDS_DBGER_CLEAR_ALL (0x1F)
103 #define NDS_EDMSW_WDV (1 << 0)
104 #define NDS_EDMSW_RDV (1 << 1)
106 #endif /* OPENOCD_TARGET_NDS32_EDM_H */