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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2013 Andes Technology                                   *
   5  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_TARGET_NDS32_EDM_H
   9 #define OPENOCD_TARGET_NDS32_EDM_H
  10
  11 #include "helper/types.h"
  12
  13 /**
  14  * @file
  15  * This is the interface to the Embedded Debug Module for Andes cores.
  16  */
  17
  18 /* EDM misc registers */
  19 enum nds_edm_misc_reg {
  20         NDS_EDM_MISC_DIMIR = 0x0,
  21         NDS_EDM_MISC_SBAR,
  22         NDS_EDM_MISC_EDM_CMDR,
  23         NDS_EDM_MISC_DBGER,
  24         NDS_EDM_MISC_ACC_CTL,
  25         NDS_EDM_MISC_EDM_PROBE,
  26         NDS_EDM_MISC_GEN_PORT0,
  27         NDS_EDM_MISC_GEN_PORT1,
  28 };
  29
  30 /* EDM system registers */
  31 enum nds_edm_system_reg {
  32         NDS_EDM_SR_BPC0 = 0x00,
  33         NDS_EDM_SR_BPC1,
  34         NDS_EDM_SR_BPC2,
  35         NDS_EDM_SR_BPC3,
  36         NDS_EDM_SR_BPC4,
  37         NDS_EDM_SR_BPC5,
  38         NDS_EDM_SR_BPC6,
  39         NDS_EDM_SR_BPC7,
  40         NDS_EDM_SR_BPA0 = 0x08,
  41         NDS_EDM_SR_BPA1,
  42         NDS_EDM_SR_BPA2,
  43         NDS_EDM_SR_BPA3,
  44         NDS_EDM_SR_BPA4,
  45         NDS_EDM_SR_BPA5,
  46         NDS_EDM_SR_BPA6,
  47         NDS_EDM_SR_BPA7,
  48         NDS_EDM_SR_BPAM0 = 0x10,
  49         NDS_EDM_SR_BPAM1,
  50         NDS_EDM_SR_BPAM2,
  51         NDS_EDM_SR_BPAM3,
  52         NDS_EDM_SR_BPAM4,
  53         NDS_EDM_SR_BPAM5,
  54         NDS_EDM_SR_BPAM6,
  55         NDS_EDM_SR_BPAM7,
  56         NDS_EDM_SR_BPV0 = 0x18,
  57         NDS_EDM_SR_BPV1,
  58         NDS_EDM_SR_BPV2,
  59         NDS_EDM_SR_BPV3,
  60         NDS_EDM_SR_BPV4,
  61         NDS_EDM_SR_BPV5,
  62         NDS_EDM_SR_BPV6,
  63         NDS_EDM_SR_BPV7,
  64         NDS_EDM_SR_BPCID0 = 0x20,
  65         NDS_EDM_SR_BPCID1,
  66         NDS_EDM_SR_BPCID2,
  67         NDS_EDM_SR_BPCID3,
  68         NDS_EDM_SR_BPCID4,
  69         NDS_EDM_SR_BPCID5,
  70         NDS_EDM_SR_BPCID6,
  71         NDS_EDM_SR_BPCID7,
  72         NDS_EDM_SR_EDM_CFG = 0x28,
  73         NDS_EDM_SR_EDMSW = 0x30,
  74         NDS_EDM_SR_EDM_CTL = 0x38,
  75         NDS_EDM_SR_EDM_DTR = 0x40,
  76         NDS_EDM_SR_BPMTV = 0x48,
  77         NDS_EDM_SR_DIMBR = 0x50,
  78         NDS_EDM_SR_TECR0 = 0x70,
  79         NDS_EDM_SR_TECR1 = 0x71,
  80 };
  81
  82 enum nds_memory_access {
  83         NDS_MEMORY_ACC_BUS = 0,
  84         NDS_MEMORY_ACC_CPU,
  85 };
  86
  87 enum nds_memory_select {
  88         NDS_MEMORY_SELECT_AUTO = 0,
  89         NDS_MEMORY_SELECT_MEM = 1,
  90         NDS_MEMORY_SELECT_ILM = 2,
  91         NDS_MEMORY_SELECT_DLM = 3,
  92 };
  93
  94 #define NDS_DBGER_DEX           (0x1)
  95 #define NDS_DBGER_DPED          (0x2)
  96 #define NDS_DBGER_CRST          (0x4)
  97 #define NDS_DBGER_AT_MAX        (0x8)
  98 #define NDS_DBGER_ILL_SEC_ACC   (0x10)
  99 #define NDS_DBGER_ALL_SUPRS_EX  (0x40000000)
 100 #define NDS_DBGER_RESACC        (0x80000000)
 101 #define NDS_DBGER_CLEAR_ALL     (0x1F)
 102
 103 #define NDS_EDMSW_WDV           (1 << 0)
 104 #define NDS_EDMSW_RDV           (1 << 1)
 105
 106 #endif /* OPENOCD_TARGET_NDS32_EDM_H */