1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2013 Andes Technology *
5 * Hsiangkai Wang <hkwang@andestech.com> *
6 ***************************************************************************/
12 #include <helper/log.h>
13 #include <target/target.h>
14 #include "nds32_disassembler.h"
16 static const int enable4_bits[] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4};
18 int nds32_read_opcode(struct nds32 *nds32, uint32_t address, uint32_t *value)
20 struct target *target = nds32->target;
23 if (!target_was_examined(target)) {
24 LOG_ERROR("Target not examined yet");
28 int retval = target_read_buffer(target, address, 4, value_buf);
30 if (retval == ERROR_OK) {
31 /* instructions are always big-endian */
32 *value = be_to_h_u32(value_buf);
34 LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8" PRIx32 "",
39 LOG_DEBUG("address: 0x%8.8" PRIx32 " failed",
46 static int nds32_parse_type_0(uint32_t opcode, int32_t *imm)
48 *imm = opcode & 0x1FFFFFF;
53 static int nds32_parse_type_1(uint32_t opcode, uint8_t *rt, int32_t *imm)
55 *rt = (opcode >> 20) & 0x1F;
56 *imm = opcode & 0xFFFFF;
61 static int nds32_parse_type_2(uint32_t opcode, uint8_t *rt, uint8_t *ra, int32_t *imm)
63 *rt = (opcode >> 20) & 0x1F;
64 *ra = (opcode >> 15) & 0x1F;
65 *imm = opcode & 0x7FFF;
70 static int nds32_parse_type_3(uint32_t opcode, uint8_t *rt, uint8_t *ra,
71 uint8_t *rb, int32_t *imm)
73 *rt = (opcode >> 20) & 0x1F;
74 *ra = (opcode >> 15) & 0x1F;
75 *rb = (opcode >> 10) & 0x1F;
76 *imm = opcode & 0x3FF;
81 static int nds32_parse_type_4(uint32_t opcode, uint8_t *rt, uint8_t *ra,
82 uint8_t *rb, uint8_t *rd, uint8_t *sub_opc)
84 *rt = (opcode >> 20) & 0x1F;
85 *ra = (opcode >> 15) & 0x1F;
86 *rb = (opcode >> 10) & 0x1F;
87 *rd = (opcode >> 5) & 0x1F;
88 *sub_opc = opcode & 0x1F;
93 /* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */
94 static int nds32_parse_group_0_insn(struct nds32 *nds32, uint32_t opcode,
96 struct nds32_instruction *instruction)
100 opc_6 = instruction->info.opc_6;
102 switch (opc_6 & 0x7) {
104 nds32_parse_type_2(opcode, &(instruction->info.rt),
105 &(instruction->info.ra), &(instruction->info.imm));
106 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
107 instruction->type = NDS32_INSN_LOAD_STORE;
108 nds32_get_mapped_reg(nds32, instruction->info.ra,
109 &(instruction->access_start));
110 instruction->access_start += instruction->info.imm;
111 instruction->access_end = instruction->access_start + 1;
112 snprintf(instruction->text,
114 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
115 "\tLBI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
117 opcode, instruction->info.rt, instruction->info.ra,
118 instruction->info.imm);
121 nds32_parse_type_2(opcode, &(instruction->info.rt),
122 &(instruction->info.ra), &(instruction->info.imm));
123 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
124 instruction->type = NDS32_INSN_LOAD_STORE;
125 nds32_get_mapped_reg(nds32, instruction->info.ra,
126 &(instruction->access_start));
127 instruction->access_start += instruction->info.imm;
128 instruction->access_end = instruction->access_start + 2;
129 snprintf(instruction->text,
131 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
132 "\tLHI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
134 opcode, instruction->info.rt, instruction->info.ra,
135 instruction->info.imm);
138 nds32_parse_type_2(opcode, &(instruction->info.rt),
139 &(instruction->info.ra), &(instruction->info.imm));
140 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
141 instruction->type = NDS32_INSN_LOAD_STORE;
142 nds32_get_mapped_reg(nds32, instruction->info.ra,
143 &(instruction->access_start));
144 instruction->access_start += instruction->info.imm;
145 instruction->access_end = instruction->access_start + 4;
146 snprintf(instruction->text,
148 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
149 "\tLWI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
151 opcode, instruction->info.rt, instruction->info.ra,
152 instruction->info.imm);
155 nds32_parse_type_2(opcode, &(instruction->info.rt),
156 &(instruction->info.ra), &(instruction->info.imm));
157 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
158 instruction->type = NDS32_INSN_LOAD_STORE;
159 nds32_get_mapped_reg(nds32, instruction->info.ra,
160 &(instruction->access_start));
161 instruction->access_end = instruction->access_start + 1;
162 snprintf(instruction->text,
164 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
165 "\tLBI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
167 opcode, instruction->info.rt, instruction->info.ra,
168 instruction->info.imm);
171 nds32_parse_type_2(opcode, &(instruction->info.rt),
172 &(instruction->info.ra), &(instruction->info.imm));
173 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
174 instruction->type = NDS32_INSN_LOAD_STORE;
175 nds32_get_mapped_reg(nds32, instruction->info.ra,
176 &(instruction->access_start));
177 instruction->access_end = instruction->access_start + 2;
178 snprintf(instruction->text,
180 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
181 "\tLHI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
183 opcode, instruction->info.rt, instruction->info.ra,
184 instruction->info.imm);
187 nds32_parse_type_2(opcode, &(instruction->info.rt),
188 &(instruction->info.ra), &(instruction->info.imm));
189 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
190 instruction->type = NDS32_INSN_LOAD_STORE;
191 nds32_get_mapped_reg(nds32, instruction->info.ra,
192 &(instruction->access_start));
193 instruction->access_end = instruction->access_start + 4;
194 snprintf(instruction->text,
196 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
197 "\tLWI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32 "",
199 opcode, instruction->info.rt, instruction->info.ra,
200 instruction->info.imm);
203 snprintf(instruction->text,
205 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
214 static int nds32_parse_group_1_insn(struct nds32 *nds32, uint32_t opcode,
215 uint32_t address, struct nds32_instruction *instruction)
219 opc_6 = instruction->info.opc_6;
221 switch (opc_6 & 0x7) {
223 nds32_parse_type_2(opcode, &(instruction->info.rt),
224 &(instruction->info.ra), &(instruction->info.imm));
225 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
226 instruction->type = NDS32_INSN_LOAD_STORE;
227 nds32_get_mapped_reg(nds32, instruction->info.ra,
228 &(instruction->access_start));
229 instruction->access_start += instruction->info.imm;
230 instruction->access_end = instruction->access_start + 1;
231 snprintf(instruction->text,
233 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
234 "\tSBI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
236 opcode, instruction->info.rt, instruction->info.ra,
237 instruction->info.imm);
240 nds32_parse_type_2(opcode, &(instruction->info.rt),
241 &(instruction->info.ra), &(instruction->info.imm));
242 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
243 instruction->type = NDS32_INSN_LOAD_STORE;
244 nds32_get_mapped_reg(nds32, instruction->info.ra,
245 &(instruction->access_start));
246 instruction->access_start += instruction->info.imm;
247 instruction->access_end = instruction->access_start + 2;
248 snprintf(instruction->text,
250 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
251 "\tSHI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
253 opcode, instruction->info.rt, instruction->info.ra,
254 instruction->info.imm);
257 nds32_parse_type_2(opcode, &(instruction->info.rt),
258 &(instruction->info.ra), &(instruction->info.imm));
259 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
260 instruction->type = NDS32_INSN_LOAD_STORE;
261 nds32_get_mapped_reg(nds32, instruction->info.ra,
262 &(instruction->access_start));
263 instruction->access_start += instruction->info.imm;
264 instruction->access_end = instruction->access_start + 4;
265 snprintf(instruction->text,
267 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
268 "\tSWI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
270 opcode, instruction->info.rt, instruction->info.ra,
271 instruction->info.imm);
274 nds32_parse_type_2(opcode, &(instruction->info.rt),
275 &(instruction->info.ra), &(instruction->info.imm));
276 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
277 instruction->type = NDS32_INSN_LOAD_STORE;
278 nds32_get_mapped_reg(nds32, instruction->info.ra,
279 &(instruction->access_start));
280 instruction->access_end = instruction->access_start + 1;
281 snprintf(instruction->text,
283 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
284 "\tSBI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
286 opcode, instruction->info.rt, instruction->info.ra,
287 instruction->info.imm);
290 nds32_parse_type_2(opcode, &(instruction->info.rt),
291 &(instruction->info.ra), &(instruction->info.imm));
292 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
293 instruction->type = NDS32_INSN_LOAD_STORE;
294 nds32_get_mapped_reg(nds32, instruction->info.ra,
295 &(instruction->access_start));
296 instruction->access_end = instruction->access_start + 2;
297 snprintf(instruction->text,
299 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
300 "\tSHI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
302 opcode, instruction->info.rt, instruction->info.ra,
303 instruction->info.imm);
306 nds32_parse_type_2(opcode, &(instruction->info.rt),
307 &(instruction->info.ra), &(instruction->info.imm));
308 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
309 instruction->type = NDS32_INSN_LOAD_STORE;
310 nds32_get_mapped_reg(nds32, instruction->info.ra,
311 &(instruction->access_start));
312 instruction->access_end = instruction->access_start + 4;
313 snprintf(instruction->text,
315 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
316 "\tSWI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
318 opcode, instruction->info.rt, instruction->info.ra,
319 instruction->info.imm);
322 snprintf(instruction->text,
324 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
333 static int nds32_parse_group_2_insn(struct nds32 *nds32, uint32_t opcode,
334 uint32_t address, struct nds32_instruction *instruction)
338 opc_6 = instruction->info.opc_6;
340 switch (opc_6 & 0x7) {
342 nds32_parse_type_2(opcode, &(instruction->info.rt),
343 &(instruction->info.ra), &(instruction->info.imm));
344 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
345 instruction->type = NDS32_INSN_LOAD_STORE;
346 nds32_get_mapped_reg(nds32, instruction->info.ra,
347 &(instruction->access_start));
348 instruction->access_start += instruction->info.imm;
349 instruction->access_end = instruction->access_start + 1;
350 snprintf(instruction->text,
352 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
353 "\tLBSI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
355 opcode, instruction->info.rt, instruction->info.ra,
356 instruction->info.imm);
359 nds32_parse_type_2(opcode, &(instruction->info.rt),
360 &(instruction->info.ra), &(instruction->info.imm));
361 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
362 instruction->type = NDS32_INSN_LOAD_STORE;
363 nds32_get_mapped_reg(nds32, instruction->info.ra,
364 &(instruction->access_start));
365 instruction->access_start += instruction->info.imm;
366 instruction->access_end = instruction->access_start + 2;
367 snprintf(instruction->text,
369 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
370 "\tLHSI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
372 opcode, instruction->info.rt, instruction->info.ra,
373 instruction->info.imm);
375 case 3: { /* DPREFI */
377 nds32_parse_type_2(opcode, &sub_type, &(instruction->info.ra),
378 &(instruction->info.imm));
379 instruction->info.sub_opc = sub_type & 0xF;
380 instruction->type = NDS32_INSN_MISC;
381 if (sub_type & 0x10) { /* DPREFI.d */
383 instruction->info.imm = (instruction->info.imm << 17) >> 14;
384 snprintf(instruction->text,
386 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
387 "\tDPREFI.d\t%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
389 opcode, instruction->info.sub_opc,
390 instruction->info.ra, instruction->info.imm);
391 } else { /* DPREFI.w */
393 instruction->info.imm = (instruction->info.imm << 17) >> 15;
394 snprintf(instruction->text,
396 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
397 "\tDPREFI.w\t%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
399 opcode, instruction->info.sub_opc,
400 instruction->info.ra, instruction->info.imm);
404 case 4: /* LBSI.bi */
405 nds32_parse_type_2(opcode, &(instruction->info.rt),
406 &(instruction->info.ra), &(instruction->info.imm));
407 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
408 instruction->type = NDS32_INSN_LOAD_STORE;
409 nds32_get_mapped_reg(nds32, instruction->info.ra,
410 &(instruction->access_start));
411 instruction->access_end = instruction->access_start + 1;
412 snprintf(instruction->text,
414 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
415 "\tLBSI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
417 opcode, instruction->info.rt, instruction->info.ra,
418 instruction->info.imm);
420 case 5: /* LHSI.bi */
421 nds32_parse_type_2(opcode, &(instruction->info.rt),
422 &(instruction->info.ra), &(instruction->info.imm));
423 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
424 instruction->type = NDS32_INSN_LOAD_STORE;
425 nds32_get_mapped_reg(nds32, instruction->info.ra,
426 &(instruction->access_start));
427 instruction->access_end = instruction->access_start + 2;
428 snprintf(instruction->text,
430 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
431 "\tLHSI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
433 opcode, instruction->info.rt, instruction->info.ra,
434 instruction->info.imm);
437 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
438 instruction->type = NDS32_INSN_LOAD_STORE;
439 if ((instruction->info.imm >> 19) & 0x1) { /* LBSI.gp */
440 instruction->info.imm = (instruction->info.imm << 13) >> 13;
441 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
442 instruction->access_start += instruction->info.imm;
443 instruction->access_end = instruction->access_start + 1;
444 snprintf(instruction->text,
446 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
447 "\tLBSI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
449 opcode, instruction->info.rt, instruction->info.imm);
450 } else { /* LBI.gp */
451 instruction->info.imm = (instruction->info.imm << 13) >> 13;
452 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
453 instruction->access_start += instruction->info.imm;
454 instruction->access_end = instruction->access_start + 1;
455 snprintf(instruction->text,
457 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
458 "\tLBI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
460 opcode, instruction->info.rt, instruction->info.imm);
464 snprintf(instruction->text,
466 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
475 static int nds32_parse_mem(struct nds32 *nds32, uint32_t opcode, uint32_t address,
476 struct nds32_instruction *instruction)
478 uint32_t sub_opcode = opcode & 0x3F;
479 uint32_t val_ra, val_rb;
480 switch (sub_opcode >> 3) {
482 switch (sub_opcode & 0x7) {
484 nds32_parse_type_3(opcode, &(instruction->info.rt),
485 &(instruction->info.ra),
486 &(instruction->info.rb), &(instruction->info.imm));
487 instruction->type = NDS32_INSN_LOAD_STORE;
488 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
489 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
490 instruction->access_start = val_ra +
491 (val_rb << ((instruction->info.imm >> 8) & 0x3));
492 instruction->access_end = instruction->access_start + 1;
493 snprintf(instruction->text,
495 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
496 "\tLB\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
498 opcode, instruction->info.rt, instruction->info.ra,
499 instruction->info.rb,
500 (instruction->info.imm >> 8) & 0x3);
503 nds32_parse_type_3(opcode, &(instruction->info.rt),
504 &(instruction->info.ra),
505 &(instruction->info.rb), &(instruction->info.imm));
506 instruction->type = NDS32_INSN_LOAD_STORE;
507 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
508 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
509 instruction->access_start = val_ra +
510 (val_rb << ((instruction->info.imm >> 8) & 0x3));
511 instruction->access_end = instruction->access_start + 2;
512 snprintf(instruction->text,
514 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
515 "\tLH\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
517 opcode, instruction->info.rt, instruction->info.ra,
518 instruction->info.rb,
519 (instruction->info.imm >> 8) & 0x3);
522 nds32_parse_type_3(opcode, &(instruction->info.rt),
523 &(instruction->info.ra),
524 &(instruction->info.rb), &(instruction->info.imm));
525 instruction->type = NDS32_INSN_LOAD_STORE;
526 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
527 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
528 instruction->access_start = val_ra +
529 (val_rb << ((instruction->info.imm >> 8) & 0x3));
530 instruction->access_end = instruction->access_start + 4;
531 snprintf(instruction->text,
533 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
534 "\tLW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
536 opcode, instruction->info.rt, instruction->info.ra,
537 instruction->info.rb,
538 (instruction->info.imm >> 8) & 0x3);
541 nds32_parse_type_3(opcode, &(instruction->info.rt),
542 &(instruction->info.ra),
543 &(instruction->info.rb), &(instruction->info.imm));
544 instruction->type = NDS32_INSN_LOAD_STORE;
545 nds32_get_mapped_reg(nds32, instruction->info.ra,
546 &(instruction->access_start));
547 instruction->access_end = instruction->access_start + 1;
548 snprintf(instruction->text,
550 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
551 "\tLB.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
553 opcode, instruction->info.rt,
554 instruction->info.ra, instruction->info.rb,
555 (instruction->info.imm >> 8) & 0x3);
558 nds32_parse_type_3(opcode, &(instruction->info.rt),
559 &(instruction->info.ra),
560 &(instruction->info.rb), &(instruction->info.imm));
561 instruction->type = NDS32_INSN_LOAD_STORE;
562 nds32_get_mapped_reg(nds32, instruction->info.ra,
563 &(instruction->access_start));
564 instruction->access_end = instruction->access_start + 2;
565 snprintf(instruction->text,
567 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
568 "\tLH.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
570 opcode, instruction->info.rt, instruction->info.ra,
571 instruction->info.rb,
572 (instruction->info.imm >> 8) & 0x3);
575 nds32_parse_type_3(opcode, &(instruction->info.rt),
576 &(instruction->info.ra),
577 &(instruction->info.rb), &(instruction->info.imm));
578 instruction->type = NDS32_INSN_LOAD_STORE;
579 nds32_get_mapped_reg(nds32, instruction->info.ra,
580 &(instruction->access_start));
581 instruction->access_end = instruction->access_start + 4;
582 snprintf(instruction->text,
584 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
585 "\tLW.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
587 opcode, instruction->info.rt, instruction->info.ra,
588 instruction->info.rb,
589 (instruction->info.imm >> 8) & 0x3);
594 switch (sub_opcode & 0x7) {
596 nds32_parse_type_3(opcode, &(instruction->info.rt),
597 &(instruction->info.ra),
598 &(instruction->info.rb), &(instruction->info.imm));
599 instruction->type = NDS32_INSN_LOAD_STORE;
600 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
601 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
602 instruction->access_start = val_ra +
603 (val_rb << ((instruction->info.imm >> 8) & 0x3));
604 instruction->access_end = instruction->access_start + 1;
605 snprintf(instruction->text,
607 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
608 "\tSB\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
610 opcode, instruction->info.rt,
611 instruction->info.ra, instruction->info.rb,
612 (instruction->info.imm >> 8) & 0x3);
615 nds32_parse_type_3(opcode, &(instruction->info.rt),
616 &(instruction->info.ra),
617 &(instruction->info.rb), &(instruction->info.imm));
618 instruction->type = NDS32_INSN_LOAD_STORE;
619 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
620 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
621 instruction->access_start = val_ra +
622 (val_rb << ((instruction->info.imm >> 8) & 0x3));
623 instruction->access_end = instruction->access_start + 2;
624 snprintf(instruction->text,
626 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
627 "\tSH\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
629 opcode, instruction->info.rt, instruction->info.ra,
630 instruction->info.rb,
631 (instruction->info.imm >> 8) & 0x3);
634 nds32_parse_type_3(opcode, &(instruction->info.rt),
635 &(instruction->info.ra),
636 &(instruction->info.rb), &(instruction->info.imm));
637 instruction->type = NDS32_INSN_LOAD_STORE;
638 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
639 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
640 instruction->access_start = val_ra +
641 (val_rb << ((instruction->info.imm >> 8) & 0x3));
642 instruction->access_end = instruction->access_start + 4;
643 snprintf(instruction->text,
645 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
646 "\tSW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
648 opcode, instruction->info.rt,
649 instruction->info.ra, instruction->info.rb,
650 (instruction->info.imm >> 8) & 0x3);
653 nds32_parse_type_3(opcode, &(instruction->info.rt),
654 &(instruction->info.ra),
655 &(instruction->info.rb), &(instruction->info.imm));
656 instruction->type = NDS32_INSN_LOAD_STORE;
657 nds32_get_mapped_reg(nds32, instruction->info.ra,
658 &(instruction->access_start));
659 instruction->access_end = instruction->access_start + 1;
660 snprintf(instruction->text,
662 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
663 "\tSB.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
665 opcode, instruction->info.rt, instruction->info.ra,
666 instruction->info.rb,
667 (instruction->info.imm >> 8) & 0x3);
670 nds32_parse_type_3(opcode, &(instruction->info.rt),
671 &(instruction->info.ra),
672 &(instruction->info.rb), &(instruction->info.imm));
673 instruction->type = NDS32_INSN_LOAD_STORE;
674 nds32_get_mapped_reg(nds32, instruction->info.ra,
675 &(instruction->access_start));
676 instruction->access_end = instruction->access_start + 2;
677 snprintf(instruction->text,
679 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
680 "\tSH.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
682 opcode, instruction->info.rt, instruction->info.ra,
683 instruction->info.rb,
684 (instruction->info.imm >> 8) & 0x3);
687 nds32_parse_type_3(opcode, &(instruction->info.rt),
688 &(instruction->info.ra),
689 &(instruction->info.rb), &(instruction->info.imm));
690 instruction->type = NDS32_INSN_LOAD_STORE;
691 nds32_get_mapped_reg(nds32, instruction->info.ra,
692 &(instruction->access_start));
693 instruction->access_end = instruction->access_start + 4;
694 snprintf(instruction->text,
696 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
697 "\tSW.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
699 opcode, instruction->info.rt, instruction->info.ra,
700 instruction->info.rb,
701 (instruction->info.imm >> 8) & 0x3);
706 switch (sub_opcode & 0x7) {
708 nds32_parse_type_3(opcode, &(instruction->info.rt),
709 &(instruction->info.ra),
710 &(instruction->info.rb), &(instruction->info.imm));
711 instruction->type = NDS32_INSN_LOAD_STORE;
712 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
713 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
714 instruction->access_start = val_ra +
715 (val_rb << ((instruction->info.imm >> 8) & 0x3));
716 instruction->access_end = instruction->access_start + 1;
717 snprintf(instruction->text,
719 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
720 "\tLBS\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
722 opcode, instruction->info.rt,
723 instruction->info.ra, instruction->info.rb,
724 (instruction->info.imm >> 8) & 0x3);
727 nds32_parse_type_3(opcode, &(instruction->info.rt),
728 &(instruction->info.ra),
729 &(instruction->info.rb), &(instruction->info.imm));
730 instruction->type = NDS32_INSN_LOAD_STORE;
731 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
732 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
733 instruction->access_start = val_ra +
734 (val_rb << ((instruction->info.imm >> 8) & 0x3));
735 instruction->access_end = instruction->access_start + 2;
736 snprintf(instruction->text,
738 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
739 "\tLHS\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
741 opcode, instruction->info.rt, instruction->info.ra,
742 instruction->info.rb,
743 (instruction->info.imm >> 8) & 0x3);
746 nds32_parse_type_3(opcode, &(instruction->info.sub_opc),
747 &(instruction->info.ra),
748 &(instruction->info.rb), &(instruction->info.imm));
749 instruction->type = NDS32_INSN_MISC;
750 snprintf(instruction->text,
752 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
753 "\tDPREF\t#%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<#%" PRId32 ")]",
755 opcode, instruction->info.sub_opc,
756 instruction->info.ra, instruction->info.rb,
757 (instruction->info.imm >> 8) & 0x3);
760 nds32_parse_type_3(opcode, &(instruction->info.rt),
761 &(instruction->info.ra),
762 &(instruction->info.rb), &(instruction->info.imm));
763 instruction->type = NDS32_INSN_LOAD_STORE;
764 nds32_get_mapped_reg(nds32, instruction->info.ra,
765 &(instruction->access_start));
766 instruction->access_end = instruction->access_start + 1;
767 snprintf(instruction->text,
769 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
770 "\tLBS.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
772 opcode, instruction->info.rt, instruction->info.ra,
773 instruction->info.rb,
774 (instruction->info.imm >> 8) & 0x3);
777 nds32_parse_type_3(opcode, &(instruction->info.rt),
778 &(instruction->info.ra),
779 &(instruction->info.rb), &(instruction->info.imm));
780 instruction->type = NDS32_INSN_LOAD_STORE;
781 nds32_get_mapped_reg(nds32, instruction->info.ra,
782 &(instruction->access_start));
783 instruction->access_end = instruction->access_start + 2;
784 snprintf(instruction->text,
786 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
787 "\tLHS.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
789 opcode, instruction->info.rt, instruction->info.ra,
790 instruction->info.rb,
791 (instruction->info.imm >> 8) & 0x3);
796 switch (sub_opcode & 0x7) {
798 nds32_parse_type_3(opcode, &(instruction->info.rt),
799 &(instruction->info.ra),
800 &(instruction->info.rb), &(instruction->info.imm));
801 instruction->type = NDS32_INSN_LOAD_STORE;
802 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
803 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
804 instruction->access_start = val_ra +
805 (val_rb << ((instruction->info.imm >> 8) & 0x3));
806 instruction->access_end = instruction->access_start + 4;
807 snprintf(instruction->text,
809 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
810 "\tLLW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
812 opcode, instruction->info.rt, instruction->info.ra,
813 instruction->info.rb,
814 (instruction->info.imm >> 8) & 0x3);
817 nds32_parse_type_3(opcode, &(instruction->info.rt),
818 &(instruction->info.ra),
819 &(instruction->info.rb), &(instruction->info.imm));
820 instruction->type = NDS32_INSN_LOAD_STORE;
821 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
822 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
823 instruction->access_start = val_ra +
824 (val_rb << ((instruction->info.imm >> 8) & 0x3));
825 instruction->access_end = instruction->access_start + 4;
826 snprintf(instruction->text,
828 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
829 "\tSCW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
831 opcode, instruction->info.rt, instruction->info.ra,
832 instruction->info.rb,
833 (instruction->info.imm >> 8) & 0x3);
838 switch (sub_opcode & 0x7) {
840 nds32_parse_type_3(opcode, &(instruction->info.rt),
841 &(instruction->info.ra),
842 &(instruction->info.rb), &(instruction->info.imm));
843 instruction->type = NDS32_INSN_LOAD_STORE;
844 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
845 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
846 instruction->access_start = val_ra +
847 (val_rb << ((instruction->info.imm >> 8) & 0x3));
848 instruction->access_end = instruction->access_start + 1;
849 snprintf(instruction->text,
851 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
852 "\tLBUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
854 opcode, instruction->info.rt, instruction->info.ra,
855 instruction->info.rb,
856 (instruction->info.imm >> 8) & 0x3);
859 nds32_parse_type_3(opcode, &(instruction->info.rt),
860 &(instruction->info.ra),
861 &(instruction->info.rb), &(instruction->info.imm));
862 instruction->type = NDS32_INSN_LOAD_STORE;
863 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
864 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
865 instruction->access_start = val_ra +
866 (val_rb << ((instruction->info.imm >> 8) & 0x3));
867 instruction->access_end = instruction->access_start + 4;
868 snprintf(instruction->text,
870 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
871 "\tLWUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
873 opcode, instruction->info.rt, instruction->info.ra,
874 instruction->info.rb,
875 (instruction->info.imm >> 8) & 0x3);
880 switch (sub_opcode & 0x7) {
882 nds32_parse_type_3(opcode, &(instruction->info.rt),
883 &(instruction->info.ra),
884 &(instruction->info.rb), &(instruction->info.imm));
885 instruction->type = NDS32_INSN_LOAD_STORE;
886 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
887 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
888 instruction->access_start = val_ra +
889 (val_rb << ((instruction->info.imm >> 8) & 0x3));
890 instruction->access_end = instruction->access_start + 1;
891 snprintf(instruction->text,
893 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
894 "\tSBUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
896 opcode, instruction->info.rt, instruction->info.ra,
897 instruction->info.rb,
898 (instruction->info.imm >> 8) & 0x3);
901 nds32_parse_type_3(opcode, &(instruction->info.rt),
902 &(instruction->info.ra),
903 &(instruction->info.rb), &(instruction->info.imm));
904 instruction->type = NDS32_INSN_LOAD_STORE;
905 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
906 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
907 instruction->access_start = val_ra +
908 (val_rb << ((instruction->info.imm >> 8) & 0x3));
909 instruction->access_end = instruction->access_start + 4;
910 snprintf(instruction->text,
912 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
913 "\tSWUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
915 opcode, instruction->info.rt, instruction->info.ra,
916 instruction->info.rb,
917 (instruction->info.imm >> 8) & 0x3);
922 snprintf(instruction->text,
924 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
933 static int nds32_calculate_lsmw_access_range(struct nds32 *nds32,
934 struct nds32_instruction *instruction)
940 enable4 = (instruction->info.imm >> 6) & 0xF;
941 ba = (instruction->info.imm >> 4) & 0x1;
942 id = (instruction->info.imm >> 3) & 0x1;
945 nds32_get_mapped_reg(nds32, instruction->info.ra, &(instruction->access_start));
946 if (id) { /* decrease */
947 /* access_end is the (last_element+1), so no need to minus 4 */
948 /* instruction->access_end -= 4; */
949 instruction->access_end = instruction->access_start;
950 } else { /* increase */
951 instruction->access_start += 4;
954 nds32_get_mapped_reg(nds32, instruction->info.ra, &(instruction->access_start));
955 instruction->access_end = instruction->access_start - 4;
958 if (id) { /* decrease */
959 instruction->access_start = instruction->access_end -
960 4 * (instruction->info.rd - instruction->info.rb + 1);
961 instruction->access_start -= (4 * enable4_bits[enable4]);
962 } else { /* increase */
963 instruction->access_end = instruction->access_start +
964 4 * (instruction->info.rd - instruction->info.rb + 1);
965 instruction->access_end += (4 * enable4_bits[enable4]);
971 static int nds32_parse_lsmw(struct nds32 *nds32, uint32_t opcode, uint32_t address,
972 struct nds32_instruction *instruction)
974 if (opcode & 0x20) { /* SMW, SMWA, SMWZB */
975 switch (opcode & 0x3) {
979 nds32_parse_type_3(opcode, &(instruction->info.rb),
980 &(instruction->info.ra),
981 &(instruction->info.rd), &(instruction->info.imm));
982 instruction->type = NDS32_INSN_LOAD_STORE;
983 nds32_calculate_lsmw_access_range(nds32, instruction);
984 snprintf(instruction->text,
986 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
987 "\tSMW\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
989 opcode, instruction->info.rb, instruction->info.ra,
990 instruction->info.rd,
991 (instruction->info.imm >> 6) & 0xF);
994 nds32_parse_type_3(opcode, &(instruction->info.rb),
995 &(instruction->info.ra),
996 &(instruction->info.rd), &(instruction->info.imm));
997 instruction->type = NDS32_INSN_LOAD_STORE;
998 nds32_calculate_lsmw_access_range(nds32, instruction);
999 snprintf(instruction->text,
1001 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1002 "\tSMWA\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1004 opcode, instruction->info.rb, instruction->info.ra,
1005 instruction->info.rd,
1006 (instruction->info.imm >> 6) & 0xF);
1009 nds32_parse_type_3(opcode, &(instruction->info.rb),
1010 &(instruction->info.ra),
1011 &(instruction->info.rd), &(instruction->info.imm));
1012 instruction->type = NDS32_INSN_LOAD_STORE;
1013 /* TODO: calculate access_start/access_end */
1014 snprintf(instruction->text,
1016 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1017 "\tSMWZB\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1019 opcode, instruction->info.rb, instruction->info.ra,
1020 instruction->info.rd,
1021 (instruction->info.imm >> 6) & 0xF);
1024 snprintf(instruction->text,
1026 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1031 } else { /* LMW, LMWA, LMWZB */
1032 switch (opcode & 0x3) {
1034 nds32_parse_type_3(opcode, &(instruction->info.rb),
1035 &(instruction->info.ra),
1036 &(instruction->info.rd), &(instruction->info.imm));
1037 instruction->type = NDS32_INSN_LOAD_STORE;
1038 nds32_calculate_lsmw_access_range(nds32, instruction);
1039 snprintf(instruction->text,
1041 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1042 "\tLMW\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1044 opcode, instruction->info.rb, instruction->info.ra,
1045 instruction->info.rd,
1046 (instruction->info.imm >> 6) & 0xF);
1049 nds32_parse_type_3(opcode, &(instruction->info.rb),
1050 &(instruction->info.ra),
1051 &(instruction->info.rd), &(instruction->info.imm));
1052 instruction->type = NDS32_INSN_LOAD_STORE;
1053 nds32_calculate_lsmw_access_range(nds32, instruction);
1054 snprintf(instruction->text,
1056 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1057 "\tLMWA\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1059 opcode, instruction->info.rb, instruction->info.ra,
1060 instruction->info.rd,
1061 (instruction->info.imm >> 6) & 0xF);
1064 nds32_parse_type_3(opcode, &(instruction->info.rb),
1065 &(instruction->info.ra),
1066 &(instruction->info.rd), &(instruction->info.imm));
1067 instruction->type = NDS32_INSN_LOAD_STORE;
1068 /* TODO: calculate access_start/access_end */
1069 snprintf(instruction->text,
1071 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1072 "\tLMWZB\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1074 opcode, instruction->info.rb, instruction->info.ra,
1075 instruction->info.rd,
1076 (instruction->info.imm >> 6) & 0xF);
1079 snprintf(instruction->text,
1081 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1091 static int nds32_parse_hwgp(struct nds32 *nds32, uint32_t opcode, uint32_t address,
1092 struct nds32_instruction *instruction)
1094 switch ((opcode >> 18) & 0x3) {
1095 case 0: /* LHI.gp */
1096 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1097 instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */
1098 instruction->type = NDS32_INSN_LOAD_STORE;
1099 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1100 instruction->access_start += instruction->info.imm;
1101 instruction->access_end = instruction->access_start + 2;
1102 snprintf(instruction->text,
1104 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1105 "\tLHI.gp\t$r%" PRIu8 ",[#%" PRId32"]",
1107 opcode, instruction->info.rt, instruction->info.imm);
1109 case 1: /* LHSI.gp */
1110 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1111 instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */
1112 instruction->type = NDS32_INSN_LOAD_STORE;
1113 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1114 instruction->access_start += instruction->info.imm;
1115 instruction->access_end = instruction->access_start + 2;
1116 snprintf(instruction->text,
1118 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1119 "\tLHSI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1121 opcode, instruction->info.rt, instruction->info.imm);
1123 case 2: /* SHI.gp */
1124 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1125 instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */
1126 instruction->type = NDS32_INSN_LOAD_STORE;
1127 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1128 instruction->access_start += instruction->info.imm;
1129 instruction->access_end = instruction->access_start + 2;
1130 snprintf(instruction->text,
1132 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1133 "\tSHI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1135 opcode, instruction->info.rt, instruction->info.imm);
1138 instruction->type = NDS32_INSN_LOAD_STORE;
1139 if ((opcode >> 17) & 0x1) { /* SWI.gp */
1140 nds32_parse_type_1(opcode, &(instruction->info.rt),
1141 &(instruction->info.imm));
1143 instruction->info.imm = (instruction->info.imm << 15) >> 13;
1144 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1145 instruction->access_start += instruction->info.imm;
1146 instruction->access_end = instruction->access_start + 4;
1147 snprintf(instruction->text,
1149 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1150 "\tSWI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1152 opcode, instruction->info.rt, instruction->info.imm);
1153 } else { /* LWI.gp */
1154 nds32_parse_type_1(opcode, &(instruction->info.rt),
1155 &(instruction->info.imm));
1157 instruction->info.imm = (instruction->info.imm << 15) >> 13;
1158 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1159 instruction->access_start += instruction->info.imm;
1160 instruction->access_end = instruction->access_start + 4;
1161 snprintf(instruction->text,
1163 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1164 "\tLWI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1166 opcode, instruction->info.rt, instruction->info.imm);
1171 snprintf(instruction->text,
1173 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1182 static int nds32_parse_sbgp(struct nds32 *nds32, uint32_t opcode, uint32_t address,
1183 struct nds32_instruction *instruction)
1185 switch ((opcode >> 19) & 0x1) {
1186 case 0: /* SBI.gp */
1187 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1188 instruction->info.imm = (instruction->info.imm << 13) >> 13; /* sign-extend */
1189 instruction->type = NDS32_INSN_LOAD_STORE;
1190 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1191 instruction->access_start += instruction->info.imm;
1192 instruction->access_end = instruction->access_start + 1;
1193 snprintf(instruction->text,
1195 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1196 "\tSBI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1198 opcode, instruction->info.rt, instruction->info.imm);
1200 case 1: /* ADDI.gp */
1201 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1202 instruction->info.imm = (instruction->info.imm << 13) >> 13; /* sign-extend */
1203 instruction->type = NDS32_INSN_DATA_PROC;
1204 snprintf(instruction->text,
1206 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1207 "\tADDI.gp\t$r%" PRIu8 ",#%" PRId32 "",
1209 opcode, instruction->info.rt, instruction->info.imm);
1212 snprintf(instruction->text,
1214 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1223 static int nds32_parse_group_3_insn(struct nds32 *nds32, uint32_t opcode, uint32_t address,
1224 struct nds32_instruction *instruction)
1228 opc_6 = instruction->info.opc_6;
1230 switch (opc_6 & 0x7) {
1232 nds32_parse_mem(nds32, opcode, address, instruction);
1235 nds32_parse_lsmw(nds32, opcode, address, instruction);
1238 nds32_parse_hwgp(nds32, opcode, address, instruction);
1241 nds32_parse_sbgp(nds32, opcode, address, instruction);
1244 snprintf(instruction->text,
1246 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1255 static int nds32_parse_alu_1(uint32_t opcode, uint32_t address,
1256 struct nds32_instruction *instruction)
1258 switch (opcode & 0x1F) {
1260 nds32_parse_type_3(opcode, &(instruction->info.rt), &(instruction->info.ra),
1261 &(instruction->info.rb), &(instruction->info.imm));
1262 instruction->type = NDS32_INSN_DATA_PROC;
1263 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1264 if (instruction->info.imm)
1265 snprintf(instruction->text,
1267 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1268 "\tADD_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1270 opcode, instruction->info.rt, instruction->info.ra,
1271 instruction->info.rb,
1272 instruction->info.imm);
1274 snprintf(instruction->text,
1276 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1277 "\tADD\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1279 opcode, instruction->info.rt, instruction->info.ra,
1280 instruction->info.rb);
1283 nds32_parse_type_3(opcode, &(instruction->info.rt),
1284 &(instruction->info.ra),
1285 &(instruction->info.rb), &(instruction->info.imm));
1286 instruction->type = NDS32_INSN_DATA_PROC;
1287 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1288 if (instruction->info.imm)
1289 snprintf(instruction->text,
1291 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1292 "\tSUB_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1294 opcode, instruction->info.rt, instruction->info.ra,
1295 instruction->info.rb,
1296 instruction->info.imm);
1298 snprintf(instruction->text,
1300 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1301 "\tSUB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 "",
1303 opcode, instruction->info.rt, instruction->info.ra,
1304 instruction->info.rb);
1307 nds32_parse_type_3(opcode, &(instruction->info.rt),
1308 &(instruction->info.ra),
1309 &(instruction->info.rb), &(instruction->info.imm));
1310 instruction->type = NDS32_INSN_DATA_PROC;
1311 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1312 if (instruction->info.imm)
1313 snprintf(instruction->text,
1315 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1316 "\tAND_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1318 opcode, instruction->info.rt, instruction->info.ra,
1319 instruction->info.rb,
1320 instruction->info.imm);
1322 snprintf(instruction->text,
1324 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1325 "\tAND\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 "",
1327 opcode, instruction->info.rt, instruction->info.ra,
1328 instruction->info.rb);
1331 nds32_parse_type_3(opcode, &(instruction->info.rt),
1332 &(instruction->info.ra),
1333 &(instruction->info.rb), &(instruction->info.imm));
1334 instruction->type = NDS32_INSN_DATA_PROC;
1335 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1336 if (instruction->info.imm)
1337 snprintf(instruction->text,
1339 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1340 "\tXOR_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1342 opcode, instruction->info.rt, instruction->info.ra,
1343 instruction->info.rb,
1344 instruction->info.imm);
1346 snprintf(instruction->text,
1348 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1349 "\tXOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1351 opcode, instruction->info.rt, instruction->info.ra,
1352 instruction->info.rb);
1355 nds32_parse_type_3(opcode, &(instruction->info.rt),
1356 &(instruction->info.ra),
1357 &(instruction->info.rb), &(instruction->info.imm));
1358 instruction->type = NDS32_INSN_DATA_PROC;
1359 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1360 if (instruction->info.imm)
1361 snprintf(instruction->text,
1363 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1364 "\tOR_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1366 opcode, instruction->info.rt, instruction->info.ra,
1367 instruction->info.rb,
1368 instruction->info.imm);
1370 snprintf(instruction->text,
1372 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1373 "\tOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1375 opcode, instruction->info.rt, instruction->info.ra,
1376 instruction->info.rb);
1379 nds32_parse_type_3(opcode, &(instruction->info.rt),
1380 &(instruction->info.ra),
1381 &(instruction->info.rb), &(instruction->info.imm));
1382 instruction->type = NDS32_INSN_DATA_PROC;
1383 snprintf(instruction->text,
1385 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1386 "\tNOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1388 opcode, instruction->info.rt, instruction->info.ra,
1389 instruction->info.rb);
1392 nds32_parse_type_3(opcode, &(instruction->info.rt),
1393 &(instruction->info.ra),
1394 &(instruction->info.rb), &(instruction->info.imm));
1395 instruction->type = NDS32_INSN_DATA_PROC;
1396 snprintf(instruction->text,
1398 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1399 "\tSLT\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1401 opcode, instruction->info.rt, instruction->info.ra,
1402 instruction->info.rb);
1405 nds32_parse_type_3(opcode, &(instruction->info.rt),
1406 &(instruction->info.ra),
1407 &(instruction->info.rb), &(instruction->info.imm));
1408 instruction->type = NDS32_INSN_DATA_PROC;
1409 snprintf(instruction->text,
1411 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1412 "\tSLTS\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1414 opcode, instruction->info.rt, instruction->info.ra,
1415 instruction->info.rb);
1417 case 8: { /* SLLI */
1420 nds32_parse_type_3(opcode, &(instruction->info.rt),
1421 &(instruction->info.ra),
1423 instruction->info.imm = imm;
1424 instruction->type = NDS32_INSN_DATA_PROC;
1425 snprintf(instruction->text,
1427 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1428 "\tSLLI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1430 opcode, instruction->info.rt, instruction->info.ra,
1431 instruction->info.imm);
1434 case 9: { /* SRLI */
1437 nds32_parse_type_3(opcode, &(instruction->info.rt),
1438 &(instruction->info.ra),
1440 instruction->info.imm = imm;
1441 instruction->type = NDS32_INSN_DATA_PROC;
1442 snprintf(instruction->text,
1444 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1445 "\tSRLI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1447 opcode, instruction->info.rt, instruction->info.ra,
1448 instruction->info.imm);
1451 case 10: { /* SRAI */
1454 nds32_parse_type_3(opcode, &(instruction->info.rt),
1455 &(instruction->info.ra),
1457 instruction->info.imm = imm;
1458 instruction->type = NDS32_INSN_DATA_PROC;
1459 snprintf(instruction->text,
1461 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1462 "\tSRAI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1464 opcode, instruction->info.rt, instruction->info.ra,
1465 instruction->info.imm);
1468 case 11: { /* ROTRI */
1471 nds32_parse_type_3(opcode, &(instruction->info.rt),
1472 &(instruction->info.ra),
1474 instruction->info.imm = imm;
1475 instruction->type = NDS32_INSN_DATA_PROC;
1476 snprintf(instruction->text,
1478 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1479 "\tROTRI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1481 opcode, instruction->info.rt, instruction->info.ra,
1482 instruction->info.imm);
1485 case 12: { /* SLL */
1486 nds32_parse_type_3(opcode, &(instruction->info.rt),
1487 &(instruction->info.ra),
1488 &(instruction->info.rb), &(instruction->info.imm));
1489 instruction->type = NDS32_INSN_DATA_PROC;
1490 snprintf(instruction->text,
1492 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1493 "\tSLL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1495 opcode, instruction->info.rt, instruction->info.ra,
1496 instruction->info.rb);
1499 case 13: { /* SRL */
1500 nds32_parse_type_3(opcode, &(instruction->info.rt),
1501 &(instruction->info.ra),
1502 &(instruction->info.rb), &(instruction->info.imm));
1503 instruction->type = NDS32_INSN_DATA_PROC;
1504 snprintf(instruction->text,
1506 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1507 "\tSRL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1509 opcode, instruction->info.rt, instruction->info.ra,
1510 instruction->info.rb);
1513 case 14: { /* SRA */
1514 nds32_parse_type_3(opcode, &(instruction->info.rt),
1515 &(instruction->info.ra),
1516 &(instruction->info.rb), &(instruction->info.imm));
1517 instruction->type = NDS32_INSN_DATA_PROC;
1518 snprintf(instruction->text,
1520 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1521 "\tSRA\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1523 opcode, instruction->info.rt, instruction->info.ra,
1524 instruction->info.rb);
1527 case 15: { /* ROTR */
1528 nds32_parse_type_3(opcode, &(instruction->info.rt),
1529 &(instruction->info.ra),
1530 &(instruction->info.rb), &(instruction->info.imm));
1531 instruction->type = NDS32_INSN_DATA_PROC;
1532 snprintf(instruction->text,
1534 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1535 "\tROTR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1537 opcode, instruction->info.rt, instruction->info.ra,
1538 instruction->info.rb);
1541 case 16: { /* SEB */
1542 nds32_parse_type_2(opcode, &(instruction->info.rt),
1543 &(instruction->info.ra),
1544 &(instruction->info.imm));
1545 instruction->type = NDS32_INSN_DATA_PROC;
1546 snprintf(instruction->text,
1548 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1549 "\tSEB\t$r%" PRIu8 ",$r%" PRIu8,
1551 opcode, instruction->info.rt, instruction->info.ra);
1554 case 17: { /* SEH */
1555 nds32_parse_type_2(opcode, &(instruction->info.rt),
1556 &(instruction->info.ra),
1557 &(instruction->info.imm));
1558 instruction->type = NDS32_INSN_DATA_PROC;
1559 snprintf(instruction->text,
1561 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1562 "\tSEH\t$r%" PRIu8 ",$r%" PRIu8,
1564 opcode, instruction->info.rt, instruction->info.ra);
1568 nds32_parse_type_3(opcode, &(instruction->info.rt),
1569 &(instruction->info.ra),
1570 &(instruction->info.rb), &(instruction->info.imm));
1571 instruction->type = NDS32_INSN_DATA_PROC;
1572 snprintf(instruction->text,
1574 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1575 "\tBITC\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1577 opcode, instruction->info.rt, instruction->info.ra,
1578 instruction->info.rb);
1580 case 19: { /* ZEH */
1581 nds32_parse_type_2(opcode, &(instruction->info.rt),
1582 &(instruction->info.ra),
1583 &(instruction->info.imm));
1584 instruction->type = NDS32_INSN_DATA_PROC;
1585 snprintf(instruction->text,
1587 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1588 "\tZEH\t$r%" PRIu8 ",$r%" PRIu8,
1590 opcode, instruction->info.rt, instruction->info.ra);
1593 case 20: { /* WSBH */
1594 nds32_parse_type_2(opcode, &(instruction->info.rt),
1595 &(instruction->info.ra),
1596 &(instruction->info.imm));
1597 instruction->type = NDS32_INSN_DATA_PROC;
1598 snprintf(instruction->text,
1600 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1601 "\tWSBH\t$r%" PRIu8 ",$r%" PRIu8,
1603 opcode, instruction->info.rt, instruction->info.ra);
1606 case 21: /* OR_SRLI */
1607 nds32_parse_type_3(opcode, &(instruction->info.rt),
1608 &(instruction->info.ra),
1609 &(instruction->info.rb), &(instruction->info.imm));
1610 instruction->type = NDS32_INSN_DATA_PROC;
1611 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1612 if (instruction->info.imm)
1613 snprintf(instruction->text,
1615 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1616 "\tOR_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1618 opcode, instruction->info.rt, instruction->info.ra,
1619 instruction->info.rb,
1620 instruction->info.imm);
1622 snprintf(instruction->text,
1624 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1625 "\tOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1627 opcode, instruction->info.rt, instruction->info.ra,
1628 instruction->info.rb);
1630 case 22: { /* DIVSR */
1631 nds32_parse_type_4(opcode, &(instruction->info.rt),
1632 &(instruction->info.ra),
1633 &(instruction->info.rb), &(instruction->info.rd),
1634 &(instruction->info.sub_opc));
1635 instruction->type = NDS32_INSN_DATA_PROC;
1636 snprintf(instruction->text,
1638 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1639 "\tDIVSR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1641 opcode, instruction->info.rt, instruction->info.ra,
1642 instruction->info.rb,
1643 instruction->info.rd);
1646 case 23: { /* DIVR */
1647 nds32_parse_type_4(opcode, &(instruction->info.rt),
1648 &(instruction->info.ra),
1649 &(instruction->info.rb), &(instruction->info.rd),
1650 &(instruction->info.sub_opc));
1651 instruction->type = NDS32_INSN_DATA_PROC;
1652 snprintf(instruction->text,
1654 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1655 "\tDIVR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1657 opcode, instruction->info.rt, instruction->info.ra,
1658 instruction->info.rb,
1659 instruction->info.rd);
1662 case 24: { /* SVA */
1663 nds32_parse_type_3(opcode, &(instruction->info.rt),
1664 &(instruction->info.ra),
1665 &(instruction->info.rb), &(instruction->info.imm));
1666 instruction->type = NDS32_INSN_DATA_PROC;
1667 snprintf(instruction->text,
1669 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1670 "\tSVA\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1672 opcode, instruction->info.rt, instruction->info.ra,
1673 instruction->info.rb);
1676 case 25: { /* SVS */
1677 nds32_parse_type_3(opcode, &(instruction->info.rt),
1678 &(instruction->info.ra),
1679 &(instruction->info.rb), &(instruction->info.imm));
1680 instruction->type = NDS32_INSN_DATA_PROC;
1681 snprintf(instruction->text,
1683 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1684 "\tSVS\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1686 opcode, instruction->info.rt, instruction->info.ra,
1687 instruction->info.rb);
1690 case 26: { /* CMOVZ */
1691 nds32_parse_type_3(opcode, &(instruction->info.rt),
1692 &(instruction->info.ra),
1693 &(instruction->info.rb), &(instruction->info.imm));
1694 instruction->type = NDS32_INSN_MISC;
1695 snprintf(instruction->text,
1697 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1698 "\tCMOVZ\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1700 opcode, instruction->info.rt, instruction->info.ra,
1701 instruction->info.rb);
1704 case 27: { /* CMOVN */
1705 nds32_parse_type_3(opcode, &(instruction->info.rt),
1706 &(instruction->info.ra),
1707 &(instruction->info.rb), &(instruction->info.imm));
1708 instruction->type = NDS32_INSN_MISC;
1709 snprintf(instruction->text,
1711 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1712 "\tCMOVN\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1714 opcode, instruction->info.rt, instruction->info.ra,
1715 instruction->info.rb);
1718 case 28: /* ADD_SRLI */
1719 nds32_parse_type_3(opcode, &(instruction->info.rt),
1720 &(instruction->info.ra),
1721 &(instruction->info.rb), &(instruction->info.imm));
1722 instruction->type = NDS32_INSN_DATA_PROC;
1723 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1724 if (instruction->info.imm)
1725 snprintf(instruction->text,
1727 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1728 "\tADD_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1730 opcode, instruction->info.rt, instruction->info.ra,
1731 instruction->info.rb,
1732 instruction->info.imm);
1734 snprintf(instruction->text,
1736 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1737 "\tADD\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1739 opcode, instruction->info.rt, instruction->info.ra,
1740 instruction->info.rb);
1742 case 29: /* SUB_SRLI */
1743 nds32_parse_type_3(opcode, &(instruction->info.rt),
1744 &(instruction->info.ra),
1745 &(instruction->info.rb), &(instruction->info.imm));
1746 instruction->type = NDS32_INSN_DATA_PROC;
1747 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1748 if (instruction->info.imm)
1749 snprintf(instruction->text,
1751 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1752 "\tSUB_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1754 opcode, instruction->info.rt, instruction->info.ra,
1755 instruction->info.rb,
1756 instruction->info.imm);
1758 snprintf(instruction->text,
1760 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1761 "\tSUB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1763 opcode, instruction->info.rt, instruction->info.ra,
1764 instruction->info.rb);
1766 case 30: /* AND_SRLI */
1767 nds32_parse_type_3(opcode, &(instruction->info.rt),
1768 &(instruction->info.ra),
1769 &(instruction->info.rb), &(instruction->info.imm));
1770 instruction->type = NDS32_INSN_DATA_PROC;
1771 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1772 if (instruction->info.imm)
1773 snprintf(instruction->text,
1775 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1776 "\tAND_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1778 opcode, instruction->info.rt, instruction->info.ra,
1779 instruction->info.rb,
1780 instruction->info.imm);
1782 snprintf(instruction->text,
1784 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1785 "\tAND\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1787 opcode, instruction->info.rt, instruction->info.ra,
1788 instruction->info.rb);
1790 case 31: /* XOR_SRLI */
1791 nds32_parse_type_3(opcode, &(instruction->info.rt),
1792 &(instruction->info.ra),
1793 &(instruction->info.rb), &(instruction->info.imm));
1794 instruction->type = NDS32_INSN_DATA_PROC;
1795 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1796 if (instruction->info.imm)
1797 snprintf(instruction->text,
1799 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1800 "\tXOR_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1802 opcode, instruction->info.rt, instruction->info.ra,
1803 instruction->info.rb,
1804 instruction->info.imm);
1806 snprintf(instruction->text,
1808 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1809 "\tXOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1811 opcode, instruction->info.rt, instruction->info.ra,
1812 instruction->info.rb);
1815 snprintf(instruction->text,
1817 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1826 static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
1827 struct nds32_instruction *instruction)
1829 switch (opcode & 0x3F) {
1831 nds32_parse_type_3(opcode, &(instruction->info.rt),
1832 &(instruction->info.ra),
1833 &(instruction->info.rb), &(instruction->info.imm));
1834 instruction->type = NDS32_INSN_DATA_PROC;
1835 snprintf(instruction->text,
1837 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1838 "\tMAX\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1840 opcode, instruction->info.rt, instruction->info.ra,
1841 instruction->info.rb);
1844 nds32_parse_type_3(opcode, &(instruction->info.rt),
1845 &(instruction->info.ra),
1846 &(instruction->info.rb), &(instruction->info.imm));
1847 instruction->type = NDS32_INSN_DATA_PROC;
1848 snprintf(instruction->text,
1850 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1851 "\tMIN\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1853 opcode, instruction->info.rt, instruction->info.ra,
1854 instruction->info.rb);
1857 nds32_parse_type_3(opcode, &(instruction->info.rt),
1858 &(instruction->info.ra),
1859 &(instruction->info.rb), &(instruction->info.imm));
1860 instruction->type = NDS32_INSN_DATA_PROC;
1861 snprintf(instruction->text,
1863 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1864 "\tAVE\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1866 opcode, instruction->info.rt, instruction->info.ra,
1867 instruction->info.rb);
1870 nds32_parse_type_2(opcode, &(instruction->info.rt),
1871 &(instruction->info.ra),
1872 &(instruction->info.imm));
1873 instruction->type = NDS32_INSN_DATA_PROC;
1874 snprintf(instruction->text,
1876 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1877 "\tAVE\t$r%" PRIu8 ",$r%" PRIu8,
1879 opcode, instruction->info.rt, instruction->info.ra);
1881 case 4: { /* CLIPS */
1883 nds32_parse_type_3(opcode, &(instruction->info.rt),
1884 &(instruction->info.ra),
1885 &imm, &(instruction->info.imm));
1886 instruction->info.imm = imm;
1887 instruction->type = NDS32_INSN_DATA_PROC;
1888 snprintf(instruction->text,
1890 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1891 "\tCLIPS\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1893 opcode, instruction->info.rt, instruction->info.ra,
1894 instruction->info.imm);
1897 case 5: { /* CLIP */
1899 nds32_parse_type_3(opcode, &(instruction->info.rt),
1900 &(instruction->info.ra),
1901 &imm, &(instruction->info.imm));
1902 instruction->info.imm = imm;
1903 instruction->type = NDS32_INSN_DATA_PROC;
1904 snprintf(instruction->text,
1906 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1907 "\tCLIP\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1909 opcode, instruction->info.rt, instruction->info.ra,
1910 instruction->info.imm);
1914 nds32_parse_type_2(opcode, &(instruction->info.rt),
1915 &(instruction->info.ra),
1916 &(instruction->info.imm));
1917 instruction->type = NDS32_INSN_DATA_PROC;
1918 snprintf(instruction->text,
1920 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1921 "\tCLO\t$r%" PRIu8 ",$r%" PRIu8,
1923 opcode, instruction->info.rt, instruction->info.ra);
1926 nds32_parse_type_2(opcode, &(instruction->info.rt),
1927 &(instruction->info.ra),
1928 &(instruction->info.imm));
1929 instruction->type = NDS32_INSN_DATA_PROC;
1930 snprintf(instruction->text,
1932 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1933 "\tCLZ\t$r%" PRIu8 ",$r%" PRIu8,
1935 opcode, instruction->info.rt, instruction->info.ra);
1937 case 8: { /* BSET */
1939 nds32_parse_type_3(opcode, &(instruction->info.rt),
1940 &(instruction->info.ra),
1941 &imm, &(instruction->info.imm));
1942 instruction->info.imm = imm;
1943 instruction->type = NDS32_INSN_DATA_PROC;
1944 snprintf(instruction->text,
1946 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1947 "\tBSET\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1949 opcode, instruction->info.rt, instruction->info.ra,
1950 instruction->info.imm);
1953 case 9: { /* BCLR */
1955 nds32_parse_type_3(opcode, &(instruction->info.rt),
1956 &(instruction->info.ra),
1957 &imm, &(instruction->info.imm));
1958 instruction->info.imm = imm;
1959 instruction->type = NDS32_INSN_DATA_PROC;
1960 snprintf(instruction->text,
1962 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1963 "\tBCLR\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1965 opcode, instruction->info.rt, instruction->info.ra,
1966 instruction->info.imm);
1969 case 10: { /* BTGL */
1971 nds32_parse_type_3(opcode, &(instruction->info.rt),
1972 &(instruction->info.ra),
1973 &imm, &(instruction->info.imm));
1974 instruction->info.imm = imm;
1975 instruction->type = NDS32_INSN_DATA_PROC;
1976 snprintf(instruction->text,
1978 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1979 "\tBTGL\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1981 opcode, instruction->info.rt, instruction->info.ra,
1982 instruction->info.imm);
1985 case 11: { /* BTST */
1987 nds32_parse_type_3(opcode, &(instruction->info.rt),
1988 &(instruction->info.ra),
1989 &imm, &(instruction->info.imm));
1990 instruction->info.imm = imm;
1991 instruction->type = NDS32_INSN_DATA_PROC;
1992 snprintf(instruction->text,
1994 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1995 "\tBTST\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1997 opcode, instruction->info.rt, instruction->info.ra,
1998 instruction->info.imm);
2002 nds32_parse_type_3(opcode, &(instruction->info.rt),
2003 &(instruction->info.ra),
2004 &(instruction->info.rb), &(instruction->info.imm));
2005 instruction->type = NDS32_INSN_DATA_PROC;
2006 snprintf(instruction->text,
2008 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2009 "\tBSE\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2011 opcode, instruction->info.rt, instruction->info.ra,
2012 instruction->info.rb);
2015 nds32_parse_type_3(opcode, &(instruction->info.rt),
2016 &(instruction->info.ra),
2017 &(instruction->info.rb), &(instruction->info.imm));
2018 instruction->type = NDS32_INSN_DATA_PROC;
2019 snprintf(instruction->text,
2021 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2022 "\tBSP\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2024 opcode, instruction->info.rt, instruction->info.ra,
2025 instruction->info.rb);
2028 nds32_parse_type_3(opcode, &(instruction->info.rt),
2029 &(instruction->info.ra),
2030 &(instruction->info.rb), &(instruction->info.imm));
2031 instruction->type = NDS32_INSN_DATA_PROC;
2032 snprintf(instruction->text,
2034 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2035 "\tFFB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2037 opcode, instruction->info.rt, instruction->info.ra,
2038 instruction->info.rb);
2040 case 15: /* FFMISM */
2041 nds32_parse_type_3(opcode, &(instruction->info.rt),
2042 &(instruction->info.ra),
2043 &(instruction->info.rb), &(instruction->info.imm));
2044 instruction->type = NDS32_INSN_DATA_PROC;
2045 snprintf(instruction->text,
2047 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2048 "\tFFMISM\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2050 opcode, instruction->info.rt, instruction->info.ra,
2051 instruction->info.rb);
2053 case 23: /* FFZMISM */
2054 nds32_parse_type_3(opcode, &(instruction->info.rt),
2055 &(instruction->info.ra),
2056 &(instruction->info.rb), &(instruction->info.imm));
2057 instruction->type = NDS32_INSN_DATA_PROC;
2058 snprintf(instruction->text,
2060 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2061 "\tFFZMISM\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2063 opcode, instruction->info.rt, instruction->info.ra,
2064 instruction->info.rb);
2066 case 32: /* MFUSR */
2067 nds32_parse_type_1(opcode, &(instruction->info.rt),
2068 &(instruction->info.imm));
2069 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2070 snprintf(instruction->text,
2072 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2073 "\tMFUSR\t$r%" PRIu8 ",#%" PRId32,
2075 opcode, instruction->info.rt,
2076 (instruction->info.imm >> 10) & 0x3FF);
2078 case 33: /* MTUSR */
2079 nds32_parse_type_1(opcode, &(instruction->info.rt),
2080 &(instruction->info.imm));
2081 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2082 snprintf(instruction->text,
2084 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2085 "\tMTUSR\t$r%" PRIu8 ",#%" PRId32,
2087 opcode, instruction->info.rt,
2088 (instruction->info.imm >> 10) & 0x3FF);
2091 nds32_parse_type_3(opcode, &(instruction->info.rt),
2092 &(instruction->info.ra),
2093 &(instruction->info.rb), &(instruction->info.imm));
2094 instruction->type = NDS32_INSN_DATA_PROC;
2095 snprintf(instruction->text,
2097 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2098 "\tMUL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2100 opcode, instruction->info.rt, instruction->info.ra,
2101 instruction->info.rb);
2103 case 40: { /* MULTS64 */
2105 nds32_parse_type_3(opcode, &dt_val,
2106 &(instruction->info.ra),
2107 &(instruction->info.rb), &(instruction->info.imm));
2108 instruction->type = NDS32_INSN_DATA_PROC;
2109 snprintf(instruction->text,
2111 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2112 "\tMULTS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2114 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2115 instruction->info.rb);
2118 case 41: { /* MULT64 */
2120 nds32_parse_type_3(opcode, &dt_val,
2121 &(instruction->info.ra),
2122 &(instruction->info.rb), &(instruction->info.imm));
2123 instruction->type = NDS32_INSN_DATA_PROC;
2124 snprintf(instruction->text,
2126 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2127 "\tMULT64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2129 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2130 instruction->info.rb);
2133 case 42: { /* MADDS64 */
2135 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2136 &(instruction->info.rb), &(instruction->info.imm));
2137 instruction->type = NDS32_INSN_DATA_PROC;
2138 snprintf(instruction->text,
2140 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2141 "\tMADDS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2143 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2144 instruction->info.rb);
2147 case 43: { /* MADD64 */
2149 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2150 &(instruction->info.rb), &(instruction->info.imm));
2151 instruction->type = NDS32_INSN_DATA_PROC;
2152 snprintf(instruction->text,
2154 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2155 "\tMADD64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2157 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2158 instruction->info.rb);
2161 case 44: { /* MSUBS64 */
2163 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2164 &(instruction->info.rb), &(instruction->info.imm));
2165 instruction->type = NDS32_INSN_DATA_PROC;
2166 snprintf(instruction->text,
2168 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2169 "\tMSUBS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2171 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2172 instruction->info.rb);
2175 case 45: { /* MSUB64 */
2177 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2178 &(instruction->info.rb), &(instruction->info.imm));
2179 instruction->type = NDS32_INSN_DATA_PROC;
2180 snprintf(instruction->text,
2182 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2183 "\tMSUB64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2185 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2186 instruction->info.rb);
2189 case 46: { /* DIVS */
2191 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2192 &(instruction->info.rb), &(instruction->info.imm));
2193 instruction->type = NDS32_INSN_DATA_PROC;
2194 snprintf(instruction->text,
2196 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2197 "\tDIVS\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2199 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2200 instruction->info.rb);
2203 case 47: { /* DIV */
2205 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2206 &(instruction->info.rb), &(instruction->info.imm));
2207 instruction->type = NDS32_INSN_DATA_PROC;
2208 snprintf(instruction->text,
2210 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2211 "\tDIV\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2213 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2214 instruction->info.rb);
2217 case 49: { /* MULT32 */
2219 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2220 &(instruction->info.rb), &(instruction->info.imm));
2221 instruction->type = NDS32_INSN_DATA_PROC;
2222 snprintf(instruction->text,
2224 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2225 "\tMULT32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2227 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2228 instruction->info.rb);
2231 case 51: { /* MADD32 */
2233 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2234 &(instruction->info.rb), &(instruction->info.imm));
2235 instruction->type = NDS32_INSN_DATA_PROC;
2236 snprintf(instruction->text,
2238 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2239 "\tMADD32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2241 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2242 instruction->info.rb);
2245 case 53: { /* MSUB32 */
2247 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2248 &(instruction->info.rb), &(instruction->info.imm));
2249 instruction->type = NDS32_INSN_DATA_PROC;
2250 snprintf(instruction->text,
2252 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2253 "\tMSUB32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2255 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2256 instruction->info.rb);
2260 snprintf(instruction->text,
2262 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2271 static int nds32_parse_group_4_insn(struct nds32 *nds32, uint32_t opcode,
2272 uint32_t address, struct nds32_instruction *instruction)
2276 opc_6 = instruction->info.opc_6;
2278 switch (opc_6 & 0x7) {
2280 nds32_parse_alu_1(opcode, address, instruction);
2283 nds32_parse_alu_2(opcode, address, instruction);
2286 nds32_parse_type_1(opcode, &(instruction->info.rt),
2287 &(instruction->info.imm));
2289 instruction->info.imm = (instruction->info.imm << 12) >> 12;
2290 instruction->type = NDS32_INSN_DATA_PROC;
2291 snprintf(instruction->text,
2293 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2294 "\tMOVI\t$r%" PRIu8 ",#%" PRId32,
2296 opcode, instruction->info.rt, instruction->info.imm);
2299 nds32_parse_type_1(opcode, &(instruction->info.rt),
2300 &(instruction->info.imm));
2301 instruction->type = NDS32_INSN_DATA_PROC;
2302 snprintf(instruction->text,
2304 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2305 "\tSETHI\t$r%" PRIu8 ",0x%8.8" PRIx32,
2307 opcode, instruction->info.rt, instruction->info.imm);
2310 nds32_parse_type_0(opcode, &(instruction->info.imm));
2312 instruction->info.imm = (instruction->info.imm << 8) >> 8;
2313 instruction->type = NDS32_INSN_JUMP_BRANCH;
2314 if ((instruction->info.imm >> 24) & 0x1) { /* JAL */
2315 snprintf(instruction->text,
2317 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2320 opcode, instruction->info.imm);
2322 snprintf(instruction->text,
2324 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2327 opcode, instruction->info.imm);
2330 case 5: { /* JREG */
2332 nds32_parse_type_0(opcode, &imm);
2333 instruction->info.rb = (imm >> 10) & 0x1F;
2334 instruction->type = NDS32_INSN_JUMP_BRANCH;
2335 switch (imm & 0x1F) {
2338 if (imm & 0x20) { /* RET */
2339 snprintf(instruction->text,
2341 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2344 opcode, instruction->info.rb);
2346 snprintf(instruction->text,
2348 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2351 opcode, instruction->info.rb);
2355 instruction->info.rt = (imm >> 20) & 0x1F;
2356 snprintf(instruction->text,
2358 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2359 "\tJRAL\t$r%" PRIu8 ",$r%" PRIu8,
2361 opcode, instruction->info.rt, instruction->info.rb);
2364 snprintf(instruction->text,
2366 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2367 "\tJRNEZ\t$r%" PRIu8,
2369 opcode, instruction->info.rb);
2371 case 3: /* JRALNEZ */
2372 instruction->info.rt = (imm >> 20) & 0x1F;
2373 if (instruction->info.rt == R30)
2374 snprintf(instruction->text,
2376 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2377 "\tJRALNEZ\t$r%" PRIu8,
2379 opcode, instruction->info.rb);
2381 snprintf(instruction->text,
2383 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2384 "\tJRALNEZ\t$r%" PRIu8 ",$r%" PRIu8,
2387 instruction->info.rt,
2388 instruction->info.rb);
2396 nds32_parse_type_0(opcode, &imm);
2397 instruction->type = NDS32_INSN_JUMP_BRANCH;
2398 if ((imm >> 14) & 0x1) { /* BNE */
2399 nds32_parse_type_2(opcode, &(instruction->info.rt),
2400 &(instruction->info.ra), &(instruction->info.imm));
2402 instruction->info.imm = (instruction->info.imm << 18) >> 18;
2403 snprintf(instruction->text,
2405 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2406 "\tBNE\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2408 opcode, instruction->info.rt, instruction->info.ra,
2409 instruction->info.imm);
2411 nds32_parse_type_2(opcode, &(instruction->info.rt),
2412 &(instruction->info.ra), &(instruction->info.imm));
2414 instruction->info.imm = (instruction->info.imm << 18) >> 18;
2415 snprintf(instruction->text,
2417 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2418 "\tBEQ\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2420 opcode, instruction->info.rt,
2421 instruction->info.ra,
2422 instruction->info.imm);
2429 nds32_parse_type_0(opcode, &imm);
2430 instruction->type = NDS32_INSN_JUMP_BRANCH;
2431 switch ((imm >> 16) & 0xF) {
2433 nds32_parse_type_1(opcode, &(instruction->info.rt),
2434 &(instruction->info.imm));
2435 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2436 snprintf(instruction->text,
2438 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2439 "\tBEQZ\t$r%" PRIu8 ",#%" PRId32,
2441 opcode, instruction->info.rt, instruction->info.imm);
2444 nds32_parse_type_1(opcode, &(instruction->info.rt),
2445 &(instruction->info.imm));
2446 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2447 snprintf(instruction->text,
2449 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2450 "\tBNEZ\t$r%" PRIu8 ",#%" PRId32,
2452 opcode, instruction->info.rt, instruction->info.imm);
2455 nds32_parse_type_1(opcode, &(instruction->info.rt),
2456 &(instruction->info.imm));
2457 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2458 snprintf(instruction->text,
2460 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2461 "\tBGEZ\t$r%" PRIu8 ",#%" PRId32,
2463 opcode, instruction->info.rt, instruction->info.imm);
2466 nds32_parse_type_1(opcode, &(instruction->info.rt),
2467 &(instruction->info.imm));
2468 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2469 snprintf(instruction->text,
2471 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2472 "\tBLTZ\t$r%" PRIu8 ",#%" PRId32,
2474 opcode, instruction->info.rt, instruction->info.imm);
2477 nds32_parse_type_1(opcode, &(instruction->info.rt),
2478 &(instruction->info.imm));
2479 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2480 snprintf(instruction->text,
2482 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2483 "\tBGTZ\t$r%" PRIu8 ",#%" PRId32,
2485 opcode, instruction->info.rt, instruction->info.imm);
2488 nds32_parse_type_1(opcode, &(instruction->info.rt),
2489 &(instruction->info.imm));
2490 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2491 snprintf(instruction->text,
2493 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2494 "\tBLEZ\t$r%" PRIu8 ",#%" PRId32,
2496 opcode, instruction->info.rt, instruction->info.imm);
2498 case 12: /* BGEZAL */
2499 nds32_parse_type_1(opcode, &(instruction->info.rt),
2500 &(instruction->info.imm));
2501 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2502 snprintf(instruction->text,
2504 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2505 "\tBGEZAL\t$r%" PRIu8 ",#%" PRId32,
2507 opcode, instruction->info.rt, instruction->info.imm);
2509 case 13: /* BLTZAL */
2510 nds32_parse_type_1(opcode, &(instruction->info.rt),
2511 &(instruction->info.imm));
2512 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2513 snprintf(instruction->text,
2515 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2516 "\tBLTZAL\t$r%" PRIu8 ",#%" PRId32,
2518 opcode, instruction->info.rt, instruction->info.imm);
2524 snprintf(instruction->text,
2526 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2535 static int nds32_parse_group_5_insn(struct nds32 *nds32, uint32_t opcode,
2536 uint32_t address, struct nds32_instruction *instruction)
2540 opc_6 = instruction->info.opc_6;
2542 switch (opc_6 & 0x7) {
2544 nds32_parse_type_2(opcode, &(instruction->info.rt),
2545 &(instruction->info.ra), &(instruction->info.imm));
2546 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2547 instruction->type = NDS32_INSN_DATA_PROC;
2548 snprintf(instruction->text,
2550 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2551 "\tADDI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2553 opcode, instruction->info.rt, instruction->info.ra,
2554 instruction->info.imm);
2557 nds32_parse_type_2(opcode, &(instruction->info.rt),
2558 &(instruction->info.ra), &(instruction->info.imm));
2559 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2560 instruction->type = NDS32_INSN_DATA_PROC;
2561 snprintf(instruction->text,
2563 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2564 "\tSUBRI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2566 opcode, instruction->info.rt, instruction->info.ra,
2567 instruction->info.imm);
2570 nds32_parse_type_2(opcode, &(instruction->info.rt),
2571 &(instruction->info.ra), &(instruction->info.imm));
2572 instruction->type = NDS32_INSN_DATA_PROC;
2573 snprintf(instruction->text,
2575 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2576 "\tANDI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2578 opcode, instruction->info.rt, instruction->info.ra,
2579 instruction->info.imm);
2582 nds32_parse_type_2(opcode, &(instruction->info.rt),
2583 &(instruction->info.ra), &(instruction->info.imm));
2584 instruction->type = NDS32_INSN_DATA_PROC;
2585 snprintf(instruction->text,
2587 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2588 "\tXORI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2590 opcode, instruction->info.rt, instruction->info.ra,
2591 instruction->info.imm);
2594 nds32_parse_type_2(opcode, &(instruction->info.rt),
2595 &(instruction->info.ra), &(instruction->info.imm));
2596 instruction->type = NDS32_INSN_DATA_PROC;
2597 snprintf(instruction->text,
2599 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2600 "\tORI\t$r%" PRIu8 ",$r%" PRIu8 ",0x%8.8" PRIx32,
2602 opcode, instruction->info.rt, instruction->info.ra,
2603 instruction->info.imm);
2606 nds32_parse_type_2(opcode, &(instruction->info.rt),
2607 &(instruction->info.ra), &(instruction->info.imm));
2608 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2609 instruction->type = NDS32_INSN_DATA_PROC;
2610 snprintf(instruction->text,
2612 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2613 "\tSLTI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2615 opcode, instruction->info.rt, instruction->info.ra,
2616 instruction->info.imm);
2619 nds32_parse_type_2(opcode, &(instruction->info.rt),
2620 &(instruction->info.ra), &(instruction->info.imm));
2621 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2622 instruction->type = NDS32_INSN_DATA_PROC;
2623 snprintf(instruction->text,
2625 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2626 "\tSLTSI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2628 opcode, instruction->info.rt, instruction->info.ra,
2629 instruction->info.imm);
2632 snprintf(instruction->text,
2634 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2643 static int nds32_parse_group_6_insn(struct nds32 *nds32, uint32_t opcode,
2644 uint32_t address, struct nds32_instruction *instruction)
2648 opc_6 = instruction->info.opc_6;
2650 switch (opc_6 & 0x7) {
2651 case 2: { /* MISC */
2655 nds32_parse_type_0(opcode, &imm);
2657 sub_opc = imm & 0x1F;
2659 case 0: /* STANDBY */
2660 instruction->type = NDS32_INSN_MISC;
2661 snprintf(instruction->text,
2663 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2664 "\tSTANDBY\t#%" PRIu32,
2666 opcode, (opcode >> 5) & 0x3);
2670 nds32_parse_type_2(opcode, &(instruction->info.rt),
2671 &(instruction->info.ra), &(instruction->info.imm));
2672 instruction->type = NDS32_INSN_MISC;
2673 snprintf(instruction->text,
2675 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCCTL",
2680 nds32_parse_type_1(opcode, &(instruction->info.rt),
2681 &(instruction->info.imm));
2682 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2683 snprintf(instruction->text,
2685 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2686 "\tMFSR\t$r%" PRIu8 ",#%" PRId32,
2688 opcode, instruction->info.rt,
2689 (instruction->info.imm >> 10) & 0x3FF);
2692 nds32_parse_type_1(opcode, &(instruction->info.ra),
2693 &(instruction->info.imm));
2694 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2695 snprintf(instruction->text,
2697 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2698 "\tMTSR\t$r%" PRIu8 ",#%" PRId32,
2700 opcode, instruction->info.ra,
2701 (instruction->info.imm >> 10) & 0x3FF);
2704 instruction->type = NDS32_INSN_MISC;
2705 snprintf(instruction->text,
2707 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tIRET",
2712 instruction->type = NDS32_INSN_MISC;
2713 snprintf(instruction->text,
2715 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2716 "\tTRAP\t#%" PRId32,
2718 opcode, (imm >> 5) & 0x7FFF);
2721 nds32_parse_type_1(opcode, &(instruction->info.ra),
2722 &(instruction->info.imm));
2723 instruction->type = NDS32_INSN_MISC;
2724 snprintf(instruction->text,
2726 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2727 "\tTEQZ\t$r%" PRIu8 ",#%" PRId32,
2729 opcode, instruction->info.ra,
2730 (instruction->info.imm >> 5) & 0x7FFF);
2733 nds32_parse_type_1(opcode, &(instruction->info.ra),
2734 &(instruction->info.imm));
2735 instruction->type = NDS32_INSN_MISC;
2736 snprintf(instruction->text,
2738 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2739 "\tTNEZ\t$r%" PRIu8 ",#%" PRId32,
2741 opcode, instruction->info.ra,
2742 (instruction->info.imm >> 5) & 0x7FFF);
2745 instruction->type = NDS32_INSN_MISC;
2746 snprintf(instruction->text,
2748 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tDSB",
2753 instruction->type = NDS32_INSN_MISC;
2754 snprintf(instruction->text,
2756 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tISB",
2760 case 10: /* BREAK */
2761 instruction->type = NDS32_INSN_MISC;
2762 instruction->info.sub_opc = imm & 0x1F;
2763 instruction->info.imm = (imm >> 5) & 0x7FFF;
2764 snprintf(instruction->text,
2766 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2767 "\tBREAK\t#%" PRId32,
2769 opcode, instruction->info.imm);
2771 case 11: /* SYSCALL */
2772 instruction->type = NDS32_INSN_MISC;
2773 snprintf(instruction->text,
2775 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2776 "\tSYSCALL\t#%" PRId32,
2778 opcode, (imm >> 5) & 0x7FFF);
2780 case 12: /* MSYNC */
2781 instruction->type = NDS32_INSN_MISC;
2782 snprintf(instruction->text,
2784 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2785 "\tMSYNC\t#%" PRId32,
2787 opcode, (imm >> 5) & 0x7);
2789 case 13: /* ISYNC */
2790 nds32_parse_type_1(opcode, &(instruction->info.ra),
2791 &(instruction->info.imm));
2792 instruction->type = NDS32_INSN_MISC;
2793 snprintf(instruction->text,
2795 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2796 "\tISYNC\t$r%" PRIu8,
2798 opcode, instruction->info.ra);
2800 case 14: /* TLBOP */
2802 nds32_parse_type_2(opcode, &(instruction->info.rt),
2803 &(instruction->info.ra), &(instruction->info.imm));
2804 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2805 snprintf(instruction->text,
2807 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tTLBOP",
2816 snprintf(instruction->text,
2818 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2827 static uint32_t field_mask[9] = {
2839 static uint8_t nds32_extract_field_8u(uint16_t opcode, uint32_t start, uint32_t length)
2841 if (length > 0 && length < 9)
2842 return (opcode >> start) & field_mask[length];
2847 static int nds32_parse_group_0_insn_16(struct nds32 *nds32, uint16_t opcode,
2848 uint32_t address, struct nds32_instruction *instruction)
2850 switch ((opcode >> 10) & 0x7) {
2852 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 5);
2853 instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5);
2854 instruction->type = NDS32_INSN_MISC;
2855 snprintf(instruction->text,
2857 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2858 "\t\tMOV55\t$r%" PRIu8 ",$r%" PRIu8,
2860 opcode, instruction->info.rt, instruction->info.ra);
2862 case 1: /* MOVI55 */
2863 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 5);
2864 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
2865 instruction->info.imm = (instruction->info.imm << 27) >> 27;
2866 instruction->type = NDS32_INSN_MISC;
2867 snprintf(instruction->text,
2869 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2870 "\t\tMOVI55\t$r%" PRIu8 ",#%" PRId32,
2872 opcode, instruction->info.rt, instruction->info.imm);
2874 case 2: /* ADD45, SUB45 */
2875 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
2876 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
2877 instruction->type = NDS32_INSN_DATA_PROC;
2878 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADD45 */
2879 snprintf(instruction->text,
2881 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2882 "\t\tADD45\t$r%" PRIu8 ",$r%" PRIu8,
2884 opcode, instruction->info.rt, instruction->info.rb);
2885 } else { /* SUB45 */
2886 snprintf(instruction->text,
2888 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2889 "\t\tSUB45\t$r%" PRIu8 ",$r%" PRIu8,
2891 opcode, instruction->info.rt, instruction->info.rb);
2895 case 3: /* ADDI45, SUBI45 */
2896 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
2897 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
2898 instruction->type = NDS32_INSN_DATA_PROC;
2899 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADDI45 */
2900 snprintf(instruction->text,
2902 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2903 "\t\tADDI45\t$r%" PRIu8 ",#%" PRId32,
2905 opcode, instruction->info.rt, instruction->info.imm);
2906 } else { /* SUBI45 */
2907 snprintf(instruction->text,
2909 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2910 "\t\tSUBI45\t$r%" PRIu8 ",#%" PRId32,
2912 opcode, instruction->info.rt, instruction->info.imm);
2915 case 4: /* SRAI45, SRLI45 */
2916 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
2917 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
2918 instruction->type = NDS32_INSN_DATA_PROC;
2919 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* SRAI45 */
2920 snprintf(instruction->text,
2922 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2923 "\t\tSRAI45\t$r%" PRIu8 ",#%" PRId32,
2925 opcode, instruction->info.rt, instruction->info.imm);
2926 } else { /* SRLI45 */
2927 if ((instruction->info.rt == 0) && (instruction->info.imm == 0)) {
2928 snprintf(instruction->text,
2930 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 "\t\tNOP",
2934 snprintf(instruction->text,
2936 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2937 "\t\tSRLI45\t$r%" PRIu8 ",#%" PRId32,
2939 opcode, instruction->info.rt, instruction->info.imm);
2944 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
2945 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
2946 instruction->type = NDS32_INSN_DATA_PROC;
2947 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* SLLI333 */
2948 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
2949 snprintf(instruction->text,
2951 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2952 "\t\tSLLI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2954 opcode, instruction->info.rt, instruction->info.ra,
2955 instruction->info.imm);
2957 instruction->info.sub_opc = nds32_extract_field_8u(opcode, 0, 3);
2958 switch (instruction->info.sub_opc) {
2960 snprintf(instruction->text,
2962 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2963 "\t\tZEB33\t$r%" PRIu8 ",$r%" PRIu8,
2965 opcode, instruction->info.rt, instruction->info.ra);
2968 snprintf(instruction->text,
2970 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2971 "\t\tZEH33\t$r%" PRIu8 ",$r%" PRIu8,
2973 opcode, instruction->info.rt, instruction->info.ra);
2976 snprintf(instruction->text,
2978 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2979 "\t\tSEB33\t$r%" PRIu8 ",$r%" PRIu8,
2981 opcode, instruction->info.rt, instruction->info.ra);
2984 snprintf(instruction->text,
2986 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2987 "\t\tSEH33\t$r%" PRIu8 ",$r%" PRIu8,
2989 opcode, instruction->info.rt, instruction->info.ra);
2991 case 4: /* XLSB33 */
2992 snprintf(instruction->text,
2994 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2995 "\t\tXLSB33\t$r%" PRIu8 ",$r%" PRIu8,
2997 opcode, instruction->info.rt, instruction->info.ra);
2999 case 5: /* XLLB33 */
3000 snprintf(instruction->text,
3002 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3003 "\t\tXLLB33\t$r%" PRIu8 ",$r%" PRIu8,
3005 opcode, instruction->info.rt, instruction->info.ra);
3007 case 6: /* BMSKI33 */
3008 instruction->info.ra = 0;
3009 instruction->info.imm = nds32_extract_field_8u(opcode, 3, 3);
3010 snprintf(instruction->text,
3012 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3013 "\t\tBMSKI33\t$r%" PRIu8 ",$r%" PRId32,
3015 opcode, instruction->info.rt, instruction->info.imm);
3017 case 7: /* FEXTI33 */
3018 instruction->info.ra = 0;
3019 instruction->info.imm = nds32_extract_field_8u(opcode, 3, 3);
3020 snprintf(instruction->text,
3022 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3023 "\t\tFEXTI33\t$r%" PRIu8 ",$r%" PRId32,
3025 opcode, instruction->info.rt, instruction->info.imm);
3028 snprintf(instruction->text,
3030 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16
3031 "\tUNDEFINED INSTRUCTION",
3038 case 6: /* ADD333, SUB333 */
3039 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3040 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3041 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 3);
3042 instruction->type = NDS32_INSN_DATA_PROC;
3043 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADD333 */
3044 snprintf(instruction->text,
3046 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3047 "\t\tADD333\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
3049 opcode, instruction->info.rt, instruction->info.ra,
3050 instruction->info.rb);
3051 } else { /* SUB333 */
3052 snprintf(instruction->text,
3054 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3055 "\t\tSUB333\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
3057 opcode, instruction->info.rt, instruction->info.ra,
3058 instruction->info.rb);
3061 case 7: /* ADDI333, SUBI333 */
3062 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3063 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3064 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3065 instruction->type = NDS32_INSN_DATA_PROC;
3066 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADDI333 */
3067 snprintf(instruction->text,
3069 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3070 "\t\tADDI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
3072 opcode, instruction->info.rt, instruction->info.ra,
3073 instruction->info.imm);
3074 } else { /* SUBI333 */
3075 snprintf(instruction->text,
3077 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3078 "\t\tSUBI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
3080 opcode, instruction->info.rt, instruction->info.ra,
3081 instruction->info.imm);
3085 snprintf(instruction->text,
3087 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION",
3096 static int nds32_parse_group_1_insn_16(struct nds32 *nds32, uint16_t opcode,
3097 uint32_t address, struct nds32_instruction *instruction)
3099 switch ((opcode >> 9) & 0xF) {
3100 case 0: /* LWI333 */
3101 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3102 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3103 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2;
3104 instruction->type = NDS32_INSN_LOAD_STORE;
3105 nds32_get_mapped_reg(nds32, instruction->info.ra,
3106 &(instruction->access_start));
3107 instruction->access_start += instruction->info.imm;
3108 instruction->access_end = instruction->access_start + 4;
3109 snprintf(instruction->text,
3111 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3112 "\t\tLWI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3114 opcode, instruction->info.rt, instruction->info.ra,
3115 instruction->info.imm);
3117 case 1: /* LWI333.BI */
3118 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3119 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3120 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3121 instruction->type = NDS32_INSN_LOAD_STORE;
3122 nds32_get_mapped_reg(nds32, instruction->info.ra,
3123 &(instruction->access_start));
3124 instruction->access_end = instruction->access_start + 4;
3125 snprintf(instruction->text,
3127 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3128 "\t\tLWI333.BI\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
3130 opcode, instruction->info.rt, instruction->info.ra,
3131 instruction->info.imm << 2);
3133 case 2: /* LHI333 */
3134 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3135 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3136 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 1;
3137 instruction->type = NDS32_INSN_LOAD_STORE;
3138 nds32_get_mapped_reg(nds32, instruction->info.ra,
3139 &(instruction->access_start));
3140 instruction->access_start += instruction->info.imm;
3141 instruction->access_end = instruction->access_start + 2;
3142 snprintf(instruction->text,
3144 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3145 "\t\tLHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3147 opcode, instruction->info.rt, instruction->info.ra,
3148 instruction->info.imm);
3150 case 3: /* LBI333 */
3151 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3152 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3153 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3154 instruction->type = NDS32_INSN_LOAD_STORE;
3155 nds32_get_mapped_reg(nds32, instruction->info.ra,
3156 &(instruction->access_start));
3157 instruction->access_start += instruction->info.imm;
3158 instruction->access_end = instruction->access_start + 1;
3159 snprintf(instruction->text,
3161 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3162 "\t\tLBI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3164 opcode, instruction->info.rt, instruction->info.ra,
3165 instruction->info.imm);
3167 case 4: /* SWI333 */
3168 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3169 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3170 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2;
3171 instruction->type = NDS32_INSN_LOAD_STORE;
3172 nds32_get_mapped_reg(nds32, instruction->info.ra,
3173 &(instruction->access_start));
3174 instruction->access_start += instruction->info.imm;
3175 instruction->access_end = instruction->access_start + 4;
3176 snprintf(instruction->text,
3178 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3179 "\t\tSWI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3181 opcode, instruction->info.rt, instruction->info.ra,
3182 instruction->info.imm);
3184 case 5: /* SWI333.BI */
3185 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3186 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3187 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2;
3188 instruction->type = NDS32_INSN_LOAD_STORE;
3189 nds32_get_mapped_reg(nds32, instruction->info.ra,
3190 &(instruction->access_start));
3191 instruction->access_end = instruction->access_start + 4;
3192 snprintf(instruction->text,
3194 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3195 "\t\tSWI333.BI\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
3197 opcode, instruction->info.rt, instruction->info.ra,
3198 instruction->info.imm);
3200 case 6: /* SHI333 */
3201 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3202 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3203 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 1;
3204 instruction->type = NDS32_INSN_LOAD_STORE;
3205 nds32_get_mapped_reg(nds32, instruction->info.ra,
3206 &(instruction->access_start));
3207 instruction->access_start += instruction->info.imm;
3208 instruction->access_end = instruction->access_start + 2;
3209 snprintf(instruction->text,
3211 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3212 "\t\tSHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3214 opcode, instruction->info.rt, instruction->info.ra,
3215 instruction->info.imm);
3217 case 7: /* SBI333 */
3218 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3219 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3220 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3221 instruction->type = NDS32_INSN_LOAD_STORE;
3222 nds32_get_mapped_reg(nds32, instruction->info.ra,
3223 &(instruction->access_start));
3224 instruction->access_start += instruction->info.imm;
3225 instruction->access_end = instruction->access_start + 1;
3226 snprintf(instruction->text,
3228 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3229 "\t\tSHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3231 opcode, instruction->info.rt, instruction->info.ra,
3232 instruction->info.imm);
3234 case 8: /* ADDRI36.SP */
3235 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3236 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 6) << 2;
3237 instruction->type = NDS32_INSN_DATA_PROC;
3238 snprintf(instruction->text,
3240 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3241 "\t\tADDRI36.SP\t$r%" PRIu8 ",#%" PRId32,
3243 opcode, instruction->info.rt, instruction->info.imm);
3245 case 9: /* LWI45.FE */
3246 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3247 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3248 instruction->info.imm -= 32;
3249 instruction->info.imm <<= 2;
3250 instruction->type = NDS32_INSN_LOAD_STORE;
3251 nds32_get_mapped_reg(nds32, R8, &(instruction->access_start));
3252 instruction->access_start += instruction->info.imm;
3253 instruction->access_end = instruction->access_start + 4;
3254 snprintf(instruction->text,
3256 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3257 "\t\tLWI45.FE\t$r%" PRIu8 ",[#%" PRId32 "]",
3259 opcode, instruction->info.rt, instruction->info.imm);
3261 case 10: /* LWI450 */
3262 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3263 instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5);
3264 instruction->type = NDS32_INSN_LOAD_STORE;
3265 nds32_get_mapped_reg(nds32, instruction->info.ra,
3266 &(instruction->access_start));
3267 instruction->access_end = instruction->access_start + 4;
3268 snprintf(instruction->text,
3270 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3271 "\t\tLWI450\t$r%" PRIu8 ",$r%" PRIu8,
3273 opcode, instruction->info.rt, instruction->info.ra);
3275 case 11: /* SWI450 */
3276 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3277 instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5);
3278 instruction->type = NDS32_INSN_LOAD_STORE;
3279 nds32_get_mapped_reg(nds32, instruction->info.ra,
3280 &(instruction->access_start));
3281 instruction->access_end = instruction->access_start + 4;
3282 snprintf(instruction->text,
3284 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3285 "\t\tSWI450\t$r%" PRIu8 ",$r%" PRIu8,
3287 opcode, instruction->info.rt, instruction->info.ra);
3292 case 15: /* LWI37, SWI37 */
3293 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3294 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 7) << 2;
3295 instruction->type = NDS32_INSN_LOAD_STORE;
3296 nds32_get_mapped_reg(nds32, R28, &(instruction->access_start));
3297 instruction->access_start += instruction->info.imm;
3298 instruction->access_end = instruction->access_start + 4;
3299 if (nds32_extract_field_8u(opcode, 7, 1) == 0) { /* LWI37 */
3300 snprintf(instruction->text,
3302 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3303 "\t\tLWI37\t$r%" PRIu8 ",[fp+#%" PRId32 "]",
3305 opcode, instruction->info.rt, instruction->info.imm);
3306 } else { /* SWI37 */
3307 snprintf(instruction->text,
3309 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3310 "\t\tSWI37\t$r%" PRIu8 ",[fp+#%" PRId32 "]",
3312 opcode, instruction->info.rt, instruction->info.imm);
3315 default: /* ERROR */
3316 snprintf(instruction->text,
3318 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION",
3327 static int nds32_parse_group_2_insn_16(struct nds32 *nds32, uint16_t opcode,
3328 uint32_t address, struct nds32_instruction *instruction)
3330 switch ((opcode >> 11) & 0x3) {
3331 case 0: /* BEQZ38 */
3332 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3333 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3334 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3335 instruction->type = NDS32_INSN_JUMP_BRANCH;
3336 snprintf(instruction->text,
3338 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3339 "\t\tBEQZ38\t$r%" PRIu8 ",#%" PRId32,
3341 opcode, instruction->info.rt, instruction->info.imm);
3343 case 1: /* BNEZ38 */
3344 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3345 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3346 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3347 instruction->type = NDS32_INSN_JUMP_BRANCH;
3348 snprintf(instruction->text,
3350 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3351 "\t\tBNEZ38\t$r%" PRIu8 ",#%" PRId32,
3353 opcode, instruction->info.rt, instruction->info.imm);
3355 case 2: /* BEQS38,J8 */
3356 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3357 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3358 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3359 instruction->type = NDS32_INSN_JUMP_BRANCH;
3360 if (instruction->info.rt == 5) { /* J8 */
3361 snprintf(instruction->text,
3363 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3364 "\t\tJ8\t#%" PRId32,
3366 opcode, instruction->info.imm);
3367 } else { /* BEQS38 */
3368 snprintf(instruction->text,
3370 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3371 "\t\tBEQS38\t$r%" PRIu8 ",#%" PRId32,
3373 opcode, instruction->info.rt, instruction->info.imm);
3376 case 3: /* BNES38, JR5, RET5, JRAL5 */
3377 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3378 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3379 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3380 instruction->type = NDS32_INSN_JUMP_BRANCH;
3381 if (instruction->info.rt == 5) {
3382 instruction->info.imm = 0;
3383 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
3384 switch (nds32_extract_field_8u(opcode, 5, 3)) {
3386 snprintf(instruction->text,
3388 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3389 "\t\tJR5\t$r%" PRIu8,
3391 opcode, instruction->info.rb);
3394 snprintf(instruction->text,
3396 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3397 "\t\tJRAL5\t$r%" PRIu8,
3399 opcode, instruction->info.rb);
3401 case 2: /* EX9.IT */
3402 instruction->info.rb = 0;
3403 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3404 /* TODO: implement real instruction semantics */
3405 snprintf(instruction->text,
3407 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3408 "\t\tEX9.IT\t#%" PRId32,
3410 opcode, instruction->info.imm);
3413 snprintf(instruction->text,
3415 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3416 "\t\tRET5\t$r%" PRIu8,
3418 opcode, instruction->info.rb);
3420 case 5: /* ADD5.PC */
3421 instruction->info.rt = 0;
3422 instruction->info.rt = nds32_extract_field_8u(opcode, 0, 5);
3423 instruction->type = NDS32_INSN_DATA_PROC;
3424 snprintf(instruction->text,
3426 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3427 "\t\tADD5.PC\t$r%" PRIu8,
3429 opcode, instruction->info.rt);
3432 snprintf(instruction->text,
3434 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16
3435 "\tUNDEFINED INSTRUCTION",
3440 } else { /* BNES38 */
3441 snprintf(instruction->text,
3443 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3444 "\t\tBNES38\t$r%" PRIu8 ",#%" PRId32,
3446 opcode, instruction->info.rt, instruction->info.imm);
3454 static int nds32_parse_group_3_insn_16(struct nds32 *nds32, uint16_t opcode,
3455 uint32_t address, struct nds32_instruction *instruction)
3457 switch ((opcode >> 11) & 0x3) {
3459 switch ((opcode >> 9) & 0x3) {
3460 case 0: /* SLTS45 */
3461 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3462 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
3463 instruction->type = NDS32_INSN_DATA_PROC;
3464 snprintf(instruction->text,
3466 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3467 "\t\tSLTS45\t$r%" PRIu8 ",$r%" PRIu8,
3469 opcode, instruction->info.ra, instruction->info.rb);
3472 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3473 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
3474 instruction->type = NDS32_INSN_DATA_PROC;
3475 snprintf(instruction->text,
3477 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3478 "\t\tSLT45\t$r%" PRIu8 ",$r%" PRIu8,
3480 opcode, instruction->info.ra, instruction->info.rb);
3482 case 2: /* SLTSI45 */
3483 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3484 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3485 instruction->type = NDS32_INSN_DATA_PROC;
3486 snprintf(instruction->text,
3488 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3489 "\t\tSLTSI45\t$r%" PRIu8 ",#%" PRId32,
3491 opcode, instruction->info.ra, instruction->info.imm);
3493 case 3: /* SLTI45 */
3494 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3495 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3496 instruction->type = NDS32_INSN_DATA_PROC;
3497 snprintf(instruction->text,
3499 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3500 "\t\tSLTI45\t$r%" PRIu8 ",#%" PRId32,
3502 opcode, instruction->info.ra, instruction->info.imm);
3507 switch ((opcode >> 9) & 0x3) {
3509 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3510 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3511 instruction->type = NDS32_INSN_JUMP_BRANCH;
3512 if (nds32_extract_field_8u(opcode, 8, 1) == 0) { /* BEQZS8 */
3513 snprintf(instruction->text,
3515 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3516 "\t\tBEQZS8\t#%" PRId32,
3518 opcode, instruction->info.imm);
3519 } else { /* BNEZS8 */
3520 snprintf(instruction->text,
3522 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3523 "\t\tBNEZS8\t#%" PRId32,
3525 opcode, instruction->info.imm);
3528 case 1: /* BREAK16 */
3529 if (((opcode >> 5) & 0xF) == 0) {
3530 instruction->type = NDS32_INSN_MISC;
3531 snprintf(instruction->text,
3533 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3534 "\t\tBREAK16\t#%" PRId16,
3536 opcode, (int16_t)(opcode & 0x1F));
3537 } else { /* EX9.IT */
3538 instruction->type = NDS32_INSN_MISC;
3539 /* TODO: implement real instruction semantics */
3540 snprintf(instruction->text,
3542 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3543 "\t\tEX9.IT\t#%" PRId16,
3545 opcode, (int16_t)(opcode & 0x1FF));
3548 case 2: /* ADDI10S */
3550 instruction->info.imm = opcode & 0x3FF;
3551 instruction->info.imm = (instruction->info.imm << 22) >> 22;
3552 instruction->type = NDS32_INSN_DATA_PROC;
3553 snprintf(instruction->text,
3555 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3556 "\t\tADDI10.SP\t#%" PRId32,
3558 opcode, instruction->info.imm);
3563 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3564 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 7) << 2;
3565 instruction->type = NDS32_INSN_LOAD_STORE;
3566 nds32_get_mapped_reg(nds32, R31, &(instruction->access_start));
3567 instruction->access_start += instruction->info.imm;
3568 instruction->access_end = instruction->access_start + 4;
3569 if (nds32_extract_field_8u(opcode, 7, 1) == 0) { /* LWI37.SP */
3570 snprintf(instruction->text,
3572 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3573 "\t\tLWI37.SP\t$r%" PRIu8 ",[+#%" PRId32 "]",
3575 opcode, instruction->info.rt, instruction->info.imm);
3576 } else { /* SWI37.SP */
3577 snprintf(instruction->text,
3579 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3580 "\t\tSWI37.SP\t$r%" PRIu8 ",[+#%" PRId32 "]",
3582 opcode, instruction->info.rt, instruction->info.imm);
3586 switch ((opcode >> 9) & 0x3) {
3587 case 0: /* IFCALL9 */
3588 instruction->info.imm = opcode & 0x1FF;
3589 instruction->type = NDS32_INSN_JUMP_BRANCH;
3590 snprintf(instruction->text,
3592 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3593 "\t\tIFCALL9\t#%" PRId32 "",
3595 opcode, instruction->info.imm);
3597 case 1: /* MOVPI45 */
3598 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5) + 16;
3599 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3600 instruction->type = NDS32_INSN_MISC;
3601 snprintf(instruction->text,
3603 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3604 "\t\tMOVPI45\t$r%" PRIu8 ",#%" PRId32 "",
3606 opcode, instruction->info.rt, instruction->info.imm);
3608 case 2: /* PUSH25, POP25, MOVD44 */
3609 switch ((opcode >> 7) & 0x3) {
3610 case 0: /* PUSH25 */
3615 instruction->type = NDS32_INSN_LOAD_STORE;
3616 instruction->info.imm =
3617 nds32_extract_field_8u(opcode, 0, 5) << 3;
3618 re = nds32_extract_field_8u(opcode, 5, 2);
3629 instruction->info.rd = re;
3630 /* GPRs list: R6 ~ Re and fp, gp, lp */
3631 gpr_count = 3 + (re - 5);
3633 nds32_get_mapped_reg(nds32, R31,
3634 &(instruction->access_end));
3635 instruction->access_start =
3636 instruction->access_end - (gpr_count * 4);
3638 snprintf(instruction->text,
3640 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3641 "\t\tPUSH25\t$r%" PRIu8 ",#%" PRId32,
3643 opcode, instruction->info.rd,
3644 instruction->info.imm);
3652 instruction->type = NDS32_INSN_LOAD_STORE;
3653 instruction->info.imm =
3654 nds32_extract_field_8u(opcode, 0, 5) << 3;
3655 re = nds32_extract_field_8u(opcode, 5, 2);
3666 instruction->info.rd = re;
3667 /* GPRs list: R6 ~ Re and fp, gp, lp */
3668 gpr_count = 3 + (re - 5);
3670 nds32_get_mapped_reg(nds32, R31,
3671 &(instruction->access_start));
3672 instruction->access_start += instruction->info.imm;
3673 instruction->access_end =
3674 instruction->access_start + (gpr_count * 4);
3676 snprintf(instruction->text,
3678 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3679 "\t\tPOP25\t$r%" PRIu8 ",#%" PRId32,
3681 opcode, instruction->info.rd,
3682 instruction->info.imm);
3685 case 2: /* MOVD44 */
3687 instruction->info.ra =
3688 nds32_extract_field_8u(opcode, 0, 4) * 2;
3689 instruction->info.rt =
3690 nds32_extract_field_8u(opcode, 4, 4) * 2;
3691 instruction->type = NDS32_INSN_MISC;
3692 snprintf(instruction->text,
3694 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3695 "\t\tMOVD44\t$r%" PRIu8 ",$r%" PRIu8,
3697 opcode, instruction->info.rt, instruction->info.ra);
3701 case 3: /* NEG33, NOT33, MUL33, XOR33, AND33, OR33 */
3702 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3703 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3704 instruction->type = NDS32_INSN_DATA_PROC;
3705 switch (opcode & 0x7) {
3707 snprintf(instruction->text,
3709 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3710 "\t\tNEG33\t$r%" PRIu8 ",$r%" PRIu8,
3712 opcode, instruction->info.rt, instruction->info.ra);
3715 snprintf(instruction->text,
3717 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3718 "\t\tNOT33\t$r%" PRIu8 ",$r%" PRIu8,
3720 opcode, instruction->info.rt, instruction->info.ra);
3723 snprintf(instruction->text,
3725 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3726 "\t\tMUL33\t$r%" PRIu8 ",$r%" PRIu8,
3728 opcode, instruction->info.rt, instruction->info.ra);
3731 snprintf(instruction->text,
3733 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3734 "\t\tXOR33\t$r%" PRIu8 ",$r%" PRIu8,
3736 opcode, instruction->info.rt, instruction->info.ra);
3739 snprintf(instruction->text,
3741 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3742 "\t\tAND33\t$r%" PRIu8 ",$r%" PRIu8,
3744 opcode, instruction->info.rt, instruction->info.ra);
3747 snprintf(instruction->text,
3749 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3750 "\t\tOR33\t$r%" PRIu8 ",$r%" PRIu8,
3752 opcode, instruction->info.rt, instruction->info.ra);
3759 snprintf(instruction->text,
3761 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION",
3770 int nds32_evaluate_opcode(struct nds32 *nds32, uint32_t opcode, uint32_t address,
3771 struct nds32_instruction *instruction)
3773 int retval = ERROR_OK;
3775 /* clear fields, to avoid confusion */
3776 memset(instruction, 0, sizeof(struct nds32_instruction));
3779 /* 16 bits instruction */
3780 instruction->instruction_size = 2;
3781 opcode = (opcode >> 16) & 0xFFFF;
3782 instruction->opcode = opcode;
3784 switch ((opcode >> 13) & 0x3) {
3786 retval = nds32_parse_group_0_insn_16(nds32, opcode, address, instruction);
3789 retval = nds32_parse_group_1_insn_16(nds32, opcode, address, instruction);
3792 retval = nds32_parse_group_2_insn_16(nds32, opcode, address, instruction);
3795 retval = nds32_parse_group_3_insn_16(nds32, opcode, address, instruction);
3798 snprintf(instruction->text,
3800 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
3806 /* 32 bits instruction */
3807 instruction->instruction_size = 4;
3808 instruction->opcode = opcode;
3811 opc_6 = opcode >> 25;
3812 instruction->info.opc_6 = opc_6;
3814 switch ((opc_6 >> 3) & 0x7) {
3815 case 0: /* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */
3816 retval = nds32_parse_group_0_insn(nds32, opcode, address, instruction);
3818 case 1: /* SBI, SHI, SWI, SBI.bi, SHI.bi, SWI.bi */
3819 retval = nds32_parse_group_1_insn(nds32, opcode, address, instruction);
3821 case 2: /* LBSI, LHSI, DPREFI, LBSI.bi, LHSI.bi, LBGP */
3822 retval = nds32_parse_group_2_insn(nds32, opcode, address, instruction);
3824 case 3: /* MEM, LSMW, HWGP, SBGP */
3825 retval = nds32_parse_group_3_insn(nds32, opcode, address, instruction);
3827 case 4: /* ALU_1, ALU_2, MOVI, SETHI, JI, JREG, BR1, BR2 */
3828 retval = nds32_parse_group_4_insn(nds32, opcode, address, instruction);
3830 case 5: /* ADDI, SUBRI, ANDI, XORI, ORI, SLTI, SLTSI */
3831 retval = nds32_parse_group_5_insn(nds32, opcode, address, instruction);
3834 retval = nds32_parse_group_6_insn(nds32, opcode, address, instruction);
3836 default: /* ERROR */
3837 snprintf(instruction->text,
3839 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",