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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
  10  *   drasko.draskovic@gmail.com                                            *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  26  ***************************************************************************/
  27
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include "breakpoints.h"
  33 #include "mips32.h"
  34 #include "mips_m4k.h"
  35 #include "mips32_dmaacc.h"
  36 #include "target_type.h"
  37 #include "register.h"
  38
  39 static void mips_m4k_enable_breakpoints(struct target *target);
  40 static void mips_m4k_enable_watchpoints(struct target *target);
  41 static int mips_m4k_set_breakpoint(struct target *target,
  42                 struct breakpoint *breakpoint);
  43 static int mips_m4k_unset_breakpoint(struct target *target,
  44                 struct breakpoint *breakpoint);
  45 static int mips_m4k_internal_restore(struct target *target, int current,
  46                 uint32_t address, int handle_breakpoints,
  47                 int debug_execution);
  48 static int mips_m4k_halt(struct target *target);
  49 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
  50                 uint32_t count, const uint8_t *buffer);
  51
  52 static int mips_m4k_examine_debug_reason(struct target *target)
  53 {
  54         struct mips32_common *mips32 = target_to_mips32(target);
  55         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  56         uint32_t break_status;
  57         int retval;
  58
  59         if ((target->debug_reason != DBG_REASON_DBGRQ)
  60                         && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
  61                 if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
  62                         /* get info about inst breakpoint support */
  63                         retval = target_read_u32(target,
  64                                 ejtag_info->ejtag_ibs_addr, &break_status);
  65                         if (retval != ERROR_OK)
  66                                 return retval;
  67                         if (break_status & 0x1f) {
  68                                 /* we have halted on a  breakpoint */
  69                                 retval = target_write_u32(target,
  70                                         ejtag_info->ejtag_ibs_addr, 0);
  71                                 if (retval != ERROR_OK)
  72                                         return retval;
  73                                 target->debug_reason = DBG_REASON_BREAKPOINT;
  74                         }
  75                 }
  76
  77                 if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
  78                         /* get info about data breakpoint support */
  79                         retval = target_read_u32(target,
  80                                 ejtag_info->ejtag_dbs_addr, &break_status);
  81                         if (retval != ERROR_OK)
  82                                 return retval;
  83                         if (break_status & 0x1f) {
  84                                 /* we have halted on a  breakpoint */
  85                                 retval = target_write_u32(target,
  86                                         ejtag_info->ejtag_dbs_addr, 0);
  87                                 if (retval != ERROR_OK)
  88                                         return retval;
  89                                 target->debug_reason = DBG_REASON_WATCHPOINT;
  90                         }
  91                 }
  92         }
  93
  94         return ERROR_OK;
  95 }
  96
  97 static int mips_m4k_debug_entry(struct target *target)
  98 {
  99         struct mips32_common *mips32 = target_to_mips32(target);
 100         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 101
 102         mips32_save_context(target);
 103
 104         /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
 105         mips_ejtag_config_step(ejtag_info, 0);
 106
 107         /* make sure break unit configured */
 108         mips32_configure_break_unit(target);
 109
 110         /* attempt to find halt reason */
 111         mips_m4k_examine_debug_reason(target);
 112
 113         /* default to mips32 isa, it will be changed below if required */
 114         mips32->isa_mode = MIPS32_ISA_MIPS32;
 115
 116         if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
 117                 mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
 118
 119         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
 120                         buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
 121                         target_state_name(target));
 122
 123         return ERROR_OK;
 124 }
 125
 126 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
 127 {
 128         struct target_list *head;
 129         struct target *curr;
 130
 131         head = target->head;
 132         while (head != (struct target_list *)NULL) {
 133                 curr = head->target;
 134                 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
 135                         return curr;
 136                 head = head->next;
 137         }
 138         return target;
 139 }
 140
 141 static int mips_m4k_halt_smp(struct target *target)
 142 {
 143         int retval = ERROR_OK;
 144         struct target_list *head;
 145         struct target *curr;
 146         head = target->head;
 147         while (head != (struct target_list *)NULL) {
 148                 int ret = ERROR_OK;
 149                 curr = head->target;
 150                 if ((curr != target) && (curr->state != TARGET_HALTED))
 151                         ret = mips_m4k_halt(curr);
 152
 153                 if (ret != ERROR_OK) {
 154                         LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
 155                         retval = ret;
 156                 }
 157                 head = head->next;
 158         }
 159         return retval;
 160 }
 161
 162 static int update_halt_gdb(struct target *target)
 163 {
 164         int retval = ERROR_OK;
 165         if (target->gdb_service->core[0] == -1) {
 166                 target->gdb_service->target = target;
 167                 target->gdb_service->core[0] = target->coreid;
 168                 retval = mips_m4k_halt_smp(target);
 169         }
 170         return retval;
 171 }
 172
 173 static int mips_m4k_poll(struct target *target)
 174 {
 175         int retval = ERROR_OK;
 176         struct mips32_common *mips32 = target_to_mips32(target);
 177         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 178         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 179         enum target_state prev_target_state = target->state;
 180
 181         /*  toggle to another core is done by gdb as follow */
 182         /*  maint packet J core_id */
 183         /*  continue */
 184         /*  the next polling trigger an halt event sent to gdb */
 185         if ((target->state == TARGET_HALTED) && (target->smp) &&
 186                 (target->gdb_service) &&
 187                 (target->gdb_service->target == NULL)) {
 188                 target->gdb_service->target =
 189                         get_mips_m4k(target, target->gdb_service->core[1]);
 190                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 191                 return retval;
 192         }
 193
 194         /* read ejtag control reg */
 195         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 196         retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 197         if (retval != ERROR_OK)
 198                 return retval;
 199
 200         /* clear this bit before handling polling
 201          * as after reset registers will read zero */
 202         if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
 203                 /* we have detected a reset, clear flag
 204                  * otherwise ejtag will not work */
 205                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 206
 207                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 208                 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 209                 if (retval != ERROR_OK)
 210                         return retval;
 211                 LOG_DEBUG("Reset Detected");
 212         }
 213
 214         /* check for processor halted */
 215         if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
 216                 if ((target->state != TARGET_HALTED)
 217                     && (target->state != TARGET_DEBUG_RUNNING)) {
 218                         if (target->state == TARGET_UNKNOWN)
 219                                 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
 220
 221                         /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
 222                          * (maybe put on by HALT-ing the board in the previous session).
 223                          *
 224                          * Force enable debug entry for this session.
 225                          */
 226                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 227                         target->state = TARGET_HALTED;
 228                         retval = mips_m4k_debug_entry(target);
 229                         if (retval != ERROR_OK)
 230                                 return retval;
 231
 232                         if (target->smp &&
 233                                 ((prev_target_state == TARGET_RUNNING)
 234                              || (prev_target_state == TARGET_RESET))) {
 235                                 retval = update_halt_gdb(target);
 236                                 if (retval != ERROR_OK)
 237                                         return retval;
 238                         }
 239                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 240                 } else if (target->state == TARGET_DEBUG_RUNNING) {
 241                         target->state = TARGET_HALTED;
 242
 243                         retval = mips_m4k_debug_entry(target);
 244                         if (retval != ERROR_OK)
 245                                 return retval;
 246
 247                         if (target->smp) {
 248                                 retval = update_halt_gdb(target);
 249                                 if (retval != ERROR_OK)
 250                                         return retval;
 251                         }
 252
 253                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 254                 }
 255         } else
 256                 target->state = TARGET_RUNNING;
 257
 258 /*      LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
 259
 260         return ERROR_OK;
 261 }
 262
 263 static int mips_m4k_halt(struct target *target)
 264 {
 265         struct mips32_common *mips32 = target_to_mips32(target);
 266         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 267
 268         LOG_DEBUG("target->state: %s", target_state_name(target));
 269
 270         if (target->state == TARGET_HALTED) {
 271                 LOG_DEBUG("target was already halted");
 272                 return ERROR_OK;
 273         }
 274
 275         if (target->state == TARGET_UNKNOWN)
 276                 LOG_WARNING("target was in unknown state when halt was requested");
 277
 278         if (target->state == TARGET_RESET) {
 279                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 280                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 281                         return ERROR_TARGET_FAILURE;
 282                 } else {
 283                         /* we came here in a reset_halt or reset_init sequence
 284                          * debug entry was already prepared in mips_m4k_assert_reset()
 285                          */
 286                         target->debug_reason = DBG_REASON_DBGRQ;
 287
 288                         return ERROR_OK;
 289                 }
 290         }
 291
 292         /* break processor */
 293         mips_ejtag_enter_debug(ejtag_info);
 294
 295         target->debug_reason = DBG_REASON_DBGRQ;
 296
 297         return ERROR_OK;
 298 }
 299
 300 static int mips_m4k_assert_reset(struct target *target)
 301 {
 302         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
 303         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 304
 305         LOG_DEBUG("target->state: %s",
 306                 target_state_name(target));
 307
 308         enum reset_types jtag_reset_config = jtag_get_reset_config();
 309
 310         /* some cores support connecting while srst is asserted
 311          * use that mode is it has been configured */
 312
 313         bool srst_asserted = false;
 314
 315         if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
 316                         (jtag_reset_config & RESET_SRST_NO_GATING)) {
 317                 jtag_add_reset(0, 1);
 318                 srst_asserted = true;
 319         }
 320
 321
 322         /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
 323         if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
 324                 if (target->reset_halt) {
 325                         /* use hardware to catch reset */
 326                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
 327                 } else
 328                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 329         }
 330
 331         if (jtag_reset_config & RESET_HAS_SRST) {
 332                 /* here we should issue a srst only, but we may have to assert trst as well */
 333                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 334                         jtag_add_reset(1, 1);
 335                 else if (!srst_asserted)
 336                         jtag_add_reset(0, 1);
 337         } else {
 338                 if (mips_m4k->is_pic32mx) {
 339                         LOG_DEBUG("Using MTAP reset to reset processor...");
 340
 341                         /* use microchip specific MTAP reset */
 342                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
 343                         mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 344
 345                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
 346                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
 347                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 348                 } else {
 349                         /* use ejtag reset - not supported by all cores */
 350                         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 351                         LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 352                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 353                         mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
 354                 }
 355         }
 356
 357         target->state = TARGET_RESET;
 358         jtag_add_sleep(50000);
 359
 360         register_cache_invalidate(mips_m4k->mips32.core_cache);
 361
 362         if (target->reset_halt) {
 363                 int retval = target_halt(target);
 364                 if (retval != ERROR_OK)
 365                         return retval;
 366         }
 367
 368         return ERROR_OK;
 369 }
 370
 371 static int mips_m4k_deassert_reset(struct target *target)
 372 {
 373         LOG_DEBUG("target->state: %s", target_state_name(target));
 374
 375         /* deassert reset lines */
 376         jtag_add_reset(0, 0);
 377
 378         return ERROR_OK;
 379 }
 380
 381 static int mips_m4k_single_step_core(struct target *target)
 382 {
 383         struct mips32_common *mips32 = target_to_mips32(target);
 384         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 385
 386         /* configure single step mode */
 387         mips_ejtag_config_step(ejtag_info, 1);
 388
 389         /* disable interrupts while stepping */
 390         mips32_enable_interrupts(target, 0);
 391
 392         /* exit debug mode */
 393         mips_ejtag_exit_debug(ejtag_info);
 394
 395         mips_m4k_debug_entry(target);
 396
 397         return ERROR_OK;
 398 }
 399
 400 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
 401 {
 402         int retval = ERROR_OK;
 403         struct target_list *head;
 404         struct target *curr;
 405
 406         head = target->head;
 407         while (head != (struct target_list *)NULL) {
 408                 int ret = ERROR_OK;
 409                 curr = head->target;
 410                 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
 411                         /*  resume current address , not in step mode */
 412                         ret = mips_m4k_internal_restore(curr, 1, address,
 413                                                    handle_breakpoints, 0);
 414
 415                         if (ret != ERROR_OK) {
 416                                 LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
 417                                                   curr->coreid, address);
 418                                 retval = ret;
 419                         }
 420                 }
 421                 head = head->next;
 422         }
 423         return retval;
 424 }
 425
 426 static int mips_m4k_internal_restore(struct target *target, int current,
 427                 uint32_t address, int handle_breakpoints, int debug_execution)
 428 {
 429         struct mips32_common *mips32 = target_to_mips32(target);
 430         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 431         struct breakpoint *breakpoint = NULL;
 432         uint32_t resume_pc;
 433
 434         if (target->state != TARGET_HALTED) {
 435                 LOG_WARNING("target not halted");
 436                 return ERROR_TARGET_NOT_HALTED;
 437         }
 438
 439         if (!debug_execution) {
 440                 target_free_all_working_areas(target);
 441                 mips_m4k_enable_breakpoints(target);
 442                 mips_m4k_enable_watchpoints(target);
 443         }
 444
 445         /* current = 1: continue on current pc, otherwise continue at <address> */
 446         if (!current) {
 447                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 448                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 449                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 450         }
 451
 452         if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
 453                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
 454
 455         if (!current)
 456                 resume_pc = address;
 457         else
 458                 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 459
 460         mips32_restore_context(target);
 461
 462         /* the front-end may request us not to handle breakpoints */
 463         if (handle_breakpoints) {
 464                 /* Single step past breakpoint at current address */
 465                 breakpoint = breakpoint_find(target, resume_pc);
 466                 if (breakpoint) {
 467                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 468                         mips_m4k_unset_breakpoint(target, breakpoint);
 469                         mips_m4k_single_step_core(target);
 470                         mips_m4k_set_breakpoint(target, breakpoint);
 471                 }
 472         }
 473
 474         /* enable interrupts if we are running */
 475         mips32_enable_interrupts(target, !debug_execution);
 476
 477         /* exit debug mode */
 478         mips_ejtag_exit_debug(ejtag_info);
 479         target->debug_reason = DBG_REASON_NOTHALTED;
 480
 481         /* registers are now invalid */
 482         register_cache_invalidate(mips32->core_cache);
 483
 484         if (!debug_execution) {
 485                 target->state = TARGET_RUNNING;
 486                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 487                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 488         } else {
 489                 target->state = TARGET_DEBUG_RUNNING;
 490                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 491                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 492         }
 493
 494         return ERROR_OK;
 495 }
 496
 497 static int mips_m4k_resume(struct target *target, int current,
 498                 uint32_t address, int handle_breakpoints, int debug_execution)
 499 {
 500         int retval = ERROR_OK;
 501
 502         /* dummy resume for smp toggle in order to reduce gdb impact  */
 503         if ((target->smp) && (target->gdb_service->core[1] != -1)) {
 504                 /*   simulate a start and halt of target */
 505                 target->gdb_service->target = NULL;
 506                 target->gdb_service->core[0] = target->gdb_service->core[1];
 507                 /*  fake resume at next poll we play the  target core[1], see poll*/
 508                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 509                 return retval;
 510         }
 511
 512         retval = mips_m4k_internal_restore(target, current, address,
 513                                 handle_breakpoints,
 514                                 debug_execution);
 515
 516         if (retval == ERROR_OK && target->smp) {
 517                 target->gdb_service->core[0] = -1;
 518                 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
 519         }
 520
 521         return retval;
 522 }
 523
 524 static int mips_m4k_step(struct target *target, int current,
 525                 uint32_t address, int handle_breakpoints)
 526 {
 527         /* get pointers to arch-specific information */
 528         struct mips32_common *mips32 = target_to_mips32(target);
 529         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 530         struct breakpoint *breakpoint = NULL;
 531
 532         if (target->state != TARGET_HALTED) {
 533                 LOG_WARNING("target not halted");
 534                 return ERROR_TARGET_NOT_HALTED;
 535         }
 536
 537         /* current = 1: continue on current pc, otherwise continue at <address> */
 538         if (!current) {
 539                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 540                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 541                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 542         }
 543
 544         /* the front-end may request us not to handle breakpoints */
 545         if (handle_breakpoints) {
 546                 breakpoint = breakpoint_find(target,
 547                                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 548                 if (breakpoint)
 549                         mips_m4k_unset_breakpoint(target, breakpoint);
 550         }
 551
 552         /* restore context */
 553         mips32_restore_context(target);
 554
 555         /* configure single step mode */
 556         mips_ejtag_config_step(ejtag_info, 1);
 557
 558         target->debug_reason = DBG_REASON_SINGLESTEP;
 559
 560         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 561
 562         /* disable interrupts while stepping */
 563         mips32_enable_interrupts(target, 0);
 564
 565         /* exit debug mode */
 566         mips_ejtag_exit_debug(ejtag_info);
 567
 568         /* registers are now invalid */
 569         register_cache_invalidate(mips32->core_cache);
 570
 571         LOG_DEBUG("target stepped ");
 572         mips_m4k_debug_entry(target);
 573
 574         if (breakpoint)
 575                 mips_m4k_set_breakpoint(target, breakpoint);
 576
 577         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 578
 579         return ERROR_OK;
 580 }
 581
 582 static void mips_m4k_enable_breakpoints(struct target *target)
 583 {
 584         struct breakpoint *breakpoint = target->breakpoints;
 585
 586         /* set any pending breakpoints */
 587         while (breakpoint) {
 588                 if (breakpoint->set == 0)
 589                         mips_m4k_set_breakpoint(target, breakpoint);
 590                 breakpoint = breakpoint->next;
 591         }
 592 }
 593
 594 static int mips_m4k_set_breakpoint(struct target *target,
 595                 struct breakpoint *breakpoint)
 596 {
 597         struct mips32_common *mips32 = target_to_mips32(target);
 598         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 599         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 600         int retval;
 601
 602         if (breakpoint->set) {
 603                 LOG_WARNING("breakpoint already set");
 604                 return ERROR_OK;
 605         }
 606
 607         if (breakpoint->type == BKPT_HARD) {
 608                 int bp_num = 0;
 609
 610                 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 611                         bp_num++;
 612                 if (bp_num >= mips32->num_inst_bpoints) {
 613                         LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
 614                                         breakpoint->unique_id);
 615                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 616                 }
 617                 breakpoint->set = bp_num + 1;
 618                 comparator_list[bp_num].used = 1;
 619                 comparator_list[bp_num].bp_value = breakpoint->address;
 620
 621                 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
 622                  * Warning: there is no IB ASID registers in 2.0.
 623                  * Do not set it! :) */
 624                 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 625                         comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
 626
 627                 target_write_u32(target, comparator_list[bp_num].reg_address,
 628                                 comparator_list[bp_num].bp_value);
 629                 target_write_u32(target, comparator_list[bp_num].reg_address +
 630                                  ejtag_info->ejtag_ibm_offs, 0x00000000);
 631                 target_write_u32(target, comparator_list[bp_num].reg_address +
 632                                  ejtag_info->ejtag_ibc_offs, 1);
 633                 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
 634                                   breakpoint->unique_id,
 635                                   bp_num, comparator_list[bp_num].bp_value);
 636         } else if (breakpoint->type == BKPT_SOFT) {
 637                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 638                 if (breakpoint->length == 4) {
 639                         uint32_t verify = 0xffffffff;
 640
 641                         retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 642                                         breakpoint->orig_instr);
 643                         if (retval != ERROR_OK)
 644                                 return retval;
 645                         retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP);
 646                         if (retval != ERROR_OK)
 647                                 return retval;
 648
 649                         retval = target_read_u32(target, breakpoint->address, &verify);
 650                         if (retval != ERROR_OK)
 651                                 return retval;
 652                         if (verify != MIPS32_SDBBP) {
 653                                 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32
 654                                                 " - check that memory is read/writable", breakpoint->address);
 655                                 return ERROR_OK;
 656                         }
 657                 } else {
 658                         uint16_t verify = 0xffff;
 659
 660                         retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 661                                         breakpoint->orig_instr);
 662                         if (retval != ERROR_OK)
 663                                 return retval;
 664                         retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP);
 665                         if (retval != ERROR_OK)
 666                                 return retval;
 667
 668                         retval = target_read_u16(target, breakpoint->address, &verify);
 669                         if (retval != ERROR_OK)
 670                                 return retval;
 671                         if (verify != MIPS16_SDBBP) {
 672                                 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32
 673                                                 " - check that memory is read/writable", breakpoint->address);
 674                                 return ERROR_OK;
 675                         }
 676                 }
 677
 678                 breakpoint->set = 20; /* Any nice value but 0 */
 679         }
 680
 681         return ERROR_OK;
 682 }
 683
 684 static int mips_m4k_unset_breakpoint(struct target *target,
 685                 struct breakpoint *breakpoint)
 686 {
 687         /* get pointers to arch-specific information */
 688         struct mips32_common *mips32 = target_to_mips32(target);
 689         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 690         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 691         int retval;
 692
 693         if (!breakpoint->set) {
 694                 LOG_WARNING("breakpoint not set");
 695                 return ERROR_OK;
 696         }
 697
 698         if (breakpoint->type == BKPT_HARD) {
 699                 int bp_num = breakpoint->set - 1;
 700                 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
 701                         LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
 702                                           breakpoint->unique_id);
 703                         return ERROR_OK;
 704                 }
 705                 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
 706                                 breakpoint->unique_id,
 707                                 bp_num);
 708                 comparator_list[bp_num].used = 0;
 709                 comparator_list[bp_num].bp_value = 0;
 710                 target_write_u32(target, comparator_list[bp_num].reg_address +
 711                                  ejtag_info->ejtag_ibc_offs, 0);
 712
 713         } else {
 714                 /* restore original instruction (kept in target endianness) */
 715                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 716                 if (breakpoint->length == 4) {
 717                         uint32_t current_instr;
 718
 719                         /* check that user program has not modified breakpoint instruction */
 720                         retval = target_read_memory(target, breakpoint->address, 4, 1,
 721                                         (uint8_t *)&current_instr);
 722                         if (retval != ERROR_OK)
 723                                 return retval;
 724
 725                         /**
 726                          * target_read_memory() gets us data in _target_ endianess.
 727                          * If we want to use this data on the host for comparisons with some macros
 728                          * we must first transform it to _host_ endianess using target_buffer_get_u32().
 729                          */
 730                         current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
 731
 732                         if (current_instr == MIPS32_SDBBP) {
 733                                 retval = target_write_memory(target, breakpoint->address, 4, 1,
 734                                                 breakpoint->orig_instr);
 735                                 if (retval != ERROR_OK)
 736                                         return retval;
 737                         }
 738                 } else {
 739                         uint16_t current_instr;
 740
 741                         /* check that user program has not modified breakpoint instruction */
 742                         retval = target_read_memory(target, breakpoint->address, 2, 1,
 743                                         (uint8_t *)&current_instr);
 744                         if (retval != ERROR_OK)
 745                                 return retval;
 746                         current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
 747                         if (current_instr == MIPS16_SDBBP) {
 748                                 retval = target_write_memory(target, breakpoint->address, 2, 1,
 749                                                 breakpoint->orig_instr);
 750                                 if (retval != ERROR_OK)
 751                                         return retval;
 752                         }
 753                 }
 754         }
 755         breakpoint->set = 0;
 756
 757         return ERROR_OK;
 758 }
 759
 760 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 761 {
 762         struct mips32_common *mips32 = target_to_mips32(target);
 763
 764         if (breakpoint->type == BKPT_HARD) {
 765                 if (mips32->num_inst_bpoints_avail < 1) {
 766                         LOG_INFO("no hardware breakpoint available");
 767                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 768                 }
 769
 770                 mips32->num_inst_bpoints_avail--;
 771         }
 772
 773         return mips_m4k_set_breakpoint(target, breakpoint);
 774 }
 775
 776 static int mips_m4k_remove_breakpoint(struct target *target,
 777                 struct breakpoint *breakpoint)
 778 {
 779         /* get pointers to arch-specific information */
 780         struct mips32_common *mips32 = target_to_mips32(target);
 781
 782         if (target->state != TARGET_HALTED) {
 783                 LOG_WARNING("target not halted");
 784                 return ERROR_TARGET_NOT_HALTED;
 785         }
 786
 787         if (breakpoint->set)
 788                 mips_m4k_unset_breakpoint(target, breakpoint);
 789
 790         if (breakpoint->type == BKPT_HARD)
 791                 mips32->num_inst_bpoints_avail++;
 792
 793         return ERROR_OK;
 794 }
 795
 796 static int mips_m4k_set_watchpoint(struct target *target,
 797                 struct watchpoint *watchpoint)
 798 {
 799         struct mips32_common *mips32 = target_to_mips32(target);
 800         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 801         struct mips32_comparator *comparator_list = mips32->data_break_list;
 802         int wp_num = 0;
 803         /*
 804          * watchpoint enabled, ignore all byte lanes in value register
 805          * and exclude both load and store accesses from  watchpoint
 806          * condition evaluation
 807         */
 808         int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
 809                         (0xff << EJTAG_DBCn_BLM_SHIFT);
 810
 811         if (watchpoint->set) {
 812                 LOG_WARNING("watchpoint already set");
 813                 return ERROR_OK;
 814         }
 815
 816         while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
 817                 wp_num++;
 818         if (wp_num >= mips32->num_data_bpoints) {
 819                 LOG_ERROR("Can not find free FP Comparator");
 820                 return ERROR_FAIL;
 821         }
 822
 823         if (watchpoint->length != 4) {
 824                 LOG_ERROR("Only watchpoints of length 4 are supported");
 825                 return ERROR_TARGET_UNALIGNED_ACCESS;
 826         }
 827
 828         if (watchpoint->address % 4) {
 829                 LOG_ERROR("Watchpoints address should be word aligned");
 830                 return ERROR_TARGET_UNALIGNED_ACCESS;
 831         }
 832
 833         switch (watchpoint->rw) {
 834                 case WPT_READ:
 835                         enable &= ~EJTAG_DBCn_NOLB;
 836                         break;
 837                 case WPT_WRITE:
 838                         enable &= ~EJTAG_DBCn_NOSB;
 839                         break;
 840                 case WPT_ACCESS:
 841                         enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
 842                         break;
 843                 default:
 844                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
 845         }
 846
 847         watchpoint->set = wp_num + 1;
 848         comparator_list[wp_num].used = 1;
 849         comparator_list[wp_num].bp_value = watchpoint->address;
 850
 851         /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
 852          * There is as well no ASID register support. */
 853         if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 854                 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
 855         else
 856                 target_write_u32(target, comparator_list[wp_num].reg_address +
 857                          ejtag_info->ejtag_dbasid_offs, 0x00000000);
 858
 859         target_write_u32(target, comparator_list[wp_num].reg_address,
 860                          comparator_list[wp_num].bp_value);
 861         target_write_u32(target, comparator_list[wp_num].reg_address +
 862                          ejtag_info->ejtag_dbm_offs, 0x00000000);
 863
 864         target_write_u32(target, comparator_list[wp_num].reg_address +
 865                          ejtag_info->ejtag_dbc_offs, enable);
 866         /* TODO: probably this value is ignored on 2.0 */
 867         target_write_u32(target, comparator_list[wp_num].reg_address +
 868                          ejtag_info->ejtag_dbv_offs, 0);
 869         LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
 870
 871         return ERROR_OK;
 872 }
 873
 874 static int mips_m4k_unset_watchpoint(struct target *target,
 875                 struct watchpoint *watchpoint)
 876 {
 877         /* get pointers to arch-specific information */
 878         struct mips32_common *mips32 = target_to_mips32(target);
 879         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 880         struct mips32_comparator *comparator_list = mips32->data_break_list;
 881
 882         if (!watchpoint->set) {
 883                 LOG_WARNING("watchpoint not set");
 884                 return ERROR_OK;
 885         }
 886
 887         int wp_num = watchpoint->set - 1;
 888         if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {
 889                 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
 890                 return ERROR_OK;
 891         }
 892         comparator_list[wp_num].used = 0;
 893         comparator_list[wp_num].bp_value = 0;
 894         target_write_u32(target, comparator_list[wp_num].reg_address +
 895                          ejtag_info->ejtag_dbc_offs, 0);
 896         watchpoint->set = 0;
 897
 898         return ERROR_OK;
 899 }
 900
 901 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 902 {
 903         struct mips32_common *mips32 = target_to_mips32(target);
 904
 905         if (mips32->num_data_bpoints_avail < 1) {
 906                 LOG_INFO("no hardware watchpoints available");
 907                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 908         }
 909
 910         mips32->num_data_bpoints_avail--;
 911
 912         mips_m4k_set_watchpoint(target, watchpoint);
 913         return ERROR_OK;
 914 }
 915
 916 static int mips_m4k_remove_watchpoint(struct target *target,
 917                 struct watchpoint *watchpoint)
 918 {
 919         /* get pointers to arch-specific information */
 920         struct mips32_common *mips32 = target_to_mips32(target);
 921
 922         if (target->state != TARGET_HALTED) {
 923                 LOG_WARNING("target not halted");
 924                 return ERROR_TARGET_NOT_HALTED;
 925         }
 926
 927         if (watchpoint->set)
 928                 mips_m4k_unset_watchpoint(target, watchpoint);
 929
 930         mips32->num_data_bpoints_avail++;
 931
 932         return ERROR_OK;
 933 }
 934
 935 static void mips_m4k_enable_watchpoints(struct target *target)
 936 {
 937         struct watchpoint *watchpoint = target->watchpoints;
 938
 939         /* set any pending watchpoints */
 940         while (watchpoint) {
 941                 if (watchpoint->set == 0)
 942                         mips_m4k_set_watchpoint(target, watchpoint);
 943                 watchpoint = watchpoint->next;
 944         }
 945 }
 946
 947 static int mips_m4k_read_memory(struct target *target, uint32_t address,
 948                 uint32_t size, uint32_t count, uint8_t *buffer)
 949 {
 950         struct mips32_common *mips32 = target_to_mips32(target);
 951         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 952
 953         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
 954                         address, size, count);
 955
 956         if (target->state != TARGET_HALTED) {
 957                 LOG_WARNING("target not halted");
 958                 return ERROR_TARGET_NOT_HALTED;
 959         }
 960
 961         /* sanitize arguments */
 962         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 963                 return ERROR_COMMAND_SYNTAX_ERROR;
 964
 965         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 966                 return ERROR_TARGET_UNALIGNED_ACCESS;
 967
 968         /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
 969         void *t = NULL;
 970
 971         if (size > 1) {
 972                 t = malloc(count * size * sizeof(uint8_t));
 973                 if (t == NULL) {
 974                         LOG_ERROR("Out of memory");
 975                         return ERROR_FAIL;
 976                 }
 977         } else
 978                 t = buffer;
 979
 980         /* if noDMA off, use DMAACC mode for memory read */
 981         int retval;
 982         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
 983                 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
 984         else
 985                 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
 986
 987         /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
 988         /* endianness, but byte array should represent target endianness       */
 989         if (ERROR_OK == retval) {
 990                 switch (size) {
 991                 case 4:
 992                         target_buffer_set_u32_array(target, buffer, count, t);
 993                         break;
 994                 case 2:
 995                         target_buffer_set_u16_array(target, buffer, count, t);
 996                         break;
 997                 }
 998         }
 999
1000         if ((size > 1) && (t != NULL))
1001                 free(t);
1002
1003         return retval;
1004 }
1005
1006 static int mips_m4k_write_memory(struct target *target, uint32_t address,
1007                 uint32_t size, uint32_t count, const uint8_t *buffer)
1008 {
1009         struct mips32_common *mips32 = target_to_mips32(target);
1010         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1011
1012         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1013                         address, size, count);
1014
1015         if (target->state != TARGET_HALTED) {
1016                 LOG_WARNING("target not halted");
1017                 return ERROR_TARGET_NOT_HALTED;
1018         }
1019
1020         if (size == 4 && count > 32) {
1021                 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1022                 if (retval == ERROR_OK)
1023                         return ERROR_OK;
1024                 LOG_WARNING("Falling back to non-bulk write");
1025         }
1026
1027         /* sanitize arguments */
1028         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1029                 return ERROR_COMMAND_SYNTAX_ERROR;
1030
1031         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1032                 return ERROR_TARGET_UNALIGNED_ACCESS;
1033
1034         /** correct endianess if we have word or hword access */
1035         void *t = NULL;
1036         if (size > 1) {
1037                 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1038                 /* endianness, but byte array represents target endianness               */
1039                 t = malloc(count * size * sizeof(uint8_t));
1040                 if (t == NULL) {
1041                         LOG_ERROR("Out of memory");
1042                         return ERROR_FAIL;
1043                 }
1044
1045                 switch (size) {
1046                 case 4:
1047                         target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1048                         break;
1049                 case 2:
1050                         target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1051                         break;
1052                 }
1053                 buffer = t;
1054         }
1055
1056         /* if noDMA off, use DMAACC mode for memory write */
1057         int retval;
1058         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1059                 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1060         else
1061                 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1062
1063         if (t != NULL)
1064                 free(t);
1065
1066         if (ERROR_OK != retval)
1067                 return retval;
1068
1069         return ERROR_OK;
1070 }
1071
1072 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1073                 struct target *target)
1074 {
1075         mips32_build_reg_cache(target);
1076
1077         return ERROR_OK;
1078 }
1079
1080 static int mips_m4k_init_arch_info(struct target *target,
1081                 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1082 {
1083         struct mips32_common *mips32 = &mips_m4k->mips32;
1084
1085         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1086
1087         /* initialize mips4k specific info */
1088         mips32_init_arch_info(target, mips32, tap);
1089         mips32->arch_info = mips_m4k;
1090
1091         return ERROR_OK;
1092 }
1093
1094 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1095 {
1096         struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1097
1098         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1099
1100         return ERROR_OK;
1101 }
1102
1103 static int mips_m4k_examine(struct target *target)
1104 {
1105         int retval;
1106         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1107         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1108         uint32_t idcode = 0;
1109
1110         if (!target_was_examined(target)) {
1111                 retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
1112                 if (retval != ERROR_OK)
1113                         return retval;
1114                 ejtag_info->idcode = idcode;
1115
1116                 if (((idcode >> 1) & 0x7FF) == 0x29) {
1117                         /* we are using a pic32mx so select ejtag port
1118                          * as it is not selected by default */
1119                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1120                         LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1121                         mips_m4k->is_pic32mx = true;
1122                 }
1123         }
1124
1125         /* init rest of ejtag interface */
1126         retval = mips_ejtag_init(ejtag_info);
1127         if (retval != ERROR_OK)
1128                 return retval;
1129
1130         retval = mips32_examine(target);
1131         if (retval != ERROR_OK)
1132                 return retval;
1133
1134         return ERROR_OK;
1135 }
1136
1137 static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
1138                 uint32_t count, const uint8_t *buffer)
1139 {
1140         struct mips32_common *mips32 = target_to_mips32(target);
1141         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1142         struct working_area *fast_data_area;
1143         int retval;
1144         int write_t = 1;
1145
1146         LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
1147
1148         /* check alignment */
1149         if (address & 0x3u)
1150                 return ERROR_TARGET_UNALIGNED_ACCESS;
1151
1152         if (mips32->fast_data_area == NULL) {
1153                 /* Get memory for block write handler
1154                  * we preserve this area between calls and gain a speed increase
1155                  * of about 3kb/sec when writing flash
1156                  * this will be released/nulled by the system when the target is resumed or reset */
1157                 retval = target_alloc_working_area(target,
1158                                 MIPS32_FASTDATA_HANDLER_SIZE,
1159                                 &mips32->fast_data_area);
1160                 if (retval != ERROR_OK) {
1161                         LOG_ERROR("No working area available");
1162                         return retval;
1163                 }
1164
1165                 /* reset fastadata state so the algo get reloaded */
1166                 ejtag_info->fast_access_save = -1;
1167         }
1168
1169         fast_data_area = mips32->fast_data_area;
1170
1171         if (address <= fast_data_area->address + fast_data_area->size &&
1172                         fast_data_area->address <= address + count) {
1173                 LOG_ERROR("fast_data (0x%8.8" PRIx32 ") is within write area "
1174                           "(0x%8.8" PRIx32 "-0x%8.8" PRIx32 ").",
1175                           fast_data_area->address, address, address + count);
1176                 LOG_ERROR("Change work-area-phys or load_image address!");
1177                 return ERROR_FAIL;
1178         }
1179
1180         /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1181         /* but byte array represents target endianness                      */
1182         uint32_t *t = NULL;
1183         t = malloc(count * sizeof(uint32_t));
1184         if (t == NULL) {
1185                 LOG_ERROR("Out of memory");
1186                 return ERROR_FAIL;
1187         }
1188
1189         target_buffer_get_u32_array(target, buffer, count, t);
1190
1191         retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1192                         count, t);
1193
1194         if (t != NULL)
1195                 free(t);
1196
1197         if (retval != ERROR_OK)
1198                 LOG_ERROR("Fastdata access Failed");
1199
1200         return retval;
1201 }
1202
1203 static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
1204                 struct mips_m4k_common *mips_m4k)
1205 {
1206         if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1207                 command_print(cmd_ctx, "target is not an MIPS_M4K");
1208                 return ERROR_TARGET_INVALID;
1209         }
1210         return ERROR_OK;
1211 }
1212
1213 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1214 {
1215         int retval;
1216         struct target *target = get_current_target(CMD_CTX);
1217         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1218         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1219
1220         retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
1221         if (retval != ERROR_OK)
1222                 return retval;
1223
1224         if (target->state != TARGET_HALTED) {
1225                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1226                 return ERROR_OK;
1227         }
1228
1229         /* two or more argument, access a single register/select (write if third argument is given) */
1230         if (CMD_ARGC < 2)
1231                 return ERROR_COMMAND_SYNTAX_ERROR;
1232         else {
1233                 uint32_t cp0_reg, cp0_sel;
1234                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1235                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1236
1237                 if (CMD_ARGC == 2) {
1238                         uint32_t value;
1239                         retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1240                         if (retval != ERROR_OK) {
1241                                 command_print(CMD_CTX,
1242                                                 "couldn't access reg %" PRIi32,
1243                                                 cp0_reg);
1244                                 return ERROR_OK;
1245                         }
1246                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1247                                         cp0_reg, cp0_sel, value);
1248
1249                 } else if (CMD_ARGC == 3) {
1250                         uint32_t value;
1251                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1252                         retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1253                         if (retval != ERROR_OK) {
1254                                 command_print(CMD_CTX,
1255                                                 "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
1256                                                 cp0_reg,  cp0_sel);
1257                                 return ERROR_OK;
1258                         }
1259                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1260                                         cp0_reg, cp0_sel, value);
1261                 }
1262         }
1263
1264         return ERROR_OK;
1265 }
1266
1267 COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
1268 {
1269         struct target *target = get_current_target(CMD_CTX);
1270         /* check target is an smp target */
1271         struct target_list *head;
1272         struct target *curr;
1273         head = target->head;
1274         target->smp = 0;
1275         if (head != (struct target_list *)NULL) {
1276                 while (head != (struct target_list *)NULL) {
1277                         curr = head->target;
1278                         curr->smp = 0;
1279                         head = head->next;
1280                 }
1281                 /*  fixes the target display to the debugger */
1282                 target->gdb_service->target = target;
1283         }
1284         return ERROR_OK;
1285 }
1286
1287 COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
1288 {
1289         struct target *target = get_current_target(CMD_CTX);
1290         struct target_list *head;
1291         struct target *curr;
1292         head = target->head;
1293         if (head != (struct target_list *)NULL) {
1294                 target->smp = 1;
1295                 while (head != (struct target_list *)NULL) {
1296                         curr = head->target;
1297                         curr->smp = 1;
1298                         head = head->next;
1299                 }
1300         }
1301         return ERROR_OK;
1302 }
1303
1304 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
1305 {
1306         struct target *target = get_current_target(CMD_CTX);
1307         int retval = ERROR_OK;
1308         struct target_list *head;
1309         head = target->head;
1310         if (head != (struct target_list *)NULL) {
1311                 if (CMD_ARGC == 1) {
1312                         int coreid = 0;
1313                         COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
1314                         if (ERROR_OK != retval)
1315                                 return retval;
1316                         target->gdb_service->core[1] = coreid;
1317
1318                 }
1319                 command_print(CMD_CTX, "gdb coreid  %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
1320                         , target->gdb_service->core[1]);
1321         }
1322         return ERROR_OK;
1323 }
1324
1325 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1326 {
1327         struct target *target = get_current_target(CMD_CTX);
1328         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1329         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1330
1331         if (CMD_ARGC == 1)
1332                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1333         else if (CMD_ARGC > 1)
1334                         return ERROR_COMMAND_SYNTAX_ERROR;
1335
1336         command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
1337         if (ejtag_info->scan_delay >= 20000000) {
1338                 ejtag_info->mode = 0;
1339                 command_print(CMD_CTX, "running in legacy mode");
1340         } else {
1341                 ejtag_info->mode = 1;
1342                 command_print(CMD_CTX, "running in fast queued mode");
1343         }
1344
1345         return ERROR_OK;
1346 }
1347
1348 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1349         {
1350                 .name = "cp0",
1351                 .handler = mips_m4k_handle_cp0_command,
1352                 .mode = COMMAND_EXEC,
1353                 .usage = "regnum [value]",
1354                 .help = "display/modify cp0 register",
1355         },
1356         {
1357                 .name = "smp_off",
1358                 .handler = mips_m4k_handle_smp_off_command,
1359                 .mode = COMMAND_EXEC,
1360                 .help = "Stop smp handling",
1361                 .usage = "",},
1362
1363         {
1364                 .name = "smp_on",
1365                 .handler = mips_m4k_handle_smp_on_command,
1366                 .mode = COMMAND_EXEC,
1367                 .help = "Restart smp handling",
1368                 .usage = "",
1369         },
1370         {
1371                 .name = "smp_gdb",
1372                 .handler = mips_m4k_handle_smp_gdb_command,
1373                 .mode = COMMAND_EXEC,
1374                 .help = "display/fix current core played to gdb",
1375                 .usage = "",
1376         },
1377         {
1378                 .name = "scan_delay",
1379                 .handler = mips_m4k_handle_scan_delay_command,
1380                 .mode = COMMAND_ANY,
1381                 .help = "display/set scan delay in nano seconds",
1382                 .usage = "[value]",
1383         },
1384         COMMAND_REGISTRATION_DONE
1385 };
1386
1387 const struct command_registration mips_m4k_command_handlers[] = {
1388         {
1389                 .chain = mips32_command_handlers,
1390         },
1391         {
1392                 .name = "mips_m4k",
1393                 .mode = COMMAND_ANY,
1394                 .help = "mips_m4k command group",
1395                 .usage = "",
1396                 .chain = mips_m4k_exec_command_handlers,
1397         },
1398         COMMAND_REGISTRATION_DONE
1399 };
1400
1401 struct target_type mips_m4k_target = {
1402         .name = "mips_m4k",
1403
1404         .poll = mips_m4k_poll,
1405         .arch_state = mips32_arch_state,
1406
1407         .halt = mips_m4k_halt,
1408         .resume = mips_m4k_resume,
1409         .step = mips_m4k_step,
1410
1411         .assert_reset = mips_m4k_assert_reset,
1412         .deassert_reset = mips_m4k_deassert_reset,
1413
1414         .get_gdb_reg_list = mips32_get_gdb_reg_list,
1415
1416         .read_memory = mips_m4k_read_memory,
1417         .write_memory = mips_m4k_write_memory,
1418         .checksum_memory = mips32_checksum_memory,
1419         .blank_check_memory = mips32_blank_check_memory,
1420
1421         .run_algorithm = mips32_run_algorithm,
1422
1423         .add_breakpoint = mips_m4k_add_breakpoint,
1424         .remove_breakpoint = mips_m4k_remove_breakpoint,
1425         .add_watchpoint = mips_m4k_add_watchpoint,
1426         .remove_watchpoint = mips_m4k_remove_watchpoint,
1427
1428         .commands = mips_m4k_command_handlers,
1429         .target_create = mips_m4k_target_create,
1430         .init_target = mips_m4k_init_target,
1431         .examine = mips_m4k_examine,
1432 };