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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
  10  *   drasko.draskovic@gmail.com                                            *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  24  ***************************************************************************/
  25
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "breakpoints.h"
  31 #include "mips32.h"
  32 #include "mips_m4k.h"
  33 #include "mips32_dmaacc.h"
  34 #include "target_type.h"
  35 #include "register.h"
  36
  37 static void mips_m4k_enable_breakpoints(struct target *target);
  38 static void mips_m4k_enable_watchpoints(struct target *target);
  39 static int mips_m4k_set_breakpoint(struct target *target,
  40                 struct breakpoint *breakpoint);
  41 static int mips_m4k_unset_breakpoint(struct target *target,
  42                 struct breakpoint *breakpoint);
  43 static int mips_m4k_internal_restore(struct target *target, int current,
  44                 target_addr_t address, int handle_breakpoints,
  45                 int debug_execution);
  46 static int mips_m4k_halt(struct target *target);
  47 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
  48                 uint32_t count, const uint8_t *buffer);
  49
  50 static int mips_m4k_examine_debug_reason(struct target *target)
  51 {
  52         struct mips32_common *mips32 = target_to_mips32(target);
  53         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  54         uint32_t break_status;
  55         int retval;
  56
  57         if ((target->debug_reason != DBG_REASON_DBGRQ)
  58                         && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
  59                 if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
  60                         /* get info about inst breakpoint support */
  61                         retval = target_read_u32(target,
  62                                 ejtag_info->ejtag_ibs_addr, &break_status);
  63                         if (retval != ERROR_OK)
  64                                 return retval;
  65                         if (break_status & 0x1f) {
  66                                 /* we have halted on a  breakpoint */
  67                                 retval = target_write_u32(target,
  68                                         ejtag_info->ejtag_ibs_addr, 0);
  69                                 if (retval != ERROR_OK)
  70                                         return retval;
  71                                 target->debug_reason = DBG_REASON_BREAKPOINT;
  72                         }
  73                 }
  74
  75                 if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
  76                         /* get info about data breakpoint support */
  77                         retval = target_read_u32(target,
  78                                 ejtag_info->ejtag_dbs_addr, &break_status);
  79                         if (retval != ERROR_OK)
  80                                 return retval;
  81                         if (break_status & 0x1f) {
  82                                 /* we have halted on a  breakpoint */
  83                                 retval = target_write_u32(target,
  84                                         ejtag_info->ejtag_dbs_addr, 0);
  85                                 if (retval != ERROR_OK)
  86                                         return retval;
  87                                 target->debug_reason = DBG_REASON_WATCHPOINT;
  88                         }
  89                 }
  90         }
  91
  92         return ERROR_OK;
  93 }
  94
  95 static int mips_m4k_debug_entry(struct target *target)
  96 {
  97         struct mips32_common *mips32 = target_to_mips32(target);
  98         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  99
 100         mips32_save_context(target);
 101
 102         /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
 103         mips_ejtag_config_step(ejtag_info, 0);
 104
 105         /* make sure break unit configured */
 106         mips32_configure_break_unit(target);
 107
 108         /* attempt to find halt reason */
 109         mips_m4k_examine_debug_reason(target);
 110
 111         mips32_read_config_regs(target);
 112
 113         /* default to mips32 isa, it will be changed below if required */
 114         mips32->isa_mode = MIPS32_ISA_MIPS32;
 115
 116         /* other than mips32 only and isa bit set ? */
 117         if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1))
 118                 mips32->isa_mode = mips32->isa_imp == 2 ? MIPS32_ISA_MIPS16E : MIPS32_ISA_MMIPS32;
 119
 120         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
 121                         buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
 122                         target_state_name(target));
 123
 124         return ERROR_OK;
 125 }
 126
 127 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
 128 {
 129         struct target_list *head;
 130         struct target *curr;
 131
 132         head = target->head;
 133         while (head != (struct target_list *)NULL) {
 134                 curr = head->target;
 135                 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
 136                         return curr;
 137                 head = head->next;
 138         }
 139         return target;
 140 }
 141
 142 static int mips_m4k_halt_smp(struct target *target)
 143 {
 144         int retval = ERROR_OK;
 145         struct target_list *head;
 146         struct target *curr;
 147         head = target->head;
 148         while (head != (struct target_list *)NULL) {
 149                 int ret = ERROR_OK;
 150                 curr = head->target;
 151                 if ((curr != target) && (curr->state != TARGET_HALTED))
 152                         ret = mips_m4k_halt(curr);
 153
 154                 if (ret != ERROR_OK) {
 155                         LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
 156                         retval = ret;
 157                 }
 158                 head = head->next;
 159         }
 160         return retval;
 161 }
 162
 163 static int update_halt_gdb(struct target *target)
 164 {
 165         int retval = ERROR_OK;
 166         if (target->gdb_service->core[0] == -1) {
 167                 target->gdb_service->target = target;
 168                 target->gdb_service->core[0] = target->coreid;
 169                 retval = mips_m4k_halt_smp(target);
 170         }
 171         return retval;
 172 }
 173
 174 static int mips_m4k_poll(struct target *target)
 175 {
 176         int retval = ERROR_OK;
 177         struct mips32_common *mips32 = target_to_mips32(target);
 178         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 179         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 180         enum target_state prev_target_state = target->state;
 181
 182         /*  toggle to another core is done by gdb as follow */
 183         /*  maint packet J core_id */
 184         /*  continue */
 185         /*  the next polling trigger an halt event sent to gdb */
 186         if ((target->state == TARGET_HALTED) && (target->smp) &&
 187                 (target->gdb_service) &&
 188                 (target->gdb_service->target == NULL)) {
 189                 target->gdb_service->target =
 190                         get_mips_m4k(target, target->gdb_service->core[1]);
 191                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 192                 return retval;
 193         }
 194
 195         /* read ejtag control reg */
 196         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 197         retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 198         if (retval != ERROR_OK)
 199                 return retval;
 200
 201         ejtag_info->isa = (ejtag_ctrl & EJTAG_CTRL_DBGISA) ? 1 : 0;
 202
 203         /* clear this bit before handling polling
 204          * as after reset registers will read zero */
 205         if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
 206                 /* we have detected a reset, clear flag
 207                  * otherwise ejtag will not work */
 208                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 209
 210                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 211                 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 212                 if (retval != ERROR_OK)
 213                         return retval;
 214                 LOG_DEBUG("Reset Detected");
 215         }
 216
 217         /* check for processor halted */
 218         if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
 219                 if ((target->state != TARGET_HALTED)
 220                     && (target->state != TARGET_DEBUG_RUNNING)) {
 221                         if (target->state == TARGET_UNKNOWN)
 222                                 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
 223
 224                         /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
 225                          * (maybe put on by HALT-ing the board in the previous session).
 226                          *
 227                          * Force enable debug entry for this session.
 228                          */
 229                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 230                         target->state = TARGET_HALTED;
 231                         retval = mips_m4k_debug_entry(target);
 232                         if (retval != ERROR_OK)
 233                                 return retval;
 234
 235                         if (target->smp &&
 236                                 ((prev_target_state == TARGET_RUNNING)
 237                              || (prev_target_state == TARGET_RESET))) {
 238                                 retval = update_halt_gdb(target);
 239                                 if (retval != ERROR_OK)
 240                                         return retval;
 241                         }
 242                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 243                 } else if (target->state == TARGET_DEBUG_RUNNING) {
 244                         target->state = TARGET_HALTED;
 245
 246                         retval = mips_m4k_debug_entry(target);
 247                         if (retval != ERROR_OK)
 248                                 return retval;
 249
 250                         if (target->smp) {
 251                                 retval = update_halt_gdb(target);
 252                                 if (retval != ERROR_OK)
 253                                         return retval;
 254                         }
 255
 256                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 257                 }
 258         } else
 259                 target->state = TARGET_RUNNING;
 260
 261 /*      LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
 262
 263         return ERROR_OK;
 264 }
 265
 266 static int mips_m4k_halt(struct target *target)
 267 {
 268         struct mips32_common *mips32 = target_to_mips32(target);
 269         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 270
 271         LOG_DEBUG("target->state: %s", target_state_name(target));
 272
 273         if (target->state == TARGET_HALTED) {
 274                 LOG_DEBUG("target was already halted");
 275                 return ERROR_OK;
 276         }
 277
 278         if (target->state == TARGET_UNKNOWN)
 279                 LOG_WARNING("target was in unknown state when halt was requested");
 280
 281         if (target->state == TARGET_RESET) {
 282                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 283                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 284                         return ERROR_TARGET_FAILURE;
 285                 } else {
 286                         /* we came here in a reset_halt or reset_init sequence
 287                          * debug entry was already prepared in mips_m4k_assert_reset()
 288                          */
 289                         target->debug_reason = DBG_REASON_DBGRQ;
 290
 291                         return ERROR_OK;
 292                 }
 293         }
 294
 295         /* break processor */
 296         mips_ejtag_enter_debug(ejtag_info);
 297
 298         target->debug_reason = DBG_REASON_DBGRQ;
 299
 300         return ERROR_OK;
 301 }
 302
 303 static int mips_m4k_assert_reset(struct target *target)
 304 {
 305         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
 306         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 307
 308         /* TODO: apply hw reset signal in not examined state */
 309         if (!(target_was_examined(target))) {
 310                 LOG_WARNING("Reset is not asserted because the target is not examined.");
 311                 LOG_WARNING("Use a reset button or power cycle the target.");
 312                 return ERROR_TARGET_NOT_EXAMINED;
 313         }
 314
 315         LOG_DEBUG("target->state: %s",
 316                 target_state_name(target));
 317
 318         enum reset_types jtag_reset_config = jtag_get_reset_config();
 319
 320         /* some cores support connecting while srst is asserted
 321          * use that mode is it has been configured */
 322
 323         bool srst_asserted = false;
 324
 325         if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
 326                         (jtag_reset_config & RESET_SRST_NO_GATING)) {
 327                 jtag_add_reset(0, 1);
 328                 srst_asserted = true;
 329         }
 330
 331
 332         /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
 333         if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
 334                 if (target->reset_halt) {
 335                         /* use hardware to catch reset */
 336                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
 337                 } else
 338                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 339         }
 340
 341         if (jtag_reset_config & RESET_HAS_SRST) {
 342                 /* here we should issue a srst only, but we may have to assert trst as well */
 343                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 344                         jtag_add_reset(1, 1);
 345                 else if (!srst_asserted)
 346                         jtag_add_reset(0, 1);
 347         } else {
 348                 if (mips_m4k->is_pic32mx) {
 349                         LOG_DEBUG("Using MTAP reset to reset processor...");
 350
 351                         /* use microchip specific MTAP reset */
 352                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
 353                         mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 354
 355                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
 356                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
 357                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 358                 } else {
 359                         /* use ejtag reset - not supported by all cores */
 360                         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 361                         LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 362                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 363                         mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
 364                 }
 365         }
 366
 367         target->state = TARGET_RESET;
 368         jtag_add_sleep(50000);
 369
 370         register_cache_invalidate(mips_m4k->mips32.core_cache);
 371
 372         if (target->reset_halt) {
 373                 int retval = target_halt(target);
 374                 if (retval != ERROR_OK)
 375                         return retval;
 376         }
 377
 378         return ERROR_OK;
 379 }
 380
 381 static int mips_m4k_deassert_reset(struct target *target)
 382 {
 383         LOG_DEBUG("target->state: %s", target_state_name(target));
 384
 385         /* deassert reset lines */
 386         jtag_add_reset(0, 0);
 387
 388         return ERROR_OK;
 389 }
 390
 391 static int mips_m4k_single_step_core(struct target *target)
 392 {
 393         struct mips32_common *mips32 = target_to_mips32(target);
 394         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 395
 396         /* configure single step mode */
 397         mips_ejtag_config_step(ejtag_info, 1);
 398
 399         /* disable interrupts while stepping */
 400         mips32_enable_interrupts(target, 0);
 401
 402         /* exit debug mode */
 403         mips_ejtag_exit_debug(ejtag_info);
 404
 405         mips_m4k_debug_entry(target);
 406
 407         return ERROR_OK;
 408 }
 409
 410 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
 411 {
 412         int retval = ERROR_OK;
 413         struct target_list *head;
 414         struct target *curr;
 415
 416         head = target->head;
 417         while (head != (struct target_list *)NULL) {
 418                 int ret = ERROR_OK;
 419                 curr = head->target;
 420                 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
 421                         /*  resume current address , not in step mode */
 422                         ret = mips_m4k_internal_restore(curr, 1, address,
 423                                                    handle_breakpoints, 0);
 424
 425                         if (ret != ERROR_OK) {
 426                                 LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
 427                                                   curr->coreid, address);
 428                                 retval = ret;
 429                         }
 430                 }
 431                 head = head->next;
 432         }
 433         return retval;
 434 }
 435
 436 static int mips_m4k_internal_restore(struct target *target, int current,
 437                 target_addr_t address, int handle_breakpoints, int debug_execution)
 438 {
 439         struct mips32_common *mips32 = target_to_mips32(target);
 440         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 441         struct breakpoint *breakpoint = NULL;
 442         uint32_t resume_pc;
 443
 444         if (target->state != TARGET_HALTED) {
 445                 LOG_WARNING("target not halted");
 446                 return ERROR_TARGET_NOT_HALTED;
 447         }
 448
 449         if (!debug_execution) {
 450                 target_free_all_working_areas(target);
 451                 mips_m4k_enable_breakpoints(target);
 452                 mips_m4k_enable_watchpoints(target);
 453         }
 454
 455         /* current = 1: continue on current pc, otherwise continue at <address> */
 456         if (!current) {
 457                 mips_m4k_isa_filter(mips32->isa_imp, &address);
 458                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 459                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 460                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 461         }
 462
 463         if ((mips32->isa_imp > 1) &&  debug_execution)  /* if more than one isa supported */
 464                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
 465
 466         if (!current)
 467                 resume_pc = address;
 468         else
 469                 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 470
 471         mips32_restore_context(target);
 472
 473         /* the front-end may request us not to handle breakpoints */
 474         if (handle_breakpoints) {
 475                 /* Single step past breakpoint at current address */
 476                 breakpoint = breakpoint_find(target, resume_pc);
 477                 if (breakpoint) {
 478                         LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
 479                                           breakpoint->address);
 480                         mips_m4k_unset_breakpoint(target, breakpoint);
 481                         mips_m4k_single_step_core(target);
 482                         mips_m4k_set_breakpoint(target, breakpoint);
 483                 }
 484         }
 485
 486         /* enable interrupts if we are running */
 487         mips32_enable_interrupts(target, !debug_execution);
 488
 489         /* exit debug mode */
 490         mips_ejtag_exit_debug(ejtag_info);
 491         target->debug_reason = DBG_REASON_NOTHALTED;
 492
 493         /* registers are now invalid */
 494         register_cache_invalidate(mips32->core_cache);
 495
 496         if (!debug_execution) {
 497                 target->state = TARGET_RUNNING;
 498                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 499                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 500         } else {
 501                 target->state = TARGET_DEBUG_RUNNING;
 502                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 503                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 504         }
 505
 506         return ERROR_OK;
 507 }
 508
 509 static int mips_m4k_resume(struct target *target, int current,
 510                 target_addr_t address, int handle_breakpoints, int debug_execution)
 511 {
 512         int retval = ERROR_OK;
 513
 514         /* dummy resume for smp toggle in order to reduce gdb impact  */
 515         if ((target->smp) && (target->gdb_service->core[1] != -1)) {
 516                 /*   simulate a start and halt of target */
 517                 target->gdb_service->target = NULL;
 518                 target->gdb_service->core[0] = target->gdb_service->core[1];
 519                 /*  fake resume at next poll we play the  target core[1], see poll*/
 520                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 521                 return retval;
 522         }
 523
 524         retval = mips_m4k_internal_restore(target, current, address,
 525                                 handle_breakpoints,
 526                                 debug_execution);
 527
 528         if (retval == ERROR_OK && target->smp) {
 529                 target->gdb_service->core[0] = -1;
 530                 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
 531         }
 532
 533         return retval;
 534 }
 535
 536 static int mips_m4k_step(struct target *target, int current,
 537                 target_addr_t address, int handle_breakpoints)
 538 {
 539         /* get pointers to arch-specific information */
 540         struct mips32_common *mips32 = target_to_mips32(target);
 541         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 542         struct breakpoint *breakpoint = NULL;
 543
 544         if (target->state != TARGET_HALTED) {
 545                 LOG_WARNING("target not halted");
 546                 return ERROR_TARGET_NOT_HALTED;
 547         }
 548
 549         /* current = 1: continue on current pc, otherwise continue at <address> */
 550         if (!current) {
 551                 mips_m4k_isa_filter(mips32->isa_imp, &address);
 552                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 553                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 554                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 555         }
 556
 557         /* the front-end may request us not to handle breakpoints */
 558         if (handle_breakpoints) {
 559                 breakpoint = breakpoint_find(target,
 560                                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 561                 if (breakpoint)
 562                         mips_m4k_unset_breakpoint(target, breakpoint);
 563         }
 564
 565         /* restore context */
 566         mips32_restore_context(target);
 567
 568         /* configure single step mode */
 569         mips_ejtag_config_step(ejtag_info, 1);
 570
 571         target->debug_reason = DBG_REASON_SINGLESTEP;
 572
 573         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 574
 575         /* disable interrupts while stepping */
 576         mips32_enable_interrupts(target, 0);
 577
 578         /* exit debug mode */
 579         mips_ejtag_exit_debug(ejtag_info);
 580
 581         /* registers are now invalid */
 582         register_cache_invalidate(mips32->core_cache);
 583
 584         LOG_DEBUG("target stepped ");
 585         mips_m4k_debug_entry(target);
 586
 587         if (breakpoint)
 588                 mips_m4k_set_breakpoint(target, breakpoint);
 589
 590         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 591
 592         return ERROR_OK;
 593 }
 594
 595 static void mips_m4k_enable_breakpoints(struct target *target)
 596 {
 597         struct breakpoint *breakpoint = target->breakpoints;
 598
 599         /* set any pending breakpoints */
 600         while (breakpoint) {
 601                 if (breakpoint->set == 0)
 602                         mips_m4k_set_breakpoint(target, breakpoint);
 603                 breakpoint = breakpoint->next;
 604         }
 605 }
 606
 607 static int mips_m4k_set_breakpoint(struct target *target,
 608                 struct breakpoint *breakpoint)
 609 {
 610         struct mips32_common *mips32 = target_to_mips32(target);
 611         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 612         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 613         int retval;
 614
 615         if (breakpoint->set) {
 616                 LOG_WARNING("breakpoint already set");
 617                 return ERROR_OK;
 618         }
 619
 620         if (breakpoint->type == BKPT_HARD) {
 621                 int bp_num = 0;
 622
 623                 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 624                         bp_num++;
 625                 if (bp_num >= mips32->num_inst_bpoints) {
 626                         LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
 627                                         breakpoint->unique_id);
 628                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 629                 }
 630                 breakpoint->set = bp_num + 1;
 631                 comparator_list[bp_num].used = 1;
 632                 comparator_list[bp_num].bp_value = breakpoint->address;
 633
 634                 if (breakpoint->length != 4)                    /* make sure isa bit set */
 635                         comparator_list[bp_num].bp_value |= 1;
 636                 else                                            /* make sure isa bit cleared */
 637                         comparator_list[bp_num].bp_value &= ~1;
 638
 639                 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
 640                  * Warning: there is no IB ASID registers in 2.0.
 641                  * Do not set it! :) */
 642                 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 643                         comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
 644
 645                 target_write_u32(target, comparator_list[bp_num].reg_address,
 646                                 comparator_list[bp_num].bp_value);
 647                 target_write_u32(target, comparator_list[bp_num].reg_address +
 648                                  ejtag_info->ejtag_ibm_offs, 0x00000000);
 649                 target_write_u32(target, comparator_list[bp_num].reg_address +
 650                                  ejtag_info->ejtag_ibc_offs, 1);
 651                 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
 652                                   breakpoint->unique_id,
 653                                   bp_num, comparator_list[bp_num].bp_value);
 654         } else if (breakpoint->type == BKPT_SOFT) {
 655                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 656
 657                 uint32_t isa_req = breakpoint->length & 1;      /* micro mips request bit */
 658                 uint32_t bplength = breakpoint->length & ~1;    /* drop micro mips request bit for length */
 659                 uint32_t bpaddr = breakpoint->address & ~1;     /* drop isa bit from address, if set */
 660
 661                 if (bplength == 4) {
 662                         uint32_t verify = 0xffffffff;
 663                         uint32_t sdbbp32_instr = MIPS32_SDBBP(isa_req);
 664                         if (ejtag_info->endianness && isa_req)
 665                                 sdbbp32_instr = SWAP16(sdbbp32_instr);
 666
 667                         if ((breakpoint->address & 3) == 0) {   /* word alligned */
 668
 669                                 retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
 670                                 if (retval != ERROR_OK)
 671                                         return retval;
 672
 673                                 retval = target_write_u32(target, bpaddr, sdbbp32_instr);
 674                                 if (retval != ERROR_OK)
 675                                         return retval;
 676
 677                                 retval = target_read_u32(target, bpaddr, &verify);
 678                                 if (retval != ERROR_OK)
 679                                         return retval;
 680
 681                                 if (verify != sdbbp32_instr)
 682                                         verify = 0;
 683
 684                         } else {        /* 16 bit aligned */
 685                                 retval = target_read_memory(target, bpaddr, 2, 2, breakpoint->orig_instr);
 686                                 if (retval != ERROR_OK)
 687                                         return retval;
 688
 689                                 uint8_t sdbbp_buf[4];
 690                                 target_buffer_set_u32(target, sdbbp_buf, sdbbp32_instr);
 691
 692                                 retval = target_write_memory(target, bpaddr, 2, 2, sdbbp_buf);
 693                                 if (retval != ERROR_OK)
 694                                         return retval;
 695
 696                                 retval = target_read_memory(target, bpaddr, 2, 2, sdbbp_buf);
 697                                 if (retval != ERROR_OK)
 698                                         return retval;
 699
 700                                 if (target_buffer_get_u32(target, sdbbp_buf) != sdbbp32_instr)
 701                                         verify = 0;
 702                         }
 703
 704                         if (verify == 0) {
 705                                 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx64
 706                                         " - check that memory is read/writable", breakpoint->address);
 707                                 return ERROR_OK;
 708                         }
 709
 710                 } else {
 711                         uint16_t verify = 0xffff;
 712
 713                         retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
 714                         if (retval != ERROR_OK)
 715                                 return retval;
 716
 717                         retval = target_write_u16(target, bpaddr, MIPS16_SDBBP(isa_req));
 718                         if (retval != ERROR_OK)
 719                                 return retval;
 720
 721                         retval = target_read_u16(target, bpaddr, &verify);
 722                         if (retval != ERROR_OK)
 723                                 return retval;
 724
 725                         if (verify != MIPS16_SDBBP(isa_req)) {
 726                                 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx64
 727                                                 " - check that memory is read/writable", breakpoint->address);
 728                                 return ERROR_OK;
 729                         }
 730                 }
 731
 732                 breakpoint->set = 20; /* Any nice value but 0 */
 733         }
 734
 735         return ERROR_OK;
 736 }
 737
 738 static int mips_m4k_unset_breakpoint(struct target *target,
 739                 struct breakpoint *breakpoint)
 740 {
 741         /* get pointers to arch-specific information */
 742         struct mips32_common *mips32 = target_to_mips32(target);
 743         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 744         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 745         int retval;
 746
 747         if (!breakpoint->set) {
 748                 LOG_WARNING("breakpoint not set");
 749                 return ERROR_OK;
 750         }
 751
 752         if (breakpoint->type == BKPT_HARD) {
 753                 int bp_num = breakpoint->set - 1;
 754                 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) {
 755                         LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
 756                                           breakpoint->unique_id);
 757                         return ERROR_OK;
 758                 }
 759                 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
 760                                 breakpoint->unique_id,
 761                                 bp_num);
 762                 comparator_list[bp_num].used = 0;
 763                 comparator_list[bp_num].bp_value = 0;
 764                 target_write_u32(target, comparator_list[bp_num].reg_address +
 765                                  ejtag_info->ejtag_ibc_offs, 0);
 766
 767         } else {
 768                 /* restore original instruction (kept in target endianness) */
 769                 uint32_t isa_req = breakpoint->length & 1;
 770                 uint32_t bplength = breakpoint->length & ~1;
 771                 uint8_t current_instr[4];
 772                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 773                 if (bplength == 4) {
 774                         uint32_t sdbbp32_instr =  MIPS32_SDBBP(isa_req);
 775                         if (ejtag_info->endianness && isa_req)
 776                                 sdbbp32_instr = SWAP16(sdbbp32_instr);
 777
 778                         if ((breakpoint->address & 3) == 0) {           /* 32bit aligned */
 779                                 /* check that user program has not modified breakpoint instruction */
 780                                 retval = target_read_memory(target, breakpoint->address, 4, 1, current_instr);
 781                                 if (retval != ERROR_OK)
 782                                         return retval;
 783                                 /**
 784                                 * target_read_memory() gets us data in _target_ endianess.
 785                                 * If we want to use this data on the host for comparisons with some macros
 786                                 * we must first transform it to _host_ endianess using target_buffer_get_u16().
 787                                 */
 788                                 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
 789                                         retval = target_write_memory(target, breakpoint->address, 4, 1,
 790                                                                                 breakpoint->orig_instr);
 791                                         if (retval != ERROR_OK)
 792                                                 return retval;
 793                                 }
 794                         } else {        /* 16bit alligned */
 795                                 retval = target_read_memory(target, breakpoint->address, 2, 2, current_instr);
 796                                 if (retval != ERROR_OK)
 797                                         return retval;
 798
 799                                 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
 800                                         retval = target_write_memory(target, breakpoint->address, 2, 2,
 801                                                                                 breakpoint->orig_instr);
 802                                         if (retval != ERROR_OK)
 803                                                 return retval;
 804                                 }
 805                         }
 806                 } else {
 807                         /* check that user program has not modified breakpoint instruction */
 808                         retval = target_read_memory(target, breakpoint->address, 2, 1, current_instr);
 809                         if (retval != ERROR_OK)
 810                                 return retval;
 811
 812                         if (target_buffer_get_u16(target, current_instr) == MIPS16_SDBBP(isa_req)) {
 813                                 retval = target_write_memory(target, breakpoint->address, 2, 1,
 814                                                                         breakpoint->orig_instr);
 815                                 if (retval != ERROR_OK)
 816                                         return retval;
 817                         }
 818                 }
 819         }
 820
 821         breakpoint->set = 0;
 822
 823         return ERROR_OK;
 824 }
 825
 826 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 827 {
 828         struct mips32_common *mips32 = target_to_mips32(target);
 829
 830         if ((breakpoint->length > 5 || breakpoint->length < 2) ||               /* out of range */
 831                 (breakpoint->length == 4 && (breakpoint->address & 2)) ||       /* mips32 unaligned */
 832                 (mips32->isa_imp == MIPS32_ONLY && breakpoint->length != 4) ||  /* misp32 specific */
 833                 ((mips32->isa_imp & 1) != (breakpoint->length & 1)))            /* isa not implemented */
 834                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 835
 836         if (breakpoint->type == BKPT_HARD) {
 837                 if (mips32->num_inst_bpoints_avail < 1) {
 838                         LOG_INFO("no hardware breakpoint available");
 839                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 840                 }
 841
 842                 mips32->num_inst_bpoints_avail--;
 843         }
 844
 845         return mips_m4k_set_breakpoint(target, breakpoint);
 846 }
 847
 848 static int mips_m4k_remove_breakpoint(struct target *target,
 849                 struct breakpoint *breakpoint)
 850 {
 851         /* get pointers to arch-specific information */
 852         struct mips32_common *mips32 = target_to_mips32(target);
 853
 854         if (target->state != TARGET_HALTED) {
 855                 LOG_WARNING("target not halted");
 856                 return ERROR_TARGET_NOT_HALTED;
 857         }
 858
 859         if (breakpoint->set)
 860                 mips_m4k_unset_breakpoint(target, breakpoint);
 861
 862         if (breakpoint->type == BKPT_HARD)
 863                 mips32->num_inst_bpoints_avail++;
 864
 865         return ERROR_OK;
 866 }
 867
 868 static int mips_m4k_set_watchpoint(struct target *target,
 869                 struct watchpoint *watchpoint)
 870 {
 871         struct mips32_common *mips32 = target_to_mips32(target);
 872         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 873         struct mips32_comparator *comparator_list = mips32->data_break_list;
 874         int wp_num = 0;
 875         /*
 876          * watchpoint enabled, ignore all byte lanes in value register
 877          * and exclude both load and store accesses from  watchpoint
 878          * condition evaluation
 879         */
 880         int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
 881                         (0xff << EJTAG_DBCn_BLM_SHIFT);
 882
 883         if (watchpoint->set) {
 884                 LOG_WARNING("watchpoint already set");
 885                 return ERROR_OK;
 886         }
 887
 888         while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
 889                 wp_num++;
 890         if (wp_num >= mips32->num_data_bpoints) {
 891                 LOG_ERROR("Can not find free FP Comparator");
 892                 return ERROR_FAIL;
 893         }
 894
 895         if (watchpoint->length != 4) {
 896                 LOG_ERROR("Only watchpoints of length 4 are supported");
 897                 return ERROR_TARGET_UNALIGNED_ACCESS;
 898         }
 899
 900         if (watchpoint->address % 4) {
 901                 LOG_ERROR("Watchpoints address should be word aligned");
 902                 return ERROR_TARGET_UNALIGNED_ACCESS;
 903         }
 904
 905         switch (watchpoint->rw) {
 906                 case WPT_READ:
 907                         enable &= ~EJTAG_DBCn_NOLB;
 908                         break;
 909                 case WPT_WRITE:
 910                         enable &= ~EJTAG_DBCn_NOSB;
 911                         break;
 912                 case WPT_ACCESS:
 913                         enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
 914                         break;
 915                 default:
 916                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
 917         }
 918
 919         watchpoint->set = wp_num + 1;
 920         comparator_list[wp_num].used = 1;
 921         comparator_list[wp_num].bp_value = watchpoint->address;
 922
 923         /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
 924          * There is as well no ASID register support. */
 925         if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 926                 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
 927         else
 928                 target_write_u32(target, comparator_list[wp_num].reg_address +
 929                          ejtag_info->ejtag_dbasid_offs, 0x00000000);
 930
 931         target_write_u32(target, comparator_list[wp_num].reg_address,
 932                          comparator_list[wp_num].bp_value);
 933         target_write_u32(target, comparator_list[wp_num].reg_address +
 934                          ejtag_info->ejtag_dbm_offs, 0x00000000);
 935
 936         target_write_u32(target, comparator_list[wp_num].reg_address +
 937                          ejtag_info->ejtag_dbc_offs, enable);
 938         /* TODO: probably this value is ignored on 2.0 */
 939         target_write_u32(target, comparator_list[wp_num].reg_address +
 940                          ejtag_info->ejtag_dbv_offs, 0);
 941         LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
 942
 943         return ERROR_OK;
 944 }
 945
 946 static int mips_m4k_unset_watchpoint(struct target *target,
 947                 struct watchpoint *watchpoint)
 948 {
 949         /* get pointers to arch-specific information */
 950         struct mips32_common *mips32 = target_to_mips32(target);
 951         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 952         struct mips32_comparator *comparator_list = mips32->data_break_list;
 953
 954         if (!watchpoint->set) {
 955                 LOG_WARNING("watchpoint not set");
 956                 return ERROR_OK;
 957         }
 958
 959         int wp_num = watchpoint->set - 1;
 960         if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) {
 961                 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
 962                 return ERROR_OK;
 963         }
 964         comparator_list[wp_num].used = 0;
 965         comparator_list[wp_num].bp_value = 0;
 966         target_write_u32(target, comparator_list[wp_num].reg_address +
 967                          ejtag_info->ejtag_dbc_offs, 0);
 968         watchpoint->set = 0;
 969
 970         return ERROR_OK;
 971 }
 972
 973 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 974 {
 975         struct mips32_common *mips32 = target_to_mips32(target);
 976
 977         if (mips32->num_data_bpoints_avail < 1) {
 978                 LOG_INFO("no hardware watchpoints available");
 979                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 980         }
 981
 982         mips32->num_data_bpoints_avail--;
 983
 984         mips_m4k_set_watchpoint(target, watchpoint);
 985         return ERROR_OK;
 986 }
 987
 988 static int mips_m4k_remove_watchpoint(struct target *target,
 989                 struct watchpoint *watchpoint)
 990 {
 991         /* get pointers to arch-specific information */
 992         struct mips32_common *mips32 = target_to_mips32(target);
 993
 994         if (target->state != TARGET_HALTED) {
 995                 LOG_WARNING("target not halted");
 996                 return ERROR_TARGET_NOT_HALTED;
 997         }
 998
 999         if (watchpoint->set)
1000                 mips_m4k_unset_watchpoint(target, watchpoint);
1001
1002         mips32->num_data_bpoints_avail++;
1003
1004         return ERROR_OK;
1005 }
1006
1007 static void mips_m4k_enable_watchpoints(struct target *target)
1008 {
1009         struct watchpoint *watchpoint = target->watchpoints;
1010
1011         /* set any pending watchpoints */
1012         while (watchpoint) {
1013                 if (watchpoint->set == 0)
1014                         mips_m4k_set_watchpoint(target, watchpoint);
1015                 watchpoint = watchpoint->next;
1016         }
1017 }
1018
1019 static int mips_m4k_read_memory(struct target *target, target_addr_t address,
1020                 uint32_t size, uint32_t count, uint8_t *buffer)
1021 {
1022         struct mips32_common *mips32 = target_to_mips32(target);
1023         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1024
1025         LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1026                         address, size, count);
1027
1028         if (target->state != TARGET_HALTED) {
1029                 LOG_WARNING("target not halted");
1030                 return ERROR_TARGET_NOT_HALTED;
1031         }
1032
1033         /* sanitize arguments */
1034         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1035                 return ERROR_COMMAND_SYNTAX_ERROR;
1036
1037         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1038                 return ERROR_TARGET_UNALIGNED_ACCESS;
1039
1040         /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
1041         void *t = NULL;
1042
1043         if (size > 1) {
1044                 t = malloc(count * size * sizeof(uint8_t));
1045                 if (t == NULL) {
1046                         LOG_ERROR("Out of memory");
1047                         return ERROR_FAIL;
1048                 }
1049         } else
1050                 t = buffer;
1051
1052         /* if noDMA off, use DMAACC mode for memory read */
1053         int retval;
1054         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1055                 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
1056         else
1057                 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
1058
1059         /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
1060         /* endianness, but byte array should represent target endianness       */
1061         if (ERROR_OK == retval) {
1062                 switch (size) {
1063                 case 4:
1064                         target_buffer_set_u32_array(target, buffer, count, t);
1065                         break;
1066                 case 2:
1067                         target_buffer_set_u16_array(target, buffer, count, t);
1068                         break;
1069                 }
1070         }
1071
1072         if ((size > 1) && (t != NULL))
1073                 free(t);
1074
1075         return retval;
1076 }
1077
1078 static int mips_m4k_write_memory(struct target *target, target_addr_t address,
1079                 uint32_t size, uint32_t count, const uint8_t *buffer)
1080 {
1081         struct mips32_common *mips32 = target_to_mips32(target);
1082         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1083
1084         LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1085                         address, size, count);
1086
1087         if (target->state != TARGET_HALTED) {
1088                 LOG_WARNING("target not halted");
1089                 return ERROR_TARGET_NOT_HALTED;
1090         }
1091
1092         if (size == 4 && count > 32) {
1093                 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1094                 if (retval == ERROR_OK)
1095                         return ERROR_OK;
1096                 LOG_WARNING("Falling back to non-bulk write");
1097         }
1098
1099         /* sanitize arguments */
1100         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1101                 return ERROR_COMMAND_SYNTAX_ERROR;
1102
1103         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1104                 return ERROR_TARGET_UNALIGNED_ACCESS;
1105
1106         /** correct endianess if we have word or hword access */
1107         void *t = NULL;
1108         if (size > 1) {
1109                 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1110                 /* endianness, but byte array represents target endianness               */
1111                 t = malloc(count * size * sizeof(uint8_t));
1112                 if (t == NULL) {
1113                         LOG_ERROR("Out of memory");
1114                         return ERROR_FAIL;
1115                 }
1116
1117                 switch (size) {
1118                 case 4:
1119                         target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1120                         break;
1121                 case 2:
1122                         target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1123                         break;
1124                 }
1125                 buffer = t;
1126         }
1127
1128         /* if noDMA off, use DMAACC mode for memory write */
1129         int retval;
1130         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1131                 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1132         else
1133                 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1134
1135         if (t != NULL)
1136                 free(t);
1137
1138         if (ERROR_OK != retval)
1139                 return retval;
1140
1141         return ERROR_OK;
1142 }
1143
1144 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1145                 struct target *target)
1146 {
1147         mips32_build_reg_cache(target);
1148
1149         return ERROR_OK;
1150 }
1151
1152 static int mips_m4k_init_arch_info(struct target *target,
1153                 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1154 {
1155         struct mips32_common *mips32 = &mips_m4k->mips32;
1156
1157         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1158
1159         /* initialize mips4k specific info */
1160         mips32_init_arch_info(target, mips32, tap);
1161         mips32->arch_info = mips_m4k;
1162
1163         return ERROR_OK;
1164 }
1165
1166 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1167 {
1168         struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1169
1170         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1171
1172         return ERROR_OK;
1173 }
1174
1175 static int mips_m4k_examine(struct target *target)
1176 {
1177         int retval;
1178         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1179         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1180         uint32_t idcode = 0;
1181
1182         if (!target_was_examined(target)) {
1183                 retval = mips_ejtag_get_idcode(ejtag_info, &idcode);
1184                 if (retval != ERROR_OK)
1185                         return retval;
1186                 ejtag_info->idcode = idcode;
1187
1188                 if (((idcode >> 1) & 0x7FF) == 0x29) {
1189                         /* we are using a pic32mx so select ejtag port
1190                          * as it is not selected by default */
1191                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1192                         LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1193                         mips_m4k->is_pic32mx = true;
1194                 }
1195         }
1196
1197         /* init rest of ejtag interface */
1198         retval = mips_ejtag_init(ejtag_info);
1199         if (retval != ERROR_OK)
1200                 return retval;
1201
1202         retval = mips32_examine(target);
1203         if (retval != ERROR_OK)
1204                 return retval;
1205
1206         return ERROR_OK;
1207 }
1208
1209 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
1210                 uint32_t count, const uint8_t *buffer)
1211 {
1212         struct mips32_common *mips32 = target_to_mips32(target);
1213         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1214         struct working_area *fast_data_area;
1215         int retval;
1216         int write_t = 1;
1217
1218         LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
1219                           address, count);
1220
1221         /* check alignment */
1222         if (address & 0x3u)
1223                 return ERROR_TARGET_UNALIGNED_ACCESS;
1224
1225         if (mips32->fast_data_area == NULL) {
1226                 /* Get memory for block write handler
1227                  * we preserve this area between calls and gain a speed increase
1228                  * of about 3kb/sec when writing flash
1229                  * this will be released/nulled by the system when the target is resumed or reset */
1230                 retval = target_alloc_working_area(target,
1231                                 MIPS32_FASTDATA_HANDLER_SIZE,
1232                                 &mips32->fast_data_area);
1233                 if (retval != ERROR_OK) {
1234                         LOG_ERROR("No working area available");
1235                         return retval;
1236                 }
1237
1238                 /* reset fastadata state so the algo get reloaded */
1239                 ejtag_info->fast_access_save = -1;
1240         }
1241
1242         fast_data_area = mips32->fast_data_area;
1243
1244         if (address <= fast_data_area->address + fast_data_area->size &&
1245                         fast_data_area->address <= address + count) {
1246                 LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area "
1247                           "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
1248                           fast_data_area->address, address, address + count);
1249                 LOG_ERROR("Change work-area-phys or load_image address!");
1250                 return ERROR_FAIL;
1251         }
1252
1253         /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1254         /* but byte array represents target endianness                      */
1255         uint32_t *t = NULL;
1256         t = malloc(count * sizeof(uint32_t));
1257         if (t == NULL) {
1258                 LOG_ERROR("Out of memory");
1259                 return ERROR_FAIL;
1260         }
1261
1262         target_buffer_get_u32_array(target, buffer, count, t);
1263
1264         retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1265                         count, t);
1266
1267         if (t != NULL)
1268                 free(t);
1269
1270         if (retval != ERROR_OK)
1271                 LOG_ERROR("Fastdata access Failed");
1272
1273         return retval;
1274 }
1275
1276 static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
1277                 struct mips_m4k_common *mips_m4k)
1278 {
1279         if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1280                 command_print(cmd_ctx, "target is not an MIPS_M4K");
1281                 return ERROR_TARGET_INVALID;
1282         }
1283         return ERROR_OK;
1284 }
1285
1286 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1287 {
1288         int retval;
1289         struct target *target = get_current_target(CMD_CTX);
1290         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1291         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1292
1293         retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
1294         if (retval != ERROR_OK)
1295                 return retval;
1296
1297         if (target->state != TARGET_HALTED) {
1298                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1299                 return ERROR_OK;
1300         }
1301
1302         /* two or more argument, access a single register/select (write if third argument is given) */
1303         if (CMD_ARGC < 2)
1304                 return ERROR_COMMAND_SYNTAX_ERROR;
1305         else {
1306                 uint32_t cp0_reg, cp0_sel;
1307                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1308                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1309
1310                 if (CMD_ARGC == 2) {
1311                         uint32_t value;
1312                         retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1313                         if (retval != ERROR_OK) {
1314                                 command_print(CMD_CTX,
1315                                                 "couldn't access reg %" PRIi32,
1316                                                 cp0_reg);
1317                                 return ERROR_OK;
1318                         }
1319                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1320                                         cp0_reg, cp0_sel, value);
1321
1322                 } else if (CMD_ARGC == 3) {
1323                         uint32_t value;
1324                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1325                         retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1326                         if (retval != ERROR_OK) {
1327                                 command_print(CMD_CTX,
1328                                                 "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
1329                                                 cp0_reg,  cp0_sel);
1330                                 return ERROR_OK;
1331                         }
1332                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
1333                                         cp0_reg, cp0_sel, value);
1334                 }
1335         }
1336
1337         return ERROR_OK;
1338 }
1339
1340 COMMAND_HANDLER(mips_m4k_handle_smp_off_command)
1341 {
1342         struct target *target = get_current_target(CMD_CTX);
1343         /* check target is an smp target */
1344         struct target_list *head;
1345         struct target *curr;
1346         head = target->head;
1347         target->smp = 0;
1348         if (head != (struct target_list *)NULL) {
1349                 while (head != (struct target_list *)NULL) {
1350                         curr = head->target;
1351                         curr->smp = 0;
1352                         head = head->next;
1353                 }
1354                 /*  fixes the target display to the debugger */
1355                 target->gdb_service->target = target;
1356         }
1357         return ERROR_OK;
1358 }
1359
1360 COMMAND_HANDLER(mips_m4k_handle_smp_on_command)
1361 {
1362         struct target *target = get_current_target(CMD_CTX);
1363         struct target_list *head;
1364         struct target *curr;
1365         head = target->head;
1366         if (head != (struct target_list *)NULL) {
1367                 target->smp = 1;
1368                 while (head != (struct target_list *)NULL) {
1369                         curr = head->target;
1370                         curr->smp = 1;
1371                         head = head->next;
1372                 }
1373         }
1374         return ERROR_OK;
1375 }
1376
1377 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command)
1378 {
1379         struct target *target = get_current_target(CMD_CTX);
1380         int retval = ERROR_OK;
1381         struct target_list *head;
1382         head = target->head;
1383         if (head != (struct target_list *)NULL) {
1384                 if (CMD_ARGC == 1) {
1385                         int coreid = 0;
1386                         COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
1387                         if (ERROR_OK != retval)
1388                                 return retval;
1389                         target->gdb_service->core[1] = coreid;
1390
1391                 }
1392                 command_print(CMD_CTX, "gdb coreid  %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
1393                         , target->gdb_service->core[1]);
1394         }
1395         return ERROR_OK;
1396 }
1397
1398 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1399 {
1400         struct target *target = get_current_target(CMD_CTX);
1401         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1402         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1403
1404         if (CMD_ARGC == 1)
1405                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1406         else if (CMD_ARGC > 1)
1407                         return ERROR_COMMAND_SYNTAX_ERROR;
1408
1409         command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
1410         if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
1411                 ejtag_info->mode = 0;
1412                 command_print(CMD_CTX, "running in legacy mode");
1413         } else {
1414                 ejtag_info->mode = 1;
1415                 command_print(CMD_CTX, "running in fast queued mode");
1416         }
1417
1418         return ERROR_OK;
1419 }
1420
1421 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1422         {
1423                 .name = "cp0",
1424                 .handler = mips_m4k_handle_cp0_command,
1425                 .mode = COMMAND_EXEC,
1426                 .usage = "regnum [value]",
1427                 .help = "display/modify cp0 register",
1428         },
1429         {
1430                 .name = "smp_off",
1431                 .handler = mips_m4k_handle_smp_off_command,
1432                 .mode = COMMAND_EXEC,
1433                 .help = "Stop smp handling",
1434                 .usage = "",},
1435
1436         {
1437                 .name = "smp_on",
1438                 .handler = mips_m4k_handle_smp_on_command,
1439                 .mode = COMMAND_EXEC,
1440                 .help = "Restart smp handling",
1441                 .usage = "",
1442         },
1443         {
1444                 .name = "smp_gdb",
1445                 .handler = mips_m4k_handle_smp_gdb_command,
1446                 .mode = COMMAND_EXEC,
1447                 .help = "display/fix current core played to gdb",
1448                 .usage = "",
1449         },
1450         {
1451                 .name = "scan_delay",
1452                 .handler = mips_m4k_handle_scan_delay_command,
1453                 .mode = COMMAND_ANY,
1454                 .help = "display/set scan delay in nano seconds",
1455                 .usage = "[value]",
1456         },
1457         COMMAND_REGISTRATION_DONE
1458 };
1459
1460 const struct command_registration mips_m4k_command_handlers[] = {
1461         {
1462                 .chain = mips32_command_handlers,
1463         },
1464         {
1465                 .name = "mips_m4k",
1466                 .mode = COMMAND_ANY,
1467                 .help = "mips_m4k command group",
1468                 .usage = "",
1469                 .chain = mips_m4k_exec_command_handlers,
1470         },
1471         COMMAND_REGISTRATION_DONE
1472 };
1473
1474 struct target_type mips_m4k_target = {
1475         .name = "mips_m4k",
1476
1477         .poll = mips_m4k_poll,
1478         .arch_state = mips32_arch_state,
1479
1480         .halt = mips_m4k_halt,
1481         .resume = mips_m4k_resume,
1482         .step = mips_m4k_step,
1483
1484         .assert_reset = mips_m4k_assert_reset,
1485         .deassert_reset = mips_m4k_deassert_reset,
1486
1487         .get_gdb_reg_list = mips32_get_gdb_reg_list,
1488
1489         .read_memory = mips_m4k_read_memory,
1490         .write_memory = mips_m4k_write_memory,
1491         .checksum_memory = mips32_checksum_memory,
1492         .blank_check_memory = mips32_blank_check_memory,
1493
1494         .run_algorithm = mips32_run_algorithm,
1495
1496         .add_breakpoint = mips_m4k_add_breakpoint,
1497         .remove_breakpoint = mips_m4k_remove_breakpoint,
1498         .add_watchpoint = mips_m4k_add_watchpoint,
1499         .remove_watchpoint = mips_m4k_remove_watchpoint,
1500
1501         .commands = mips_m4k_command_handlers,
1502         .target_create = mips_m4k_target_create,
1503         .init_target = mips_m4k_init_target,
1504         .examine = mips_m4k_examine,
1505 };