1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2008 by Spencer Oliver *
5 * spen@spen-soft.co.uk *
7 * Copyright (C) 2008 by David T.L. Wong *
8 ***************************************************************************/
10 #ifndef OPENOCD_TARGET_MIPS_EJTAG_H
11 #define OPENOCD_TARGET_MIPS_EJTAG_H
13 #include <jtag/jtag.h>
15 /* tap instructions */
16 #define EJTAG_INST_IDCODE 0x01
17 #define EJTAG_INST_IMPCODE 0x03
18 #define EJTAG_INST_ADDRESS 0x08
19 #define EJTAG_INST_DATA 0x09
20 #define EJTAG_INST_CONTROL 0x0A
21 #define EJTAG_INST_ALL 0x0B
22 #define EJTAG_INST_EJTAGBOOT 0x0C
23 #define EJTAG_INST_NORMALBOOT 0x0D
24 #define EJTAG_INST_FASTDATA 0x0E
25 #define EJTAG_INST_TCBCONTROLA 0x10
26 #define EJTAG_INST_TCBCONTROLB 0x11
27 #define EJTAG_INST_TCBDATA 0x12
28 #define EJTAG_INST_TCBCONTROLC 0x13
29 #define EJTAG_INST_PCSAMPLE 0x14
30 #define EJTAG_INST_TCBCONTROLD 0x15
31 #define EJTAG_INST_TCBCONTROLE 0x16
32 #define EJTAG_INST_FDC 0x17
33 #define EJTAG_INST_BYPASS 0xFF
35 /* microchip PIC32MX specific instructions */
36 #define MTAP_SW_MTAP 0x04
37 #define MTAP_SW_ETAP 0x05
38 #define MTAP_COMMAND 0x07
40 /* microchip specific cmds */
41 #define MCHP_ASERT_RST 0xd1
42 #define MCHP_DE_ASSERT_RST 0xd0
43 #define MCHP_ERASE 0xfc
44 #define MCHP_STATUS 0x00
46 /* ejtag control register bits ECR */
47 #define EJTAG_CTRL_TOF (1 << 1)
48 #define EJTAG_CTRL_TIF (1 << 2)
49 #define EJTAG_CTRL_BRKST (1 << 3)
50 #define EJTAG_CTRL_DLOCK (1 << 5)
51 #define EJTAG_CTRL_DRWN (1 << 9)
52 #define EJTAG_CTRL_DERR (1 << 10)
53 #define EJTAG_CTRL_DSTRT (1 << 11)
54 #define EJTAG_CTRL_JTAGBRK (1 << 12)
55 #define EJTAG_CTRL_DBGISA (1 << 13)
56 #define EJTAG_CTRL_SETDEV (1 << 14)
57 #define EJTAG_CTRL_PROBEN (1 << 15)
58 #define EJTAG_CTRL_PRRST (1 << 16)
59 #define EJTAG_CTRL_DMAACC (1 << 17)
60 #define EJTAG_CTRL_PRACC (1 << 18)
61 #define EJTAG_CTRL_PRNW (1 << 19)
62 #define EJTAG_CTRL_PERRST (1 << 20)
63 #define EJTAG_CTRL_SYNC (1 << 23)
64 #define EJTAG_CTRL_DNM (1 << 28)
65 #define EJTAG_CTRL_ROCC (1 << 31)
67 /* Debug Register (CP0 Register 23, Select 0) */
69 #define EJTAG_DEBUG_DSS (1 << 0)
70 #define EJTAG_DEBUG_DBP (1 << 1)
71 #define EJTAG_DEBUG_DDBL (1 << 2)
72 #define EJTAG_DEBUG_DDBS (1 << 3)
73 #define EJTAG_DEBUG_DIB (1 << 4)
74 #define EJTAG_DEBUG_DINT (1 << 5)
75 #define EJTAG_DEBUG_OFFLINE (1 << 7)
76 #define EJTAG_DEBUG_SST (1 << 8)
77 #define EJTAG_DEBUG_NOSST (1 << 9)
78 #define EJTAG_DEBUG_DDBLIMPR (1 << 18)
79 #define EJTAG_DEBUG_DDBSIMPR (1 << 19)
80 #define EJTAG_DEBUG_IEXI (1 << 20)
81 #define EJTAG_DEBUG_DBUSEP (1 << 21)
82 #define EJTAG_DEBUG_CACHEEP (1 << 22)
83 #define EJTAG_DEBUG_MCHECKP (1 << 23)
84 #define EJTAG_DEBUG_IBUSEP (1 << 24)
85 #define EJTAG_DEBUG_COUNTDM (1 << 25)
86 #define EJTAG_DEBUG_HALT (1 << 26)
87 #define EJTAG_DEBUG_DOZE (1 << 27)
88 #define EJTAG_DEBUG_LSNM (1 << 28)
89 #define EJTAG_DEBUG_NODCR (1 << 29)
90 #define EJTAG_DEBUG_DM (1 << 30)
91 #define EJTAG_DEBUG_DBD (1 << 31)
93 /* implementation MIPS register bits.
94 * Bits marked with V20 or v2.0 mean that, this registers supported only
95 * by EJTAG v2.0. Bits marked with Lexra or BMIPS are different from the
97 * NOTE: Lexra or BMIPS use EJTAG v2.0 */
99 #define EJTAG_IMP_HAS(x) (ejtag_info->impcode & (x))
100 /* v2.0(Lexra) 29 - 1’b1 - Lexra Internal Trace Buffer implemented. This bit
101 * overlaps with version bit of MIPS EJTAG specification. */
102 #define EJTAG_V26_IMP_R3K (1 << 28)
103 /* v2.0 - 24:25 - 2’b00- No profiling support */
104 #define EJTAG_V26_IMP_DINT (1 << 24)
105 #define EJTAG_V20_IMP_SDBBP (1 << 23) /* 1’b1 - sdbbp is Special2 Opcode */
106 #define EJTAG_IMP_ASID8 (1 << 22)
107 #define EJTAG_IMP_ASID6 (1 << 21)
108 #define EJTAG_V20_IMP_COMPLEX_BREAK (1 << 20) /* Complex Breaks supported*/
109 #define EJTAG_V20_IMP_EADDR_NO32BIT (1 << 19) /* EJTAG_ADDR > 32 bits wide */
110 #define EJTAG_V20_IMP_DCACHE_COH (1 << 18) /* DCache does keep DMA coherent */
111 #define EJTAG_V20_IMP_ICACHE_COH (1 << 17) /* DCache does keep DMA coherent */
112 #define EJTAG_IMP_MIPS16 (1 << 16)
113 #define EJTAG_IMP_NODMA (1 << 14)
114 /* v2.0 - 11:13 external PC trace. Trace PC Width. */
115 /* v2.0 - 8:10 external PC trace. PCST Width and DCLK Division Factor */
116 #define EJTAG_V20_IMP_NOPB (1 << 7) /* no processor breaks */
117 #define EJTAG_V20_IMP_NODB (1 << 6) /* no data breaks */
118 #define EJTAG_V20_IMP_NOIB (1 << 5) /* no instruction breaks implemented */
119 /* v2.0 - 1:4 Number of Break Channels. */
120 #define EJTAG_V20_IMP_BCHANNELS_MASK 0xf
121 #define EJTAG_V20_IMP_BCHANNELS_SHIFT 1
122 #define EJTAG_IMP_MIPS64 (1 << 0)
124 /* Debug Control Register DCR */
125 #define EJTAG_DCR 0xFF300000
126 #define EJTAG_DCR_ENM (1 << 29)
127 #define EJTAG_DCR_DB (1 << 17)
128 #define EJTAG_DCR_IB (1 << 16)
129 #define EJTAG_DCR_INTE (1 << 4)
130 #define EJTAG_DCR_MP (1 << 2)
132 /* breakpoint support */
133 /* EJTAG_V20_* was tested on Broadcom BCM7401
134 * and may or will differ with other hardware. For example EZ4021-FC. */
135 #define EJTAG_V20_IBS 0xFF300004
136 #define EJTAG_V20_IBA0 0xFF300100
137 #define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */
138 #define EJTAG_V20_IBM_OFFS 0x8
139 #define EJTAG_V20_IBAN_STEP 0x10 /* Offset for next channel */
140 #define EJTAG_V20_DBS 0xFF300008
141 #define EJTAG_V20_DBA0 0xFF300200
142 #define EJTAG_V20_DBC_OFFS 0x4
143 #define EJTAG_V20_DBM_OFFS 0x8
144 #define EJTAG_V20_DBV_OFFS 0xc
145 #define EJTAG_V20_DBAN_STEP 0x10
147 #define EJTAG_V25_IBS 0xFF301000
148 #define EJTAG_V25_IBA0 0xFF301100
149 #define EJTAG_V25_IBM_OFFS 0x8
150 #define EJTAG_V25_IBASID_OFFS 0x10
151 #define EJTAG_V25_IBC_OFFS 0x18
152 #define EJTAG_V25_IBAN_STEP 0x100
153 #define EJTAG_V25_DBS 0xFF302000
154 #define EJTAG_V25_DBA0 0xFF302100
155 #define EJTAG_V25_DBM_OFFS 0x8
156 #define EJTAG_V25_DBASID_OFFS 0x10
157 #define EJTAG_V25_DBC_OFFS 0x18
158 #define EJTAG_V25_DBV_OFFS 0x20
159 #define EJTAG_V25_DBAN_STEP 0x100
161 #define EJTAG_DBCN_NOSB (1 << 13)
162 #define EJTAG_DBCN_NOLB (1 << 12)
163 #define EJTAG_DBCN_BLM_MASK 0xff
164 #define EJTAG_DBCN_BLM_SHIFT 4
165 #define EJTAG_DBCN_BE (1 << 0)
167 #define EJTAG_VERSION_20 0
168 #define EJTAG_VERSION_25 1
169 #define EJTAG_VERSION_26 2
170 #define EJTAG_VERSION_31 3
171 #define EJTAG_VERSION_41 4
172 #define EJTAG_VERSION_51 5
175 * Additional defines for MIPS64 EJTAG
177 #define EJTAG64_DCR 0xFFFFFFFFFF300000ull
178 #define EJTAG64_DCR_ENM (1llu << 29)
179 #define EJTAG64_DCR_DB (1llu << 17)
180 #define EJTAG64_DCR_IB (1llu << 16)
181 #define EJTAG64_DCR_INTE (1llu << 4)
182 #define EJTAG64_DCR_MP (1llu << 2)
183 #define EJTAG64_V25_DBA0 0xFFFFFFFFFF302100ull
184 #define EJTAG64_V25_DBS 0xFFFFFFFFFF302000ull
185 #define EJTAG64_V25_IBA0 0xFFFFFFFFFF301100ull
186 #define EJTAG64_V25_IBS 0xFFFFFFFFFF301000ull
189 struct jtag_tap *tap;
193 int fast_access_save;
194 uint32_t config_regs; /* number of config registers read */
195 uint32_t config[4]; /* cp0 config to config3 */
203 unsigned int ejtag_version;
207 /* Memory-Mapped Registers. This addresses are not same on different
210 uint32_t ejtag_ibs_addr; /* Instruction Address Break Status */
211 uint32_t ejtag_iba0_addr; /* IAB channel 0 */
212 uint32_t ejtag_ibc_offs; /* IAB Control offset */
213 uint32_t ejtag_ibm_offs; /* IAB Mask offset */
214 uint32_t ejtag_ibasid_offs; /* IAB ASID (4Kc) */
216 uint32_t ejtag_dbs_addr; /* Data Address Break Status Register */
217 uint32_t ejtag_dba0_addr; /* DAB channel 0 */
218 uint32_t ejtag_dbc_offs; /* DAB Control offset */
219 uint32_t ejtag_dbm_offs; /* DAB Mask offset */
220 uint32_t ejtag_dbv_offs; /* DAB Value offset */
221 uint32_t ejtag_dbasid_offs; /* DAB ASID (4Kc) */
223 uint32_t ejtag_iba_step_size;
224 uint32_t ejtag_dba_step_size; /* size of step till next *DBAn register. */
227 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr);
228 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
229 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
230 int mips64_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
231 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info);
232 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
233 uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
234 int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data);
235 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
236 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
237 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
238 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data);
239 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
240 int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint64_t *data);
242 int mips_ejtag_init(struct mips_ejtag *ejtag_info);
243 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
244 int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step);
246 static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
248 uint8_t *in = (uint8_t *)arg;
249 *((uint32_t *)arg) = le_to_h_u32(in);
252 static inline void mips_le_to_h_u64(jtag_callback_data_t arg)
254 uint8_t *in = (uint8_t *)arg;
255 *((uint64_t *)arg) = le_to_h_u64(in);
258 #endif /* OPENOCD_TARGET_MIPS_EJTAG_H */