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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  21  ***************************************************************************/
  22
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "mips32.h"
  28 #include "mips_ejtag.h"
  29 #include "mips32_dmaacc.h"
  30
  31 #if BUILD_TARGET64 == 1
  32 #include "mips64.h"
  33 #include "mips64_pracc.h"
  34 #endif
  35
  36 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
  37 {
  38         assert(ejtag_info->tap != NULL);
  39         struct jtag_tap *tap = ejtag_info->tap;
  40
  41         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
  42
  43                 struct scan_field field;
  44                 field.num_bits = tap->ir_length;
  45
  46                 uint8_t t[4];
  47                 field.out_value = t;
  48                 buf_set_u32(t, 0, field.num_bits, new_instr);
  49
  50                 field.in_value = NULL;
  51
  52                 jtag_add_ir_scan(tap, &field, TAP_IDLE);
  53         }
  54 }
  55
  56 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info)
  57 {
  58         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
  59
  60         ejtag_info->idcode = 0;
  61         return mips_ejtag_drscan_32(ejtag_info, &ejtag_info->idcode);
  62 }
  63
  64 int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info)
  65 {
  66         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
  67
  68         ejtag_info->impcode = 0;
  69         return mips_ejtag_drscan_32(ejtag_info, &ejtag_info->impcode);
  70 }
  71
  72 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
  73 {
  74         assert(ejtag_info->tap != NULL);
  75         struct jtag_tap *tap = ejtag_info->tap;
  76
  77         struct scan_field field;
  78         uint8_t out_scan[12];
  79
  80         /* processor access "all" register 96 bit */
  81         field.num_bits = 96;
  82
  83         field.out_value = out_scan;
  84         buf_set_u32(out_scan, 0, 32, ctrl);
  85         buf_set_u32(out_scan + 4, 0, 32, data);
  86         buf_set_u32(out_scan + 8, 0, 32, 0);
  87
  88         field.in_value = in_scan_buf;
  89
  90         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
  91
  92         keep_alive();
  93 }
  94
  95 int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data)
  96 {
  97         struct jtag_tap *tap;
  98         tap  = ejtag_info->tap;
  99
 100         if (tap == NULL)
 101                 return ERROR_FAIL;
 102         struct scan_field field;
 103         uint8_t t[8], r[8];
 104         int retval;
 105
 106         field.num_bits = 64;
 107         field.out_value = t;
 108         buf_set_u64(t, 0, field.num_bits, *data);
 109         field.in_value = r;
 110
 111         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 112         retval = jtag_execute_queue();
 113         if (retval != ERROR_OK) {
 114                 LOG_ERROR("register read failed");
 115                 return retval;
 116         }
 117
 118         *data = buf_get_u64(field.in_value, 0, 64);
 119
 120         keep_alive();
 121
 122         return ERROR_OK;
 123 }
 124
 125 void mips_ejtag_drscan_32_queued(struct mips_ejtag *ejtag_info, uint32_t data_out, uint8_t *data_in)
 126 {
 127         assert(ejtag_info->tap != NULL);
 128         struct jtag_tap *tap = ejtag_info->tap;
 129
 130         struct scan_field field;
 131         field.num_bits = 32;
 132
 133         uint8_t scan_out[4];
 134         field.out_value = scan_out;
 135         buf_set_u32(scan_out, 0, field.num_bits, data_out);
 136
 137         field.in_value = data_in;
 138         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 139
 140         keep_alive();
 141 }
 142
 143 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 144 {
 145         uint8_t scan_in[4];
 146         mips_ejtag_drscan_32_queued(ejtag_info, *data, scan_in);
 147
 148         int retval = jtag_execute_queue();
 149         if (retval != ERROR_OK) {
 150                 LOG_ERROR("register read failed");
 151                 return retval;
 152         }
 153
 154         *data = buf_get_u32(scan_in, 0, 32);
 155         return ERROR_OK;
 156 }
 157
 158 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
 159 {
 160         mips_ejtag_drscan_32_queued(ejtag_info, data, NULL);
 161 }
 162
 163 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data)
 164 {
 165         assert(ejtag_info->tap != NULL);
 166         struct jtag_tap *tap = ejtag_info->tap;
 167
 168         struct scan_field field;
 169         field.num_bits = 8;
 170
 171         field.out_value = data;
 172         field.in_value = data;
 173
 174         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 175
 176         int retval = jtag_execute_queue();
 177         if (retval != ERROR_OK) {
 178                 LOG_ERROR("register read failed");
 179                 return retval;
 180         }
 181         return ERROR_OK;
 182 }
 183
 184 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
 185 {
 186         assert(ejtag_info->tap != NULL);
 187         struct jtag_tap *tap = ejtag_info->tap;
 188
 189         struct scan_field field;
 190         field.num_bits = 8;
 191
 192         field.out_value = &data;
 193         field.in_value = NULL;
 194
 195         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 196 }
 197
 198 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
 199 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
 200 {
 201         struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
 202         pracc_queue_init(&ctx);
 203
 204         pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, 23, 0));                     /* move COP0 Debug to $8 */
 205         pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, 0x0100));                  /* set SSt bit in debug reg */
 206         if (!enable_step)
 207                 pracc_add(&ctx, 0, MIPS32_XORI(ctx.isa, 8, 8, 0x0100));         /* clear SSt bit in debug reg */
 208
 209         pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 8, 23, 0));                     /* move $8 to COP0 Debug */
 210         pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8)));  /* restore upper 16 bits  of $8 */
 211         pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));          /* jump to start */
 212         pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
 213
 214         ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
 215         pracc_queue_free(&ctx);
 216         return ctx.retval;
 217 }
 218
 219 /*
 220  * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
 221  * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
 222  * For example bcm7401 and others. At leas on some
 223  * CPUs, DebugMode wont start if this bit is not removed.
 224  */
 225 static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
 226 {
 227         uint32_t dcr;
 228         int retval;
 229
 230         retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
 231         if (retval != ERROR_OK)
 232                 goto error;
 233
 234         dcr &= ~EJTAG_DCR_MP;
 235         retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
 236         if (retval != ERROR_OK)
 237                 goto error;
 238         return ERROR_OK;
 239 error:
 240         LOG_ERROR("Failed to remove DCR MPbit!");
 241         return retval;
 242 }
 243
 244 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
 245 {
 246         uint32_t ejtag_ctrl;
 247         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 248
 249         if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
 250                 if (disable_dcr_mp(ejtag_info) != ERROR_OK)
 251                         goto error;
 252         }
 253
 254         /* set debug break bit */
 255         ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
 256         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 257
 258         /* break bit will be cleared by hardware */
 259         ejtag_ctrl = ejtag_info->ejtag_ctrl;
 260         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 261         LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
 262         if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
 263                 goto error;
 264
 265         return ERROR_OK;
 266 error:
 267         LOG_ERROR("Failed to enter Debug Mode!");
 268         return ERROR_FAIL;
 269 }
 270
 271 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
 272 {
 273         pa_list pracc_list = {.instr = MIPS32_DRET(ejtag_info->isa), .addr = 0};
 274         struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &pracc_list, .code_count = 1, .store_count = 0};
 275
 276         /* execute our dret instruction */
 277         ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 0); /* shift out instr, omit last check */
 278
 279         /* pic32mx workaround, false pending at low core clock */
 280         jtag_add_sleep(1000);
 281         return ctx.retval;
 282 }
 283
 284 /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
 285  *                      on EJTAG version.
 286  */
 287 static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
 288 {
 289         if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
 290                 ejtag_info->ejtag_ibs_addr      = EJTAG_V20_IBS;
 291                 ejtag_info->ejtag_iba0_addr     = EJTAG_V20_IBA0;
 292                 ejtag_info->ejtag_ibc_offs      = EJTAG_V20_IBC_OFFS;
 293                 ejtag_info->ejtag_ibm_offs      = EJTAG_V20_IBM_OFFS;
 294
 295                 ejtag_info->ejtag_dbs_addr      = EJTAG_V20_DBS;
 296                 ejtag_info->ejtag_dba0_addr     = EJTAG_V20_DBA0;
 297                 ejtag_info->ejtag_dbc_offs      = EJTAG_V20_DBC_OFFS;
 298                 ejtag_info->ejtag_dbm_offs      = EJTAG_V20_DBM_OFFS;
 299                 ejtag_info->ejtag_dbv_offs      = EJTAG_V20_DBV_OFFS;
 300
 301                 ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP;
 302                 ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP;
 303         } else {
 304                 ejtag_info->ejtag_ibs_addr      = EJTAG_V25_IBS;
 305                 ejtag_info->ejtag_iba0_addr     = EJTAG_V25_IBA0;
 306                 ejtag_info->ejtag_ibm_offs      = EJTAG_V25_IBM_OFFS;
 307                 ejtag_info->ejtag_ibasid_offs   = EJTAG_V25_IBASID_OFFS;
 308                 ejtag_info->ejtag_ibc_offs      = EJTAG_V25_IBC_OFFS;
 309
 310                 ejtag_info->ejtag_dbs_addr      = EJTAG_V25_DBS;
 311                 ejtag_info->ejtag_dba0_addr     = EJTAG_V25_DBA0;
 312                 ejtag_info->ejtag_dbm_offs      = EJTAG_V25_DBM_OFFS;
 313                 ejtag_info->ejtag_dbasid_offs   = EJTAG_V25_DBASID_OFFS;
 314                 ejtag_info->ejtag_dbc_offs      = EJTAG_V25_DBC_OFFS;
 315                 ejtag_info->ejtag_dbv_offs      = EJTAG_V25_DBV_OFFS;
 316
 317                 ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP;
 318                 ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP;
 319         }
 320 }
 321
 322 static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info)
 323 {
 324         LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
 325                 EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP) ? " SDBBP_SPECIAL2" : " SDBBP",
 326                 EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT) ? " EADDR>32bit" : " EADDR=32bit",
 327                 EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK) ? " COMPLEX_BREAK" : "",
 328                 EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH) ? " DCACHE_COH" : " DCACHE_NOT_COH",
 329                 EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH) ? " ICACHE_COH" : " ICACHE_NOT_COH",
 330                 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
 331                 EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
 332                 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
 333         LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
 334                 (uint8_t)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
 335                 EJTAG_V20_IMP_BCHANNELS_MASK));
 336 }
 337
 338 static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)
 339 {
 340         LOG_DEBUG("EJTAG v2.6: features:%s%s",
 341                 EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K) ? " R3k" : " R4k",
 342                 EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT) ? " DINT" : "");
 343 }
 344
 345 static void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
 346 {
 347         LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
 348                 EJTAG_IMP_HAS(EJTAG_IMP_ASID8) ? " ASID_8" : "",
 349                 EJTAG_IMP_HAS(EJTAG_IMP_ASID6) ? " ASID_6" : "",
 350                 EJTAG_IMP_HAS(EJTAG_IMP_MIPS16) ? " MIPS16" : "",
 351                 EJTAG_IMP_HAS(EJTAG_IMP_NODMA) ? " noDMA" : " DMA",
 352                 EJTAG_IMP_HAS(EJTAG_DCR_MIPS64) ? " MIPS64" : " MIPS32");
 353
 354         switch (ejtag_info->ejtag_version) {
 355                 case EJTAG_VERSION_20:
 356                         ejtag_v20_print_imp(ejtag_info);
 357                         break;
 358                 case EJTAG_VERSION_25:
 359                 case EJTAG_VERSION_26:
 360                 case EJTAG_VERSION_31:
 361                 case EJTAG_VERSION_41:
 362                 case EJTAG_VERSION_51:
 363                         ejtag_v26_print_imp(ejtag_info);
 364                         break;
 365                 default:
 366                         break;
 367         }
 368 }
 369
 370 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
 371 {
 372         int retval = mips_ejtag_get_impcode(ejtag_info);
 373         if (retval != ERROR_OK) {
 374                 LOG_ERROR("impcode read failed");
 375                 return retval;
 376         }
 377
 378         /* get ejtag version */
 379         ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
 380
 381         switch (ejtag_info->ejtag_version) {
 382                 case EJTAG_VERSION_20:
 383                         LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
 384                         break;
 385                 case EJTAG_VERSION_25:
 386                         LOG_DEBUG("EJTAG: Version 2.5 Detected");
 387                         break;
 388                 case EJTAG_VERSION_26:
 389                         LOG_DEBUG("EJTAG: Version 2.6 Detected");
 390                         break;
 391                 case EJTAG_VERSION_31:
 392                         LOG_DEBUG("EJTAG: Version 3.1 Detected");
 393                         break;
 394                 case EJTAG_VERSION_41:
 395                         LOG_DEBUG("EJTAG: Version 4.1 Detected");
 396                         break;
 397                 case EJTAG_VERSION_51:
 398                         LOG_DEBUG("EJTAG: Version 5.1 Detected");
 399                         break;
 400                 default:
 401                         LOG_DEBUG("EJTAG: Unknown Version Detected");
 402                         break;
 403         }
 404         ejtag_main_print_imp(ejtag_info);
 405
 406         if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0) {
 407                 LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
 408                           "workaround current broken code.");
 409                 ejtag_info->impcode |= EJTAG_IMP_NODMA;
 410         }
 411
 412         ejtag_info->ejtag_ctrl = EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN;
 413
 414         if (ejtag_info->ejtag_version != EJTAG_VERSION_20)
 415                 ejtag_info->ejtag_ctrl |= EJTAG_CTRL_ROCC | EJTAG_CTRL_SETDEV;
 416
 417         ejtag_info->fast_access_save = -1;
 418
 419         mips_ejtag_init_mmr(ejtag_info);
 420
 421         return ERROR_OK;
 422 }
 423
 424 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
 425 {
 426         assert(ejtag_info->tap != NULL);
 427         struct jtag_tap *tap = ejtag_info->tap;
 428
 429         struct scan_field fields[2];
 430
 431         /* fastdata 1-bit register */
 432         fields[0].num_bits = 1;
 433
 434         uint8_t spracc = 0;
 435         fields[0].out_value = &spracc;
 436         fields[0].in_value = NULL;
 437
 438         /* processor access data register 32 bit */
 439         fields[1].num_bits = 32;
 440
 441         uint8_t t[4] = {0, 0, 0, 0};
 442         fields[1].out_value = t;
 443
 444         if (write_t) {
 445                 fields[1].in_value = NULL;
 446                 buf_set_u32(t, 0, 32, *data);
 447         } else
 448                 fields[1].in_value = (uint8_t *) data;
 449
 450         jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
 451
 452         if (!write_t && data)
 453                 jtag_add_callback(mips_le_to_h_u32,
 454                         (jtag_callback_data_t) data);
 455
 456         keep_alive();
 457
 458         return ERROR_OK;
 459 }
 460
 461 #if BUILD_TARGET64 == 1
 462
 463 int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step)
 464 {
 465         const uint32_t code_enable[] = {
 466                 MIPS64_MTC0(1, 31, 0),              /* move $1 to COP0 DeSave */
 467                 MIPS64_MFC0(1, 23, 0),              /* move COP0 Debug to $1 */
 468                 MIPS64_ORI(1, 1, 0x0100),                /* set SSt bit in debug reg */
 469                 MIPS64_MTC0(1, 23, 0),              /* move $1 to COP0 Debug */
 470                 MIPS64_B(NEG16(5)),
 471                 MIPS64_MFC0(1, 31, 0),              /* move COP0 DeSave to $1 */
 472                 MIPS64_NOP,
 473                 MIPS64_NOP,
 474                 MIPS64_NOP,
 475                 MIPS64_NOP,
 476                 MIPS64_NOP,
 477                 MIPS64_NOP,
 478                 MIPS64_NOP,
 479                 MIPS64_NOP,
 480         };
 481
 482         const uint32_t code_disable[] = {
 483                 MIPS64_MTC0(15, 31, 0),                           /* move $15 to COP0 DeSave */
 484                 MIPS64_LUI(15, UPPER16(MIPS64_PRACC_STACK)),     /* $15 = MIPS64_PRACC_STACK */
 485                 MIPS64_ORI(15, 15, LOWER16(MIPS64_PRACC_STACK)),
 486                 MIPS64_SD(1, 0, 15),                              /* sw $1,($15) */
 487                 MIPS64_SD(2, 0, 15),                              /* sw $2,($15) */
 488                 MIPS64_MFC0(1, 23, 0),                            /* move COP0 Debug to $1 */
 489                 MIPS64_LUI(2, 0xFFFF),                           /* $2 = 0xfffffeff */
 490                 MIPS64_ORI(2, 2, 0xFEFF),
 491                 MIPS64_AND(1, 1, 2),
 492                 MIPS64_MTC0(1, 23, 0),                            /* move $1 to COP0 Debug */
 493                 MIPS64_LD(2, 0, 15),
 494                 MIPS64_LD(1, 0, 15),
 495                 MIPS64_SYNC,
 496                 MIPS64_B(NEG16(14)),
 497                 MIPS64_MFC0(15, 31, 0),                           /* move COP0 DeSave to $15 */
 498                 MIPS64_NOP,
 499                 MIPS64_NOP,
 500                 MIPS64_NOP,
 501                 MIPS64_NOP,
 502                 MIPS64_NOP,
 503                 MIPS64_NOP,
 504                 MIPS64_NOP,
 505                 MIPS64_NOP,
 506         };
 507         const uint32_t *code = enable_step ? code_enable : code_disable;
 508         unsigned code_len = enable_step ? ARRAY_SIZE(code_enable) :
 509                                           ARRAY_SIZE(code_disable);
 510
 511         return mips64_pracc_exec(ejtag_info,
 512                                  code_len, code, 0, NULL, 0, NULL);
 513 }
 514
 515 int mips64_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
 516 {
 517         const uint32_t code[] = {
 518                 MIPS64_DRET,
 519                 MIPS64_NOP,
 520                 MIPS64_NOP,
 521                 MIPS64_NOP,
 522                 MIPS64_NOP,
 523                 MIPS64_NOP,
 524                 MIPS64_NOP,
 525                 MIPS64_NOP,
 526         };
 527         LOG_DEBUG("enter mips64_pracc_exec");
 528         return mips64_pracc_exec(ejtag_info,
 529                                  ARRAY_SIZE(code), code, 0, NULL, 0, NULL);
 530 }
 531
 532 int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint64_t *data)
 533 {
 534         struct jtag_tap *tap;
 535
 536         tap = ejtag_info->tap;
 537         assert(tap != NULL);
 538
 539         struct scan_field fields[2];
 540         uint8_t spracc = 0;
 541         uint8_t t[8] = {0, 0, 0, 0, 0, 0, 0, 0};
 542
 543         /* fastdata 1-bit register */
 544         fields[0].num_bits = 1;
 545         fields[0].out_value = &spracc;
 546         fields[0].in_value = NULL;
 547
 548         /* processor access data register 64 bit */
 549         fields[1].num_bits = 64;
 550         fields[1].out_value = t;
 551
 552         if (write_t) {
 553                 fields[1].in_value = NULL;
 554                 buf_set_u64(t, 0, 64, *data);
 555         } else
 556                 fields[1].in_value = (uint8_t *) data;
 557
 558         jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
 559
 560         if (!write_t && data)
 561                 jtag_add_callback(mips_le_to_h_u64,
 562                         (jtag_callback_data_t) data);
 563         keep_alive();
 564
 565         return ERROR_OK;
 566 }
 567
 568 #endif /* BUILD_TARGET64 */