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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "mips32.h"
  29 #include "mips_ejtag.h"
  30
  31
  32 int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *delete_me_and_submit_patch)
  33 {
  34         struct jtag_tap *tap;
  35
  36         tap = ejtag_info->tap;
  37         if (tap == NULL)
  38                 return ERROR_FAIL;
  39
  40         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr)
  41         {
  42                 struct scan_field field;
  43                 uint8_t t[4];
  44
  45                 field.tap = tap;
  46                 field.num_bits = tap->ir_length;
  47                 field.out_value = t;
  48                 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  49                 field.in_value = NULL;
  50
  51                 jtag_add_ir_scan(1, &field, jtag_get_end_state());
  52         }
  53
  54         return ERROR_OK;
  55 }
  56
  57 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
  58 {
  59         struct scan_field field;
  60
  61         jtag_set_end_state(TAP_IDLE);
  62
  63         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
  64
  65         field.tap = ejtag_info->tap;
  66         field.num_bits = 32;
  67         field.out_value = NULL;
  68         field.in_value = (void*)idcode;
  69
  70         jtag_add_dr_scan(1, &field, jtag_get_end_state());
  71
  72         if (jtag_execute_queue() != ERROR_OK)
  73         {
  74                 LOG_ERROR("register read failed");
  75         }
  76
  77         return ERROR_OK;
  78 }
  79
  80 int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
  81 {
  82         struct scan_field field;
  83
  84         jtag_set_end_state(TAP_IDLE);
  85
  86         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
  87
  88         field.tap = ejtag_info->tap;
  89         field.num_bits = 32;
  90         field.out_value = NULL;
  91         field.in_value = (void*)impcode;
  92
  93         jtag_add_dr_scan(1, &field, jtag_get_end_state());
  94
  95         if (jtag_execute_queue() != ERROR_OK)
  96         {
  97                 LOG_ERROR("register read failed");
  98         }
  99
 100         return ERROR_OK;
 101 }
 102
 103 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 104 {
 105         struct jtag_tap *tap;
 106         tap  = ejtag_info->tap;
 107
 108         if (tap == NULL)
 109                 return ERROR_FAIL;
 110         struct scan_field field;
 111         uint8_t t[4], r[4];
 112         int retval;
 113
 114         field.tap = tap;
 115         field.num_bits = 32;
 116         field.out_value = t;
 117         buf_set_u32(field.out_value, 0, field.num_bits, *data);
 118         field.in_value = r;
 119
 120         jtag_add_dr_scan(1, &field, jtag_get_end_state());
 121
 122         if ((retval = jtag_execute_queue()) != ERROR_OK)
 123         {
 124                 LOG_ERROR("register read failed");
 125                 return retval;
 126         }
 127
 128         *data = buf_get_u32(field.in_value, 0, 32);
 129
 130         keep_alive();
 131
 132         return ERROR_OK;
 133 }
 134
 135 int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
 136 {
 137         uint32_t code[] = {
 138                         MIPS32_MTC0(1,31,0),                    /* move $1 to COP0 DeSave */
 139                         MIPS32_MFC0(1,23,0),                    /* move COP0 Debug to $1 */
 140                         MIPS32_ORI(1,1,0x0100),                 /* set SSt bit in debug reg */
 141                         MIPS32_MTC0(1,23,0),                    /* move $1 to COP0 Debug */
 142                         MIPS32_B(NEG16(5)),
 143                         MIPS32_MFC0(1,31,0),                    /* move COP0 DeSave to $1 */
 144         };
 145
 146         mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
 147                 0, NULL, 0, NULL, 1);
 148
 149         return ERROR_OK;
 150 }
 151 int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info)
 152 {
 153         uint32_t code[] = {
 154                         MIPS32_MTC0(15,31,0),                                                   /* move $15 to COP0 DeSave */
 155                         MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)),     /* $15 = MIPS32_PRACC_STACK */
 156                         MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
 157                         MIPS32_SW(1,0,15),                                                              /* sw $1,($15) */
 158                         MIPS32_SW(2,0,15),                                                              /* sw $2,($15) */
 159                         MIPS32_MFC0(1,23,0),                                                    /* move COP0 Debug to $1 */
 160                         MIPS32_LUI(2,0xFFFF),                                                   /* $2 = 0xfffffeff */
 161                         MIPS32_ORI(2,2,0xFEFF),
 162                         MIPS32_AND(1,1,2),
 163                         MIPS32_MTC0(1,23,0),                                                    /* move $1 to COP0 Debug */
 164                         MIPS32_LW(2,0,15),
 165                         MIPS32_LW(1,0,15),
 166                         MIPS32_B(NEG16(13)),
 167                         MIPS32_MFC0(15,31,0),                                                   /* move COP0 DeSave to $15 */
 168         };
 169
 170         mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
 171                 0, NULL, 0, NULL, 1);
 172
 173         return ERROR_OK;
 174 }
 175
 176 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
 177 {
 178         if (enable_step)
 179                 return mips_ejtag_step_enable(ejtag_info);
 180         return mips_ejtag_step_disable(ejtag_info);
 181 }
 182
 183 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
 184 {
 185         uint32_t ejtag_ctrl;
 186         jtag_set_end_state(TAP_IDLE);
 187         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 188
 189         /* set debug break bit */
 190         ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
 191         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 192
 193         /* break bit will be cleared by hardware */
 194         ejtag_ctrl = ejtag_info->ejtag_ctrl;
 195         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 196         LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
 197         if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
 198                 LOG_DEBUG("Failed to enter Debug Mode!");
 199
 200         return ERROR_OK;
 201 }
 202
 203 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
 204 {
 205         uint32_t inst;
 206         inst = MIPS32_DRET;
 207
 208         /* execute our dret instruction */
 209         mips32_pracc_exec(ejtag_info, 1, &inst, 0, NULL, 0, NULL, 0);
 210
 211         return ERROR_OK;
 212 }
 213
 214 int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg)
 215 {
 216         /* read ejtag ECR */
 217         uint32_t code[] = {
 218                         MIPS32_MTC0(15,31,0),                                                   /* move $15 to COP0 DeSave */
 219                         MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)),     /* $15 = MIPS32_PRACC_STACK */
 220                         MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
 221                         MIPS32_SW(1,0,15),                                                              /* sw $1,($15) */
 222                         MIPS32_SW(2,0,15),                                                              /* sw $2,($15) */
 223                         MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)),  /* $1 = MIPS32_PRACC_PARAM_OUT */
 224                         MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)),
 225                         MIPS32_MFC0(2,23,0),                                                    /* move COP0 Debug to $2 */
 226                         MIPS32_SW(2,0,1),
 227                         MIPS32_LW(2,0,15),
 228                         MIPS32_LW(1,0,15),
 229                         MIPS32_B(NEG16(12)),
 230                         MIPS32_MFC0(15,31,0),                                                   /* move COP0 DeSave to $15 */
 231         };
 232
 233         mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \
 234                 0, NULL, 1, debug_reg, 1);
 235
 236         return ERROR_OK;
 237 }
 238
 239 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
 240 {
 241         uint32_t ejtag_version;
 242
 243         mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
 244         LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
 245
 246         /* get ejtag version */
 247         ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
 248
 249         switch (ejtag_version)
 250         {
 251                 case 0:
 252                         LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
 253                         break;
 254                 case 1:
 255                         LOG_DEBUG("EJTAG: Version 2.5 Detected");
 256                         break;
 257                 case 2:
 258                         LOG_DEBUG("EJTAG: Version 2.6 Detected");
 259                         break;
 260                 case 3:
 261                         LOG_DEBUG("EJTAG: Version 3.1 Detected");
 262                         break;
 263                 default:
 264                         LOG_DEBUG("EJTAG: Unknown Version Detected");
 265                         break;
 266         }
 267         LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
 268                 ejtag_info->impcode & (1 << 28) ? " R3k":    " R4k",
 269                 ejtag_info->impcode & (1 << 24) ? " DINT":   "",
 270                 ejtag_info->impcode & (1 << 22) ? " ASID_8": "",
 271                 ejtag_info->impcode & (1 << 21) ? " ASID_6": "",
 272                 ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
 273                 ejtag_info->impcode & (1 << 14) ? " noDMA":  " DMA",
 274                 ejtag_info->impcode & (1 << 0)  ? " MIPS64": " MIPS32"
 275 );
 276
 277         if ((ejtag_info->impcode & (1 << 14)) == 0)
 278                 LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
 279
 280         /* set initial state for ejtag control reg */
 281         ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
 282
 283         return ERROR_OK;
 284 }
 285
 286 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t *data)
 287 {
 288         struct jtag_tap *tap;
 289         tap = ejtag_info->tap;
 290
 291         if (tap == NULL)
 292                 return ERROR_FAIL;
 293
 294         struct scan_field fields[2];
 295         uint8_t spracc = 0;
 296         uint8_t t[4] = {0, 0, 0, 0};
 297
 298         /* fastdata 1-bit register */
 299         fields[0].tap = tap;
 300         fields[0].num_bits = 1;
 301         fields[0].out_value = &spracc;
 302         fields[0].in_value = NULL;
 303
 304         /* processor access data register 32 bit */
 305         fields[1].tap = tap;
 306         fields[1].num_bits = 32;
 307         fields[1].out_value = t;
 308
 309         if (write)
 310         {
 311                 fields[1].in_value = NULL;
 312                 buf_set_u32(t, 0, 32, *data);
 313         }
 314         else
 315         {
 316                 fields[1].in_value = (uint8_t *) data;
 317         }
 318
 319         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 320         keep_alive();
 321
 322         return ERROR_OK;
 323 }