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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  21  ***************************************************************************/
  22
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "mips32.h"
  28 #include "mips_ejtag.h"
  29 #include "mips32_dmaacc.h"
  30
  31 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
  32 {
  33         struct jtag_tap *tap;
  34
  35         tap = ejtag_info->tap;
  36         assert(tap != NULL);
  37
  38         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) {
  39                 struct scan_field field;
  40                 uint8_t t[4];
  41
  42                 field.num_bits = tap->ir_length;
  43                 field.out_value = t;
  44                 buf_set_u32(t, 0, field.num_bits, new_instr);
  45                 field.in_value = NULL;
  46
  47                 jtag_add_ir_scan(tap, &field, TAP_IDLE);
  48         }
  49 }
  50
  51 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
  52 {
  53         struct scan_field field;
  54         uint8_t r[4];
  55
  56         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
  57
  58         field.num_bits = 32;
  59         field.out_value = NULL;
  60         field.in_value = r;
  61
  62         jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
  63
  64         int retval;
  65         retval = jtag_execute_queue();
  66         if (retval != ERROR_OK) {
  67                 LOG_ERROR("register read failed");
  68                 return retval;
  69         }
  70
  71         *idcode = buf_get_u32(field.in_value, 0, 32);
  72
  73         return ERROR_OK;
  74 }
  75
  76 static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
  77 {
  78         struct scan_field field;
  79         uint8_t r[4];
  80
  81         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
  82
  83         field.num_bits = 32;
  84         field.out_value = NULL;
  85         field.in_value = r;
  86
  87         jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
  88
  89         int retval;
  90         retval = jtag_execute_queue();
  91         if (retval != ERROR_OK) {
  92                 LOG_ERROR("register read failed");
  93                 return retval;
  94         }
  95
  96         *impcode = buf_get_u32(field.in_value, 0, 32);
  97
  98         return ERROR_OK;
  99 }
 100
 101 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
 102 {
 103         assert(ejtag_info->tap != NULL);
 104         struct jtag_tap *tap = ejtag_info->tap;
 105
 106         struct scan_field field;
 107         uint8_t out_scan[12];
 108
 109         /* processor access "all" register 96 bit */
 110         field.num_bits = 96;
 111
 112         field.out_value = out_scan;
 113         buf_set_u32(out_scan, 0, 32, ctrl);
 114         buf_set_u32(out_scan + 4, 0, 32, data);
 115         buf_set_u32(out_scan + 8, 0, 32, 0);
 116
 117         field.in_value = in_scan_buf;
 118
 119         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 120
 121         keep_alive();
 122 }
 123
 124 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 125 {
 126         struct jtag_tap *tap;
 127         tap  = ejtag_info->tap;
 128         assert(tap != NULL);
 129
 130         struct scan_field field;
 131         uint8_t t[4], r[4];
 132         int retval;
 133
 134         field.num_bits = 32;
 135         field.out_value = t;
 136         buf_set_u32(t, 0, field.num_bits, *data);
 137         field.in_value = r;
 138
 139         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 140
 141         retval = jtag_execute_queue();
 142         if (retval != ERROR_OK) {
 143                 LOG_ERROR("register read failed");
 144                 return retval;
 145         }
 146
 147         *data = buf_get_u32(field.in_value, 0, 32);
 148
 149         keep_alive();
 150
 151         return ERROR_OK;
 152 }
 153
 154 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
 155 {
 156         uint8_t t[4];
 157         struct jtag_tap *tap;
 158         tap  = ejtag_info->tap;
 159         assert(tap != NULL);
 160
 161         struct scan_field field;
 162
 163         field.num_bits = 32;
 164         field.out_value = t;
 165         buf_set_u32(t, 0, field.num_bits, data);
 166
 167         field.in_value = NULL;
 168
 169         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 170 }
 171
 172 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
 173 {
 174         struct jtag_tap *tap;
 175         tap  = ejtag_info->tap;
 176         assert(tap != NULL);
 177
 178         struct scan_field field;
 179         uint8_t t[4] = {0, 0, 0, 0}, r[4];
 180         int retval;
 181
 182         field.num_bits = 8;
 183         field.out_value = t;
 184         buf_set_u32(t, 0, field.num_bits, *data);
 185         field.in_value = r;
 186
 187         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 188
 189         retval = jtag_execute_queue();
 190         if (retval != ERROR_OK) {
 191                 LOG_ERROR("register read failed");
 192                 return retval;
 193         }
 194
 195         *data = buf_get_u32(field.in_value, 0, 32);
 196
 197         return ERROR_OK;
 198 }
 199
 200 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
 201 {
 202         struct jtag_tap *tap;
 203         tap  = ejtag_info->tap;
 204         assert(tap != NULL);
 205
 206         struct scan_field field;
 207
 208         field.num_bits = 8;
 209         field.out_value = &data;
 210         field.in_value = NULL;
 211
 212         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 213 }
 214
 215 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
 216 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
 217 {
 218         struct pracc_queue_info ctx = {.max_code = 7};
 219         pracc_queue_init(&ctx);
 220         if (ctx.retval != ERROR_OK)
 221                 goto exit;
 222
 223         pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0));                      /* move COP0 Debug to $8 */
 224         pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100));                   /* set SSt bit in debug reg */
 225         if (!enable_step)
 226                 pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100));          /* clear SSt bit in debug reg */
 227
 228         pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0));                      /* move $8 to COP0 Debug */
 229         pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8)));           /* restore upper 16 bits  of $8 */
 230         pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1))));                      /* jump to start */
 231         pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8)));        /* restore lower 16 bits of $8 */
 232
 233         ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
 234 exit:
 235         pracc_queue_free(&ctx);
 236         return ctx.retval;
 237 }
 238
 239 /*
 240  * Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
 241  * It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
 242  * For example bcm7401 and others. At leas on some
 243  * CPUs, DebugMode wont start if this bit is not removed.
 244  */
 245 static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
 246 {
 247         uint32_t dcr;
 248         int retval;
 249
 250         retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
 251         if (retval != ERROR_OK)
 252                 goto error;
 253
 254         dcr &= ~EJTAG_DCR_MP;
 255         retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
 256         if (retval != ERROR_OK)
 257                 goto error;
 258         return ERROR_OK;
 259 error:
 260         LOG_ERROR("Failed to remove DCR MPbit!");
 261         return retval;
 262 }
 263
 264 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
 265 {
 266         uint32_t ejtag_ctrl;
 267         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 268
 269         if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
 270                 if (disable_dcr_mp(ejtag_info) != ERROR_OK)
 271                         goto error;
 272         }
 273
 274         /* set debug break bit */
 275         ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
 276         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 277
 278         /* break bit will be cleared by hardware */
 279         ejtag_ctrl = ejtag_info->ejtag_ctrl;
 280         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 281         LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
 282         if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
 283                 goto error;
 284
 285         return ERROR_OK;
 286 error:
 287         LOG_ERROR("Failed to enter Debug Mode!");
 288         return ERROR_FAIL;
 289 }
 290
 291 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
 292 {
 293         uint32_t pracc_list[] = {MIPS32_DRET, 0};
 294         struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = pracc_list, .code_count = 1, .store_count = 0};
 295
 296         /* execute our dret instruction */
 297         ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
 298
 299         /* pic32mx workaround, false pending at low core clock */
 300         jtag_add_sleep(1000);
 301         return ctx.retval;
 302 }
 303
 304 /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
 305  *                      on EJTAG version.
 306  */
 307 static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
 308 {
 309         if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
 310                 ejtag_info->ejtag_ibs_addr      = EJTAG_V20_IBS;
 311                 ejtag_info->ejtag_iba0_addr     = EJTAG_V20_IBA0;
 312                 ejtag_info->ejtag_ibc_offs      = EJTAG_V20_IBC_OFFS;
 313                 ejtag_info->ejtag_ibm_offs      = EJTAG_V20_IBM_OFFS;
 314
 315                 ejtag_info->ejtag_dbs_addr      = EJTAG_V20_DBS;
 316                 ejtag_info->ejtag_dba0_addr     = EJTAG_V20_DBA0;
 317                 ejtag_info->ejtag_dbc_offs      = EJTAG_V20_DBC_OFFS;
 318                 ejtag_info->ejtag_dbm_offs      = EJTAG_V20_DBM_OFFS;
 319                 ejtag_info->ejtag_dbv_offs      = EJTAG_V20_DBV_OFFS;
 320
 321                 ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP;
 322                 ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP;
 323         } else {
 324                 ejtag_info->ejtag_ibs_addr      = EJTAG_V25_IBS;
 325                 ejtag_info->ejtag_iba0_addr     = EJTAG_V25_IBA0;
 326                 ejtag_info->ejtag_ibm_offs      = EJTAG_V25_IBM_OFFS;
 327                 ejtag_info->ejtag_ibasid_offs   = EJTAG_V25_IBASID_OFFS;
 328                 ejtag_info->ejtag_ibc_offs      = EJTAG_V25_IBC_OFFS;
 329
 330                 ejtag_info->ejtag_dbs_addr      = EJTAG_V25_DBS;
 331                 ejtag_info->ejtag_dba0_addr     = EJTAG_V25_DBA0;
 332                 ejtag_info->ejtag_dbm_offs      = EJTAG_V25_DBM_OFFS;
 333                 ejtag_info->ejtag_dbasid_offs   = EJTAG_V25_DBASID_OFFS;
 334                 ejtag_info->ejtag_dbc_offs      = EJTAG_V25_DBC_OFFS;
 335                 ejtag_info->ejtag_dbv_offs      = EJTAG_V25_DBV_OFFS;
 336
 337                 ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP;
 338                 ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP;
 339         }
 340 }
 341
 342 static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info)
 343 {
 344         LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
 345                 EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP) ? " SDBBP_SPECIAL2" : " SDBBP",
 346                 EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT) ? " EADDR>32bit" : " EADDR=32bit",
 347                 EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK) ? " COMPLEX_BREAK" : "",
 348                 EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH) ? " DCACHE_COH" : " DCACHE_NOT_COH",
 349                 EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH) ? " ICACHE_COH" : " ICACHE_NOT_COH",
 350                 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
 351                 EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
 352                 EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
 353         LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
 354                 (uint8_t)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
 355                 EJTAG_V20_IMP_BCHANNELS_MASK));
 356 }
 357
 358 static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)
 359 {
 360         LOG_DEBUG("EJTAG v2.6: features:%s%s",
 361                 EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K) ? " R3k" : " R4k",
 362                 EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT) ? " DINT" : "");
 363 }
 364
 365 static void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
 366 {
 367         LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
 368                 EJTAG_IMP_HAS(EJTAG_IMP_ASID8) ? " ASID_8" : "",
 369                 EJTAG_IMP_HAS(EJTAG_IMP_ASID6) ? " ASID_6" : "",
 370                 EJTAG_IMP_HAS(EJTAG_IMP_MIPS16) ? " MIPS16" : "",
 371                 EJTAG_IMP_HAS(EJTAG_IMP_NODMA) ? " noDMA" : " DMA",
 372                 EJTAG_IMP_HAS(EJTAG_DCR_MIPS64) ? " MIPS64" : " MIPS32");
 373
 374         switch (ejtag_info->ejtag_version) {
 375                 case EJTAG_VERSION_20:
 376                         ejtag_v20_print_imp(ejtag_info);
 377                         break;
 378                 case EJTAG_VERSION_25:
 379                 case EJTAG_VERSION_26:
 380                 case EJTAG_VERSION_31:
 381                 case EJTAG_VERSION_41:
 382                 case EJTAG_VERSION_51:
 383                         ejtag_v26_print_imp(ejtag_info);
 384                         break;
 385                 default:
 386                         break;
 387         }
 388 }
 389
 390 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
 391 {
 392         int retval;
 393
 394         retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
 395         if (retval != ERROR_OK)
 396                 return retval;
 397         LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
 398
 399         /* get ejtag version */
 400         ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
 401
 402         switch (ejtag_info->ejtag_version) {
 403                 case EJTAG_VERSION_20:
 404                         LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
 405                         break;
 406                 case EJTAG_VERSION_25:
 407                         LOG_DEBUG("EJTAG: Version 2.5 Detected");
 408                         break;
 409                 case EJTAG_VERSION_26:
 410                         LOG_DEBUG("EJTAG: Version 2.6 Detected");
 411                         break;
 412                 case EJTAG_VERSION_31:
 413                         LOG_DEBUG("EJTAG: Version 3.1 Detected");
 414                         break;
 415                 case EJTAG_VERSION_41:
 416                         LOG_DEBUG("EJTAG: Version 4.1 Detected");
 417                         break;
 418                 case EJTAG_VERSION_51:
 419                         LOG_DEBUG("EJTAG: Version 5.1 Detected");
 420                         break;
 421                 default:
 422                         LOG_DEBUG("EJTAG: Unknown Version Detected");
 423                         break;
 424         }
 425         ejtag_main_print_imp(ejtag_info);
 426
 427         if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0) {
 428                 LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
 429                           "workaround current broken code.");
 430                 ejtag_info->impcode |= EJTAG_IMP_NODMA;
 431         }
 432
 433         ejtag_info->ejtag_ctrl = EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN;
 434
 435         if (ejtag_info->ejtag_version != EJTAG_VERSION_20)
 436                 ejtag_info->ejtag_ctrl |= EJTAG_CTRL_ROCC | EJTAG_CTRL_SETDEV;
 437
 438         ejtag_info->fast_access_save = -1;
 439
 440         mips_ejtag_init_mmr(ejtag_info);
 441
 442         return ERROR_OK;
 443 }
 444
 445 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
 446 {
 447         struct jtag_tap *tap;
 448
 449         tap = ejtag_info->tap;
 450         assert(tap != NULL);
 451
 452         struct scan_field fields[2];
 453         uint8_t spracc = 0;
 454         uint8_t t[4] = {0, 0, 0, 0};
 455
 456         /* fastdata 1-bit register */
 457         fields[0].num_bits = 1;
 458         fields[0].out_value = &spracc;
 459         fields[0].in_value = NULL;
 460
 461         /* processor access data register 32 bit */
 462         fields[1].num_bits = 32;
 463         fields[1].out_value = t;
 464
 465         if (write_t) {
 466                 fields[1].in_value = NULL;
 467                 buf_set_u32(t, 0, 32, *data);
 468         } else
 469                 fields[1].in_value = (uint8_t *) data;
 470
 471         jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
 472
 473         if (!write_t && data)
 474                 jtag_add_callback(mips_le_to_h_u32,
 475                         (jtag_callback_data_t) data);
 476
 477         keep_alive();
 478
 479         return ERROR_OK;
 480 }