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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "mips32.h"
  30 #include "mips_ejtag.h"
  31
  32 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
  33 {
  34         struct jtag_tap *tap;
  35
  36         tap = ejtag_info->tap;
  37         assert(tap != NULL);
  38
  39         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) {
  40                 struct scan_field field;
  41                 uint8_t t[4];
  42
  43                 field.num_bits = tap->ir_length;
  44                 field.out_value = t;
  45                 buf_set_u32(t, 0, field.num_bits, new_instr);
  46                 field.in_value = NULL;
  47
  48                 jtag_add_ir_scan(tap, &field, TAP_IDLE);
  49         }
  50 }
  51
  52 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
  53 {
  54         struct scan_field field;
  55         uint8_t r[4];
  56
  57         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
  58
  59         field.num_bits = 32;
  60         field.out_value = NULL;
  61         field.in_value = r;
  62
  63         jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
  64
  65         int retval;
  66         retval = jtag_execute_queue();
  67         if (retval != ERROR_OK) {
  68                 LOG_ERROR("register read failed");
  69                 return retval;
  70         }
  71
  72         *idcode = buf_get_u32(field.in_value, 0, 32);
  73
  74         return ERROR_OK;
  75 }
  76
  77 static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
  78 {
  79         struct scan_field field;
  80         uint8_t r[4];
  81
  82         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
  83
  84         field.num_bits = 32;
  85         field.out_value = NULL;
  86         field.in_value = r;
  87
  88         jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
  89
  90         int retval;
  91         retval = jtag_execute_queue();
  92         if (retval != ERROR_OK) {
  93                 LOG_ERROR("register read failed");
  94                 return retval;
  95         }
  96
  97         *impcode = buf_get_u32(field.in_value, 0, 32);
  98
  99         return ERROR_OK;
 100 }
 101
 102 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
 103 {
 104         assert(ejtag_info->tap != NULL);
 105         struct jtag_tap *tap = ejtag_info->tap;
 106
 107         struct scan_field field;
 108         uint8_t out_scan[12];
 109
 110         /* processor access "all" register 96 bit */
 111         field.num_bits = 96;
 112
 113         field.out_value = out_scan;
 114         buf_set_u32(out_scan, 0, 32, ctrl);
 115         buf_set_u32(out_scan + 4, 0, 32, data);
 116         buf_set_u32(out_scan + 8, 0, 32, 0);
 117
 118         field.in_value = in_scan_buf;
 119
 120         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 121
 122         keep_alive();
 123 }
 124
 125 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 126 {
 127         struct jtag_tap *tap;
 128         tap  = ejtag_info->tap;
 129         assert(tap != NULL);
 130
 131         struct scan_field field;
 132         uint8_t t[4], r[4];
 133         int retval;
 134
 135         field.num_bits = 32;
 136         field.out_value = t;
 137         buf_set_u32(t, 0, field.num_bits, *data);
 138         field.in_value = r;
 139
 140         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 141
 142         retval = jtag_execute_queue();
 143         if (retval != ERROR_OK) {
 144                 LOG_ERROR("register read failed");
 145                 return retval;
 146         }
 147
 148         *data = buf_get_u32(field.in_value, 0, 32);
 149
 150         keep_alive();
 151
 152         return ERROR_OK;
 153 }
 154
 155 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
 156 {
 157         uint8_t t[4];
 158         struct jtag_tap *tap;
 159         tap  = ejtag_info->tap;
 160         assert(tap != NULL);
 161
 162         struct scan_field field;
 163
 164         field.num_bits = 32;
 165         field.out_value = t;
 166         buf_set_u32(t, 0, field.num_bits, data);
 167
 168         field.in_value = NULL;
 169
 170         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 171 }
 172
 173 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
 174 {
 175         struct jtag_tap *tap;
 176         tap  = ejtag_info->tap;
 177         assert(tap != NULL);
 178
 179         struct scan_field field;
 180         uint8_t t[4] = {0, 0, 0, 0}, r[4];
 181         int retval;
 182
 183         field.num_bits = 8;
 184         field.out_value = t;
 185         buf_set_u32(t, 0, field.num_bits, *data);
 186         field.in_value = r;
 187
 188         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 189
 190         retval = jtag_execute_queue();
 191         if (retval != ERROR_OK) {
 192                 LOG_ERROR("register read failed");
 193                 return retval;
 194         }
 195
 196         *data = buf_get_u32(field.in_value, 0, 32);
 197
 198         return ERROR_OK;
 199 }
 200
 201 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
 202 {
 203         struct jtag_tap *tap;
 204         tap  = ejtag_info->tap;
 205         assert(tap != NULL);
 206
 207         struct scan_field field;
 208
 209         field.num_bits = 8;
 210         field.out_value = &data;
 211         field.in_value = NULL;
 212
 213         jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 214 }
 215
 216 /* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
 217 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
 218 {
 219         struct pracc_queue_info ctx = {.max_code = 7};
 220         pracc_queue_init(&ctx);
 221         if (ctx.retval != ERROR_OK)
 222                 goto exit;
 223
 224         pracc_add(&ctx, 0, MIPS32_MFC0(8, 23, 0));                      /* move COP0 Debug to $8 */
 225         pracc_add(&ctx, 0, MIPS32_ORI(8, 8, 0x0100));                   /* set SSt bit in debug reg */
 226         if (!enable_step)
 227                 pracc_add(&ctx, 0, MIPS32_XORI(8, 8, 0x0100));          /* clear SSt bit in debug reg */
 228
 229         pracc_add(&ctx, 0, MIPS32_MTC0(8, 23, 0));                      /* move $8 to COP0 Debug */
 230         pracc_add(&ctx, 0, MIPS32_LUI(8, UPPER16(ejtag_info->reg8)));           /* restore upper 16 bits  of $8 */
 231         pracc_add(&ctx, 0, MIPS32_B(NEG16((ctx.code_count + 1))));                      /* jump to start */
 232         pracc_add(&ctx, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info->reg8)));        /* restore lower 16 bits of $8 */
 233
 234         ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
 235 exit:
 236         pracc_queue_free(&ctx);
 237         return ctx.retval;
 238 }
 239
 240 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
 241 {
 242         uint32_t ejtag_ctrl;
 243         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 244
 245         /* set debug break bit */
 246         ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
 247         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 248
 249         /* break bit will be cleared by hardware */
 250         ejtag_ctrl = ejtag_info->ejtag_ctrl;
 251         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 252         LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
 253         if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) {
 254                 LOG_ERROR("Failed to enter Debug Mode!");
 255                 return ERROR_FAIL;
 256         }
 257
 258         return ERROR_OK;
 259 }
 260
 261 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
 262 {
 263         uint32_t instr = MIPS32_DRET;
 264         struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &instr, .code_count = 1, .store_count = 0};
 265
 266         /* execute our dret instruction */
 267         ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL);
 268
 269         /* pic32mx workaround, false pending at low core clock */
 270         jtag_add_sleep(1000);
 271         return ctx.retval;
 272 }
 273
 274 int mips_ejtag_init(struct mips_ejtag *ejtag_info)
 275 {
 276         int retval;
 277
 278         retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
 279         if (retval != ERROR_OK)
 280                 return retval;
 281         LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
 282
 283         /* get ejtag version */
 284         ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
 285
 286         switch (ejtag_info->ejtag_version) {
 287                 case EJTAG_VERSION_20:
 288                         LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
 289                         break;
 290                 case EJTAG_VERSION_25:
 291                         LOG_DEBUG("EJTAG: Version 2.5 Detected");
 292                         break;
 293                 case EJTAG_VERSION_26:
 294                         LOG_DEBUG("EJTAG: Version 2.6 Detected");
 295                         break;
 296                 case EJTAG_VERSION_31:
 297                         LOG_DEBUG("EJTAG: Version 3.1 Detected");
 298                         break;
 299                 case EJTAG_VERSION_41:
 300                         LOG_DEBUG("EJTAG: Version 4.1 Detected");
 301                         break;
 302                 case EJTAG_VERSION_51:
 303                         LOG_DEBUG("EJTAG: Version 5.1 Detected");
 304                         break;
 305                 default:
 306                         LOG_DEBUG("EJTAG: Unknown Version Detected");
 307                         break;
 308         }
 309         LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
 310                 ejtag_info->impcode & EJTAG_IMP_R3K ? " R3k" : " R4k",
 311                 ejtag_info->impcode & EJTAG_IMP_DINT ? " DINT" : "",
 312                 ejtag_info->impcode & (1 << 22) ? " ASID_8" : "",
 313                 ejtag_info->impcode & (1 << 21) ? " ASID_6" : "",
 314                 ejtag_info->impcode & EJTAG_IMP_MIPS16 ? " MIPS16" : "",
 315                 ejtag_info->impcode & EJTAG_IMP_NODMA ? " noDMA" : " DMA",
 316                 ejtag_info->impcode & EJTAG_DCR_MIPS64  ? " MIPS64" : " MIPS32");
 317
 318         if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0)
 319                 LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
 320
 321         /* set initial state for ejtag control reg */
 322         ejtag_info->ejtag_ctrl = EJTAG_CTRL_ROCC | EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN | EJTAG_CTRL_SETDEV;
 323         ejtag_info->fast_access_save = -1;
 324
 325         return ERROR_OK;
 326 }
 327
 328 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
 329 {
 330         struct jtag_tap *tap;
 331
 332         tap = ejtag_info->tap;
 333         assert(tap != NULL);
 334
 335         struct scan_field fields[2];
 336         uint8_t spracc = 0;
 337         uint8_t t[4] = {0, 0, 0, 0};
 338
 339         /* fastdata 1-bit register */
 340         fields[0].num_bits = 1;
 341         fields[0].out_value = &spracc;
 342         fields[0].in_value = NULL;
 343
 344         /* processor access data register 32 bit */
 345         fields[1].num_bits = 32;
 346         fields[1].out_value = t;
 347
 348         if (write_t) {
 349                 fields[1].in_value = NULL;
 350                 buf_set_u32(t, 0, 32, *data);
 351         } else
 352                 fields[1].in_value = (void *) data;
 353
 354         jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
 355
 356         if (!write_t && data)
 357                 jtag_add_callback(mips_le_to_h_u32,
 358                         (jtag_callback_data_t) data);
 359
 360         keep_alive();
 361
 362         return ERROR_OK;
 363 }