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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
   8  *   drasko.draskovic@gmail.com                                            *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  24  ***************************************************************************/
  25
  26 #ifndef MIPS32_PRACC_H
  27 #define MIPS32_PRACC_H
  28
  29 #include <target/mips32.h>
  30 #include <target/mips_ejtag.h>
  31
  32 #define MIPS32_PRACC_FASTDATA_AREA              0xFF200000
  33 #define MIPS32_PRACC_BASE_ADDR                  0xFF200000
  34 #define MIPS32_PRACC_FASTDATA_SIZE              16
  35 #define MIPS32_PRACC_TEXT                               0xFF200200
  36 #define MIPS32_PRACC_STACK                              0xFF204000
  37 #define MIPS32_PRACC_PARAM_IN                   0xFF201000
  38 #define MIPS32_PRACC_PARAM_IN_SIZE              0x1000
  39 #define MIPS32_PRACC_PARAM_OUT                  (MIPS32_PRACC_PARAM_IN + MIPS32_PRACC_PARAM_IN_SIZE)
  40 #define MIPS32_PRACC_PARAM_OUT_SIZE             0x1000
  41
  42 #define PRACC_UPPER_BASE_ADDR                   (MIPS32_PRACC_BASE_ADDR >> 16)
  43 #define PRACC_TEXT_OFFSET                       (MIPS32_PRACC_TEXT - MIPS32_PRACC_BASE_ADDR)
  44 #define PRACC_IN_OFFSET                         (MIPS32_PRACC_PARAM_IN - MIPS32_PRACC_BASE_ADDR)
  45 #define PRACC_OUT_OFFSET                        (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)
  46 #define PRACC_STACK_OFFSET                      (MIPS32_PRACC_STACK - MIPS32_PRACC_BASE_ADDR)
  47
  48 #define MIPS32_FASTDATA_HANDLER_SIZE    0x80
  49 #define UPPER16(uint32_t)                               (uint32_t >> 16)
  50 #define LOWER16(uint32_t)                               (uint32_t & 0xFFFF)
  51 #define NEG16(v)                                                (((~(v)) + 1) & 0xFFFF)
  52 /*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
  53
  54 struct pracc_queue_info {
  55         int retval;
  56         const int max_code;
  57         int code_count;
  58         int store_count;
  59         uint32_t *pracc_list;   /* Code and store addresses */
  60 };
  61 void pracc_queue_init(struct pracc_queue_info *ctx);
  62 void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
  63 void pracc_queue_free(struct pracc_queue_info *ctx);
  64 int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info,
  65                             struct pracc_queue_info *ctx, uint32_t *buf);
  66
  67 int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
  68                 uint32_t addr, int size, int count, void *buf);
  69 int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
  70                 uint32_t addr, int size, int count, void *buf);
  71 int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
  72                 int write_t, uint32_t addr, int count, uint32_t *buf);
  73
  74 int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
  75 int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
  76
  77 int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code,
  78                 int num_param_in, uint32_t *param_in,
  79                 int num_param_out, uint32_t *param_out, int cycle);
  80
  81 /**
  82  * \b mips32_cp0_read
  83  *
  84  * Simulates mfc0 ASM instruction (Move From C0),
  85  * i.e. implements copro C0 Register read.
  86  *
  87  * @param[in] ejtag_info
  88  * @param[in] val Storage to hold read value
  89  * @param[in] cp0_reg Number of copro C0 register we want to read
  90  * @param[in] cp0_sel Select for the given C0 register
  91  *
  92  * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
  93  */
  94 int mips32_cp0_read(struct mips_ejtag *ejtag_info,
  95                 uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
  96
  97 /**
  98  * \b mips32_cp0_write
  99  *
 100  * Simulates mtc0 ASM instruction (Move To C0),
 101  * i.e. implements copro C0 Register read.
 102  *
 103  * @param[in] ejtag_info
 104  * @param[in] val Value to be written
 105  * @param[in] cp0_reg Number of copro C0 register we want to write to
 106  * @param[in] cp0_sel Select for the given C0 register
 107  *
 108  * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
 109  */
 110 int mips32_cp0_write(struct mips_ejtag *ejtag_info,
 111                 uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
 112
 113 #endif