1 /***************************************************************************
2 * Copyright (C) 2008 by John McCarthy *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by David T.L. Wong *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ***************************************************************************/
30 #include "mips32_dmaacc.h"
32 static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info,
33 uint32_t addr, int count, uint8_t *buf);
34 static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info,
35 uint32_t addr, int count, uint16_t *buf);
36 static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info,
37 uint32_t addr, int count, uint32_t *buf);
39 static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info,
40 uint32_t addr, int count, uint8_t *buf);
41 static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info,
42 uint32_t addr, int count, uint16_t *buf);
43 static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info,
44 uint32_t addr, int count, uint32_t *buf);
47 * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
48 * to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
49 * (and any others that support EJTAG DMA transfers).
50 * Note: This only supports memory read/write. Since the BCM5352 doesn't
51 * appear to support PRACC accesses, all debug functions except halt
52 * do not work. Still, this does allow erasing/writing flash as well as
53 * displaying/modifying memory and memory mapped registers.
56 static int ejtag_dma_read(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *data)
60 int retries = RETRY_ATTEMPTS;
66 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
67 mips_ejtag_drscan_32(ejtag_info, &v);
69 /* Initiate DMA Read & set DSTRT */
70 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
71 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
72 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
74 /* Wait for DSTRT to Clear */
76 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
77 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
78 } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
81 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
82 mips_ejtag_drscan_32(ejtag_info, data);
84 /* Clear DMA & Check DERR */
85 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
86 ejtag_ctrl = ejtag_info->ejtag_ctrl;
87 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
88 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
90 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
91 goto begin_ejtag_dma_read;
93 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
94 return ERROR_JTAG_DEVICE_ERROR;
100 static int ejtag_dma_read_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint16_t *data)
104 int retries = RETRY_ATTEMPTS;
106 begin_ejtag_dma_read_h:
110 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
111 mips_ejtag_drscan_32(ejtag_info, &v);
113 /* Initiate DMA Read & set DSTRT */
114 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
115 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD |
116 EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
117 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
119 /* Wait for DSTRT to Clear */
121 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
122 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
123 } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
126 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
127 mips_ejtag_drscan_32(ejtag_info, &v);
129 /* Clear DMA & Check DERR */
130 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
131 ejtag_ctrl = ejtag_info->ejtag_ctrl;
132 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
133 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
135 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
136 goto begin_ejtag_dma_read_h;
138 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
139 return ERROR_JTAG_DEVICE_ERROR;
142 /* Handle the bigendian/littleendian */
144 *data = (v >> 16) & 0xffff;
146 *data = (v & 0x0000ffff);
151 static int ejtag_dma_read_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint8_t *data)
155 int retries = RETRY_ATTEMPTS;
157 begin_ejtag_dma_read_b:
161 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
162 mips_ejtag_drscan_32(ejtag_info, &v);
164 /* Initiate DMA Read & set DSTRT */
165 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
166 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
167 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
169 /* Wait for DSTRT to Clear */
171 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
172 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
173 } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
176 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
177 mips_ejtag_drscan_32(ejtag_info, &v);
179 /* Clear DMA & Check DERR */
180 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
181 ejtag_ctrl = ejtag_info->ejtag_ctrl;
182 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
183 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
185 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
186 goto begin_ejtag_dma_read_b;
188 LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
189 return ERROR_JTAG_DEVICE_ERROR;
192 /* Handle the bigendian/littleendian */
193 switch (addr & 0x3) {
198 *data = (v >> 8) & 0xff;
201 *data = (v >> 16) & 0xff;
204 *data = (v >> 24) & 0xff;
211 static int ejtag_dma_write(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
215 int retries = RETRY_ATTEMPTS;
217 begin_ejtag_dma_write:
221 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
222 mips_ejtag_drscan_32(ejtag_info, &v);
226 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
227 mips_ejtag_drscan_32(ejtag_info, &v);
229 /* Initiate DMA Write & set DSTRT */
230 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
231 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
232 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
234 /* Wait for DSTRT to Clear */
236 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
237 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
238 } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
240 /* Clear DMA & Check DERR */
241 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
242 ejtag_ctrl = ejtag_info->ejtag_ctrl;
243 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
244 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
246 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
247 goto begin_ejtag_dma_write;
249 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
250 return ERROR_JTAG_DEVICE_ERROR;
256 static int ejtag_dma_write_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
260 int retries = RETRY_ATTEMPTS;
262 /* Handle the bigendian/littleendian */
266 begin_ejtag_dma_write_h:
270 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
271 mips_ejtag_drscan_32(ejtag_info, &v);
275 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
276 mips_ejtag_drscan_32(ejtag_info, &v);
278 /* Initiate DMA Write & set DSTRT */
279 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
280 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
281 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
283 /* Wait for DSTRT to Clear */
285 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
286 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
287 } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
289 /* Clear DMA & Check DERR */
290 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
291 ejtag_ctrl = ejtag_info->ejtag_ctrl;
292 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
293 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
295 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
296 goto begin_ejtag_dma_write_h;
298 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
299 return ERROR_JTAG_DEVICE_ERROR;
305 static int ejtag_dma_write_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
309 int retries = RETRY_ATTEMPTS;
311 /* Handle the bigendian/littleendian */
316 begin_ejtag_dma_write_b:
320 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
321 mips_ejtag_drscan_32(ejtag_info, &v);
325 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
326 mips_ejtag_drscan_32(ejtag_info, &v);
328 /* Initiate DMA Write & set DSTRT */
329 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
330 ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
331 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
333 /* Wait for DSTRT to Clear */
335 ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
336 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
337 } while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
339 /* Clear DMA & Check DERR */
340 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
341 ejtag_ctrl = ejtag_info->ejtag_ctrl;
342 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
343 if (ejtag_ctrl & EJTAG_CTRL_DERR) {
345 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
346 goto begin_ejtag_dma_write_b;
348 LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
349 return ERROR_JTAG_DEVICE_ERROR;
355 int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
359 return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf);
361 return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf);
363 return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf);
369 static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
374 for (i = 0; i < count; i++) {
375 retval = ejtag_dma_read(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
376 if (retval != ERROR_OK)
383 static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
388 for (i = 0; i < count; i++) {
389 retval = ejtag_dma_read_h(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
390 if (retval != ERROR_OK)
397 static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
402 for (i = 0; i < count; i++) {
403 retval = ejtag_dma_read_b(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
404 if (retval != ERROR_OK)
411 int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
415 return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (uint8_t *)buf);
417 return mips32_dmaacc_write_mem16(ejtag_info, addr, count, (uint16_t *)buf);
419 return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (uint32_t *)buf);
425 static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
430 for (i = 0; i < count; i++) {
431 retval = ejtag_dma_write(ejtag_info, addr + i * sizeof(*buf), buf[i]);
432 if (retval != ERROR_OK)
439 static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
444 for (i = 0; i < count; i++) {
445 retval = ejtag_dma_write_h(ejtag_info, addr + i * sizeof(*buf), buf[i]);
446 if (retval != ERROR_OK)
453 static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
458 for (i = 0; i < count; i++) {
459 retval = ejtag_dma_write_b(ejtag_info, addr + i * sizeof(*buf), buf[i]);
460 if (retval != ERROR_OK)