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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   8  *   oyvind.harboe@zylin.com                                               *
   9  *                                                                         *
  10  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
  11  *   drasko.draskovic@gmail.com                                            *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include "mips32.h"
  33 #include "breakpoints.h"
  34 #include "algorithm.h"
  35 #include "register.h"
  36
  37 static char* mips32_core_reg_list[] =
  38 {
  39         "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
  40         "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
  41         "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
  42         "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
  43         "status", "lo", "hi", "badvaddr", "cause", "pc"
  44 };
  45
  46 static const char *mips_isa_strings[] =
  47 {
  48         "MIPS32", "MIPS16e"
  49 };
  50
  51 static struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
  52 {
  53         {0, NULL, NULL},
  54         {1, NULL, NULL},
  55         {2, NULL, NULL},
  56         {3, NULL, NULL},
  57         {4, NULL, NULL},
  58         {5, NULL, NULL},
  59         {6, NULL, NULL},
  60         {7, NULL, NULL},
  61         {8, NULL, NULL},
  62         {9, NULL, NULL},
  63         {10, NULL, NULL},
  64         {11, NULL, NULL},
  65         {12, NULL, NULL},
  66         {13, NULL, NULL},
  67         {14, NULL, NULL},
  68         {15, NULL, NULL},
  69         {16, NULL, NULL},
  70         {17, NULL, NULL},
  71         {18, NULL, NULL},
  72         {19, NULL, NULL},
  73         {20, NULL, NULL},
  74         {21, NULL, NULL},
  75         {22, NULL, NULL},
  76         {23, NULL, NULL},
  77         {24, NULL, NULL},
  78         {25, NULL, NULL},
  79         {26, NULL, NULL},
  80         {27, NULL, NULL},
  81         {28, NULL, NULL},
  82         {29, NULL, NULL},
  83         {30, NULL, NULL},
  84         {31, NULL, NULL},
  85
  86         {32, NULL, NULL},
  87         {33, NULL, NULL},
  88         {34, NULL, NULL},
  89         {35, NULL, NULL},
  90         {36, NULL, NULL},
  91         {37, NULL, NULL},
  92 };
  93
  94 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
  95  * we also add 18 unknown registers to handle gdb requests */
  96
  97 #define MIPS32NUMFPREGS 34 + 18
  98
  99 static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
 100
 101 static struct reg mips32_gdb_dummy_fp_reg =
 102 {
 103         .name = "GDB dummy floating-point register",
 104         .value = mips32_gdb_dummy_fp_value,
 105         .dirty = 0,
 106         .valid = 1,
 107         .size = 32,
 108         .arch_info = NULL,
 109 };
 110
 111 static int mips32_get_core_reg(struct reg *reg)
 112 {
 113         int retval;
 114         struct mips32_core_reg *mips32_reg = reg->arch_info;
 115         struct target *target = mips32_reg->target;
 116         struct mips32_common *mips32_target = target_to_mips32(target);
 117
 118         if (target->state != TARGET_HALTED)
 119         {
 120                 return ERROR_TARGET_NOT_HALTED;
 121         }
 122
 123         retval = mips32_target->read_core_reg(target, mips32_reg->num);
 124
 125         return retval;
 126 }
 127
 128 static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
 129 {
 130         struct mips32_core_reg *mips32_reg = reg->arch_info;
 131         struct target *target = mips32_reg->target;
 132         uint32_t value = buf_get_u32(buf, 0, 32);
 133
 134         if (target->state != TARGET_HALTED)
 135         {
 136                 return ERROR_TARGET_NOT_HALTED;
 137         }
 138
 139         buf_set_u32(reg->value, 0, 32, value);
 140         reg->dirty = 1;
 141         reg->valid = 1;
 142
 143         return ERROR_OK;
 144 }
 145
 146 static int mips32_read_core_reg(struct target *target, int num)
 147 {
 148         uint32_t reg_value;
 149
 150         /* get pointers to arch-specific information */
 151         struct mips32_common *mips32 = target_to_mips32(target);
 152
 153         if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 154                 return ERROR_COMMAND_SYNTAX_ERROR;
 155
 156         reg_value = mips32->core_regs[num];
 157         buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
 158         mips32->core_cache->reg_list[num].valid = 1;
 159         mips32->core_cache->reg_list[num].dirty = 0;
 160
 161         return ERROR_OK;
 162 }
 163
 164 static int mips32_write_core_reg(struct target *target, int num)
 165 {
 166         uint32_t reg_value;
 167
 168         /* get pointers to arch-specific information */
 169         struct mips32_common *mips32 = target_to_mips32(target);
 170
 171         if ((num < 0) || (num >= MIPS32NUMCOREREGS))
 172                 return ERROR_COMMAND_SYNTAX_ERROR;
 173
 174         reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
 175         mips32->core_regs[num] = reg_value;
 176         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 177         mips32->core_cache->reg_list[num].valid = 1;
 178         mips32->core_cache->reg_list[num].dirty = 0;
 179
 180         return ERROR_OK;
 181 }
 182
 183 int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 184 {
 185         /* get pointers to arch-specific information */
 186         struct mips32_common *mips32 = target_to_mips32(target);
 187         int i;
 188
 189         /* include floating point registers */
 190         *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
 191         *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
 192
 193         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 194         {
 195                 (*reg_list)[i] = &mips32->core_cache->reg_list[i];
 196         }
 197
 198         /* add dummy floating points regs */
 199         for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
 200         {
 201                 (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
 202         }
 203
 204         return ERROR_OK;
 205 }
 206
 207 int mips32_save_context(struct target *target)
 208 {
 209         int i;
 210
 211         /* get pointers to arch-specific information */
 212         struct mips32_common *mips32 = target_to_mips32(target);
 213         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 214
 215         /* read core registers */
 216         mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
 217
 218         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 219         {
 220                 if (!mips32->core_cache->reg_list[i].valid)
 221                 {
 222                         mips32->read_core_reg(target, i);
 223                 }
 224         }
 225
 226         return ERROR_OK;
 227 }
 228
 229 int mips32_restore_context(struct target *target)
 230 {
 231         int i;
 232
 233         /* get pointers to arch-specific information */
 234         struct mips32_common *mips32 = target_to_mips32(target);
 235         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 236
 237         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 238         {
 239                 if (mips32->core_cache->reg_list[i].dirty)
 240                 {
 241                         mips32->write_core_reg(target, i);
 242                 }
 243         }
 244
 245         /* write core regs */
 246         mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
 247
 248         return ERROR_OK;
 249 }
 250
 251 int mips32_arch_state(struct target *target)
 252 {
 253         struct mips32_common *mips32 = target_to_mips32(target);
 254
 255         LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
 256                 mips_isa_strings[mips32->isa_mode],
 257                 debug_reason_name(target),
 258                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 259
 260         return ERROR_OK;
 261 }
 262
 263 static const struct reg_arch_type mips32_reg_type = {
 264         .get = mips32_get_core_reg,
 265         .set = mips32_set_core_reg,
 266 };
 267
 268 struct reg_cache *mips32_build_reg_cache(struct target *target)
 269 {
 270         /* get pointers to arch-specific information */
 271         struct mips32_common *mips32 = target_to_mips32(target);
 272
 273         int num_regs = MIPS32NUMCOREREGS;
 274         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 275         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 276         struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
 277         struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
 278         int i;
 279
 280         register_init_dummy(&mips32_gdb_dummy_fp_reg);
 281
 282         /* Build the process context cache */
 283         cache->name = "mips32 registers";
 284         cache->next = NULL;
 285         cache->reg_list = reg_list;
 286         cache->num_regs = num_regs;
 287         (*cache_p) = cache;
 288         mips32->core_cache = cache;
 289
 290         for (i = 0; i < num_regs; i++)
 291         {
 292                 arch_info[i] = mips32_core_reg_list_arch_info[i];
 293                 arch_info[i].target = target;
 294                 arch_info[i].mips32_common = mips32;
 295                 reg_list[i].name = mips32_core_reg_list[i];
 296                 reg_list[i].size = 32;
 297                 reg_list[i].value = calloc(1, 4);
 298                 reg_list[i].dirty = 0;
 299                 reg_list[i].valid = 0;
 300                 reg_list[i].type = &mips32_reg_type;
 301                 reg_list[i].arch_info = &arch_info[i];
 302         }
 303
 304         return cache;
 305 }
 306
 307 int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
 308 {
 309         target->arch_info = mips32;
 310         mips32->common_magic = MIPS32_COMMON_MAGIC;
 311         mips32->fast_data_area = NULL;
 312
 313         /* has breakpoint/watchpint unit been scanned */
 314         mips32->bp_scanned = 0;
 315         mips32->data_break_list = NULL;
 316
 317         mips32->ejtag_info.tap = tap;
 318         mips32->read_core_reg = mips32_read_core_reg;
 319         mips32->write_core_reg = mips32_write_core_reg;
 320
 321         return ERROR_OK;
 322 }
 323
 324 /* run to exit point. return error if exit point was not reached. */
 325 static int mips32_run_and_wait(struct target *target, uint32_t entry_point,
 326                 int timeout_ms, uint32_t exit_point, struct mips32_common *mips32)
 327 {
 328         uint32_t pc;
 329         int retval;
 330         /* This code relies on the target specific  resume() and  poll()->debug_entry()
 331          * sequence to write register values to the processor and the read them back */
 332         if ((retval = target_resume(target, 0, entry_point, 0, 1)) != ERROR_OK)
 333         {
 334                 return retval;
 335         }
 336
 337         retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
 338         /* If the target fails to halt due to the breakpoint, force a halt */
 339         if (retval != ERROR_OK || target->state != TARGET_HALTED)
 340         {
 341                 if ((retval = target_halt(target)) != ERROR_OK)
 342                         return retval;
 343                 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
 344                 {
 345                         return retval;
 346                 }
 347                 return ERROR_TARGET_TIMEOUT;
 348         }
 349
 350         pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 351         if (exit_point && (pc != exit_point))
 352         {
 353                 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
 354                 return ERROR_TARGET_TIMEOUT;
 355         }
 356
 357         return ERROR_OK;
 358 }
 359
 360 int mips32_run_algorithm(struct target *target, int num_mem_params,
 361                 struct mem_param *mem_params, int num_reg_params,
 362                 struct reg_param *reg_params, uint32_t entry_point,
 363                 uint32_t exit_point, int timeout_ms, void *arch_info)
 364 {
 365         struct mips32_common *mips32 = target_to_mips32(target);
 366         struct mips32_algorithm *mips32_algorithm_info = arch_info;
 367         enum mips32_isa_mode isa_mode = mips32->isa_mode;
 368
 369         uint32_t context[MIPS32NUMCOREREGS];
 370         int i;
 371         int retval = ERROR_OK;
 372
 373         LOG_DEBUG("Running algorithm");
 374
 375         /* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint
 376          * at the exit point */
 377
 378         if (mips32->common_magic != MIPS32_COMMON_MAGIC)
 379         {
 380                 LOG_ERROR("current target isn't a MIPS32 target");
 381                 return ERROR_TARGET_INVALID;
 382         }
 383
 384         if (target->state != TARGET_HALTED)
 385         {
 386                 LOG_WARNING("target not halted");
 387                 return ERROR_TARGET_NOT_HALTED;
 388         }
 389
 390         /* refresh core register cache */
 391         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 392         {
 393                 if (!mips32->core_cache->reg_list[i].valid)
 394                         mips32->read_core_reg(target, i);
 395                 context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
 396         }
 397
 398         for (i = 0; i < num_mem_params; i++)
 399         {
 400                 if ((retval = target_write_buffer(target, mem_params[i].address,
 401                                 mem_params[i].size, mem_params[i].value)) != ERROR_OK)
 402                 {
 403                         return retval;
 404                 }
 405         }
 406
 407         for (i = 0; i < num_reg_params; i++)
 408         {
 409                 struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
 410
 411                 if (!reg)
 412                 {
 413                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 414                         return ERROR_COMMAND_SYNTAX_ERROR;
 415                 }
 416
 417                 if (reg->size != reg_params[i].size)
 418                 {
 419                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
 420                                         reg_params[i].reg_name);
 421                         return ERROR_COMMAND_SYNTAX_ERROR;
 422                 }
 423
 424                 mips32_set_core_reg(reg, reg_params[i].value);
 425         }
 426
 427         mips32->isa_mode = mips32_algorithm_info->isa_mode;
 428
 429         retval = mips32_run_and_wait(target, entry_point, timeout_ms, exit_point, mips32);
 430
 431         if (retval != ERROR_OK)
 432                 return retval;
 433
 434         for (i = 0; i < num_mem_params; i++)
 435         {
 436                 if (mem_params[i].direction != PARAM_OUT)
 437                 {
 438                         if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size,
 439                                         mem_params[i].value)) != ERROR_OK)
 440                         {
 441                                 return retval;
 442                         }
 443                 }
 444         }
 445
 446         for (i = 0; i < num_reg_params; i++)
 447         {
 448                 if (reg_params[i].direction != PARAM_OUT)
 449                 {
 450                         struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
 451                         if (!reg)
 452                         {
 453                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 454                                 return ERROR_COMMAND_SYNTAX_ERROR;
 455                         }
 456
 457                         if (reg->size != reg_params[i].size)
 458                         {
 459                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
 460                                                 reg_params[i].reg_name);
 461                                 return ERROR_COMMAND_SYNTAX_ERROR;
 462                         }
 463
 464                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 465                 }
 466         }
 467
 468         /* restore everything we saved before */
 469         for (i = 0; i < MIPS32NUMCOREREGS; i++)
 470         {
 471                 uint32_t regvalue;
 472                 regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
 473                 if (regvalue != context[i])
 474                 {
 475                         LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
 476                                 mips32->core_cache->reg_list[i].name, context[i]);
 477                         buf_set_u32(mips32->core_cache->reg_list[i].value,
 478                                         0, 32, context[i]);
 479                         mips32->core_cache->reg_list[i].valid = 1;
 480                         mips32->core_cache->reg_list[i].dirty = 1;
 481                 }
 482         }
 483
 484         mips32->isa_mode = isa_mode;
 485
 486         return ERROR_OK;
 487 }
 488
 489 int mips32_examine(struct target *target)
 490 {
 491         struct mips32_common *mips32 = target_to_mips32(target);
 492
 493         if (!target_was_examined(target))
 494         {
 495                 target_set_examined(target);
 496
 497                 /* we will configure later */
 498                 mips32->bp_scanned = 0;
 499                 mips32->num_inst_bpoints = 0;
 500                 mips32->num_data_bpoints = 0;
 501                 mips32->num_inst_bpoints_avail = 0;
 502                 mips32->num_data_bpoints_avail = 0;
 503         }
 504
 505         return ERROR_OK;
 506 }
 507
 508 int mips32_configure_break_unit(struct target *target)
 509 {
 510         /* get pointers to arch-specific information */
 511         struct mips32_common *mips32 = target_to_mips32(target);
 512         int retval;
 513         uint32_t dcr, bpinfo;
 514         int i;
 515
 516         if (mips32->bp_scanned)
 517                 return ERROR_OK;
 518
 519         /* get info about breakpoint support */
 520         if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
 521                 return retval;
 522
 523         if (dcr & EJTAG_DCR_IB)
 524         {
 525                 /* get number of inst breakpoints */
 526                 if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
 527                         return retval;
 528
 529                 mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
 530                 mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
 531                 mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
 532                 for (i = 0; i < mips32->num_inst_bpoints; i++)
 533                 {
 534                         mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
 535                 }
 536
 537                 /* clear IBIS reg */
 538                 if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
 539                         return retval;
 540         }
 541
 542         if (dcr & EJTAG_DCR_DB)
 543         {
 544                 /* get number of data breakpoints */
 545                 if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
 546                         return retval;
 547
 548                 mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
 549                 mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
 550                 mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
 551                 for (i = 0; i < mips32->num_data_bpoints; i++)
 552                 {
 553                         mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
 554                 }
 555
 556                 /* clear DBIS reg */
 557                 if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
 558                         return retval;
 559         }
 560
 561         /* check if target endianness settings matches debug control register */
 562         if ( (  (dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN) ) ||
 563                 ( !(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN)    ) )
 564         {
 565                 LOG_WARNING("DCR endianness settings does not match target settings");
 566         }
 567
 568         LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
 569                         mips32->num_data_bpoints);
 570
 571         mips32->bp_scanned = 1;
 572
 573         return ERROR_OK;
 574 }
 575
 576 int mips32_enable_interrupts(struct target *target, int enable)
 577 {
 578         int retval;
 579         int update = 0;
 580         uint32_t dcr;
 581
 582         /* read debug control register */
 583         if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
 584                 return retval;
 585
 586         if (enable)
 587         {
 588                 if (!(dcr & EJTAG_DCR_INTE))
 589                 {
 590                         /* enable interrupts */
 591                         dcr |= EJTAG_DCR_INTE;
 592                         update = 1;
 593                 }
 594         }
 595         else
 596         {
 597                 if (dcr & EJTAG_DCR_INTE)
 598                 {
 599                         /* disable interrupts */
 600                         dcr &= ~EJTAG_DCR_INTE;
 601                         update = 1;
 602                 }
 603         }
 604
 605         if (update)
 606         {
 607                 if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
 608                         return retval;
 609         }
 610
 611         return ERROR_OK;
 612 }
 613
 614 int mips32_checksum_memory(struct target *target, uint32_t address,
 615                 uint32_t count, uint32_t* checksum)
 616 {
 617         struct working_area *crc_algorithm;
 618         struct reg_param reg_params[2];
 619         struct mips32_algorithm mips32_info;
 620         int retval;
 621         uint32_t i;
 622
 623         /* see contib/loaders/checksum/mips32.s for src */
 624
 625         static const uint32_t mips_crc_code[] =
 626         {
 627                 0x248C0000,             /* addiu        $t4, $a0, 0 */
 628                 0x24AA0000,             /* addiu        $t2, $a1, 0 */
 629                 0x2404FFFF,             /* addiu        $a0, $zero, 0xffffffff */
 630                 0x10000010,             /* beq          $zero, $zero, ncomp */
 631                 0x240B0000,             /* addiu        $t3, $zero, 0 */
 632                                                 /* nbyte: */
 633                 0x81850000,             /* lb           $a1, ($t4) */
 634                 0x218C0001,             /* addi         $t4, $t4, 1 */
 635                 0x00052E00,             /* sll          $a1, $a1, 24 */
 636                 0x3C0204C1,             /* lui          $v0, 0x04c1 */
 637                 0x00852026,             /* xor          $a0, $a0, $a1 */
 638                 0x34471DB7,             /* ori          $a3, $v0, 0x1db7 */
 639                 0x00003021,             /* addu         $a2, $zero, $zero */
 640                                                 /* loop: */
 641                 0x00044040,             /* sll          $t0, $a0, 1 */
 642                 0x24C60001,             /* addiu        $a2, $a2, 1 */
 643                 0x28840000,             /* slti         $a0, $a0, 0 */
 644                 0x01074826,             /* xor          $t1, $t0, $a3 */
 645                 0x0124400B,             /* movn         $t0, $t1, $a0 */
 646                 0x28C30008,             /* slti         $v1, $a2, 8 */
 647                 0x1460FFF9,             /* bne          $v1, $zero, loop */
 648                 0x01002021,             /* addu         $a0, $t0, $zero */
 649                                                 /* ncomp: */
 650                 0x154BFFF0,             /* bne          $t2, $t3, nbyte */
 651                 0x256B0001,             /* addiu        $t3, $t3, 1 */
 652                 0x7000003F,             /* sdbbp */
 653         };
 654
 655         /* make sure we have a working area */
 656         if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
 657         {
 658                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 659         }
 660
 661         /* convert flash writing code into a buffer in target endianness */
 662         for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++)
 663                 target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]);
 664
 665         mips32_info.common_magic = MIPS32_COMMON_MAGIC;
 666         mips32_info.isa_mode = MIPS32_ISA_MIPS32;
 667
 668         init_reg_param(&reg_params[0], "a0", 32, PARAM_IN_OUT);
 669         buf_set_u32(reg_params[0].value, 0, 32, address);
 670
 671         init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
 672         buf_set_u32(reg_params[1].value, 0, 32, count);
 673
 674         int timeout = 20000 * (1 + (count / (1024 * 1024)));
 675
 676         if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
 677                         crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout,
 678                         &mips32_info)) != ERROR_OK)
 679         {
 680                 destroy_reg_param(&reg_params[0]);
 681                 destroy_reg_param(&reg_params[1]);
 682                 target_free_working_area(target, crc_algorithm);
 683                 return 0;
 684         }
 685
 686         *checksum = buf_get_u32(reg_params[0].value, 0, 32);
 687
 688         destroy_reg_param(&reg_params[0]);
 689         destroy_reg_param(&reg_params[1]);
 690
 691         target_free_working_area(target, crc_algorithm);
 692
 693         return ERROR_OK;
 694 }
 695
 696 /** Checks whether a memory region is zeroed. */
 697 int mips32_blank_check_memory(struct target *target,
 698                 uint32_t address, uint32_t count, uint32_t* blank)
 699 {
 700         struct working_area *erase_check_algorithm;
 701         struct reg_param reg_params[3];
 702         struct mips32_algorithm mips32_info;
 703         int retval;
 704         uint32_t i;
 705
 706         static const uint32_t erase_check_code[] =
 707         {
 708                                                 /* nbyte: */
 709                 0x80880000,             /* lb           $t0, ($a0) */
 710                 0x00C83024,             /* and          $a2, $a2, $t0 */
 711                 0x24A5FFFF,             /* addiu        $a1, $a1, -1 */
 712                 0x14A0FFFC,             /* bne          $a1, $zero, nbyte */
 713                 0x24840001,             /* addiu        $a0, $a0, 1 */
 714                 0x7000003F              /* sdbbp */
 715         };
 716
 717         /* make sure we have a working area */
 718         if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
 719         {
 720                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 721         }
 722
 723         /* convert flash writing code into a buffer in target endianness */
 724         for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
 725         {
 726                 target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t),
 727                                 erase_check_code[i]);
 728         }
 729
 730         mips32_info.common_magic = MIPS32_COMMON_MAGIC;
 731         mips32_info.isa_mode = MIPS32_ISA_MIPS32;
 732
 733         init_reg_param(&reg_params[0], "a0", 32, PARAM_OUT);
 734         buf_set_u32(reg_params[0].value, 0, 32, address);
 735
 736         init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
 737         buf_set_u32(reg_params[1].value, 0, 32, count);
 738
 739         init_reg_param(&reg_params[2], "a2", 32, PARAM_IN_OUT);
 740         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
 741
 742         if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 743                         erase_check_algorithm->address,
 744                         erase_check_algorithm->address + (sizeof(erase_check_code)-2),
 745                         10000, &mips32_info)) != ERROR_OK)
 746         {
 747                 destroy_reg_param(&reg_params[0]);
 748                 destroy_reg_param(&reg_params[1]);
 749                 destroy_reg_param(&reg_params[2]);
 750                 target_free_working_area(target, erase_check_algorithm);
 751                 return 0;
 752         }
 753
 754         *blank = buf_get_u32(reg_params[2].value, 0, 32);
 755
 756         destroy_reg_param(&reg_params[0]);
 757         destroy_reg_param(&reg_params[1]);
 758         destroy_reg_param(&reg_params[2]);
 759
 760         target_free_working_area(target, erase_check_algorithm);
 761
 762         return ERROR_OK;
 763 }
 764
 765 static int mips32_verify_pointer(struct command_context *cmd_ctx,
 766                 struct mips32_common *mips32)
 767 {
 768         if (mips32->common_magic != MIPS32_COMMON_MAGIC) {
 769                 command_print(cmd_ctx, "target is not an MIPS32");
 770                 return ERROR_TARGET_INVALID;
 771         }
 772         return ERROR_OK;
 773 }
 774
 775 /**
 776  * MIPS32 targets expose command interface
 777  * to manipulate CP0 registers
 778  */
 779 COMMAND_HANDLER(mips32_handle_cp0_command)
 780 {
 781         int retval;
 782         struct target *target = get_current_target(CMD_CTX);
 783         struct mips32_common *mips32 = target_to_mips32(target);
 784         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 785
 786
 787         retval = mips32_verify_pointer(CMD_CTX, mips32);
 788         if (retval != ERROR_OK)
 789                 return retval;
 790
 791         if (target->state != TARGET_HALTED)
 792         {
 793                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
 794                 return ERROR_OK;
 795         }
 796
 797         /* two or more argument, access a single register/select (write if third argument is given) */
 798         if (CMD_ARGC < 2)
 799         {
 800             return ERROR_COMMAND_SYNTAX_ERROR;
 801         }
 802         else
 803         {
 804                 uint32_t cp0_reg, cp0_sel;
 805                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
 806                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
 807
 808                 if (CMD_ARGC == 2)
 809                 {
 810                         uint32_t value;
 811
 812                         if ((retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel)) != ERROR_OK)
 813                         {
 814                                 command_print(CMD_CTX,
 815                                                 "couldn't access reg %" PRIi32,
 816                                                 cp0_reg);
 817                                 return ERROR_OK;
 818                         }
 819                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 820                         {
 821                                 return retval;
 822                         }
 823
 824                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
 825                                         cp0_reg, cp0_sel, value);
 826                 }
 827                 else if (CMD_ARGC == 3)
 828                 {
 829                         uint32_t value;
 830                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
 831                         if ((retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel)) != ERROR_OK)
 832                         {
 833                                 command_print(CMD_CTX,
 834                                                 "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
 835                                                 cp0_reg,  cp0_sel);
 836                                 return ERROR_OK;
 837                         }
 838                         command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
 839                                         cp0_reg, cp0_sel, value);
 840                 }
 841         }
 842
 843         return ERROR_OK;
 844 }
 845
 846 static const struct command_registration mips32_exec_command_handlers[] = {
 847         {
 848                 .name = "cp0",
 849                 .handler = mips32_handle_cp0_command,
 850                 .mode = COMMAND_EXEC,
 851                 .usage = "regnum select [value]",
 852                 .help = "display/modify cp0 register",
 853         },
 854         COMMAND_REGISTRATION_DONE
 855 };
 856
 857 const struct command_registration mips32_command_handlers[] = {
 858         {
 859                 .name = "mips32",
 860                 .mode = COMMAND_ANY,
 861                 .help = "mips32 command group",
 862                 .chain = mips32_exec_command_handlers,
 863         },
 864         COMMAND_REGISTRATION_DONE
 865 };
 866