1 /*****************************************************************************
2 * Copyright (C) 2016 by Matthias Welwarsky <matthias.welwarsky@sysgo.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 ****************************************************************************/
20 #include "target_type.h"
21 #include "arm_adi_v5.h"
24 #include <jtag/jtag.h>
26 #define MEM_AP_COMMON_MAGIC 0x4DE4DA50
30 struct adiv5_dap *dap;
35 static int mem_ap_target_create(struct target *target, Jim_Interp *interp)
37 struct mem_ap *mem_ap;
38 struct adiv5_private_config *pc;
40 pc = (struct adiv5_private_config *)target->private_config;
44 if (pc->ap_num == DP_APSEL_INVALID) {
45 LOG_ERROR("AP number not specified");
49 mem_ap = calloc(1, sizeof(struct mem_ap));
51 LOG_ERROR("Out of memory");
55 mem_ap->ap_num = pc->ap_num;
56 mem_ap->common_magic = MEM_AP_COMMON_MAGIC;
57 mem_ap->dap = pc->dap;
59 target->arch_info = mem_ap;
61 if (!target->gdb_port_override)
62 target->gdb_port_override = strdup("disabled");
67 static int mem_ap_init_target(struct command_context *cmd_ctx, struct target *target)
69 LOG_DEBUG("%s", __func__);
70 target->state = TARGET_UNKNOWN;
71 target->debug_reason = DBG_REASON_UNDEFINED;
75 static void mem_ap_deinit_target(struct target *target)
77 LOG_DEBUG("%s", __func__);
79 free(target->private_config);
80 free(target->arch_info);
84 static int mem_ap_arch_state(struct target *target)
86 LOG_DEBUG("%s", __func__);
90 static int mem_ap_poll(struct target *target)
92 if (target->state == TARGET_UNKNOWN) {
93 target->state = TARGET_RUNNING;
94 target->debug_reason = DBG_REASON_NOTHALTED;
100 static int mem_ap_halt(struct target *target)
102 LOG_DEBUG("%s", __func__);
103 target->state = TARGET_HALTED;
104 target->debug_reason = DBG_REASON_DBGRQ;
105 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
109 static int mem_ap_resume(struct target *target, int current, target_addr_t address,
110 int handle_breakpoints, int debug_execution)
112 LOG_DEBUG("%s", __func__);
113 target->state = TARGET_RUNNING;
114 target->debug_reason = DBG_REASON_NOTHALTED;
118 static int mem_ap_step(struct target *target, int current, target_addr_t address,
119 int handle_breakpoints)
121 LOG_DEBUG("%s", __func__);
122 target->state = TARGET_HALTED;
123 target->debug_reason = DBG_REASON_DBGRQ;
124 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
128 static int mem_ap_assert_reset(struct target *target)
130 target->state = TARGET_RESET;
131 target->debug_reason = DBG_REASON_UNDEFINED;
133 LOG_DEBUG("%s", __func__);
137 static int mem_ap_examine(struct target *target)
139 struct mem_ap *mem_ap = target->arch_info;
141 if (!target_was_examined(target)) {
142 mem_ap->ap = dap_ap(mem_ap->dap, mem_ap->ap_num);
143 target_set_examined(target);
144 target->state = TARGET_UNKNOWN;
145 target->debug_reason = DBG_REASON_UNDEFINED;
146 return mem_ap_init(mem_ap->ap);
152 static int mem_ap_deassert_reset(struct target *target)
154 if (target->reset_halt) {
155 target->state = TARGET_HALTED;
156 target->debug_reason = DBG_REASON_DBGRQ;
157 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
159 target->state = TARGET_RUNNING;
160 target->debug_reason = DBG_REASON_NOTHALTED;
163 LOG_DEBUG("%s", __func__);
167 static int mem_ap_reg_get(struct reg *reg)
172 static int mem_ap_reg_set(struct reg *reg, uint8_t *buf)
177 static struct reg_arch_type mem_ap_reg_arch_type = {
178 .get = mem_ap_reg_get,
179 .set = mem_ap_reg_set,
182 const char *mem_ap_get_gdb_arch(struct target *target)
188 * Dummy ARM register emulation:
189 * reg[0..15]: 32 bits, r0~r12, sp, lr, pc
190 * reg[16..23]: 96 bits, f0~f7
191 * reg[24]: 32 bits, fps
192 * reg[25]: 32 bits, cpsr
194 * Set 'exist' only to reg[0..15], so initial response to GDB is correct
197 #define MAX_REG_SIZE 96
198 #define REG_EXIST(n) ((n) < 16)
199 #define REG_SIZE(n) ((((n) >= 16) && ((n) < 24)) ? 96 : 32)
201 struct mem_ap_alloc_reg_list {
202 /* reg_list must be the first field */
203 struct reg *reg_list[NUM_REGS];
204 struct reg regs[NUM_REGS];
205 uint8_t regs_value[MAX_REG_SIZE / 8];
208 static int mem_ap_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
209 int *reg_list_size, enum target_register_class reg_class)
211 struct mem_ap_alloc_reg_list *mem_ap_alloc = calloc(1, sizeof(struct mem_ap_alloc_reg_list));
213 LOG_ERROR("Out of memory");
217 *reg_list = mem_ap_alloc->reg_list;
218 *reg_list_size = NUM_REGS;
219 struct reg *regs = mem_ap_alloc->regs;
221 for (int i = 0; i < NUM_REGS; i++) {
223 regs[i].value = mem_ap_alloc->regs_value;
224 regs[i].size = REG_SIZE(i);
225 regs[i].exist = REG_EXIST(i);
226 regs[i].type = &mem_ap_reg_arch_type;
227 (*reg_list)[i] = ®s[i];
233 static int mem_ap_read_memory(struct target *target, target_addr_t address,
234 uint32_t size, uint32_t count, uint8_t *buffer)
236 struct mem_ap *mem_ap = target->arch_info;
238 LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT
239 "; size %" PRIu32 "; count %" PRIu32, address, size, count);
241 if (count == 0 || !buffer)
242 return ERROR_COMMAND_SYNTAX_ERROR;
244 return mem_ap_read_buf(mem_ap->ap, buffer, size, count, address);
247 static int mem_ap_write_memory(struct target *target, target_addr_t address,
248 uint32_t size, uint32_t count,
249 const uint8_t *buffer)
251 struct mem_ap *mem_ap = target->arch_info;
253 LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT
254 "; size %" PRIu32 "; count %" PRIu32, address, size, count);
256 if (count == 0 || !buffer)
257 return ERROR_COMMAND_SYNTAX_ERROR;
259 return mem_ap_write_buf(mem_ap->ap, buffer, size, count, address);
262 struct target_type mem_ap_target = {
265 .target_create = mem_ap_target_create,
266 .init_target = mem_ap_init_target,
267 .deinit_target = mem_ap_deinit_target,
268 .examine = mem_ap_examine,
269 .target_jim_configure = adiv5_jim_configure,
272 .arch_state = mem_ap_arch_state,
275 .resume = mem_ap_resume,
278 .assert_reset = mem_ap_assert_reset,
279 .deassert_reset = mem_ap_deassert_reset,
281 .get_gdb_arch = mem_ap_get_gdb_arch,
282 .get_gdb_reg_list = mem_ap_get_gdb_reg_list,
284 .read_memory = mem_ap_read_memory,
285 .write_memory = mem_ap_write_memory,