1 /***************************************************************************
2 * Copyright (C) 2011 by Mathias Kuester *
3 * Mathias Kuester <kesmtp@freenet.de> *
5 * Copyright (C) 2011 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * revised: 4/25/13 by brent@mbari.org [DCC target request support] *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
22 ***************************************************************************/
28 #include "jtag/interface.h"
29 #include "jtag/jtag.h"
30 #include "jtag/hla/hla_transport.h"
31 #include "jtag/hla/hla_interface.h"
32 #include "jtag/hla/hla_layout.h"
34 #include "algorithm.h"
36 #include "breakpoints.h"
37 #include "target_type.h"
40 #include "arm_semihosting.h"
41 #include "target_request.h"
43 #define savedDCRDR dbgbase /* FIXME: using target->dbgbase to preserve DCRDR */
45 #define ARMV7M_SCS_DCRSR DCB_DCRSR
46 #define ARMV7M_SCS_DCRDR DCB_DCRDR
48 static inline struct hl_interface_s *target_to_adapter(struct target *target)
50 return target->tap->priv;
53 static int adapter_load_core_reg_u32(struct target *target,
54 uint32_t num, uint32_t *value)
57 struct hl_interface_s *adapter = target_to_adapter(target);
59 LOG_DEBUG("%s", __func__);
61 /* NOTE: we "know" here that the register identifiers used
62 * in the v7m header match the Cortex-M3 Debug Core Register
63 * Selector values for R0..R15, xPSR, MSP, and PSP.
67 /* read a normal core register */
68 retval = adapter->layout->api->read_reg(adapter->handle, num, value);
70 if (retval != ERROR_OK) {
71 LOG_ERROR("JTAG failure %i", retval);
72 return ERROR_JTAG_DEVICE_ERROR;
74 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
78 /* Floating-point Status and Registers */
79 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
80 if (retval != ERROR_OK)
82 retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
83 if (retval != ERROR_OK)
85 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
88 case ARMV7M_S0 ... ARMV7M_S31:
89 /* Floating-point Status and Registers */
90 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64);
91 if (retval != ERROR_OK)
93 retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
94 if (retval != ERROR_OK)
96 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
97 (int)(num - ARMV7M_S0), *value);
102 case ARMV7M_FAULTMASK:
104 /* Cortex-M3 packages these four registers as bitfields
105 * in one Debug Core register. So say r0 and r2 docs;
106 * it was removed from r1 docs, but still works.
108 retval = adapter->layout->api->read_reg(adapter->handle, 20, value);
109 if (retval != ERROR_OK)
114 *value = buf_get_u32((uint8_t *) value, 0, 1);
118 *value = buf_get_u32((uint8_t *) value, 8, 8);
121 case ARMV7M_FAULTMASK:
122 *value = buf_get_u32((uint8_t *) value, 16, 1);
126 *value = buf_get_u32((uint8_t *) value, 24, 3);
130 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "",
135 return ERROR_COMMAND_SYNTAX_ERROR;
141 static int adapter_store_core_reg_u32(struct target *target,
142 uint32_t num, uint32_t value)
146 struct armv7m_common *armv7m = target_to_armv7m(target);
147 struct hl_interface_s *adapter = target_to_adapter(target);
149 LOG_DEBUG("%s", __func__);
151 /* NOTE: we "know" here that the register identifiers used
152 * in the v7m header match the Cortex-M3 Debug Core Register
153 * Selector values for R0..R15, xPSR, MSP, and PSP.
157 retval = adapter->layout->api->write_reg(adapter->handle, num, value);
159 if (retval != ERROR_OK) {
162 LOG_ERROR("JTAG failure");
163 r = armv7m->arm.core_cache->reg_list + num;
165 return ERROR_JTAG_DEVICE_ERROR;
167 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
171 /* Floating-point Status and Registers */
172 retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
173 if (retval != ERROR_OK)
175 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
176 if (retval != ERROR_OK)
178 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
181 case ARMV7M_S0 ... ARMV7M_S31:
182 /* Floating-point Status and Registers */
183 retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
184 if (retval != ERROR_OK)
186 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
187 if (retval != ERROR_OK)
189 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
190 (int)(num - ARMV7M_S0), value);
195 case ARMV7M_FAULTMASK:
197 /* Cortex-M3 packages these four registers as bitfields
198 * in one Debug Core register. So say r0 and r2 docs;
199 * it was removed from r1 docs, but still works.
202 adapter->layout->api->read_reg(adapter->handle, 20, ®);
206 buf_set_u32((uint8_t *) ®, 0, 1, value);
210 buf_set_u32((uint8_t *) ®, 8, 8, value);
213 case ARMV7M_FAULTMASK:
214 buf_set_u32((uint8_t *) ®, 16, 1, value);
218 buf_set_u32((uint8_t *) ®, 24, 3, value);
222 adapter->layout->api->write_reg(adapter->handle, 20, reg);
224 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
228 return ERROR_COMMAND_SYNTAX_ERROR;
234 static int adapter_examine_debug_reason(struct target *target)
236 if ((target->debug_reason != DBG_REASON_DBGRQ)
237 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
238 target->debug_reason = DBG_REASON_BREAKPOINT;
244 static int hl_dcc_read(struct hl_interface_s *hl_if, uint8_t *value, uint8_t *ctrl)
247 int retval = hl_if->layout->api->read_mem(hl_if->handle,
248 DCB_DCRDR, 1, sizeof(dcrdr), (uint8_t *)&dcrdr);
249 if (retval == ERROR_OK) {
250 *ctrl = (uint8_t)dcrdr;
251 *value = (uint8_t)(dcrdr >> 8);
253 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
256 /* write ack back to software dcc register
257 * to signify we have read data */
258 /* atomically clear just the byte containing the busy bit */
259 static const uint8_t zero;
260 retval = hl_if->layout->api->write_mem(hl_if->handle, DCB_DCRDR, 1, 1, &zero);
266 static int hl_target_request_data(struct target *target,
267 uint32_t size, uint8_t *buffer)
269 struct hl_interface_s *hl_if = target_to_adapter(target);
274 for (i = 0; i < (size * 4); i++) {
275 int err = hl_dcc_read(hl_if, &data, &ctrl);
285 static int hl_handle_target_request(void *priv)
287 struct target *target = priv;
290 if (!target_was_examined(target))
292 struct hl_interface_s *hl_if = target_to_adapter(target);
294 if (!target->dbg_msg_enabled)
297 if (target->state == TARGET_RUNNING) {
301 err = hl_dcc_read(hl_if, &data, &ctrl);
305 /* check if we have data */
306 if (ctrl & (1 << 0)) {
309 /* we assume target is quick enough */
311 err = hl_dcc_read(hl_if, &data, &ctrl);
315 request |= (data << 8);
316 err = hl_dcc_read(hl_if, &data, &ctrl);
320 request |= (data << 16);
321 err = hl_dcc_read(hl_if, &data, &ctrl);
325 request |= (data << 24);
326 target_request(target, request);
333 static int adapter_init_arch_info(struct target *target,
334 struct cortex_m_common *cortex_m,
335 struct jtag_tap *tap)
337 struct armv7m_common *armv7m;
339 LOG_DEBUG("%s", __func__);
341 armv7m = &cortex_m->armv7m;
342 armv7m_init_arch_info(target, armv7m);
344 armv7m->load_core_reg_u32 = adapter_load_core_reg_u32;
345 armv7m->store_core_reg_u32 = adapter_store_core_reg_u32;
347 armv7m->examine_debug_reason = adapter_examine_debug_reason;
348 armv7m->stlink = true;
350 target_register_timer_callback(hl_handle_target_request, 1,
351 TARGET_TIMER_TYPE_PERIODIC, target);
356 static int adapter_init_target(struct command_context *cmd_ctx,
357 struct target *target)
359 LOG_DEBUG("%s", __func__);
361 armv7m_build_reg_cache(target);
362 arm_semihosting_init(target);
366 static int adapter_target_create(struct target *target,
369 LOG_DEBUG("%s", __func__);
370 struct adiv5_private_config *pc = target->private_config;
371 if (pc != NULL && pc->ap_num > 0) {
372 LOG_ERROR("hla_target: invalid parameter -ap-num (> 0)");
373 return ERROR_COMMAND_SYNTAX_ERROR;
376 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
377 if (cortex_m == NULL) {
378 LOG_ERROR("No memory creating target");
382 adapter_init_arch_info(target, cortex_m, target->tap);
387 static int adapter_load_context(struct target *target)
389 struct armv7m_common *armv7m = target_to_armv7m(target);
390 int num_regs = armv7m->arm.core_cache->num_regs;
392 for (int i = 0; i < num_regs; i++) {
394 struct reg *r = &armv7m->arm.core_cache->reg_list[i];
396 armv7m->arm.read_core_reg(target, r, i, ARM_MODE_ANY);
402 static int adapter_debug_entry(struct target *target)
404 struct hl_interface_s *adapter = target_to_adapter(target);
405 struct armv7m_common *armv7m = target_to_armv7m(target);
406 struct arm *arm = &armv7m->arm;
411 /* preserve the DCRDR across halts */
412 retval = target_read_u32(target, DCB_DCRDR, &target->savedDCRDR);
413 if (retval != ERROR_OK)
416 retval = armv7m->examine_debug_reason(target);
417 if (retval != ERROR_OK)
420 adapter_load_context(target);
422 /* make sure we clear the vector catch bit */
423 adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
426 xPSR = buf_get_u32(r->value, 0, 32);
428 /* Are we in an exception handler */
430 armv7m->exception_number = (xPSR & 0x1FF);
432 arm->core_mode = ARM_MODE_HANDLER;
433 arm->map = armv7m_msp_reg_map;
435 unsigned control = buf_get_u32(arm->core_cache
436 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
438 /* is this thread privileged? */
439 arm->core_mode = control & 1
440 ? ARM_MODE_USER_THREAD
443 /* which stack is it using? */
445 arm->map = armv7m_psp_reg_map;
447 arm->map = armv7m_msp_reg_map;
449 armv7m->exception_number = 0;
452 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
453 arm_mode_name(arm->core_mode),
454 buf_get_u32(arm->pc->value, 0, 32),
455 target_state_name(target));
460 static int adapter_poll(struct target *target)
462 enum target_state state;
463 struct hl_interface_s *adapter = target_to_adapter(target);
464 struct armv7m_common *armv7m = target_to_armv7m(target);
465 enum target_state prev_target_state = target->state;
467 state = adapter->layout->api->state(adapter->handle);
469 if (state == TARGET_UNKNOWN) {
470 LOG_ERROR("jtag status contains invalid mode value - communication failure");
471 return ERROR_TARGET_FAILURE;
474 if (prev_target_state == state)
477 if (prev_target_state == TARGET_DEBUG_RUNNING && state == TARGET_RUNNING)
480 target->state = state;
482 if (state == TARGET_HALTED) {
484 int retval = adapter_debug_entry(target);
485 if (retval != ERROR_OK)
488 if (prev_target_state == TARGET_DEBUG_RUNNING) {
489 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
491 if (arm_semihosting(target, &retval) != 0)
494 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
497 LOG_DEBUG("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
503 static int hl_assert_reset(struct target *target)
506 struct hl_interface_s *adapter = target_to_adapter(target);
507 struct armv7m_common *armv7m = target_to_armv7m(target);
508 bool use_srst_fallback = true;
510 LOG_DEBUG("%s", __func__);
512 enum reset_types jtag_reset_config = jtag_get_reset_config();
514 bool srst_asserted = false;
516 if ((jtag_reset_config & RESET_HAS_SRST) &&
517 (jtag_reset_config & RESET_SRST_NO_GATING)) {
518 res = adapter_assert_reset();
519 srst_asserted = true;
522 adapter->layout->api->write_debug_reg(adapter->handle, DCB_DHCSR, DBGKEY|C_DEBUGEN);
524 /* only set vector catch if halt is requested */
525 if (target->reset_halt)
526 adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA|VC_CORERESET);
528 adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
530 if (jtag_reset_config & RESET_HAS_SRST) {
531 if (!srst_asserted) {
532 res = adapter_assert_reset();
534 if (res == ERROR_COMMAND_NOTFOUND)
535 LOG_ERROR("Hardware srst not supported, falling back to software reset");
536 else if (res == ERROR_OK) {
537 /* hardware srst supported */
538 use_srst_fallback = false;
542 if (use_srst_fallback) {
543 /* stlink v1 api does not support hardware srst, so we use a software reset fallback */
544 adapter->layout->api->write_debug_reg(adapter->handle, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
547 res = adapter->layout->api->reset(adapter->handle);
552 /* registers are now invalid */
553 register_cache_invalidate(armv7m->arm.core_cache);
555 if (target->reset_halt) {
556 target->state = TARGET_RESET;
557 target->debug_reason = DBG_REASON_DBGRQ;
559 target->state = TARGET_HALTED;
565 static int hl_deassert_reset(struct target *target)
567 enum reset_types jtag_reset_config = jtag_get_reset_config();
569 LOG_DEBUG("%s", __func__);
571 if (jtag_reset_config & RESET_HAS_SRST)
572 adapter_deassert_reset();
574 target->savedDCRDR = 0; /* clear both DCC busy bits on initial resume */
576 return target->reset_halt ? ERROR_OK : target_resume(target, 1, 0, 0, 0);
579 static int adapter_halt(struct target *target)
582 struct hl_interface_s *adapter = target_to_adapter(target);
584 LOG_DEBUG("%s", __func__);
586 if (target->state == TARGET_HALTED) {
587 LOG_DEBUG("target was already halted");
591 if (target->state == TARGET_UNKNOWN)
592 LOG_WARNING("target was in unknown state when halt was requested");
594 res = adapter->layout->api->halt(adapter->handle);
599 target->debug_reason = DBG_REASON_DBGRQ;
604 static int adapter_resume(struct target *target, int current,
605 target_addr_t address, int handle_breakpoints,
609 struct hl_interface_s *adapter = target_to_adapter(target);
610 struct armv7m_common *armv7m = target_to_armv7m(target);
612 struct breakpoint *breakpoint = NULL;
615 LOG_DEBUG("%s %d " TARGET_ADDR_FMT " %d %d", __func__, current,
616 address, handle_breakpoints, debug_execution);
618 if (target->state != TARGET_HALTED) {
619 LOG_WARNING("target not halted");
620 return ERROR_TARGET_NOT_HALTED;
623 if (!debug_execution) {
624 target_free_all_working_areas(target);
625 cortex_m_enable_breakpoints(target);
626 cortex_m_enable_watchpoints(target);
631 buf_set_u32(pc->value, 0, 32, address);
636 if (!breakpoint_find(target, buf_get_u32(pc->value, 0, 32))
637 && !debug_execution) {
638 armv7m_maybe_skip_bkpt_inst(target, NULL);
641 resume_pc = buf_get_u32(pc->value, 0, 32);
643 /* write any user vector flags */
644 res = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
648 armv7m_restore_context(target);
650 /* restore savedDCRDR */
651 res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR);
655 /* registers are now invalid */
656 register_cache_invalidate(armv7m->arm.core_cache);
658 /* the front-end may request us not to handle breakpoints */
659 if (handle_breakpoints) {
660 /* Single step past breakpoint at current address */
661 breakpoint = breakpoint_find(target, resume_pc);
663 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
665 breakpoint->unique_id);
666 cortex_m_unset_breakpoint(target, breakpoint);
668 res = adapter->layout->api->step(adapter->handle);
673 cortex_m_set_breakpoint(target, breakpoint);
677 res = adapter->layout->api->run(adapter->handle);
682 target->debug_reason = DBG_REASON_NOTHALTED;
684 if (!debug_execution) {
685 target->state = TARGET_RUNNING;
686 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
688 target->state = TARGET_DEBUG_RUNNING;
689 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
695 static int adapter_step(struct target *target, int current,
696 target_addr_t address, int handle_breakpoints)
699 struct hl_interface_s *adapter = target_to_adapter(target);
700 struct armv7m_common *armv7m = target_to_armv7m(target);
701 struct breakpoint *breakpoint = NULL;
702 struct reg *pc = armv7m->arm.pc;
703 bool bkpt_inst_found = false;
705 LOG_DEBUG("%s", __func__);
707 if (target->state != TARGET_HALTED) {
708 LOG_WARNING("target not halted");
709 return ERROR_TARGET_NOT_HALTED;
713 buf_set_u32(pc->value, 0, 32, address);
718 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
720 /* the front-end may request us not to handle breakpoints */
721 if (handle_breakpoints) {
722 breakpoint = breakpoint_find(target, pc_value);
724 cortex_m_unset_breakpoint(target, breakpoint);
727 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
729 target->debug_reason = DBG_REASON_SINGLESTEP;
731 armv7m_restore_context(target);
733 /* restore savedDCRDR */
734 res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR);
738 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
740 res = adapter->layout->api->step(adapter->handle);
745 /* registers are now invalid */
746 register_cache_invalidate(armv7m->arm.core_cache);
749 cortex_m_set_breakpoint(target, breakpoint);
751 adapter_debug_entry(target);
752 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
754 LOG_INFO("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
759 static int adapter_read_memory(struct target *target, target_addr_t address,
760 uint32_t size, uint32_t count,
763 struct hl_interface_s *adapter = target_to_adapter(target);
765 if (!count || !buffer)
766 return ERROR_COMMAND_SYNTAX_ERROR;
768 LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
769 __func__, address, size, count);
771 return adapter->layout->api->read_mem(adapter->handle, address, size, count, buffer);
774 static int adapter_write_memory(struct target *target, target_addr_t address,
775 uint32_t size, uint32_t count,
776 const uint8_t *buffer)
778 struct hl_interface_s *adapter = target_to_adapter(target);
780 if (!count || !buffer)
781 return ERROR_COMMAND_SYNTAX_ERROR;
783 LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
784 __func__, address, size, count);
786 return adapter->layout->api->write_mem(adapter->handle, address, size, count, buffer);
789 static const struct command_registration adapter_command_handlers[] = {
791 .chain = arm_command_handlers,
794 .chain = armv7m_trace_command_handlers,
796 COMMAND_REGISTRATION_DONE
799 struct target_type hla_target = {
800 .name = "hla_target",
801 .deprecated_name = "stm32_stlink",
803 .init_target = adapter_init_target,
804 .deinit_target = cortex_m_deinit_target,
805 .target_create = adapter_target_create,
806 .target_jim_configure = adiv5_jim_configure,
807 .examine = cortex_m_examine,
808 .commands = adapter_command_handlers,
810 .poll = adapter_poll,
811 .arch_state = armv7m_arch_state,
813 .target_request_data = hl_target_request_data,
814 .assert_reset = hl_assert_reset,
815 .deassert_reset = hl_deassert_reset,
817 .halt = adapter_halt,
818 .resume = adapter_resume,
819 .step = adapter_step,
821 .get_gdb_arch = arm_get_gdb_arch,
822 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
824 .read_memory = adapter_read_memory,
825 .write_memory = adapter_write_memory,
826 .checksum_memory = armv7m_checksum_memory,
827 .blank_check_memory = armv7m_blank_check_memory,
829 .run_algorithm = armv7m_run_algorithm,
830 .start_algorithm = armv7m_start_algorithm,
831 .wait_algorithm = armv7m_wait_algorithm,
833 .add_breakpoint = cortex_m_add_breakpoint,
834 .remove_breakpoint = cortex_m_remove_breakpoint,
835 .add_watchpoint = cortex_m_add_watchpoint,
836 .remove_watchpoint = cortex_m_remove_watchpoint,
837 .profiling = cortex_m_profiling,