git.gag.com Git - fw/openocd/blob - src/target/hla_target.c

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Mathias Kuester                                 *
   3  *   Mathias Kuester <kesmtp@freenet.de>                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2011 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   revised:  4/25/13 by brent@mbari.org [DCC target request support]     *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  22  ***************************************************************************/
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "jtag/interface.h"
  29 #include "jtag/jtag.h"
  30 #include "jtag/hla/hla_transport.h"
  31 #include "jtag/hla/hla_interface.h"
  32 #include "jtag/hla/hla_layout.h"
  33 #include "register.h"
  34 #include "algorithm.h"
  35 #include "target.h"
  36 #include "breakpoints.h"
  37 #include "target_type.h"
  38 #include "armv7m.h"
  39 #include "cortex_m.h"
  40 #include "arm_semihosting.h"
  41 #include "target_request.h"
  42
  43 #define savedDCRDR  dbgbase  /* FIXME: using target->dbgbase to preserve DCRDR */
  44
  45 #define ARMV7M_SCS_DCRSR        DCB_DCRSR
  46 #define ARMV7M_SCS_DCRDR        DCB_DCRDR
  47
  48 static inline struct hl_interface_s *target_to_adapter(struct target *target)
  49 {
  50         return target->tap->priv;
  51 }
  52
  53 static int adapter_load_core_reg_u32(struct target *target,
  54                 uint32_t regsel, uint32_t *value)
  55 {
  56         int retval;
  57         struct hl_interface_s *adapter = target_to_adapter(target);
  58
  59         LOG_DEBUG("%s", __func__);
  60
  61         /* NOTE:  we "know" here that the register identifiers used
  62          * in the v7m header match the Cortex-M3 Debug Core Register
  63          * Selector values for R0..R15, xPSR, MSP, and PSP.
  64          */
  65         switch (regsel) {
  66         case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
  67                 /* read a normal core register */
  68                 retval = adapter->layout->api->read_reg(adapter->handle, regsel, value);
  69
  70                 if (retval != ERROR_OK) {
  71                         LOG_ERROR("JTAG failure %i", retval);
  72                         return ERROR_JTAG_DEVICE_ERROR;
  73                 }
  74                 LOG_DEBUG("load from core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
  75                 break;
  76
  77         case ARMV7M_REGSEL_FPSCR:
  78                 /* Floating-point Status and Registers */
  79                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, regsel);
  80                 if (retval != ERROR_OK)
  81                         return retval;
  82                 retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
  83                 if (retval != ERROR_OK)
  84                         return retval;
  85                 LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
  86                 break;
  87
  88         case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
  89                 /* Floating-point Status and Registers */
  90                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, regsel);
  91                 if (retval != ERROR_OK)
  92                         return retval;
  93                 retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
  94                 if (retval != ERROR_OK)
  95                         return retval;
  96                 LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
  97                           (int)(regsel - ARMV7M_REGSEL_S0), *value);
  98                 break;
  99
 100         case ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL:
 101                 retval = adapter->layout->api->read_reg(adapter->handle, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL, value);
 102                 if (retval != ERROR_OK)
 103                         return retval;
 104
 105                 LOG_DEBUG("load from special reg PRIMASK/BASEPRI/FAULTMASK/CONTROL value 0x%" PRIx32, *value);
 106                 break;
 107
 108         default:
 109                 return ERROR_COMMAND_SYNTAX_ERROR;
 110         }
 111
 112         return ERROR_OK;
 113 }
 114
 115 static int adapter_store_core_reg_u32(struct target *target,
 116                 uint32_t regsel, uint32_t value)
 117 {
 118         int retval;
 119         struct armv7m_common *armv7m = target_to_armv7m(target);
 120         struct hl_interface_s *adapter = target_to_adapter(target);
 121
 122         LOG_DEBUG("%s", __func__);
 123
 124         switch (regsel) {
 125         case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
 126                 retval = adapter->layout->api->write_reg(adapter->handle, regsel, value);
 127
 128                 if (retval != ERROR_OK) {
 129                         struct reg *r;
 130
 131                         LOG_ERROR("JTAG failure");
 132                         r = armv7m->arm.core_cache->reg_list + regsel; /* TODO: don't use regsel as register index */
 133                         r->dirty = r->valid;
 134                         return ERROR_JTAG_DEVICE_ERROR;
 135                 }
 136                 LOG_DEBUG("write core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, value);
 137                 break;
 138
 139         case ARMV7M_REGSEL_FPSCR:
 140                 /* Floating-point Status and Registers */
 141                 retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
 142                 if (retval != ERROR_OK)
 143                         return retval;
 144                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, ARMV7M_REGSEL_FPSCR | DCRSR_WnR);
 145                 if (retval != ERROR_OK)
 146                         return retval;
 147                 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
 148                 break;
 149
 150         case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
 151                 /* Floating-point Status and Registers */
 152                 retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
 153                 if (retval != ERROR_OK)
 154                         return retval;
 155                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, regsel | DCRSR_WnR);
 156                 if (retval != ERROR_OK)
 157                         return retval;
 158                 LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
 159                           (int)(regsel - ARMV7M_REGSEL_S0), value);
 160                 break;
 161
 162         case ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL:
 163                 adapter->layout->api->write_reg(adapter->handle, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL, value);
 164
 165                 LOG_DEBUG("write special reg PRIMASK/BASEPRI/FAULTMASK/CONTROL value 0x%" PRIx32, value);
 166                 break;
 167
 168         default:
 169                 return ERROR_COMMAND_SYNTAX_ERROR;
 170         }
 171
 172         return ERROR_OK;
 173 }
 174
 175 static int adapter_examine_debug_reason(struct target *target)
 176 {
 177         if ((target->debug_reason != DBG_REASON_DBGRQ)
 178                         && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 179                 target->debug_reason = DBG_REASON_BREAKPOINT;
 180         }
 181
 182         return ERROR_OK;
 183 }
 184
 185 static int hl_dcc_read(struct hl_interface_s *hl_if, uint8_t *value, uint8_t *ctrl)
 186 {
 187         uint16_t dcrdr;
 188         int retval = hl_if->layout->api->read_mem(hl_if->handle,
 189                         DCB_DCRDR, 1, sizeof(dcrdr), (uint8_t *)&dcrdr);
 190         if (retval == ERROR_OK) {
 191             *ctrl = (uint8_t)dcrdr;
 192             *value = (uint8_t)(dcrdr >> 8);
 193
 194             LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
 195
 196             if (dcrdr & 1) {
 197                         /* write ack back to software dcc register
 198                          * to signify we have read data */
 199                         /* atomically clear just the byte containing the busy bit */
 200                         static const uint8_t zero;
 201                         retval = hl_if->layout->api->write_mem(hl_if->handle, DCB_DCRDR, 1, 1, &zero);
 202                 }
 203         }
 204         return retval;
 205 }
 206
 207 static int hl_target_request_data(struct target *target,
 208         uint32_t size, uint8_t *buffer)
 209 {
 210         struct hl_interface_s *hl_if = target_to_adapter(target);
 211         uint8_t data;
 212         uint8_t ctrl;
 213         uint32_t i;
 214
 215         for (i = 0; i < (size * 4); i++) {
 216                 int err = hl_dcc_read(hl_if, &data, &ctrl);
 217                 if (err != ERROR_OK)
 218                         return err;
 219
 220                 buffer[i] = data;
 221         }
 222
 223         return ERROR_OK;
 224 }
 225
 226 static int hl_handle_target_request(void *priv)
 227 {
 228         struct target *target = priv;
 229         int err;
 230
 231         if (!target_was_examined(target))
 232                 return ERROR_OK;
 233         struct hl_interface_s *hl_if = target_to_adapter(target);
 234
 235         if (!target->dbg_msg_enabled)
 236                 return ERROR_OK;
 237
 238         if (target->state == TARGET_RUNNING) {
 239                 uint8_t data;
 240                 uint8_t ctrl;
 241
 242                 err = hl_dcc_read(hl_if, &data, &ctrl);
 243                 if (err != ERROR_OK)
 244                         return err;
 245
 246                 /* check if we have data */
 247                 if (ctrl & (1 << 0)) {
 248                         uint32_t request;
 249
 250                         /* we assume target is quick enough */
 251                         request = data;
 252                         err = hl_dcc_read(hl_if, &data, &ctrl);
 253                         if (err != ERROR_OK)
 254                                 return err;
 255
 256                         request |= (data << 8);
 257                         err = hl_dcc_read(hl_if, &data, &ctrl);
 258                         if (err != ERROR_OK)
 259                                 return err;
 260
 261                         request |= (data << 16);
 262                         err = hl_dcc_read(hl_if, &data, &ctrl);
 263                         if (err != ERROR_OK)
 264                                 return err;
 265
 266                         request |= (data << 24);
 267                         target_request(target, request);
 268                 }
 269         }
 270
 271         return ERROR_OK;
 272 }
 273
 274 static int adapter_init_arch_info(struct target *target,
 275                                        struct cortex_m_common *cortex_m,
 276                                        struct jtag_tap *tap)
 277 {
 278         struct armv7m_common *armv7m;
 279
 280         LOG_DEBUG("%s", __func__);
 281
 282         armv7m = &cortex_m->armv7m;
 283         armv7m_init_arch_info(target, armv7m);
 284
 285         armv7m->load_core_reg_u32 = adapter_load_core_reg_u32;
 286         armv7m->store_core_reg_u32 = adapter_store_core_reg_u32;
 287
 288         armv7m->examine_debug_reason = adapter_examine_debug_reason;
 289         armv7m->stlink = true;
 290
 291         target_register_timer_callback(hl_handle_target_request, 1,
 292                 TARGET_TIMER_TYPE_PERIODIC, target);
 293
 294         return ERROR_OK;
 295 }
 296
 297 static int adapter_init_target(struct command_context *cmd_ctx,
 298                                     struct target *target)
 299 {
 300         LOG_DEBUG("%s", __func__);
 301
 302         armv7m_build_reg_cache(target);
 303         arm_semihosting_init(target);
 304         return ERROR_OK;
 305 }
 306
 307 static int adapter_target_create(struct target *target,
 308                 Jim_Interp *interp)
 309 {
 310         LOG_DEBUG("%s", __func__);
 311         struct adiv5_private_config *pc = target->private_config;
 312         if (pc != NULL && pc->ap_num > 0) {
 313                 LOG_ERROR("hla_target: invalid parameter -ap-num (> 0)");
 314                 return ERROR_COMMAND_SYNTAX_ERROR;
 315         }
 316
 317         struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
 318         if (cortex_m == NULL) {
 319                 LOG_ERROR("No memory creating target");
 320                 return ERROR_FAIL;
 321         }
 322
 323         adapter_init_arch_info(target, cortex_m, target->tap);
 324
 325         return ERROR_OK;
 326 }
 327
 328 static int adapter_load_context(struct target *target)
 329 {
 330         struct armv7m_common *armv7m = target_to_armv7m(target);
 331         int num_regs = armv7m->arm.core_cache->num_regs;
 332
 333         for (int i = 0; i < num_regs; i++) {
 334
 335                 struct reg *r = &armv7m->arm.core_cache->reg_list[i];
 336                 if (!r->valid)
 337                         armv7m->arm.read_core_reg(target, r, i, ARM_MODE_ANY);
 338         }
 339
 340         return ERROR_OK;
 341 }
 342
 343 static int adapter_debug_entry(struct target *target)
 344 {
 345         struct hl_interface_s *adapter = target_to_adapter(target);
 346         struct armv7m_common *armv7m = target_to_armv7m(target);
 347         struct arm *arm = &armv7m->arm;
 348         struct reg *r;
 349         uint32_t xPSR;
 350         int retval;
 351
 352         /* preserve the DCRDR across halts */
 353         retval = target_read_u32(target, DCB_DCRDR, &target->savedDCRDR);
 354         if (retval != ERROR_OK)
 355                 return retval;
 356
 357         retval = armv7m->examine_debug_reason(target);
 358         if (retval != ERROR_OK)
 359                 return retval;
 360
 361         adapter_load_context(target);
 362
 363         /* make sure we clear the vector catch bit */
 364         adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
 365
 366         r = arm->cpsr;
 367         xPSR = buf_get_u32(r->value, 0, 32);
 368
 369         /* Are we in an exception handler */
 370         if (xPSR & 0x1FF) {
 371                 armv7m->exception_number = (xPSR & 0x1FF);
 372
 373                 arm->core_mode = ARM_MODE_HANDLER;
 374                 arm->map = armv7m_msp_reg_map;
 375         } else {
 376                 unsigned control = buf_get_u32(arm->core_cache
 377                                 ->reg_list[ARMV7M_CONTROL].value, 0, 3);
 378
 379                 /* is this thread privileged? */
 380                 arm->core_mode = control & 1
 381                                 ? ARM_MODE_USER_THREAD
 382                                 : ARM_MODE_THREAD;
 383
 384                 /* which stack is it using? */
 385                 if (control & 2)
 386                         arm->map = armv7m_psp_reg_map;
 387                 else
 388                         arm->map = armv7m_msp_reg_map;
 389
 390                 armv7m->exception_number = 0;
 391         }
 392
 393         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%08" PRIx32 ", target->state: %s",
 394                 arm_mode_name(arm->core_mode),
 395                 buf_get_u32(arm->pc->value, 0, 32),
 396                 target_state_name(target));
 397
 398         return retval;
 399 }
 400
 401 static int adapter_poll(struct target *target)
 402 {
 403         enum target_state state;
 404         struct hl_interface_s *adapter = target_to_adapter(target);
 405         struct armv7m_common *armv7m = target_to_armv7m(target);
 406         enum target_state prev_target_state = target->state;
 407
 408         state = adapter->layout->api->state(adapter->handle);
 409
 410         if (state == TARGET_UNKNOWN) {
 411                 LOG_ERROR("jtag status contains invalid mode value - communication failure");
 412                 return ERROR_TARGET_FAILURE;
 413         }
 414
 415         if (prev_target_state == state)
 416                 return ERROR_OK;
 417
 418         if (prev_target_state == TARGET_DEBUG_RUNNING && state == TARGET_RUNNING)
 419                 return ERROR_OK;
 420
 421         target->state = state;
 422
 423         if (state == TARGET_HALTED) {
 424
 425                 int retval = adapter_debug_entry(target);
 426                 if (retval != ERROR_OK)
 427                         return retval;
 428
 429                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 430                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 431                 } else {
 432                         if (arm_semihosting(target, &retval) != 0)
 433                                 return retval;
 434
 435                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 436                 }
 437
 438                 LOG_DEBUG("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
 439         }
 440
 441         return ERROR_OK;
 442 }
 443
 444 static int hl_assert_reset(struct target *target)
 445 {
 446         int res = ERROR_OK;
 447         struct hl_interface_s *adapter = target_to_adapter(target);
 448         struct armv7m_common *armv7m = target_to_armv7m(target);
 449         bool use_srst_fallback = true;
 450
 451         LOG_DEBUG("%s", __func__);
 452
 453         enum reset_types jtag_reset_config = jtag_get_reset_config();
 454
 455         bool srst_asserted = false;
 456
 457         if ((jtag_reset_config & RESET_HAS_SRST) &&
 458             (jtag_reset_config & RESET_SRST_NO_GATING)) {
 459                 res = adapter_assert_reset();
 460                 srst_asserted = true;
 461         }
 462
 463         adapter->layout->api->write_debug_reg(adapter->handle, DCB_DHCSR, DBGKEY|C_DEBUGEN);
 464
 465         /* only set vector catch if halt is requested */
 466         if (target->reset_halt)
 467                 adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA|VC_CORERESET);
 468         else
 469                 adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA);
 470
 471         if (jtag_reset_config & RESET_HAS_SRST) {
 472                 if (!srst_asserted) {
 473                         res = adapter_assert_reset();
 474                 }
 475                 if (res == ERROR_COMMAND_NOTFOUND)
 476                         LOG_ERROR("Hardware srst not supported, falling back to software reset");
 477                 else if (res == ERROR_OK) {
 478                         /* hardware srst supported */
 479                         use_srst_fallback = false;
 480                 }
 481         }
 482
 483         if (use_srst_fallback) {
 484                 /* stlink v1 api does not support hardware srst, so we use a software reset fallback */
 485                 adapter->layout->api->write_debug_reg(adapter->handle, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
 486         }
 487
 488         res = adapter->layout->api->reset(adapter->handle);
 489
 490         if (res != ERROR_OK)
 491                 return res;
 492
 493         /* registers are now invalid */
 494         register_cache_invalidate(armv7m->arm.core_cache);
 495
 496         if (target->reset_halt) {
 497                 target->state = TARGET_RESET;
 498                 target->debug_reason = DBG_REASON_DBGRQ;
 499         } else {
 500                 target->state = TARGET_HALTED;
 501         }
 502
 503         return ERROR_OK;
 504 }
 505
 506 static int hl_deassert_reset(struct target *target)
 507 {
 508         enum reset_types jtag_reset_config = jtag_get_reset_config();
 509
 510         LOG_DEBUG("%s", __func__);
 511
 512         if (jtag_reset_config & RESET_HAS_SRST)
 513                 adapter_deassert_reset();
 514
 515         target->savedDCRDR = 0;  /* clear both DCC busy bits on initial resume */
 516
 517         return target->reset_halt ? ERROR_OK : target_resume(target, 1, 0, 0, 0);
 518 }
 519
 520 static int adapter_halt(struct target *target)
 521 {
 522         int res;
 523         struct hl_interface_s *adapter = target_to_adapter(target);
 524
 525         LOG_DEBUG("%s", __func__);
 526
 527         if (target->state == TARGET_HALTED) {
 528                 LOG_DEBUG("target was already halted");
 529                 return ERROR_OK;
 530         }
 531
 532         if (target->state == TARGET_UNKNOWN)
 533                 LOG_WARNING("target was in unknown state when halt was requested");
 534
 535         res = adapter->layout->api->halt(adapter->handle);
 536
 537         if (res != ERROR_OK)
 538                 return res;
 539
 540         target->debug_reason = DBG_REASON_DBGRQ;
 541
 542         return ERROR_OK;
 543 }
 544
 545 static int adapter_resume(struct target *target, int current,
 546                 target_addr_t address, int handle_breakpoints,
 547                 int debug_execution)
 548 {
 549         int res;
 550         struct hl_interface_s *adapter = target_to_adapter(target);
 551         struct armv7m_common *armv7m = target_to_armv7m(target);
 552         uint32_t resume_pc;
 553         struct breakpoint *breakpoint = NULL;
 554         struct reg *pc;
 555
 556         LOG_DEBUG("%s %d " TARGET_ADDR_FMT " %d %d", __func__, current,
 557                         address, handle_breakpoints, debug_execution);
 558
 559         if (target->state != TARGET_HALTED) {
 560                 LOG_WARNING("target not halted");
 561                 return ERROR_TARGET_NOT_HALTED;
 562         }
 563
 564         if (!debug_execution) {
 565                 target_free_all_working_areas(target);
 566                 cortex_m_enable_breakpoints(target);
 567                 cortex_m_enable_watchpoints(target);
 568         }
 569
 570         pc = armv7m->arm.pc;
 571         if (!current) {
 572                 buf_set_u32(pc->value, 0, 32, address);
 573                 pc->dirty = true;
 574                 pc->valid = true;
 575         }
 576
 577         if (!breakpoint_find(target, buf_get_u32(pc->value, 0, 32))
 578                         && !debug_execution) {
 579                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 580         }
 581
 582         resume_pc = buf_get_u32(pc->value, 0, 32);
 583
 584         /* write any user vector flags */
 585         res = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
 586         if (res != ERROR_OK)
 587                 return res;
 588
 589         armv7m_restore_context(target);
 590
 591         /* restore savedDCRDR */
 592         res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR);
 593         if (res != ERROR_OK)
 594                 return res;
 595
 596         /* registers are now invalid */
 597         register_cache_invalidate(armv7m->arm.core_cache);
 598
 599         /* the front-end may request us not to handle breakpoints */
 600         if (handle_breakpoints) {
 601                 /* Single step past breakpoint at current address */
 602                 breakpoint = breakpoint_find(target, resume_pc);
 603                 if (breakpoint) {
 604                         LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
 605                                         breakpoint->address,
 606                                         breakpoint->unique_id);
 607                         cortex_m_unset_breakpoint(target, breakpoint);
 608
 609                         res = adapter->layout->api->step(adapter->handle);
 610
 611                         if (res != ERROR_OK)
 612                                 return res;
 613
 614                         cortex_m_set_breakpoint(target, breakpoint);
 615                 }
 616         }
 617
 618         res = adapter->layout->api->run(adapter->handle);
 619
 620         if (res != ERROR_OK)
 621                 return res;
 622
 623         target->debug_reason = DBG_REASON_NOTHALTED;
 624
 625         if (!debug_execution) {
 626                 target->state = TARGET_RUNNING;
 627                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 628         } else {
 629                 target->state = TARGET_DEBUG_RUNNING;
 630                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 631         }
 632
 633         return ERROR_OK;
 634 }
 635
 636 static int adapter_step(struct target *target, int current,
 637                 target_addr_t address, int handle_breakpoints)
 638 {
 639         int res;
 640         struct hl_interface_s *adapter = target_to_adapter(target);
 641         struct armv7m_common *armv7m = target_to_armv7m(target);
 642         struct breakpoint *breakpoint = NULL;
 643         struct reg *pc = armv7m->arm.pc;
 644         bool bkpt_inst_found = false;
 645
 646         LOG_DEBUG("%s", __func__);
 647
 648         if (target->state != TARGET_HALTED) {
 649                 LOG_WARNING("target not halted");
 650                 return ERROR_TARGET_NOT_HALTED;
 651         }
 652
 653         if (!current) {
 654                 buf_set_u32(pc->value, 0, 32, address);
 655                 pc->dirty = true;
 656                 pc->valid = true;
 657         }
 658
 659         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 660
 661         /* the front-end may request us not to handle breakpoints */
 662         if (handle_breakpoints) {
 663                 breakpoint = breakpoint_find(target, pc_value);
 664                 if (breakpoint)
 665                         cortex_m_unset_breakpoint(target, breakpoint);
 666         }
 667
 668         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 669
 670         target->debug_reason = DBG_REASON_SINGLESTEP;
 671
 672         armv7m_restore_context(target);
 673
 674         /* restore savedDCRDR */
 675         res = target_write_u32(target, DCB_DCRDR, target->savedDCRDR);
 676         if (res != ERROR_OK)
 677                 return res;
 678
 679         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 680
 681         res = adapter->layout->api->step(adapter->handle);
 682
 683         if (res != ERROR_OK)
 684                 return res;
 685
 686         /* registers are now invalid */
 687         register_cache_invalidate(armv7m->arm.core_cache);
 688
 689         if (breakpoint)
 690                 cortex_m_set_breakpoint(target, breakpoint);
 691
 692         adapter_debug_entry(target);
 693         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 694
 695         LOG_INFO("halted: PC: 0x%08" PRIx32, buf_get_u32(armv7m->arm.pc->value, 0, 32));
 696
 697         return ERROR_OK;
 698 }
 699
 700 static int adapter_read_memory(struct target *target, target_addr_t address,
 701                 uint32_t size, uint32_t count,
 702                 uint8_t *buffer)
 703 {
 704         struct hl_interface_s *adapter = target_to_adapter(target);
 705
 706         if (!count || !buffer)
 707                 return ERROR_COMMAND_SYNTAX_ERROR;
 708
 709         LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
 710                           __func__, address, size, count);
 711
 712         return adapter->layout->api->read_mem(adapter->handle, address, size, count, buffer);
 713 }
 714
 715 static int adapter_write_memory(struct target *target, target_addr_t address,
 716                 uint32_t size, uint32_t count,
 717                 const uint8_t *buffer)
 718 {
 719         struct hl_interface_s *adapter = target_to_adapter(target);
 720
 721         if (!count || !buffer)
 722                 return ERROR_COMMAND_SYNTAX_ERROR;
 723
 724         LOG_DEBUG("%s " TARGET_ADDR_FMT " %" PRIu32 " %" PRIu32,
 725                           __func__, address, size, count);
 726
 727         return adapter->layout->api->write_mem(adapter->handle, address, size, count, buffer);
 728 }
 729
 730 static const struct command_registration adapter_command_handlers[] = {
 731         {
 732                 .chain = arm_command_handlers,
 733         },
 734         {
 735                 .chain = armv7m_trace_command_handlers,
 736         },
 737         COMMAND_REGISTRATION_DONE
 738 };
 739
 740 struct target_type hla_target = {
 741         .name = "hla_target",
 742         .deprecated_name = "stm32_stlink",
 743
 744         .init_target = adapter_init_target,
 745         .deinit_target = cortex_m_deinit_target,
 746         .target_create = adapter_target_create,
 747         .target_jim_configure = adiv5_jim_configure,
 748         .examine = cortex_m_examine,
 749         .commands = adapter_command_handlers,
 750
 751         .poll = adapter_poll,
 752         .arch_state = armv7m_arch_state,
 753
 754         .target_request_data = hl_target_request_data,
 755         .assert_reset = hl_assert_reset,
 756         .deassert_reset = hl_deassert_reset,
 757
 758         .halt = adapter_halt,
 759         .resume = adapter_resume,
 760         .step = adapter_step,
 761
 762         .get_gdb_arch = arm_get_gdb_arch,
 763         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
 764
 765         .read_memory = adapter_read_memory,
 766         .write_memory = adapter_write_memory,
 767         .checksum_memory = armv7m_checksum_memory,
 768         .blank_check_memory = armv7m_blank_check_memory,
 769
 770         .run_algorithm = armv7m_run_algorithm,
 771         .start_algorithm = armv7m_start_algorithm,
 772         .wait_algorithm = armv7m_wait_algorithm,
 773
 774         .add_breakpoint = cortex_m_add_breakpoint,
 775         .remove_breakpoint = cortex_m_remove_breakpoint,
 776         .add_watchpoint = cortex_m_add_watchpoint,
 777         .remove_watchpoint = cortex_m_remove_watchpoint,
 778         .profiling = cortex_m_profiling,
 779 };