1 /***************************************************************************
2 * Copyright (C) 2009 by Paulius Zaleckas *
3 * paulius.zaleckas@gmail.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
22 * FA526 is very similar to ARM920T with following differences:
24 * - execution pipeline is 6 steps
26 * - has Branch Target Buffer
27 * - does not support reading of I/D cache contents
35 #include "target_type.h"
37 static void fa526_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
39 LOG_ERROR("%s: there is no Thumb state on FA526", __func__);
42 static void fa526_read_core_regs(target_t *target,
43 uint32_t mask, uint32_t* core_regs[16])
46 /* get pointers to arch-specific information */
47 armv4_5_common_t *armv4_5 = target->arch_info;
48 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
49 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
51 /* STMIA r0-15, [r0] at debug speed
52 * register values will start to appear on 4th DCLK
54 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
56 /* fetch NOP, STM in DECODE stage */
57 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
58 /* fetch NOP, STM in SHIFT stage */
59 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
60 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
61 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
63 for (i = 0; i <= 15; i++)
66 /* nothing fetched, STM in MEMORY (i'th cycle) */
67 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
71 static void fa526_read_core_regs_target_buffer(target_t *target,
72 uint32_t mask, void* buffer, int size)
75 /* get pointers to arch-specific information */
76 armv4_5_common_t *armv4_5 = target->arch_info;
77 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
78 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
79 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
80 uint32_t *buf_u32 = buffer;
81 uint16_t *buf_u16 = buffer;
82 uint8_t *buf_u8 = buffer;
84 /* STMIA r0-15, [r0] at debug speed
85 * register values will start to appear on 4th DCLK
87 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
89 /* fetch NOP, STM in DECODE stage */
90 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
91 /* fetch NOP, STM in SHIFT stage */
92 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
93 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
94 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
96 for (i = 0; i <= 15; i++)
99 /* nothing fetched, STM in MEMORY (i'th cycle) */
103 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
106 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
109 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
115 static void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
117 /* get pointers to arch-specific information */
118 armv4_5_common_t *armv4_5 = target->arch_info;
119 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
120 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
123 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
124 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
125 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
126 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
127 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
128 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
131 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
132 /* fetch NOP, STR in DECODE stage */
133 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
134 /* fetch NOP, STR in SHIFT stage */
135 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
136 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
137 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
138 /* nothing fetched, STR in MEMORY */
139 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
142 static void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
144 /* get pointers to arch-specific information */
145 armv4_5_common_t *armv4_5 = target->arch_info;
146 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
147 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
149 LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
152 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
153 /* MSR2 fetched, MSR1 in DECODE */
154 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
155 /* MSR3 fetched, MSR1 in SHIFT, MSR2 in DECODE */
156 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
157 /* MSR4 fetched, MSR1 in EXECUTE (1), MSR2 in SHIFT, MSR3 in DECODE */
158 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
159 /* nothing fetched, MSR1 in EXECUTE (2) */
160 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
161 /* nothing fetched, MSR1 in EXECUTE (3) */
162 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
163 /* nothing fetched, MSR2 in EXECUTE (1), MSR3 in SHIFT, MSR4 in DECODE */
164 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
165 /* nothing fetched, MSR2 in EXECUTE (2) */
166 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
167 /* nothing fetched, MSR2 in EXECUTE (3) */
168 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
169 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in SHIFT */
170 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
171 /* nothing fetched, MSR3 in EXECUTE (2) */
172 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
173 /* nothing fetched, MSR3 in EXECUTE (3) */
174 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
175 /* NOP fetched, MSR4 in EXECUTE (1) */
176 /* last MSR writes flags, which takes only one cycle */
177 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
180 static void fa526_write_xpsr_im8(target_t *target,
181 uint8_t xpsr_im, int rot, int spsr)
183 /* get pointers to arch-specific information */
184 armv4_5_common_t *armv4_5 = target->arch_info;
185 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
186 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
188 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
191 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
192 /* NOP fetched, MSR in DECODE */
193 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
194 /* NOP fetched, MSR in SHIFT */
195 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
196 /* NOP fetched, MSR in EXECUTE (1) */
197 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
199 /* rot == 4 writes flags, which takes only one cycle */
202 /* nothing fetched, MSR in EXECUTE (2) */
203 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
204 /* nothing fetched, MSR in EXECUTE (3) */
205 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
209 static void fa526_write_core_regs(target_t *target,
210 uint32_t mask, uint32_t core_regs[16])
213 /* get pointers to arch-specific information */
214 armv4_5_common_t *armv4_5 = target->arch_info;
215 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
216 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
218 /* LDMIA r0-15, [r0] at debug speed
219 * register values will start to appear on 4th DCLK
221 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
223 /* fetch NOP, LDM in DECODE stage */
224 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
225 /* fetch NOP, LDM in SHIFT stage */
226 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
227 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
228 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
230 for (i = 0; i <= 15; i++)
233 /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
234 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
236 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
239 static void fa526_write_pc(target_t *target, uint32_t pc)
241 /* get pointers to arch-specific information */
242 armv4_5_common_t *armv4_5 = target->arch_info;
243 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
244 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
246 /* LDMIA r0-15, [r0] at debug speed
247 * register values will start to appear on 4th DCLK
249 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
251 /* fetch NOP, LDM in DECODE stage */
252 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
253 /* fetch NOP, LDM in SHIFT stage */
254 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
255 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
256 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
257 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
258 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
259 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
260 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
261 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
262 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
263 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
264 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
267 static void fa526_branch_resume_thumb(target_t *target)
269 LOG_ERROR("%s: there is no Thumb state on FA526", __func__);
272 static int fa526_init_arch_info_2(target_t *target,
273 arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
275 armv4_5_common_t *armv4_5;
276 arm7_9_common_t *arm7_9;
278 arm7_9 = &arm9tdmi->arm7_9_common;
279 armv4_5 = &arm7_9->armv4_5_common;
281 /* prepare JTAG information for the new target */
282 arm7_9->jtag_info.tap = tap;
283 arm7_9->jtag_info.scann_size = 5;
285 /* register arch-specific functions */
286 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
287 arm7_9->change_to_arm = fa526_change_to_arm;
288 arm7_9->read_core_regs = fa526_read_core_regs;
289 arm7_9->read_core_regs_target_buffer = fa526_read_core_regs_target_buffer;
290 arm7_9->read_xpsr = fa526_read_xpsr;
292 arm7_9->write_xpsr = fa526_write_xpsr;
293 arm7_9->write_xpsr_im8 = fa526_write_xpsr_im8;
294 arm7_9->write_core_regs = fa526_write_core_regs;
296 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
297 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
298 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
300 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
301 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
302 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
304 arm7_9->write_pc = fa526_write_pc;
305 arm7_9->branch_resume = arm9tdmi_branch_resume;
306 arm7_9->branch_resume_thumb = fa526_branch_resume_thumb;
308 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
309 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
311 arm7_9->post_debug_entry = NULL;
313 arm7_9->pre_restore_context = NULL;
314 arm7_9->post_restore_context = NULL;
316 /* initialize arch-specific breakpoint handling */
317 arm7_9->arm_bkpt = 0xdeeedeee;
318 arm7_9->thumb_bkpt = 0xdeee;
320 arm7_9->dbgreq_adjust_pc = 3;
321 arm7_9->arch_info = arm9tdmi;
323 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
324 arm9tdmi->arch_info = NULL;
326 arm7_9_init_arch_info(target, arm7_9);
328 /* override use of DBGRQ, this is safe on ARM9TDMI */
329 arm7_9->use_dbgrq = 1;
331 /* all ARM9s have the vector catch register */
332 arm7_9->has_vector_catch = 1;
337 static int fa526_init_arch_info(target_t *target,
338 arm920t_common_t *arm920t, jtag_tap_t *tap)
340 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
341 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
343 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
345 fa526_init_arch_info_2(target, arm9tdmi, tap);
347 arm9tdmi->arch_info = arm920t;
348 arm920t->common_magic = ARM920T_COMMON_MAGIC;
350 arm7_9->post_debug_entry = arm920t_post_debug_entry;
351 arm7_9->pre_restore_context = arm920t_pre_restore_context;
353 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
354 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
355 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
356 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
357 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
358 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
359 arm920t->armv4_5_mmu.has_tiny_pages = 1;
360 arm920t->armv4_5_mmu.mmu_enabled = 0;
362 /* disabling linefills leads to lockups, so keep them enabled for now
363 * this doesn't affect correctness, but might affect timing issues, if
364 * important data is evicted from the cache during the debug session
366 arm920t->preserve_cache = 0;
368 /* override hw single-step capability from ARM9TDMI */
369 arm7_9->has_single_step = 1;
374 static int fa526_target_create(struct target_s *target, Jim_Interp *interp)
376 arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
378 return fa526_init_arch_info(target, arm920t, target->tap);
381 /** Holds methods for FA526 targets. */
382 target_type_t fa526_target =
387 .arch_state = arm920t_arch_state,
389 .target_request_data = arm7_9_target_request_data,
392 .resume = arm7_9_resume,
395 .assert_reset = arm7_9_assert_reset,
396 .deassert_reset = arm7_9_deassert_reset,
397 .soft_reset_halt = arm920t_soft_reset_halt,
399 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
401 .read_memory = arm920t_read_memory,
402 .write_memory = arm920t_write_memory,
403 .bulk_write_memory = arm7_9_bulk_write_memory,
404 .checksum_memory = arm7_9_checksum_memory,
405 .blank_check_memory = arm7_9_blank_check_memory,
407 .run_algorithm = armv4_5_run_algorithm,
409 .add_breakpoint = arm7_9_add_breakpoint,
410 .remove_breakpoint = arm7_9_remove_breakpoint,
411 .add_watchpoint = arm7_9_add_watchpoint,
412 .remove_watchpoint = arm7_9_remove_watchpoint,
414 .register_commands = arm920t_register_commands,
415 .target_create = fa526_target_create,
416 .init_target = arm9tdmi_init_target,
417 .examine = arm9tdmi_examine,