1 /***************************************************************************
2 * Copyright (C) 2009 by Paulius Zaleckas *
3 * paulius.zaleckas@gmail.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
22 * FA526 is very similar to ARM920T with following differences:
24 * - execution pipeline is 6 steps
26 * - has Branch Target Buffer
27 * - does not support reading of I/D cache contents
35 #include "target_type.h"
37 int fa526_target_create(struct target_s *target, Jim_Interp *interp);
38 int fa526_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
40 target_type_t fa526_target =
45 .arch_state = arm920t_arch_state,
47 .target_request_data = arm7_9_target_request_data,
50 .resume = arm7_9_resume,
53 .assert_reset = arm7_9_assert_reset,
54 .deassert_reset = arm7_9_deassert_reset,
55 .soft_reset_halt = arm920t_soft_reset_halt,
57 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
59 .read_memory = arm920t_read_memory,
60 .write_memory = arm920t_write_memory,
61 .bulk_write_memory = arm7_9_bulk_write_memory,
62 .checksum_memory = arm7_9_checksum_memory,
63 .blank_check_memory = arm7_9_blank_check_memory,
65 .run_algorithm = armv4_5_run_algorithm,
67 .add_breakpoint = arm7_9_add_breakpoint,
68 .remove_breakpoint = arm7_9_remove_breakpoint,
69 .add_watchpoint = arm7_9_add_watchpoint,
70 .remove_watchpoint = arm7_9_remove_watchpoint,
72 .register_commands = arm920t_register_commands,
73 .target_create = fa526_target_create,
74 .init_target = fa526_init_target,
75 .examine = arm9tdmi_examine,
78 void fa526_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
80 LOG_ERROR("%s: there is no Thumb state on FA526", __func__);
83 void fa526_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
86 /* get pointers to arch-specific information */
87 armv4_5_common_t *armv4_5 = target->arch_info;
88 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
89 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
91 /* STMIA r0-15, [r0] at debug speed
92 * register values will start to appear on 4th DCLK
94 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
96 /* fetch NOP, STM in DECODE stage */
97 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
98 /* fetch NOP, STM in SHIFT stage */
99 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
100 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
101 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
103 for (i = 0; i <= 15; i++)
106 /* nothing fetched, STM in MEMORY (i'th cycle) */
107 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
111 void fa526_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
114 /* get pointers to arch-specific information */
115 armv4_5_common_t *armv4_5 = target->arch_info;
116 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
117 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
118 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
119 uint32_t *buf_u32 = buffer;
120 uint16_t *buf_u16 = buffer;
121 uint8_t *buf_u8 = buffer;
123 /* STMIA r0-15, [r0] at debug speed
124 * register values will start to appear on 4th DCLK
126 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
128 /* fetch NOP, STM in DECODE stage */
129 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
130 /* fetch NOP, STM in SHIFT stage */
131 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
132 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
133 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
135 for (i = 0; i <= 15; i++)
138 /* nothing fetched, STM in MEMORY (i'th cycle) */
142 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
145 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
148 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
154 void fa526_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
156 /* get pointers to arch-specific information */
157 armv4_5_common_t *armv4_5 = target->arch_info;
158 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
159 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
162 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
163 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
164 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
165 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
166 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
167 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
170 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
171 /* fetch NOP, STR in DECODE stage */
172 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
173 /* fetch NOP, STR in SHIFT stage */
174 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
175 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
176 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
177 /* nothing fetched, STR in MEMORY */
178 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
181 void fa526_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
183 /* get pointers to arch-specific information */
184 armv4_5_common_t *armv4_5 = target->arch_info;
185 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
186 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
188 LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
191 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
192 /* MSR2 fetched, MSR1 in DECODE */
193 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
194 /* MSR3 fetched, MSR1 in SHIFT, MSR2 in DECODE */
195 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
196 /* MSR4 fetched, MSR1 in EXECUTE (1), MSR2 in SHIFT, MSR3 in DECODE */
197 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
198 /* nothing fetched, MSR1 in EXECUTE (2) */
199 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
200 /* nothing fetched, MSR1 in EXECUTE (3) */
201 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
202 /* nothing fetched, MSR2 in EXECUTE (1), MSR3 in SHIFT, MSR4 in DECODE */
203 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
204 /* nothing fetched, MSR2 in EXECUTE (2) */
205 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
206 /* nothing fetched, MSR2 in EXECUTE (3) */
207 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
208 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in SHIFT */
209 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
210 /* nothing fetched, MSR3 in EXECUTE (2) */
211 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
212 /* nothing fetched, MSR3 in EXECUTE (3) */
213 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
214 /* NOP fetched, MSR4 in EXECUTE (1) */
215 /* last MSR writes flags, which takes only one cycle */
216 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
219 void fa526_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
221 /* get pointers to arch-specific information */
222 armv4_5_common_t *armv4_5 = target->arch_info;
223 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
224 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
226 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
229 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
230 /* NOP fetched, MSR in DECODE */
231 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
232 /* NOP fetched, MSR in SHIFT */
233 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
234 /* NOP fetched, MSR in EXECUTE (1) */
235 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
237 /* rot == 4 writes flags, which takes only one cycle */
240 /* nothing fetched, MSR in EXECUTE (2) */
241 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
242 /* nothing fetched, MSR in EXECUTE (3) */
243 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
247 void fa526_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
250 /* get pointers to arch-specific information */
251 armv4_5_common_t *armv4_5 = target->arch_info;
252 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
253 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
255 /* LDMIA r0-15, [r0] at debug speed
256 * register values will start to appear on 4th DCLK
258 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
260 /* fetch NOP, LDM in DECODE stage */
261 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
262 /* fetch NOP, LDM in SHIFT stage */
263 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
264 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
265 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
267 for (i = 0; i <= 15; i++)
270 /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
271 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
273 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
276 void fa526_write_pc(target_t *target, uint32_t pc)
278 /* get pointers to arch-specific information */
279 armv4_5_common_t *armv4_5 = target->arch_info;
280 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
281 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
283 /* LDMIA r0-15, [r0] at debug speed
284 * register values will start to appear on 4th DCLK
286 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
288 /* fetch NOP, LDM in DECODE stage */
289 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
290 /* fetch NOP, LDM in SHIFT stage */
291 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
292 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
293 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
294 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
295 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
296 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
297 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
298 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
299 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
300 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
301 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
304 void fa526_branch_resume_thumb(target_t *target)
306 LOG_ERROR("%s: there is no Thumb state on FA526", __func__);
309 int fa526_init_arch_info_2(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
311 armv4_5_common_t *armv4_5;
312 arm7_9_common_t *arm7_9;
314 arm7_9 = &arm9tdmi->arm7_9_common;
315 armv4_5 = &arm7_9->armv4_5_common;
317 /* prepare JTAG information for the new target */
318 arm7_9->jtag_info.tap = tap;
319 arm7_9->jtag_info.scann_size = 5;
321 /* register arch-specific functions */
322 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
323 arm7_9->change_to_arm = fa526_change_to_arm;
324 arm7_9->read_core_regs = fa526_read_core_regs;
325 arm7_9->read_core_regs_target_buffer = fa526_read_core_regs_target_buffer;
326 arm7_9->read_xpsr = fa526_read_xpsr;
328 arm7_9->write_xpsr = fa526_write_xpsr;
329 arm7_9->write_xpsr_im8 = fa526_write_xpsr_im8;
330 arm7_9->write_core_regs = fa526_write_core_regs;
332 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
333 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
334 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
336 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
337 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
338 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
340 arm7_9->write_pc = fa526_write_pc;
341 arm7_9->branch_resume = arm9tdmi_branch_resume;
342 arm7_9->branch_resume_thumb = fa526_branch_resume_thumb;
344 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
345 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
347 arm7_9->post_debug_entry = NULL;
349 arm7_9->pre_restore_context = NULL;
350 arm7_9->post_restore_context = NULL;
352 /* initialize arch-specific breakpoint handling */
353 arm7_9->arm_bkpt = 0xdeeedeee;
354 arm7_9->thumb_bkpt = 0xdeee;
356 arm7_9->dbgreq_adjust_pc = 3;
357 arm7_9->arch_info = arm9tdmi;
359 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
360 arm9tdmi->arch_info = NULL;
362 arm7_9_init_arch_info(target, arm7_9);
364 /* override use of DBGRQ, this is safe on ARM9TDMI */
365 arm7_9->use_dbgrq = 1;
367 /* all ARM9s have the vector catch register */
368 arm7_9->has_vector_catch = 1;
373 int fa526_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
375 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
376 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
378 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
380 fa526_init_arch_info_2(target, arm9tdmi, tap);
382 arm9tdmi->arch_info = arm920t;
383 arm920t->common_magic = ARM920T_COMMON_MAGIC;
385 arm7_9->post_debug_entry = arm920t_post_debug_entry;
386 arm7_9->pre_restore_context = arm920t_pre_restore_context;
388 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
389 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
390 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
391 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
392 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
393 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
394 arm920t->armv4_5_mmu.has_tiny_pages = 1;
395 arm920t->armv4_5_mmu.mmu_enabled = 0;
397 /* disabling linefills leads to lockups, so keep them enabled for now
398 * this doesn't affect correctness, but might affect timing issues, if
399 * important data is evicted from the cache during the debug session
401 arm920t->preserve_cache = 0;
403 /* override hw single-step capability from ARM9TDMI */
404 arm7_9->has_single_step = 1;
409 int fa526_target_create(struct target_s *target, Jim_Interp *interp)
411 arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
413 fa526_init_arch_info(target, arm920t, target->tap);
418 int fa526_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
420 arm9tdmi_init_target(cmd_ctx, target);