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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm.h"
  25 #include "etm.h"
  26 #include "etb.h"
  27 #include "image.h"
  28 #include "arm_disassembler.h"
  29 #include "register.h"
  30 #include "etm_dummy.h"
  31
  32 #if BUILD_OOCD_TRACE == 1
  33 #include "oocd_trace.h"
  34 #endif
  35
  36
  37 /*
  38  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  39  *
  40  * ETM modules collect instruction and/or data trace information, compress
  41  * it, and transfer it to a debugging host through either a (buffered) trace
  42  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  43  *
  44  * There are several generations of these modules.  Original versions have
  45  * JTAG access through a dedicated scan chain.  Recent versions have added
  46  * access via coprocessor instructions, memory addressing, and the ARM Debug
  47  * Interface v5 (ADIv5); and phased out direct JTAG access.
  48  *
  49  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  50  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  51  * implying non-JTAG connectivity options.
  52  *
  53  * Relevant documentation includes:
  54  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  55  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  56  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  57  */
  58
  59 enum {
  60         RO,                             /* read/only */
  61         WO,                             /* write/only */
  62         RW,                             /* read/write */
  63 };
  64
  65 struct etm_reg_info {
  66         uint8_t         addr;
  67         uint8_t         size;           /* low-N of 32 bits */
  68         uint8_t         mode;           /* RO, WO, RW */
  69         uint8_t         bcd_vers;       /* 1.0, 2.0, etc */
  70         char            *name;
  71 };
  72
  73 /*
  74  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  75  * (Or on some processors, through coprocessor operations.)
  76  * Newer versions of ETM make some W/O registers R/W, and
  77  * provide definitions for some previously-unused bits.
  78  */
  79
  80 /* core registers used to version/configure the ETM */
  81 static const struct etm_reg_info etm_core[] = {
  82         /* NOTE: we "know" the order here ... */
  83         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  84         { ETM_ID, 32, RO, 0x20, "ETM_id", },
  85 };
  86
  87 /* basic registers that are always there given the right ETM version */
  88 static const struct etm_reg_info etm_basic[] = {
  89         /* ETM Trace Registers */
  90         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  91         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  92         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
  93         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
  94         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
  95
  96         /* TraceEnable configuration */
  97         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  98         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  99         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
 100         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
 101
 102         /* ViewData configuration (data trace) */
 103         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
 104         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
 105         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
 106         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
 107
 108         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 109
 110         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
 111         { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
 112         { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
 113         { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
 114         { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
 115 };
 116
 117 static const struct etm_reg_info etm_fifofull[] = {
 118         /* FIFOFULL configuration */
 119         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
 120         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
 121 };
 122
 123 static const struct etm_reg_info etm_addr_comp[] = {
 124         /* Address comparator register pairs */
 125 #define ADDR_COMPARATOR(i) \
 126                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
 127                                 "ETM_addr_" #i "_comparator_value", }, \
 128                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
 129                                 "ETM_addr_" #i "_access_type", }
 130         ADDR_COMPARATOR(1),
 131         ADDR_COMPARATOR(2),
 132         ADDR_COMPARATOR(3),
 133         ADDR_COMPARATOR(4),
 134         ADDR_COMPARATOR(5),
 135         ADDR_COMPARATOR(6),
 136         ADDR_COMPARATOR(7),
 137         ADDR_COMPARATOR(8),
 138
 139         ADDR_COMPARATOR(9),
 140         ADDR_COMPARATOR(10),
 141         ADDR_COMPARATOR(11),
 142         ADDR_COMPARATOR(12),
 143         ADDR_COMPARATOR(13),
 144         ADDR_COMPARATOR(14),
 145         ADDR_COMPARATOR(15),
 146         ADDR_COMPARATOR(16),
 147 #undef ADDR_COMPARATOR
 148 };
 149
 150 static const struct etm_reg_info etm_data_comp[] = {
 151         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 152 #define DATA_COMPARATOR(i) \
 153                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
 154                                 "ETM_data_" #i "_comparator_value", }, \
 155                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
 156                                 "ETM_data_" #i "_comparator_mask", }
 157         DATA_COMPARATOR(1),
 158         DATA_COMPARATOR(2),
 159         DATA_COMPARATOR(3),
 160         DATA_COMPARATOR(4),
 161         DATA_COMPARATOR(5),
 162         DATA_COMPARATOR(6),
 163         DATA_COMPARATOR(7),
 164         DATA_COMPARATOR(8),
 165 #undef DATA_COMPARATOR
 166 };
 167
 168 static const struct etm_reg_info etm_counters[] = {
 169 #define ETM_COUNTER(i) \
 170                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
 171                                 "ETM_counter_" #i "_reload_value", }, \
 172                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
 173                                 "ETM_counter_" #i "_enable", }, \
 174                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
 175                                 "ETM_counter_" #i "_reload_event", }, \
 176                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
 177                                 "ETM_counter_" #i "_value", }
 178         ETM_COUNTER(1),
 179         ETM_COUNTER(2),
 180         ETM_COUNTER(3),
 181         ETM_COUNTER(4),
 182 #undef ETM_COUNTER
 183 };
 184
 185 static const struct etm_reg_info etm_sequencer[] = {
 186 #define ETM_SEQ(i) \
 187                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 188                                 "ETM_sequencer_event" #i, }
 189         ETM_SEQ(0),                             /* 1->2 */
 190         ETM_SEQ(1),                             /* 2->1 */
 191         ETM_SEQ(2),                             /* 2->3 */
 192         ETM_SEQ(3),                             /* 3->1 */
 193         ETM_SEQ(4),                             /* 3->2 */
 194         ETM_SEQ(5),                             /* 1->3 */
 195 #undef ETM_SEQ
 196         /* 0x66 reserved */
 197         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
 198 };
 199
 200 static const struct etm_reg_info etm_outputs[] = {
 201 #define ETM_OUTPUT(i) \
 202                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
 203                                 "ETM_external_output" #i, }
 204
 205         ETM_OUTPUT(1),
 206         ETM_OUTPUT(2),
 207         ETM_OUTPUT(3),
 208         ETM_OUTPUT(4),
 209 #undef ETM_OUTPUT
 210 };
 211
 212 #if 0
 213         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 214
 215         /* Context ID Comparators */
 216         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
 217         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
 218         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
 219         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
 220 #endif
 221
 222 static int etm_get_reg(struct reg *reg);
 223 static int etm_read_reg_w_check(struct reg *reg,
 224                 uint8_t* check_value, uint8_t* check_mask);
 225 static int etm_register_user_commands(struct command_context *cmd_ctx);
 226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
 227 static int etm_write_reg(struct reg *reg, uint32_t value);
 228
 229 static const struct reg_arch_type etm_scan6_type = {
 230         .get = etm_get_reg,
 231         .set = etm_set_reg_w_exec,
 232 };
 233
 234 /* Look up register by ID ... most ETM instances only
 235  * support a subset of the possible registers.
 236  */
 237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
 238 {
 239         struct reg_cache *cache = etm_ctx->reg_cache;
 240         unsigned i;
 241
 242         for (i = 0; i < cache->num_regs; i++) {
 243                 struct etm_reg *reg = cache->reg_list[i].arch_info;
 244
 245                 if (reg->reg_info->addr == id)
 246                         return &cache->reg_list[i];
 247         }
 248
 249         /* caller asking for nonexistent register is a bug! */
 250         /* REVISIT say which of the N targets was involved */
 251         LOG_ERROR("ETM: register 0x%02x not available", id);
 252         return NULL;
 253 }
 254
 255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
 256                 struct reg_cache *cache, struct etm_reg *ereg,
 257                 const struct etm_reg_info *r, unsigned nreg)
 258 {
 259         struct reg *reg = cache->reg_list;
 260
 261         reg += cache->num_regs;
 262         ereg += cache->num_regs;
 263
 264         /* add up to "nreg" registers from "r", if supported by this
 265          * version of the ETM, to the specified cache.
 266          */
 267         for (; nreg--; r++) {
 268
 269                 /* this ETM may be too old to have some registers */
 270                 if (r->bcd_vers > bcd_vers)
 271                         continue;
 272
 273                 reg->name = r->name;
 274                 reg->size = r->size;
 275                 reg->value = &ereg->value;
 276                 reg->arch_info = ereg;
 277                 reg->type = &etm_scan6_type;
 278                 reg++;
 279                 cache->num_regs++;
 280
 281                 ereg->reg_info = r;
 282                 ereg->jtag_info = jtag_info;
 283                 ereg++;
 284         }
 285 }
 286
 287 struct reg_cache *etm_build_reg_cache(struct target *target,
 288                 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
 289 {
 290         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 291         struct reg *reg_list = NULL;
 292         struct etm_reg *arch_info = NULL;
 293         unsigned bcd_vers, config;
 294
 295         /* the actual registers are kept in two arrays */
 296         reg_list = calloc(128, sizeof(struct reg));
 297         arch_info = calloc(128, sizeof(struct etm_reg));
 298
 299         /* fill in values for the reg cache */
 300         reg_cache->name = "etm registers";
 301         reg_cache->next = NULL;
 302         reg_cache->reg_list = reg_list;
 303         reg_cache->num_regs = 0;
 304
 305         /* add ETM_CONFIG, then parse its values to see
 306          * which other registers exist in this ETM
 307          */
 308         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 309                         etm_core, 1);
 310
 311         etm_get_reg(reg_list);
 312         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 313         config = etm_ctx->config;
 314
 315         /* figure ETM version then add base registers */
 316         if (config & (1 << 31)) {
 317                 bcd_vers = 0x20;
 318                 LOG_WARNING("ETMv2+ support is incomplete");
 319
 320                 /* REVISIT more registers may exist; they may now be
 321                  * readable; more register bits have defined meanings;
 322                  * don't presume trace start/stop support is present;
 323                  * and include any context ID comparator registers.
 324                  */
 325                 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
 326                                 etm_core + 1, 1);
 327                 etm_get_reg(reg_list + 1);
 328                 etm_ctx->id = buf_get_u32(
 329                                 (void *)&arch_info[1].value, 0, 32);
 330                 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
 331                 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
 332
 333         } else {
 334                 switch (config >> 28) {
 335                 case 7:
 336                 case 5:
 337                 case 3:
 338                         bcd_vers = 0x13;
 339                         break;
 340                 case 4:
 341                 case 2:
 342                         bcd_vers = 0x12;
 343                         break;
 344                 case 1:
 345                         bcd_vers = 0x11;
 346                         break;
 347                 case 0:
 348                         bcd_vers = 0x10;
 349                         break;
 350                 default:
 351                         LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 352                         goto fail;
 353                 }
 354         }
 355         etm_ctx->bcd_vers = bcd_vers;
 356         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 357
 358         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 359                         etm_basic, ARRAY_SIZE(etm_basic));
 360
 361         /* address and data comparators; counters; outputs */
 362         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 363                         etm_addr_comp, 4 * (0x0f & (config >> 0)));
 364         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 365                         etm_data_comp, 2 * (0x0f & (config >> 4)));
 366         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 367                         etm_counters, 4 * (0x07 & (config >> 13)));
 368         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 369                         etm_outputs, (0x07 & (config >> 20)));
 370
 371         /* FIFOFULL presence is optional
 372          * REVISIT for ETMv1.2 and later, don't bother adding this
 373          * unless ETM_SYS_CONFIG says it's also *supported* ...
 374          */
 375         if (config & (1 << 23))
 376                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 377                                 etm_fifofull, ARRAY_SIZE(etm_fifofull));
 378
 379         /* sequencer is optional (for state-dependant triggering) */
 380         if (config & (1 << 16))
 381                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 382                                 etm_sequencer, ARRAY_SIZE(etm_sequencer));
 383
 384         /* REVISIT could realloc and likely save half the memory
 385          * in the two chunks we allocated...
 386          */
 387
 388         /* the ETM might have an ETB connected */
 389         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 390         {
 391                 struct etb *etb = etm_ctx->capture_driver_priv;
 392
 393                 if (!etb)
 394                 {
 395                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 396                         goto fail;
 397                 }
 398
 399                 reg_cache->next = etb_build_reg_cache(etb);
 400
 401                 etb->reg_cache = reg_cache->next;
 402         }
 403
 404         etm_ctx->reg_cache = reg_cache;
 405         return reg_cache;
 406
 407 fail:
 408         free(reg_cache);
 409         free(reg_list);
 410         free(arch_info);
 411         return NULL;
 412 }
 413
 414 static int etm_read_reg(struct reg *reg)
 415 {
 416         return etm_read_reg_w_check(reg, NULL, NULL);
 417 }
 418
 419 static int etm_store_reg(struct reg *reg)
 420 {
 421         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 422 }
 423
 424 int etm_setup(struct target *target)
 425 {
 426         int retval;
 427         uint32_t etm_ctrl_value;
 428         struct arm *arm = target_to_arm(target);
 429         struct etm_context *etm_ctx = arm->etm;
 430         struct reg *etm_ctrl_reg;
 431
 432         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 433         if (!etm_ctrl_reg)
 434                 return ERROR_OK;
 435
 436         /* initialize some ETM control register settings */
 437         etm_get_reg(etm_ctrl_reg);
 438         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
 439
 440         /* clear the ETM powerdown bit (0) */
 441         etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
 442
 443         /* configure port width (21,6:4), mode (13,17:16) and
 444          * for older modules clocking (13)
 445          */
 446         etm_ctrl_value = (etm_ctrl_value
 447                         & ~ETM_PORT_WIDTH_MASK
 448                         & ~ETM_PORT_MODE_MASK
 449                         & ~ETM_PORT_CLOCK_MASK)
 450                 | etm_ctx->control;
 451
 452         buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
 453         etm_store_reg(etm_ctrl_reg);
 454
 455         if ((retval = jtag_execute_queue()) != ERROR_OK)
 456                 return retval;
 457
 458         /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
 459          * verify that those width and mode settings are OK ...
 460          */
 461
 462         if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 463         {
 464                 LOG_ERROR("ETM capture driver initialization failed");
 465                 return retval;
 466         }
 467         return ERROR_OK;
 468 }
 469
 470 static int etm_get_reg(struct reg *reg)
 471 {
 472         int retval;
 473
 474         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 475         {
 476                 LOG_ERROR("BUG: error scheduling etm register read");
 477                 return retval;
 478         }
 479
 480         if ((retval = jtag_execute_queue()) != ERROR_OK)
 481         {
 482                 LOG_ERROR("register read failed");
 483                 return retval;
 484         }
 485
 486         return ERROR_OK;
 487 }
 488
 489 static int etm_read_reg_w_check(struct reg *reg,
 490                 uint8_t* check_value, uint8_t* check_mask)
 491 {
 492         struct etm_reg *etm_reg = reg->arch_info;
 493         const struct etm_reg_info *r = etm_reg->reg_info;
 494         uint8_t reg_addr = r->addr & 0x7f;
 495         struct scan_field fields[3];
 496
 497         if (etm_reg->reg_info->mode == WO) {
 498                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 499                 return ERROR_INVALID_ARGUMENTS;
 500         }
 501
 502         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 503
 504         jtag_set_end_state(TAP_IDLE);
 505         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 506         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 507
 508         fields[0].tap = etm_reg->jtag_info->tap;
 509         fields[0].num_bits = 32;
 510         fields[0].out_value = reg->value;
 511         fields[0].in_value = NULL;
 512         fields[0].check_value = NULL;
 513         fields[0].check_mask = NULL;
 514
 515         fields[1].tap = etm_reg->jtag_info->tap;
 516         fields[1].num_bits = 7;
 517         fields[1].out_value = malloc(1);
 518         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 519         fields[1].in_value = NULL;
 520         fields[1].check_value = NULL;
 521         fields[1].check_mask = NULL;
 522
 523         fields[2].tap = etm_reg->jtag_info->tap;
 524         fields[2].num_bits = 1;
 525         fields[2].out_value = malloc(1);
 526         buf_set_u32(fields[2].out_value, 0, 1, 0);
 527         fields[2].in_value = NULL;
 528         fields[2].check_value = NULL;
 529         fields[2].check_mask = NULL;
 530
 531         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 532
 533         fields[0].in_value = reg->value;
 534         fields[0].check_value = check_value;
 535         fields[0].check_mask = check_mask;
 536
 537         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 538
 539         free(fields[1].out_value);
 540         free(fields[2].out_value);
 541
 542         return ERROR_OK;
 543 }
 544
 545 static int etm_set_reg(struct reg *reg, uint32_t value)
 546 {
 547         int retval;
 548
 549         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 550         {
 551                 LOG_ERROR("BUG: error scheduling etm register write");
 552                 return retval;
 553         }
 554
 555         buf_set_u32(reg->value, 0, reg->size, value);
 556         reg->valid = 1;
 557         reg->dirty = 0;
 558
 559         return ERROR_OK;
 560 }
 561
 562 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 563 {
 564         int retval;
 565
 566         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 567
 568         if ((retval = jtag_execute_queue()) != ERROR_OK)
 569         {
 570                 LOG_ERROR("register write failed");
 571                 return retval;
 572         }
 573         return ERROR_OK;
 574 }
 575
 576 static int etm_write_reg(struct reg *reg, uint32_t value)
 577 {
 578         struct etm_reg *etm_reg = reg->arch_info;
 579         const struct etm_reg_info *r = etm_reg->reg_info;
 580         uint8_t reg_addr = r->addr & 0x7f;
 581         struct scan_field fields[3];
 582
 583         if (etm_reg->reg_info->mode == RO) {
 584                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 585                 return ERROR_INVALID_ARGUMENTS;
 586         }
 587
 588         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 589
 590         jtag_set_end_state(TAP_IDLE);
 591         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 592         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 593
 594         fields[0].tap = etm_reg->jtag_info->tap;
 595         fields[0].num_bits = 32;
 596         uint8_t tmp1[4];
 597         fields[0].out_value = tmp1;
 598         buf_set_u32(fields[0].out_value, 0, 32, value);
 599         fields[0].in_value = NULL;
 600
 601         fields[1].tap = etm_reg->jtag_info->tap;
 602         fields[1].num_bits = 7;
 603         uint8_t tmp2;
 604         fields[1].out_value = &tmp2;
 605         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 606         fields[1].in_value = NULL;
 607
 608         fields[2].tap = etm_reg->jtag_info->tap;
 609         fields[2].num_bits = 1;
 610         uint8_t tmp3;
 611         fields[2].out_value = &tmp3;
 612         buf_set_u32(fields[2].out_value, 0, 1, 1);
 613         fields[2].in_value = NULL;
 614
 615         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 616
 617         return ERROR_OK;
 618 }
 619
 620
 621 /* ETM trace analysis functionality */
 622
 623 static struct etm_capture_driver *etm_capture_drivers[] =
 624 {
 625         &etb_capture_driver,
 626         &etm_dummy_capture_driver,
 627 #if BUILD_OOCD_TRACE == 1
 628         &oocd_trace_capture_driver,
 629 #endif
 630         NULL
 631 };
 632
 633 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
 634 {
 635         int i;
 636         int section = -1;
 637         size_t size_read;
 638         uint32_t opcode;
 639         int retval;
 640
 641         if (!ctx->image)
 642                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 643
 644         /* search for the section the current instruction belongs to */
 645         for (i = 0; i < ctx->image->num_sections; i++)
 646         {
 647                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 648                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 649                 {
 650                         section = i;
 651                         break;
 652                 }
 653         }
 654
 655         if (section == -1)
 656         {
 657                 /* current instruction couldn't be found in the image */
 658                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 659         }
 660
 661         if (ctx->core_state == ARM_STATE_ARM)
 662         {
 663                 uint8_t buf[4];
 664                 if ((retval = image_read_section(ctx->image, section,
 665                         ctx->current_pc - ctx->image->sections[section].base_address,
 666                         4, buf, &size_read)) != ERROR_OK)
 667                 {
 668                         LOG_ERROR("error while reading instruction: %i", retval);
 669                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 670                 }
 671                 opcode = target_buffer_get_u32(ctx->target, buf);
 672                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 673         }
 674         else if (ctx->core_state == ARM_STATE_THUMB)
 675         {
 676                 uint8_t buf[2];
 677                 if ((retval = image_read_section(ctx->image, section,
 678                         ctx->current_pc - ctx->image->sections[section].base_address,
 679                         2, buf, &size_read)) != ERROR_OK)
 680                 {
 681                         LOG_ERROR("error while reading instruction: %i", retval);
 682                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 683                 }
 684                 opcode = target_buffer_get_u16(ctx->target, buf);
 685                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 686         }
 687         else if (ctx->core_state == ARM_STATE_JAZELLE)
 688         {
 689                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 690                 return ERROR_FAIL;
 691         }
 692         else
 693         {
 694                 LOG_ERROR("BUG: unknown core state encountered");
 695                 return ERROR_FAIL;
 696         }
 697
 698         return ERROR_OK;
 699 }
 700
 701 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
 702 {
 703         while (ctx->data_index < ctx->trace_depth)
 704         {
 705                 /* if the caller specified an address packet offset, skip until the
 706                  * we reach the n-th cycle marked with tracesync */
 707                 if (apo > 0)
 708                 {
 709                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 710                                 apo--;
 711
 712                         if (apo > 0)
 713                         {
 714                                 ctx->data_index++;
 715                                 ctx->data_half = 0;
 716                         }
 717                         continue;
 718                 }
 719
 720                 /* no tracedata output during a TD cycle
 721                  * or in a trigger cycle */
 722                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 723                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 724                 {
 725                         ctx->data_index++;
 726                         ctx->data_half = 0;
 727                         continue;
 728                 }
 729
 730                 /* FIXME there are more port widths than these... */
 731                 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 732                 {
 733                         if (ctx->data_half == 0)
 734                         {
 735                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 736                                 ctx->data_half = 1;
 737                         }
 738                         else
 739                         {
 740                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 741                                 ctx->data_half = 0;
 742                                 ctx->data_index++;
 743                         }
 744                 }
 745                 else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 746                 {
 747                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 748                         ctx->data_index++;
 749                 }
 750                 else
 751                 {
 752                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 753                         if (ctx->data_index > (ctx->trace_depth - 2))
 754                                 return -1;
 755
 756                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 757                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 758                         ctx->data_index += 2;
 759                 }
 760
 761                 return 0;
 762         }
 763
 764         return -1;
 765 }
 766
 767 static int etmv1_branch_address(struct etm_context *ctx)
 768 {
 769         int retval;
 770         uint8_t packet;
 771         int shift = 0;
 772         int apo;
 773         uint32_t i;
 774
 775         /* quit analysis if less than two cycles are left in the trace
 776          * because we can't extract the APO */
 777         if (ctx->data_index > (ctx->trace_depth - 2))
 778                 return -1;
 779
 780         /* a BE could be output during an APO cycle, skip the current
 781          * and continue with the new one */
 782         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 783                 return 1;
 784         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 785                 return 2;
 786
 787         /* address packet offset encoded in the next two cycles' pipestat bits */
 788         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 789         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 790
 791         /* count number of tracesync cycles between current pipe_index and data_index
 792          * i.e. the number of tracesyncs that data_index already passed by
 793          * to subtract them from the APO */
 794         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 795         {
 796                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 797                         apo--;
 798         }
 799
 800         /* extract up to four 7-bit packets */
 801         do {
 802                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 803                         return -1;
 804                 ctx->last_branch &= ~(0x7f << shift);
 805                 ctx->last_branch |= (packet & 0x7f) << shift;
 806                 shift += 7;
 807         } while ((packet & 0x80) && (shift < 28));
 808
 809         /* one last packet holding 4 bits of the address, plus the branch reason code */
 810         if ((shift == 28) && (packet & 0x80))
 811         {
 812                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 813                         return -1;
 814                 ctx->last_branch &= 0x0fffffff;
 815                 ctx->last_branch |= (packet & 0x0f) << 28;
 816                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 817                 shift += 4;
 818         }
 819         else
 820         {
 821                 ctx->last_branch_reason = 0;
 822         }
 823
 824         if (shift == 32)
 825         {
 826                 ctx->pc_ok = 1;
 827         }
 828
 829         /* if a full address was output, we might have branched into Jazelle state */
 830         if ((shift == 32) && (packet & 0x80))
 831         {
 832                 ctx->core_state = ARM_STATE_JAZELLE;
 833         }
 834         else
 835         {
 836                 /* if we didn't branch into Jazelle state, the current processor state is
 837                  * encoded in bit 0 of the branch target address */
 838                 if (ctx->last_branch & 0x1)
 839                 {
 840                         ctx->core_state = ARM_STATE_THUMB;
 841                         ctx->last_branch &= ~0x1;
 842                 }
 843                 else
 844                 {
 845                         ctx->core_state = ARM_STATE_ARM;
 846                         ctx->last_branch &= ~0x3;
 847                 }
 848         }
 849
 850         return 0;
 851 }
 852
 853 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
 854 {
 855         int j;
 856         uint8_t buf[4];
 857         int retval;
 858
 859         for (j = 0; j < size; j++)
 860         {
 861                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 862                         return -1;
 863         }
 864
 865         if (size == 8)
 866         {
 867                 LOG_ERROR("TODO: add support for 64-bit values");
 868                 return -1;
 869         }
 870         else if (size == 4)
 871                 *data = target_buffer_get_u32(ctx->target, buf);
 872         else if (size == 2)
 873                 *data = target_buffer_get_u16(ctx->target, buf);
 874         else if (size == 1)
 875                 *data = buf[0];
 876         else
 877                 return -1;
 878
 879         return 0;
 880 }
 881
 882 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
 883 {
 884         int retval;
 885         struct arm_instruction instruction;
 886
 887         /* read the trace data if it wasn't read already */
 888         if (ctx->trace_depth == 0)
 889                 ctx->capture_driver->read_trace(ctx);
 890
 891         /* start at the beginning of the captured trace */
 892         ctx->pipe_index = 0;
 893         ctx->data_index = 0;
 894         ctx->data_half = 0;
 895
 896         /* neither the PC nor the data pointer are valid */
 897         ctx->pc_ok = 0;
 898         ctx->ptr_ok = 0;
 899
 900         while (ctx->pipe_index < ctx->trace_depth)
 901         {
 902                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 903                 uint32_t next_pc = ctx->current_pc;
 904                 uint32_t old_data_index = ctx->data_index;
 905                 uint32_t old_data_half = ctx->data_half;
 906                 uint32_t old_index = ctx->pipe_index;
 907                 uint32_t last_instruction = ctx->last_instruction;
 908                 uint32_t cycles = 0;
 909                 int current_pc_ok = ctx->pc_ok;
 910
 911                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 912                 {
 913                         command_print(cmd_ctx, "--- trigger ---");
 914                 }
 915
 916                 /* instructions execute in IE/D or BE/D cycles */
 917                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 918                         ctx->last_instruction = ctx->pipe_index;
 919
 920                 /* if we don't have a valid pc skip until we reach an indirect branch */
 921                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 922                 {
 923                         ctx->pipe_index++;
 924                         continue;
 925                 }
 926
 927                 /* any indirect branch could have interrupted instruction flow
 928                  * - the branch reason code could indicate a trace discontinuity
 929                  * - a branch to the exception vectors indicates an exception
 930                  */
 931                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 932                 {
 933                         /* backup current data index, to be able to consume the branch address
 934                          * before examining data address and values
 935                          */
 936                         old_data_index = ctx->data_index;
 937                         old_data_half = ctx->data_half;
 938
 939                         ctx->last_instruction = ctx->pipe_index;
 940
 941                         if ((retval = etmv1_branch_address(ctx)) != 0)
 942                         {
 943                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 944                                  * quit analysing the trace */
 945                                 if (retval < 0)
 946                                         break;
 947
 948                                 /* a positive return values means the current branch was abandoned,
 949                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 950                                  */
 951                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 952                                 ctx->pipe_index += retval;
 953                                 continue;
 954                         }
 955
 956                         /* skip over APO cycles */
 957                         ctx->pipe_index += 2;
 958
 959                         switch (ctx->last_branch_reason)
 960                         {
 961                                 case 0x0:       /* normal PC change */
 962                                         next_pc = ctx->last_branch;
 963                                         break;
 964                                 case 0x1:       /* tracing enabled */
 965                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 966                                         ctx->current_pc = ctx->last_branch;
 967                                         ctx->pipe_index++;
 968                                         continue;
 969                                         break;
 970                                 case 0x2:       /* trace restarted after FIFO overflow */
 971                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 972                                         ctx->current_pc = ctx->last_branch;
 973                                         ctx->pipe_index++;
 974                                         continue;
 975                                         break;
 976                                 case 0x3:       /* exit from debug state */
 977                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 978                                         ctx->current_pc = ctx->last_branch;
 979                                         ctx->pipe_index++;
 980                                         continue;
 981                                         break;
 982                                 case 0x4:       /* periodic synchronization point */
 983                                         next_pc = ctx->last_branch;
 984                                         /* if we had no valid PC prior to this synchronization point,
 985                                          * we have to move on with the next trace cycle
 986                                          */
 987                                         if (!current_pc_ok)
 988                                         {
 989                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 990                                                 ctx->current_pc = next_pc;
 991                                                 ctx->pipe_index++;
 992                                                 continue;
 993                                         }
 994                                         break;
 995                                 default:        /* reserved */
 996                                         LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
 997                                         return ERROR_FAIL;
 998                         }
 999
1000                         /* if we got here the branch was a normal PC change
1001                          * (or a periodic synchronization point, which means the same for that matter)
1002                          * if we didn't accquire a complete PC continue with the next cycle
1003                          */
1004                         if (!ctx->pc_ok)
1005                                 continue;
1006
1007                         /* indirect branch to the exception vector means an exception occured */
1008                         if ((ctx->last_branch <= 0x20)
1009                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1010                         {
1011                                 if ((ctx->last_branch & 0xff) == 0x10)
1012                                 {
1013                                         command_print(cmd_ctx, "data abort");
1014                                 }
1015                                 else
1016                                 {
1017                                         command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1018                                         ctx->current_pc = ctx->last_branch;
1019                                         ctx->pipe_index++;
1020                                         continue;
1021                                 }
1022                         }
1023                 }
1024
1025                 /* an instruction was executed (or not, depending on the condition flags)
1026                  * retrieve it from the image for displaying */
1027                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1028                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1029                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1030                 {
1031                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1032                         {
1033                                 /* can't continue tracing with no image available */
1034                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1035                                 {
1036                                         return retval;
1037                                 }
1038                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1039                                 {
1040                                         /* TODO: handle incomplete images
1041                                          * for now we just quit the analsysis*/
1042                                         return retval;
1043                                 }
1044                         }
1045
1046                         cycles = old_index - last_instruction;
1047                 }
1048
1049                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1050                 {
1051                         uint32_t new_data_index = ctx->data_index;
1052                         uint32_t new_data_half = ctx->data_half;
1053
1054                         /* in case of a branch with data, the branch target address was consumed before
1055                          * we temporarily go back to the saved data index */
1056                         if (pipestat == STAT_BD)
1057                         {
1058                                 ctx->data_index = old_data_index;
1059                                 ctx->data_half = old_data_half;
1060                         }
1061
1062                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
1063                         {
1064                                 uint8_t packet;
1065                                 int shift = 0;
1066
1067                                 do {
1068                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1069                                                 return ERROR_ETM_ANALYSIS_FAILED;
1070                                         ctx->last_ptr &= ~(0x7f << shift);
1071                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1072                                         shift += 7;
1073                                 } while ((packet & 0x80) && (shift < 32));
1074
1075                                 if (shift >= 32)
1076                                         ctx->ptr_ok = 1;
1077
1078                                 if (ctx->ptr_ok)
1079                                 {
1080                                         command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1081                                 }
1082                         }
1083
1084                         if (ctx->tracemode & ETMV1_TRACE_DATA)
1085                         {
1086                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1087                                 {
1088                                         int i;
1089                                         for (i = 0; i < 16; i++)
1090                                         {
1091                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
1092                                                 {
1093                                                         uint32_t data;
1094                                                         if (etmv1_data(ctx, 4, &data) != 0)
1095                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1096                                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1097                                                 }
1098                                         }
1099                                 }
1100                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1101                                 {
1102                                         uint32_t data;
1103                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1104                                                 return ERROR_ETM_ANALYSIS_FAILED;
1105                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1106                                 }
1107                         }
1108
1109                         /* restore data index after consuming BD address and data */
1110                         if (pipestat == STAT_BD)
1111                         {
1112                                 ctx->data_index = new_data_index;
1113                                 ctx->data_half = new_data_half;
1114                         }
1115                 }
1116
1117                 /* adjust PC */
1118                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1119                 {
1120                         if (((instruction.type == ARM_B) ||
1121                              (instruction.type == ARM_BL) ||
1122                              (instruction.type == ARM_BLX)) &&
1123                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1124                         {
1125                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1126                         }
1127                         else
1128                         {
1129                                 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1130                         }
1131                 }
1132                 else if (pipestat == STAT_IN)
1133                 {
1134                         next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1135                 }
1136
1137                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1138                 {
1139                         char cycles_text[32] = "";
1140
1141                         /* if the trace was captured with cycle accurate tracing enabled,
1142                          * output the number of cycles since the last executed instruction
1143                          */
1144                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1145                         {
1146                                 snprintf(cycles_text, 32, " (%i %s)",
1147                                          (int)cycles,
1148                                         (cycles == 1) ? "cycle" : "cycles");
1149                         }
1150
1151                         command_print(cmd_ctx, "%s%s%s",
1152                                 instruction.text,
1153                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1154                                 cycles_text);
1155
1156                         ctx->current_pc = next_pc;
1157
1158                         /* packets for an instruction don't start on or before the preceding
1159                          * functional pipestat (i.e. other than WT or TD)
1160                          */
1161                         if (ctx->data_index <= ctx->pipe_index)
1162                         {
1163                                 ctx->data_index = ctx->pipe_index + 1;
1164                                 ctx->data_half = 0;
1165                         }
1166                 }
1167
1168                 ctx->pipe_index += 1;
1169         }
1170
1171         return ERROR_OK;
1172 }
1173
1174 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1175                 uint32_t *mode)
1176 {
1177         uint32_t tracemode;
1178
1179         /* what parts of data access are traced? */
1180         if (strcmp(CMD_ARGV[0], "none") == 0)
1181                 tracemode = ETMV1_TRACE_NONE;
1182         else if (strcmp(CMD_ARGV[0], "data") == 0)
1183                 tracemode = ETMV1_TRACE_DATA;
1184         else if (strcmp(CMD_ARGV[0], "address") == 0)
1185                 tracemode = ETMV1_TRACE_ADDR;
1186         else if (strcmp(CMD_ARGV[0], "all") == 0)
1187                 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1188         else
1189         {
1190                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1191                 return ERROR_INVALID_ARGUMENTS;
1192         }
1193
1194         uint8_t context_id;
1195         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1196         switch (context_id)
1197         {
1198         case 0:
1199                 tracemode |= ETMV1_CONTEXTID_NONE;
1200                 break;
1201         case 8:
1202                 tracemode |= ETMV1_CONTEXTID_8;
1203                 break;
1204         case 16:
1205                 tracemode |= ETMV1_CONTEXTID_16;
1206                 break;
1207         case 32:
1208                 tracemode |= ETMV1_CONTEXTID_32;
1209                 break;
1210         default:
1211                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1212                 return ERROR_INVALID_ARGUMENTS;
1213         }
1214
1215         bool etmv1_cycle_accurate;
1216         COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1217         if (etmv1_cycle_accurate)
1218                 tracemode |= ETMV1_CYCLE_ACCURATE;
1219
1220         bool etmv1_branch_output;
1221         COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1222         if (etmv1_branch_output)
1223                 tracemode |= ETMV1_BRANCH_OUTPUT;
1224
1225         /* IGNORED:
1226          *  - CPRT tracing (coprocessor register transfers)
1227          *  - debug request (causes debug entry on trigger)
1228          *  - stall on FIFOFULL (preventing tracedata lossage)
1229          */
1230         *mode = tracemode;
1231
1232         return ERROR_OK;
1233 }
1234
1235 COMMAND_HANDLER(handle_etm_tracemode_command)
1236 {
1237         struct target *target = get_current_target(CMD_CTX);
1238         struct arm *arm = target_to_arm(target);
1239         struct etm_context *etm;
1240
1241         if (!is_arm(arm)) {
1242                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1243                 return ERROR_FAIL;
1244         }
1245
1246         etm = arm->etm;
1247         if (!etm) {
1248                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1249                 return ERROR_FAIL;
1250         }
1251
1252         uint32_t tracemode = etm->tracemode;
1253
1254         switch (CMD_ARGC)
1255         {
1256         case 0:
1257                 break;
1258         case 4:
1259                 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode);
1260                 break;
1261         default:
1262                 command_print(CMD_CTX, "usage: configure trace mode "
1263                                 "<none | data | address | all> "
1264                                 "<context id bits> <cycle accurate> <branch output>");
1265                 return ERROR_FAIL;
1266         }
1267
1268         /**
1269          * todo: fail if parameters were invalid for this hardware,
1270          * or couldn't be written; display actual hardware state...
1271          */
1272
1273         command_print(CMD_CTX, "current tracemode configuration:");
1274
1275         switch (tracemode & ETMV1_TRACE_MASK)
1276         {
1277                 case ETMV1_TRACE_NONE:
1278                         command_print(CMD_CTX, "data tracing: none");
1279                         break;
1280                 case ETMV1_TRACE_DATA:
1281                         command_print(CMD_CTX, "data tracing: data only");
1282                         break;
1283                 case ETMV1_TRACE_ADDR:
1284                         command_print(CMD_CTX, "data tracing: address only");
1285                         break;
1286                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1287                         command_print(CMD_CTX, "data tracing: address and data");
1288                         break;
1289         }
1290
1291         switch (tracemode & ETMV1_CONTEXTID_MASK)
1292         {
1293                 case ETMV1_CONTEXTID_NONE:
1294                         command_print(CMD_CTX, "contextid tracing: none");
1295                         break;
1296                 case ETMV1_CONTEXTID_8:
1297                         command_print(CMD_CTX, "contextid tracing: 8 bit");
1298                         break;
1299                 case ETMV1_CONTEXTID_16:
1300                         command_print(CMD_CTX, "contextid tracing: 16 bit");
1301                         break;
1302                 case ETMV1_CONTEXTID_32:
1303                         command_print(CMD_CTX, "contextid tracing: 32 bit");
1304                         break;
1305         }
1306
1307         if (tracemode & ETMV1_CYCLE_ACCURATE)
1308         {
1309                 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1310         }
1311         else
1312         {
1313                 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1314         }
1315
1316         if (tracemode & ETMV1_BRANCH_OUTPUT)
1317         {
1318                 command_print(CMD_CTX, "full branch address output enabled");
1319         }
1320         else
1321         {
1322                 command_print(CMD_CTX, "full branch address output disabled");
1323         }
1324
1325         /* only update ETM_CTRL register if tracemode changed */
1326         if (etm->tracemode != tracemode)
1327         {
1328                 struct reg *etm_ctrl_reg;
1329
1330                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1331                 if (!etm_ctrl_reg)
1332                         return ERROR_FAIL;
1333
1334                 etm_get_reg(etm_ctrl_reg);
1335
1336                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1337                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1338                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1339                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1340                 etm_store_reg(etm_ctrl_reg);
1341
1342                 etm->tracemode = tracemode;
1343
1344                 /* invalidate old trace data */
1345                 etm->capture_status = TRACE_IDLE;
1346                 if (etm->trace_depth > 0)
1347                 {
1348                         free(etm->trace_data);
1349                         etm->trace_data = NULL;
1350                 }
1351                 etm->trace_depth = 0;
1352         }
1353
1354         return ERROR_OK;
1355 }
1356
1357 COMMAND_HANDLER(handle_etm_config_command)
1358 {
1359         struct target *target;
1360         struct arm *arm;
1361         uint32_t portmode = 0x0;
1362         struct etm_context *etm_ctx;
1363         int i;
1364
1365         if (CMD_ARGC != 5)
1366                 return ERROR_COMMAND_SYNTAX_ERROR;
1367
1368         target = get_target(CMD_ARGV[0]);
1369         if (!target)
1370         {
1371                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1372                 return ERROR_FAIL;
1373         }
1374
1375         arm = target_to_arm(target);
1376         if (!is_arm(arm)) {
1377                 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1378                                 target_name(target),
1379                                 target_type_name(target));
1380                 return ERROR_FAIL;
1381         }
1382
1383         /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1384          * version we'll be using!! -- so we can't know how to validate
1385          * params yet.  "etm config" should likely be *AFTER* hookup...
1386          *
1387          *  - Many more widths might be supported ... and we can easily
1388          *    check whether our setting "took".
1389          *
1390          *  - The "clock" and "mode" bits are interpreted differently.
1391          *    See ARM IHI 0014O table 2-17 for the old behavior, and
1392          *    table 2-18 for the new.  With ETB it's best to specify
1393          *    "normal full" ...
1394          */
1395         uint8_t port_width;
1396         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1397         switch (port_width)
1398         {
1399                 /* before ETMv3.0 */
1400                 case 4:
1401                         portmode |= ETM_PORT_4BIT;
1402                         break;
1403                 case 8:
1404                         portmode |= ETM_PORT_8BIT;
1405                         break;
1406                 case 16:
1407                         portmode |= ETM_PORT_16BIT;
1408                         break;
1409                 /* ETMv3.0 and later*/
1410                 case 24:
1411                         portmode |= ETM_PORT_24BIT;
1412                         break;
1413                 case 32:
1414                         portmode |= ETM_PORT_32BIT;
1415                         break;
1416                 case 48:
1417                         portmode |= ETM_PORT_48BIT;
1418                         break;
1419                 case 64:
1420                         portmode |= ETM_PORT_64BIT;
1421                         break;
1422                 case 1:
1423                         portmode |= ETM_PORT_1BIT;
1424                         break;
1425                 case 2:
1426                         portmode |= ETM_PORT_2BIT;
1427                         break;
1428                 default:
1429                         command_print(CMD_CTX,
1430                                 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1431                         return ERROR_FAIL;
1432         }
1433
1434         if (strcmp("normal", CMD_ARGV[2]) == 0)
1435         {
1436                 portmode |= ETM_PORT_NORMAL;
1437         }
1438         else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1439         {
1440                 portmode |= ETM_PORT_MUXED;
1441         }
1442         else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1443         {
1444                 portmode |= ETM_PORT_DEMUXED;
1445         }
1446         else
1447         {
1448                 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1449                 return ERROR_FAIL;
1450         }
1451
1452         if (strcmp("half", CMD_ARGV[3]) == 0)
1453         {
1454                 portmode |= ETM_PORT_HALF_CLOCK;
1455         }
1456         else if (strcmp("full", CMD_ARGV[3]) == 0)
1457         {
1458                 portmode |= ETM_PORT_FULL_CLOCK;
1459         }
1460         else
1461         {
1462                 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1463                 return ERROR_FAIL;
1464         }
1465
1466         etm_ctx = calloc(1, sizeof(struct etm_context));
1467         if (!etm_ctx) {
1468                 LOG_DEBUG("out of memory");
1469                 return ERROR_FAIL;
1470         }
1471
1472         for (i = 0; etm_capture_drivers[i]; i++)
1473         {
1474                 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1475                 {
1476                         int retval = register_commands(CMD_CTX, NULL,
1477                                         etm_capture_drivers[i]->commands);
1478                         if (ERROR_OK != retval)
1479                         {
1480                                 free(etm_ctx);
1481                                 return retval;
1482                         }
1483
1484                         etm_ctx->capture_driver = etm_capture_drivers[i];
1485
1486                         break;
1487                 }
1488         }
1489
1490         if (!etm_capture_drivers[i])
1491         {
1492                 /* no supported capture driver found, don't register an ETM */
1493                 free(etm_ctx);
1494                 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1495                 return ERROR_FAIL;
1496         }
1497
1498         etm_ctx->target = target;
1499         etm_ctx->trace_data = NULL;
1500         etm_ctx->control = portmode;
1501         etm_ctx->core_state = ARM_STATE_ARM;
1502
1503         arm->etm = etm_ctx;
1504
1505         return etm_register_user_commands(CMD_CTX);
1506 }
1507
1508 COMMAND_HANDLER(handle_etm_info_command)
1509 {
1510         struct target *target;
1511         struct arm *arm;
1512         struct etm_context *etm;
1513         struct reg *etm_sys_config_reg;
1514         int max_port_size;
1515         uint32_t config;
1516
1517         target = get_current_target(CMD_CTX);
1518         arm = target_to_arm(target);
1519         if (!is_arm(arm))
1520         {
1521                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1522                 return ERROR_FAIL;
1523         }
1524
1525         etm = arm->etm;
1526         if (!etm)
1527         {
1528                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1529                 return ERROR_FAIL;
1530         }
1531
1532         command_print(CMD_CTX, "ETM v%d.%d",
1533                         etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1534         command_print(CMD_CTX, "pairs of address comparators: %i",
1535                         (int) (etm->config >> 0) & 0x0f);
1536         command_print(CMD_CTX, "data comparators: %i",
1537                         (int) (etm->config >> 4) & 0x0f);
1538         command_print(CMD_CTX, "memory map decoders: %i",
1539                         (int) (etm->config >> 8) & 0x1f);
1540         command_print(CMD_CTX, "number of counters: %i",
1541                         (int) (etm->config >> 13) & 0x07);
1542         command_print(CMD_CTX, "sequencer %spresent",
1543                         (int) (etm->config & (1 << 16)) ? "" : "not ");
1544         command_print(CMD_CTX, "number of ext. inputs: %i",
1545                         (int) (etm->config >> 17) & 0x07);
1546         command_print(CMD_CTX, "number of ext. outputs: %i",
1547                         (int) (etm->config >> 20) & 0x07);
1548         command_print(CMD_CTX, "FIFO full %spresent",
1549                         (int) (etm->config & (1 << 23)) ? "" : "not ");
1550         if (etm->bcd_vers < 0x20)
1551                 command_print(CMD_CTX, "protocol version: %i",
1552                                 (int) (etm->config >> 28) & 0x07);
1553         else {
1554                 command_print(CMD_CTX,
1555                                 "coprocessor and memory access %ssupported",
1556                                 (etm->config & (1 << 26)) ? "" : "not ");
1557                 command_print(CMD_CTX, "trace start/stop %spresent",
1558                                 (etm->config & (1 << 26)) ? "" : "not ");
1559                 command_print(CMD_CTX, "number of context comparators: %i",
1560                                 (int) (etm->config >> 24) & 0x03);
1561         }
1562
1563         /* SYS_CONFIG isn't present before ETMv1.2 */
1564         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1565         if (!etm_sys_config_reg)
1566                 return ERROR_OK;
1567
1568         etm_get_reg(etm_sys_config_reg);
1569         config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1570
1571         LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1572
1573         max_port_size = config & 0x7;
1574         if (etm->bcd_vers >= 0x30)
1575                 max_port_size |= (config >> 6) & 0x08;
1576         switch (max_port_size)
1577         {
1578                 /* before ETMv3.0 */
1579                 case 0:
1580                         max_port_size = 4;
1581                         break;
1582                 case 1:
1583                         max_port_size = 8;
1584                         break;
1585                 case 2:
1586                         max_port_size = 16;
1587                         break;
1588                 /* ETMv3.0 and later*/
1589                 case 3:
1590                         max_port_size = 24;
1591                         break;
1592                 case 4:
1593                         max_port_size = 32;
1594                         break;
1595                 case 5:
1596                         max_port_size = 48;
1597                         break;
1598                 case 6:
1599                         max_port_size = 64;
1600                         break;
1601                 case 8:
1602                         max_port_size = 1;
1603                         break;
1604                 case 9:
1605                         max_port_size = 2;
1606                         break;
1607                 default:
1608                         LOG_ERROR("Illegal max_port_size");
1609                         return ERROR_FAIL;
1610         }
1611         command_print(CMD_CTX, "max. port size: %i", max_port_size);
1612
1613         if (etm->bcd_vers < 0x30) {
1614                 command_print(CMD_CTX, "half-rate clocking %ssupported",
1615                                 (config & (1 << 3)) ? "" : "not ");
1616                 command_print(CMD_CTX, "full-rate clocking %ssupported",
1617                                 (config & (1 << 4)) ? "" : "not ");
1618                 command_print(CMD_CTX, "normal trace format %ssupported",
1619                                 (config & (1 << 5)) ? "" : "not ");
1620                 command_print(CMD_CTX, "multiplex trace format %ssupported",
1621                                 (config & (1 << 6)) ? "" : "not ");
1622                 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1623                                 (config & (1 << 7)) ? "" : "not ");
1624         } else {
1625                 /* REVISIT show which size and format are selected ... */
1626                 command_print(CMD_CTX, "current port size %ssupported",
1627                                 (config & (1 << 10)) ? "" : "not ");
1628                 command_print(CMD_CTX, "current trace format %ssupported",
1629                                 (config & (1 << 11)) ? "" : "not ");
1630         }
1631         if (etm->bcd_vers >= 0x21)
1632                 command_print(CMD_CTX, "fetch comparisons %ssupported",
1633                                 (config & (1 << 17)) ? "not " : "");
1634         command_print(CMD_CTX, "FIFO full %ssupported",
1635                         (config & (1 << 8)) ? "" : "not ");
1636
1637         return ERROR_OK;
1638 }
1639
1640 COMMAND_HANDLER(handle_etm_status_command)
1641 {
1642         struct target *target;
1643         struct arm *arm;
1644         struct etm_context *etm;
1645         trace_status_t trace_status;
1646
1647         target = get_current_target(CMD_CTX);
1648         arm = target_to_arm(target);
1649         if (!is_arm(arm))
1650         {
1651                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1652                 return ERROR_FAIL;
1653         }
1654
1655         etm = arm->etm;
1656         if (!etm)
1657         {
1658                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1659                 return ERROR_FAIL;
1660         }
1661
1662         /* ETM status */
1663         if (etm->bcd_vers >= 0x11) {
1664                 struct reg *reg;
1665
1666                 reg = etm_reg_lookup(etm, ETM_STATUS);
1667                 if (!reg)
1668                         return ERROR_FAIL;
1669                 if (etm_get_reg(reg) == ERROR_OK) {
1670                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1671
1672                         command_print(CMD_CTX, "etm: %s%s%s%s",
1673                                 /* bit(1) == progbit */
1674                                 (etm->bcd_vers >= 0x12)
1675                                         ? ((s & (1 << 1))
1676                                                 ? "disabled" : "enabled")
1677                                         : "?",
1678                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1679                                         ? " triggered" : "",
1680                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1681                                         ? " start/stop" : "",
1682                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1683                                         ? " untraced-overflow" : "");
1684                 } /* else ignore and try showing trace port status */
1685         }
1686
1687         /* Trace Port Driver status */
1688         trace_status = etm->capture_driver->status(etm);
1689         if (trace_status == TRACE_IDLE)
1690         {
1691                 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1692         }
1693         else
1694         {
1695                 static char *completed = " completed";
1696                 static char *running = " is running";
1697                 static char *overflowed = ", overflowed";
1698                 static char *triggered = ", triggered";
1699
1700                 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1701                         etm->capture_driver->name,
1702                         (trace_status & TRACE_RUNNING) ? running : completed,
1703                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1704                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1705
1706                 if (etm->trace_depth > 0)
1707                 {
1708                         command_print(CMD_CTX, "%i frames of trace data read",
1709                                         (int)(etm->trace_depth));
1710                 }
1711         }
1712
1713         return ERROR_OK;
1714 }
1715
1716 COMMAND_HANDLER(handle_etm_image_command)
1717 {
1718         struct target *target;
1719         struct arm *arm;
1720         struct etm_context *etm_ctx;
1721
1722         if (CMD_ARGC < 1)
1723         {
1724                 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1725                 return ERROR_FAIL;
1726         }
1727
1728         target = get_current_target(CMD_CTX);
1729         arm = target_to_arm(target);
1730         if (!is_arm(arm))
1731         {
1732                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1733                 return ERROR_FAIL;
1734         }
1735
1736         etm_ctx = arm->etm;
1737         if (!etm_ctx)
1738         {
1739                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1740                 return ERROR_FAIL;
1741         }
1742
1743         if (etm_ctx->image)
1744         {
1745                 image_close(etm_ctx->image);
1746                 free(etm_ctx->image);
1747                 command_print(CMD_CTX, "previously loaded image found and closed");
1748         }
1749
1750         etm_ctx->image = malloc(sizeof(struct image));
1751         etm_ctx->image->base_address_set = 0;
1752         etm_ctx->image->start_address_set = 0;
1753
1754         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1755         if (CMD_ARGC >= 2)
1756         {
1757                 etm_ctx->image->base_address_set = 1;
1758                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], etm_ctx->image->base_address);
1759         }
1760         else
1761         {
1762                 etm_ctx->image->base_address_set = 0;
1763         }
1764
1765         if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1766         {
1767                 free(etm_ctx->image);
1768                 etm_ctx->image = NULL;
1769                 return ERROR_FAIL;
1770         }
1771
1772         return ERROR_OK;
1773 }
1774
1775 COMMAND_HANDLER(handle_etm_dump_command)
1776 {
1777         struct fileio file;
1778         struct target *target;
1779         struct arm *arm;
1780         struct etm_context *etm_ctx;
1781         uint32_t i;
1782
1783         if (CMD_ARGC != 1)
1784         {
1785                 command_print(CMD_CTX, "usage: etm dump <file>");
1786                 return ERROR_FAIL;
1787         }
1788
1789         target = get_current_target(CMD_CTX);
1790         arm = target_to_arm(target);
1791         if (!is_arm(arm))
1792         {
1793                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1794                 return ERROR_FAIL;
1795         }
1796
1797         etm_ctx = arm->etm;
1798         if (!etm_ctx)
1799         {
1800                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1801                 return ERROR_FAIL;
1802         }
1803
1804         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1805         {
1806                 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1807                 return ERROR_OK;
1808         }
1809
1810         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1811         {
1812                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1813                 command_print(CMD_CTX, "trace capture not completed");
1814                 return ERROR_FAIL;
1815         }
1816
1817         /* read the trace data if it wasn't read already */
1818         if (etm_ctx->trace_depth == 0)
1819                 etm_ctx->capture_driver->read_trace(etm_ctx);
1820
1821         if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1822         {
1823                 return ERROR_FAIL;
1824         }
1825
1826         fileio_write_u32(&file, etm_ctx->capture_status);
1827         fileio_write_u32(&file, etm_ctx->control);
1828         fileio_write_u32(&file, etm_ctx->tracemode);
1829         fileio_write_u32(&file, etm_ctx->trace_depth);
1830
1831         for (i = 0; i < etm_ctx->trace_depth; i++)
1832         {
1833                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1834                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1835                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1836         }
1837
1838         fileio_close(&file);
1839
1840         return ERROR_OK;
1841 }
1842
1843 COMMAND_HANDLER(handle_etm_load_command)
1844 {
1845         struct fileio file;
1846         struct target *target;
1847         struct arm *arm;
1848         struct etm_context *etm_ctx;
1849         uint32_t i;
1850
1851         if (CMD_ARGC != 1)
1852         {
1853                 command_print(CMD_CTX, "usage: etm load <file>");
1854                 return ERROR_FAIL;
1855         }
1856
1857         target = get_current_target(CMD_CTX);
1858         arm = target_to_arm(target);
1859         if (!is_arm(arm))
1860         {
1861                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1862                 return ERROR_FAIL;
1863         }
1864
1865         etm_ctx = arm->etm;
1866         if (!etm_ctx)
1867         {
1868                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1869                 return ERROR_FAIL;
1870         }
1871
1872         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1873         {
1874                 command_print(CMD_CTX, "trace capture running, stop first");
1875                 return ERROR_FAIL;
1876         }
1877
1878         if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1879         {
1880                 return ERROR_FAIL;
1881         }
1882
1883         if (file.size % 4)
1884         {
1885                 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1886                 fileio_close(&file);
1887                 return ERROR_FAIL;
1888         }
1889
1890         if (etm_ctx->trace_depth > 0)
1891         {
1892                 free(etm_ctx->trace_data);
1893                 etm_ctx->trace_data = NULL;
1894         }
1895
1896         {
1897           uint32_t tmp;
1898           fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1899           fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1900           fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1901           fileio_read_u32(&file, &etm_ctx->trace_depth);
1902         }
1903         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1904         if (etm_ctx->trace_data == NULL)
1905         {
1906                 command_print(CMD_CTX, "not enough memory to perform operation");
1907                 fileio_close(&file);
1908                 return ERROR_FAIL;
1909         }
1910
1911         for (i = 0; i < etm_ctx->trace_depth; i++)
1912         {
1913                 uint32_t pipestat, packet, flags;
1914                 fileio_read_u32(&file, &pipestat);
1915                 fileio_read_u32(&file, &packet);
1916                 fileio_read_u32(&file, &flags);
1917                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1918                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1919                 etm_ctx->trace_data[i].flags = flags;
1920         }
1921
1922         fileio_close(&file);
1923
1924         return ERROR_OK;
1925 }
1926
1927 COMMAND_HANDLER(handle_etm_start_command)
1928 {
1929         struct target *target;
1930         struct arm *arm;
1931         struct etm_context *etm_ctx;
1932         struct reg *etm_ctrl_reg;
1933
1934         target = get_current_target(CMD_CTX);
1935         arm = target_to_arm(target);
1936         if (!is_arm(arm))
1937         {
1938                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1939                 return ERROR_FAIL;
1940         }
1941
1942         etm_ctx = arm->etm;
1943         if (!etm_ctx)
1944         {
1945                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1946                 return ERROR_FAIL;
1947         }
1948
1949         /* invalidate old tracing data */
1950         etm_ctx->capture_status = TRACE_IDLE;
1951         if (etm_ctx->trace_depth > 0)
1952         {
1953                 free(etm_ctx->trace_data);
1954                 etm_ctx->trace_data = NULL;
1955         }
1956         etm_ctx->trace_depth = 0;
1957
1958         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1959         if (!etm_ctrl_reg)
1960                 return ERROR_FAIL;
1961
1962         etm_get_reg(etm_ctrl_reg);
1963
1964         /* Clear programming bit (10), set port selection bit (11) */
1965         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1966
1967         etm_store_reg(etm_ctrl_reg);
1968         jtag_execute_queue();
1969
1970         etm_ctx->capture_driver->start_capture(etm_ctx);
1971
1972         return ERROR_OK;
1973 }
1974
1975 COMMAND_HANDLER(handle_etm_stop_command)
1976 {
1977         struct target *target;
1978         struct arm *arm;
1979         struct etm_context *etm_ctx;
1980         struct reg *etm_ctrl_reg;
1981
1982         target = get_current_target(CMD_CTX);
1983         arm = target_to_arm(target);
1984         if (!is_arm(arm))
1985         {
1986                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1987                 return ERROR_FAIL;
1988         }
1989
1990         etm_ctx = arm->etm;
1991         if (!etm_ctx)
1992         {
1993                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1994                 return ERROR_FAIL;
1995         }
1996
1997         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1998         if (!etm_ctrl_reg)
1999                 return ERROR_FAIL;
2000
2001         etm_get_reg(etm_ctrl_reg);
2002
2003         /* Set programming bit (10), clear port selection bit (11) */
2004         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2005
2006         etm_store_reg(etm_ctrl_reg);
2007         jtag_execute_queue();
2008
2009         etm_ctx->capture_driver->stop_capture(etm_ctx);
2010
2011         return ERROR_OK;
2012 }
2013
2014 COMMAND_HANDLER(handle_etm_analyze_command)
2015 {
2016         struct target *target;
2017         struct arm *arm;
2018         struct etm_context *etm_ctx;
2019         int retval;
2020
2021         target = get_current_target(CMD_CTX);
2022         arm = target_to_arm(target);
2023         if (!is_arm(arm))
2024         {
2025                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2026                 return ERROR_FAIL;
2027         }
2028
2029         etm_ctx = arm->etm;
2030         if (!etm_ctx)
2031         {
2032                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2033                 return ERROR_FAIL;
2034         }
2035
2036         if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2037         {
2038                 switch (retval)
2039                 {
2040                         case ERROR_ETM_ANALYSIS_FAILED:
2041                                 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2042                                 break;
2043                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2044                                 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2045                                 break;
2046                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
2047                                 command_print(CMD_CTX, "no image available for trace analysis");
2048                                 break;
2049                         default:
2050                                 command_print(CMD_CTX, "unknown error: %i", retval);
2051                 }
2052         }
2053
2054         return retval;
2055 }
2056
2057 static const struct command_registration etm_config_command_handlers[] = {
2058         {
2059                 .name = "config",
2060                 .handler = &handle_etm_config_command,
2061                 .mode = COMMAND_CONFIG,
2062                 .usage = "<target> <port_width> <port_mode> "
2063                         "<clocking> <capture_driver>",
2064         },
2065         COMMAND_REGISTRATION_DONE
2066 };
2067 const struct command_registration etm_command_handlers[] = {
2068         {
2069                 .name = "etm",
2070                 .mode = COMMAND_ANY,
2071                 .help = "Emebdded Trace Macrocell command group",
2072                 .chain = etm_config_command_handlers,
2073         },
2074         COMMAND_REGISTRATION_DONE
2075 };
2076
2077 static const struct command_registration etm_exec_command_handlers[] = {
2078         {
2079                 .name = "tracemode", handle_etm_tracemode_command,
2080                 .mode = COMMAND_EXEC,
2081                 .help = "configure/display trace mode",
2082                 .usage = "<none | data | address | all> "
2083                         "<context_id_bits> <cycle_accurate> <branch_output>",
2084         },
2085         {
2086                 .name = "info",
2087                 .handler = &handle_etm_info_command,
2088                 .mode = COMMAND_EXEC,
2089                 .help = "display info about the current target's ETM",
2090         },
2091         {
2092                 .name = "status",
2093                 .handler = &handle_etm_status_command,
2094                 .mode = COMMAND_EXEC,
2095                 .help = "display current target's ETM status",
2096         },
2097         {
2098                 .name = "start",
2099                 .handler = &handle_etm_start_command,
2100                 .mode = COMMAND_EXEC,
2101                 .help = "start ETM trace collection",
2102         },
2103         {
2104                 .name = "stop",
2105                 .handler = &handle_etm_stop_command,
2106                 .mode = COMMAND_EXEC,
2107                 .help = "stop ETM trace collection",
2108         },
2109         {
2110                 .name = "analyze",
2111                 .handler = &handle_etm_analyze_command,
2112                 .mode = COMMAND_EXEC,
2113                 .help = "anaylze collected ETM trace",
2114         },
2115         {
2116                 .name = "image",
2117                 .handler = &handle_etm_image_command,
2118                 .mode = COMMAND_EXEC,
2119                 .help = "load image from <file> [base address]",
2120         },
2121         {
2122                 .name = "dump",
2123                 .handler = &handle_etm_dump_command,
2124                 .mode = COMMAND_EXEC,
2125                 .help = "dump captured trace data <file>",
2126         },
2127         {
2128                 .name = "load",
2129                 .handler = &handle_etm_load_command,
2130                 .mode = COMMAND_EXEC,
2131                 .help = "load trace data for analysis <file>",
2132         },
2133         COMMAND_REGISTRATION_DONE
2134 };
2135
2136 static int etm_register_user_commands(struct command_context *cmd_ctx)
2137 {
2138         struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2139         return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2140 }