git.gag.com Git - fw/openocd/blob - src/target/etm.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "armv4_5.h"
  25 #include "etb.h"
  26 #include "image.h"
  27 #include "arm_disassembler.h"
  28 #include "register.h"
  29
  30
  31 /*
  32  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  33  *
  34  * ETM modules collect instruction and/or data trace information, compress
  35  * it, and transfer it to a debugging host through either a (buffered) trace
  36  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  37  *
  38  * There are several generations of these modules.  Original versions have
  39  * JTAG access through a dedicated scan chain.  Recent versions have added
  40  * access via coprocessor instructions, memory addressing, and the ARM Debug
  41  * Interface v5 (ADIv5); and phased out direct JTAG access.
  42  *
  43  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  44  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  45  * implying non-JTAG connectivity options.
  46  *
  47  * Relevant documentation includes:
  48  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  49  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  50  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  51  */
  52
  53 enum {
  54         RO,                             /* read/only */
  55         WO,                             /* write/only */
  56         RW,                             /* read/write */
  57 };
  58
  59 struct etm_reg_info {
  60         uint8_t         addr;
  61         uint8_t         size;           /* low-N of 32 bits */
  62         uint8_t         mode;           /* RO, WO, RW */
  63         uint8_t         bcd_vers;       /* 1.0, 2.0, etc */
  64         char            *name;
  65 };
  66
  67 /*
  68  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  69  * (Or on some processors, through coprocessor operations.)
  70  * Newer versions of ETM make some W/O registers R/W, and
  71  * provide definitions for some previously-unused bits.
  72  */
  73
  74 /* core registers used to version/configure the ETM */
  75 static const struct etm_reg_info etm_core[] = {
  76         /* NOTE: we "know" the order here ... */
  77         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  78         { ETM_ID, 32, RO, 0x20, "ETM_id", },
  79 };
  80
  81 /* basic registers that are always there given the right ETM version */
  82 static const struct etm_reg_info etm_basic[] = {
  83         /* ETM Trace Registers */
  84         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  85         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  86         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
  87         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
  88         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
  89
  90         /* TraceEnable configuration */
  91         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  92         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  93         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
  94         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
  95
  96         /* ViewData configuration (data trace) */
  97         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
  98         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
  99         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
 100         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
 101
 102         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 103
 104         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
 105         { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
 106         { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
 107         { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
 108         { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
 109 };
 110
 111 static const struct etm_reg_info etm_fifofull[] = {
 112         /* FIFOFULL configuration */
 113         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
 114         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
 115 };
 116
 117 static const struct etm_reg_info etm_addr_comp[] = {
 118         /* Address comparator register pairs */
 119 #define ADDR_COMPARATOR(i) \
 120                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
 121                                 "ETM_addr_" #i "_comparator_value", }, \
 122                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
 123                                 "ETM_addr_" #i "_access_type", }
 124         ADDR_COMPARATOR(1),
 125         ADDR_COMPARATOR(2),
 126         ADDR_COMPARATOR(3),
 127         ADDR_COMPARATOR(4),
 128         ADDR_COMPARATOR(5),
 129         ADDR_COMPARATOR(6),
 130         ADDR_COMPARATOR(7),
 131         ADDR_COMPARATOR(8),
 132
 133         ADDR_COMPARATOR(9),
 134         ADDR_COMPARATOR(10),
 135         ADDR_COMPARATOR(11),
 136         ADDR_COMPARATOR(12),
 137         ADDR_COMPARATOR(13),
 138         ADDR_COMPARATOR(14),
 139         ADDR_COMPARATOR(15),
 140         ADDR_COMPARATOR(16),
 141 #undef ADDR_COMPARATOR
 142 };
 143
 144 static const struct etm_reg_info etm_data_comp[] = {
 145         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 146 #define DATA_COMPARATOR(i) \
 147                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
 148                                 "ETM_data_" #i "_comparator_value", }, \
 149                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
 150                                 "ETM_data_" #i "_comparator_mask", }
 151         DATA_COMPARATOR(1),
 152         DATA_COMPARATOR(2),
 153         DATA_COMPARATOR(3),
 154         DATA_COMPARATOR(4),
 155         DATA_COMPARATOR(5),
 156         DATA_COMPARATOR(6),
 157         DATA_COMPARATOR(7),
 158         DATA_COMPARATOR(8),
 159 #undef DATA_COMPARATOR
 160 };
 161
 162 static const struct etm_reg_info etm_counters[] = {
 163 #define ETM_COUNTER(i) \
 164                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
 165                                 "ETM_counter_" #i "_reload_value", }, \
 166                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
 167                                 "ETM_counter_" #i "_enable", }, \
 168                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
 169                                 "ETM_counter_" #i "_reload_event", }, \
 170                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
 171                                 "ETM_counter_" #i "_value", }
 172         ETM_COUNTER(1),
 173         ETM_COUNTER(2),
 174         ETM_COUNTER(3),
 175         ETM_COUNTER(4),
 176 #undef ETM_COUNTER
 177 };
 178
 179 static const struct etm_reg_info etm_sequencer[] = {
 180 #define ETM_SEQ(i) \
 181                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 182                                 "ETM_sequencer_event" #i, }
 183         ETM_SEQ(0),                             /* 1->2 */
 184         ETM_SEQ(1),                             /* 2->1 */
 185         ETM_SEQ(2),                             /* 2->3 */
 186         ETM_SEQ(3),                             /* 3->1 */
 187         ETM_SEQ(4),                             /* 3->2 */
 188         ETM_SEQ(5),                             /* 1->3 */
 189 #undef ETM_SEQ
 190         /* 0x66 reserved */
 191         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
 192 };
 193
 194 static const struct etm_reg_info etm_outputs[] = {
 195 #define ETM_OUTPUT(i) \
 196                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
 197                                 "ETM_external_output" #i, }
 198
 199         ETM_OUTPUT(1),
 200         ETM_OUTPUT(2),
 201         ETM_OUTPUT(3),
 202         ETM_OUTPUT(4),
 203 #undef ETM_OUTPUT
 204 };
 205
 206 #if 0
 207         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 208
 209         /* Context ID Comparators */
 210         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
 211         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
 212         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
 213         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
 214 #endif
 215
 216 static int etm_reg_arch_type = -1;
 217
 218 static int etm_get_reg(struct reg *reg);
 219 static int etm_read_reg_w_check(struct reg *reg,
 220                 uint8_t* check_value, uint8_t* check_mask);
 221 static int etm_register_user_commands(struct command_context *cmd_ctx);
 222 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
 223 static int etm_write_reg(struct reg *reg, uint32_t value);
 224
 225 static struct command *etm_cmd;
 226
 227
 228 /* Look up register by ID ... most ETM instances only
 229  * support a subset of the possible registers.
 230  */
 231 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
 232 {
 233         struct reg_cache *cache = etm_ctx->reg_cache;
 234         int i;
 235
 236         for (i = 0; i < cache->num_regs; i++) {
 237                 struct etm_reg *reg = cache->reg_list[i].arch_info;
 238
 239                 if (reg->reg_info->addr == id)
 240                         return &cache->reg_list[i];
 241         }
 242
 243         /* caller asking for nonexistent register is a bug! */
 244         /* REVISIT say which of the N targets was involved */
 245         LOG_ERROR("ETM: register 0x%02x not available", id);
 246         return NULL;
 247 }
 248
 249 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
 250                 struct reg_cache *cache, struct etm_reg *ereg,
 251                 const struct etm_reg_info *r, unsigned nreg)
 252 {
 253         struct reg *reg = cache->reg_list;
 254
 255         reg += cache->num_regs;
 256         ereg += cache->num_regs;
 257
 258         /* add up to "nreg" registers from "r", if supported by this
 259          * version of the ETM, to the specified cache.
 260          */
 261         for (; nreg--; r++) {
 262
 263                 /* this ETM may be too old to have some registers */
 264                 if (r->bcd_vers > bcd_vers)
 265                         continue;
 266
 267                 reg->name = r->name;
 268                 reg->size = r->size;
 269                 reg->value = &ereg->value;
 270                 reg->arch_info = ereg;
 271                 reg->arch_type = etm_reg_arch_type;
 272                 reg++;
 273                 cache->num_regs++;
 274
 275                 ereg->reg_info = r;
 276                 ereg->jtag_info = jtag_info;
 277                 ereg++;
 278         }
 279 }
 280
 281 struct reg_cache *etm_build_reg_cache(struct target *target,
 282                 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
 283 {
 284         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 285         struct reg *reg_list = NULL;
 286         struct etm_reg *arch_info = NULL;
 287         unsigned bcd_vers, config;
 288
 289         /* register a register arch-type for etm registers only once */
 290         if (etm_reg_arch_type == -1)
 291                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
 292                                 etm_set_reg_w_exec);
 293
 294         /* the actual registers are kept in two arrays */
 295         reg_list = calloc(128, sizeof(struct reg));
 296         arch_info = calloc(128, sizeof(struct etm_reg));
 297
 298         /* fill in values for the reg cache */
 299         reg_cache->name = "etm registers";
 300         reg_cache->next = NULL;
 301         reg_cache->reg_list = reg_list;
 302         reg_cache->num_regs = 0;
 303
 304         /* add ETM_CONFIG, then parse its values to see
 305          * which other registers exist in this ETM
 306          */
 307         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 308                         etm_core, 1);
 309
 310         etm_get_reg(reg_list);
 311         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 312         config = etm_ctx->config;
 313
 314         /* figure ETM version then add base registers */
 315         if (config & (1 << 31)) {
 316                 bcd_vers = 0x20;
 317                 LOG_WARNING("ETMv2+ support is incomplete");
 318
 319                 /* REVISIT more registers may exist; they may now be
 320                  * readable; more register bits have defined meanings;
 321                  * don't presume trace start/stop support is present;
 322                  * and include any context ID comparator registers.
 323                  */
 324                 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
 325                                 etm_core + 1, 1);
 326                 etm_get_reg(reg_list + 1);
 327                 etm_ctx->id = buf_get_u32(
 328                                 (void *)&arch_info[1].value, 0, 32);
 329                 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
 330                 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
 331
 332         } else {
 333                 switch (config >> 28) {
 334                 case 7:
 335                 case 5:
 336                 case 3:
 337                         bcd_vers = 0x13;
 338                         break;
 339                 case 4:
 340                 case 2:
 341                         bcd_vers = 0x12;
 342                         break;
 343                 case 1:
 344                         bcd_vers = 0x11;
 345                         break;
 346                 case 0:
 347                         bcd_vers = 0x10;
 348                         break;
 349                 default:
 350                         LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 351                         goto fail;
 352                 }
 353         }
 354         etm_ctx->bcd_vers = bcd_vers;
 355         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 356
 357         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 358                         etm_basic, ARRAY_SIZE(etm_basic));
 359
 360         /* address and data comparators; counters; outputs */
 361         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 362                         etm_addr_comp, 4 * (0x0f & (config >> 0)));
 363         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 364                         etm_data_comp, 2 * (0x0f & (config >> 4)));
 365         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 366                         etm_counters, 4 * (0x07 & (config >> 13)));
 367         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 368                         etm_outputs, (0x07 & (config >> 20)));
 369
 370         /* FIFOFULL presence is optional
 371          * REVISIT for ETMv1.2 and later, don't bother adding this
 372          * unless ETM_SYS_CONFIG says it's also *supported* ...
 373          */
 374         if (config & (1 << 23))
 375                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 376                                 etm_fifofull, ARRAY_SIZE(etm_fifofull));
 377
 378         /* sequencer is optional (for state-dependant triggering) */
 379         if (config & (1 << 16))
 380                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 381                                 etm_sequencer, ARRAY_SIZE(etm_sequencer));
 382
 383         /* REVISIT could realloc and likely save half the memory
 384          * in the two chunks we allocated...
 385          */
 386
 387         /* the ETM might have an ETB connected */
 388         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 389         {
 390                 struct etb *etb = etm_ctx->capture_driver_priv;
 391
 392                 if (!etb)
 393                 {
 394                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 395                         goto fail;
 396                 }
 397
 398                 reg_cache->next = etb_build_reg_cache(etb);
 399
 400                 etb->reg_cache = reg_cache->next;
 401         }
 402
 403         etm_ctx->reg_cache = reg_cache;
 404         return reg_cache;
 405
 406 fail:
 407         free(reg_cache);
 408         free(reg_list);
 409         free(arch_info);
 410         return NULL;
 411 }
 412
 413 static int etm_read_reg(struct reg *reg)
 414 {
 415         return etm_read_reg_w_check(reg, NULL, NULL);
 416 }
 417
 418 static int etm_store_reg(struct reg *reg)
 419 {
 420         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 421 }
 422
 423 int etm_setup(struct target *target)
 424 {
 425         int retval;
 426         uint32_t etm_ctrl_value;
 427         struct arm *arm = target_to_arm(target);
 428         struct etm_context *etm_ctx = arm->etm;
 429         struct reg *etm_ctrl_reg;
 430
 431         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 432         if (!etm_ctrl_reg)
 433                 return ERROR_OK;
 434
 435         /* initialize some ETM control register settings */
 436         etm_get_reg(etm_ctrl_reg);
 437         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
 438
 439         /* clear the ETM powerdown bit (0) */
 440         etm_ctrl_value &= ~0x1;
 441
 442         /* configure port width (21,6:4), mode (13,17:16) and
 443          * for older modules clocking (13)
 444          */
 445         etm_ctrl_value = (etm_ctrl_value
 446                         & ~ETM_PORT_WIDTH_MASK
 447                         & ~ETM_PORT_MODE_MASK
 448                         & ~ETM_PORT_CLOCK_MASK)
 449                 | etm_ctx->portmode;
 450
 451         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 452         etm_store_reg(etm_ctrl_reg);
 453
 454         if ((retval = jtag_execute_queue()) != ERROR_OK)
 455                 return retval;
 456
 457         /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
 458          * verify that those width and mode settings are OK ...
 459          */
 460
 461         if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 462         {
 463                 LOG_ERROR("ETM capture driver initialization failed");
 464                 return retval;
 465         }
 466         return ERROR_OK;
 467 }
 468
 469 static int etm_get_reg(struct reg *reg)
 470 {
 471         int retval;
 472
 473         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 474         {
 475                 LOG_ERROR("BUG: error scheduling etm register read");
 476                 return retval;
 477         }
 478
 479         if ((retval = jtag_execute_queue()) != ERROR_OK)
 480         {
 481                 LOG_ERROR("register read failed");
 482                 return retval;
 483         }
 484
 485         return ERROR_OK;
 486 }
 487
 488 static int etm_read_reg_w_check(struct reg *reg,
 489                 uint8_t* check_value, uint8_t* check_mask)
 490 {
 491         struct etm_reg *etm_reg = reg->arch_info;
 492         const struct etm_reg_info *r = etm_reg->reg_info;
 493         uint8_t reg_addr = r->addr & 0x7f;
 494         struct scan_field fields[3];
 495
 496         if (etm_reg->reg_info->mode == WO) {
 497                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 498                 return ERROR_INVALID_ARGUMENTS;
 499         }
 500
 501         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 502
 503         jtag_set_end_state(TAP_IDLE);
 504         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 505         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 506
 507         fields[0].tap = etm_reg->jtag_info->tap;
 508         fields[0].num_bits = 32;
 509         fields[0].out_value = reg->value;
 510         fields[0].in_value = NULL;
 511         fields[0].check_value = NULL;
 512         fields[0].check_mask = NULL;
 513
 514         fields[1].tap = etm_reg->jtag_info->tap;
 515         fields[1].num_bits = 7;
 516         fields[1].out_value = malloc(1);
 517         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 518         fields[1].in_value = NULL;
 519         fields[1].check_value = NULL;
 520         fields[1].check_mask = NULL;
 521
 522         fields[2].tap = etm_reg->jtag_info->tap;
 523         fields[2].num_bits = 1;
 524         fields[2].out_value = malloc(1);
 525         buf_set_u32(fields[2].out_value, 0, 1, 0);
 526         fields[2].in_value = NULL;
 527         fields[2].check_value = NULL;
 528         fields[2].check_mask = NULL;
 529
 530         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 531
 532         fields[0].in_value = reg->value;
 533         fields[0].check_value = check_value;
 534         fields[0].check_mask = check_mask;
 535
 536         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 537
 538         free(fields[1].out_value);
 539         free(fields[2].out_value);
 540
 541         return ERROR_OK;
 542 }
 543
 544 static int etm_set_reg(struct reg *reg, uint32_t value)
 545 {
 546         int retval;
 547
 548         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 549         {
 550                 LOG_ERROR("BUG: error scheduling etm register write");
 551                 return retval;
 552         }
 553
 554         buf_set_u32(reg->value, 0, reg->size, value);
 555         reg->valid = 1;
 556         reg->dirty = 0;
 557
 558         return ERROR_OK;
 559 }
 560
 561 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 562 {
 563         int retval;
 564
 565         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 566
 567         if ((retval = jtag_execute_queue()) != ERROR_OK)
 568         {
 569                 LOG_ERROR("register write failed");
 570                 return retval;
 571         }
 572         return ERROR_OK;
 573 }
 574
 575 static int etm_write_reg(struct reg *reg, uint32_t value)
 576 {
 577         struct etm_reg *etm_reg = reg->arch_info;
 578         const struct etm_reg_info *r = etm_reg->reg_info;
 579         uint8_t reg_addr = r->addr & 0x7f;
 580         struct scan_field fields[3];
 581
 582         if (etm_reg->reg_info->mode == RO) {
 583                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 584                 return ERROR_INVALID_ARGUMENTS;
 585         }
 586
 587         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 588
 589         jtag_set_end_state(TAP_IDLE);
 590         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 591         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 592
 593         fields[0].tap = etm_reg->jtag_info->tap;
 594         fields[0].num_bits = 32;
 595         uint8_t tmp1[4];
 596         fields[0].out_value = tmp1;
 597         buf_set_u32(fields[0].out_value, 0, 32, value);
 598         fields[0].in_value = NULL;
 599
 600         fields[1].tap = etm_reg->jtag_info->tap;
 601         fields[1].num_bits = 7;
 602         uint8_t tmp2;
 603         fields[1].out_value = &tmp2;
 604         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 605         fields[1].in_value = NULL;
 606
 607         fields[2].tap = etm_reg->jtag_info->tap;
 608         fields[2].num_bits = 1;
 609         uint8_t tmp3;
 610         fields[2].out_value = &tmp3;
 611         buf_set_u32(fields[2].out_value, 0, 1, 1);
 612         fields[2].in_value = NULL;
 613
 614         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 615
 616         return ERROR_OK;
 617 }
 618
 619
 620 /* ETM trace analysis functionality
 621  *
 622  */
 623 extern struct etm_capture_driver etm_dummy_capture_driver;
 624 #if BUILD_OOCD_TRACE == 1
 625 extern struct etm_capture_driver oocd_trace_capture_driver;
 626 #endif
 627
 628 static struct etm_capture_driver *etm_capture_drivers[] =
 629 {
 630         &etb_capture_driver,
 631         &etm_dummy_capture_driver,
 632 #if BUILD_OOCD_TRACE == 1
 633         &oocd_trace_capture_driver,
 634 #endif
 635         NULL
 636 };
 637
 638 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
 639 {
 640         int i;
 641         int section = -1;
 642         uint32_t size_read;
 643         uint32_t opcode;
 644         int retval;
 645
 646         if (!ctx->image)
 647                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 648
 649         /* search for the section the current instruction belongs to */
 650         for (i = 0; i < ctx->image->num_sections; i++)
 651         {
 652                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 653                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 654                 {
 655                         section = i;
 656                         break;
 657                 }
 658         }
 659
 660         if (section == -1)
 661         {
 662                 /* current instruction couldn't be found in the image */
 663                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 664         }
 665
 666         if (ctx->core_state == ARMV4_5_STATE_ARM)
 667         {
 668                 uint8_t buf[4];
 669                 if ((retval = image_read_section(ctx->image, section,
 670                         ctx->current_pc - ctx->image->sections[section].base_address,
 671                         4, buf, &size_read)) != ERROR_OK)
 672                 {
 673                         LOG_ERROR("error while reading instruction: %i", retval);
 674                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 675                 }
 676                 opcode = target_buffer_get_u32(ctx->target, buf);
 677                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 678         }
 679         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 680         {
 681                 uint8_t buf[2];
 682                 if ((retval = image_read_section(ctx->image, section,
 683                         ctx->current_pc - ctx->image->sections[section].base_address,
 684                         2, buf, &size_read)) != ERROR_OK)
 685                 {
 686                         LOG_ERROR("error while reading instruction: %i", retval);
 687                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 688                 }
 689                 opcode = target_buffer_get_u16(ctx->target, buf);
 690                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 691         }
 692         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 693         {
 694                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 695                 return ERROR_FAIL;
 696         }
 697         else
 698         {
 699                 LOG_ERROR("BUG: unknown core state encountered");
 700                 return ERROR_FAIL;
 701         }
 702
 703         return ERROR_OK;
 704 }
 705
 706 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
 707 {
 708         while (ctx->data_index < ctx->trace_depth)
 709         {
 710                 /* if the caller specified an address packet offset, skip until the
 711                  * we reach the n-th cycle marked with tracesync */
 712                 if (apo > 0)
 713                 {
 714                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 715                                 apo--;
 716
 717                         if (apo > 0)
 718                         {
 719                                 ctx->data_index++;
 720                                 ctx->data_half = 0;
 721                         }
 722                         continue;
 723                 }
 724
 725                 /* no tracedata output during a TD cycle
 726                  * or in a trigger cycle */
 727                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 728                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 729                 {
 730                         ctx->data_index++;
 731                         ctx->data_half = 0;
 732                         continue;
 733                 }
 734
 735                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 736                 {
 737                         if (ctx->data_half == 0)
 738                         {
 739                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 740                                 ctx->data_half = 1;
 741                         }
 742                         else
 743                         {
 744                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 745                                 ctx->data_half = 0;
 746                                 ctx->data_index++;
 747                         }
 748                 }
 749                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 750                 {
 751                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 752                         ctx->data_index++;
 753                 }
 754                 else
 755                 {
 756                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 757                         if (ctx->data_index > (ctx->trace_depth - 2))
 758                                 return -1;
 759
 760                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 761                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 762                         ctx->data_index += 2;
 763                 }
 764
 765                 return 0;
 766         }
 767
 768         return -1;
 769 }
 770
 771 static int etmv1_branch_address(struct etm_context *ctx)
 772 {
 773         int retval;
 774         uint8_t packet;
 775         int shift = 0;
 776         int apo;
 777         uint32_t i;
 778
 779         /* quit analysis if less than two cycles are left in the trace
 780          * because we can't extract the APO */
 781         if (ctx->data_index > (ctx->trace_depth - 2))
 782                 return -1;
 783
 784         /* a BE could be output during an APO cycle, skip the current
 785          * and continue with the new one */
 786         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 787                 return 1;
 788         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 789                 return 2;
 790
 791         /* address packet offset encoded in the next two cycles' pipestat bits */
 792         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 793         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 794
 795         /* count number of tracesync cycles between current pipe_index and data_index
 796          * i.e. the number of tracesyncs that data_index already passed by
 797          * to subtract them from the APO */
 798         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 799         {
 800                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 801                         apo--;
 802         }
 803
 804         /* extract up to four 7-bit packets */
 805         do {
 806                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 807                         return -1;
 808                 ctx->last_branch &= ~(0x7f << shift);
 809                 ctx->last_branch |= (packet & 0x7f) << shift;
 810                 shift += 7;
 811         } while ((packet & 0x80) && (shift < 28));
 812
 813         /* one last packet holding 4 bits of the address, plus the branch reason code */
 814         if ((shift == 28) && (packet & 0x80))
 815         {
 816                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 817                         return -1;
 818                 ctx->last_branch &= 0x0fffffff;
 819                 ctx->last_branch |= (packet & 0x0f) << 28;
 820                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 821                 shift += 4;
 822         }
 823         else
 824         {
 825                 ctx->last_branch_reason = 0;
 826         }
 827
 828         if (shift == 32)
 829         {
 830                 ctx->pc_ok = 1;
 831         }
 832
 833         /* if a full address was output, we might have branched into Jazelle state */
 834         if ((shift == 32) && (packet & 0x80))
 835         {
 836                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 837         }
 838         else
 839         {
 840                 /* if we didn't branch into Jazelle state, the current processor state is
 841                  * encoded in bit 0 of the branch target address */
 842                 if (ctx->last_branch & 0x1)
 843                 {
 844                         ctx->core_state = ARMV4_5_STATE_THUMB;
 845                         ctx->last_branch &= ~0x1;
 846                 }
 847                 else
 848                 {
 849                         ctx->core_state = ARMV4_5_STATE_ARM;
 850                         ctx->last_branch &= ~0x3;
 851                 }
 852         }
 853
 854         return 0;
 855 }
 856
 857 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
 858 {
 859         int j;
 860         uint8_t buf[4];
 861         int retval;
 862
 863         for (j = 0; j < size; j++)
 864         {
 865                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 866                         return -1;
 867         }
 868
 869         if (size == 8)
 870         {
 871                 LOG_ERROR("TODO: add support for 64-bit values");
 872                 return -1;
 873         }
 874         else if (size == 4)
 875                 *data = target_buffer_get_u32(ctx->target, buf);
 876         else if (size == 2)
 877                 *data = target_buffer_get_u16(ctx->target, buf);
 878         else if (size == 1)
 879                 *data = buf[0];
 880         else
 881                 return -1;
 882
 883         return 0;
 884 }
 885
 886 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
 887 {
 888         int retval;
 889         struct arm_instruction instruction;
 890
 891         /* read the trace data if it wasn't read already */
 892         if (ctx->trace_depth == 0)
 893                 ctx->capture_driver->read_trace(ctx);
 894
 895         /* start at the beginning of the captured trace */
 896         ctx->pipe_index = 0;
 897         ctx->data_index = 0;
 898         ctx->data_half = 0;
 899
 900         /* neither the PC nor the data pointer are valid */
 901         ctx->pc_ok = 0;
 902         ctx->ptr_ok = 0;
 903
 904         while (ctx->pipe_index < ctx->trace_depth)
 905         {
 906                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 907                 uint32_t next_pc = ctx->current_pc;
 908                 uint32_t old_data_index = ctx->data_index;
 909                 uint32_t old_data_half = ctx->data_half;
 910                 uint32_t old_index = ctx->pipe_index;
 911                 uint32_t last_instruction = ctx->last_instruction;
 912                 uint32_t cycles = 0;
 913                 int current_pc_ok = ctx->pc_ok;
 914
 915                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 916                 {
 917                         command_print(cmd_ctx, "--- trigger ---");
 918                 }
 919
 920                 /* instructions execute in IE/D or BE/D cycles */
 921                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 922                         ctx->last_instruction = ctx->pipe_index;
 923
 924                 /* if we don't have a valid pc skip until we reach an indirect branch */
 925                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 926                 {
 927                         ctx->pipe_index++;
 928                         continue;
 929                 }
 930
 931                 /* any indirect branch could have interrupted instruction flow
 932                  * - the branch reason code could indicate a trace discontinuity
 933                  * - a branch to the exception vectors indicates an exception
 934                  */
 935                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 936                 {
 937                         /* backup current data index, to be able to consume the branch address
 938                          * before examining data address and values
 939                          */
 940                         old_data_index = ctx->data_index;
 941                         old_data_half = ctx->data_half;
 942
 943                         ctx->last_instruction = ctx->pipe_index;
 944
 945                         if ((retval = etmv1_branch_address(ctx)) != 0)
 946                         {
 947                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 948                                  * quit analysing the trace */
 949                                 if (retval < 0)
 950                                         break;
 951
 952                                 /* a positive return values means the current branch was abandoned,
 953                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 954                                  */
 955                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 956                                 ctx->pipe_index += retval;
 957                                 continue;
 958                         }
 959
 960                         /* skip over APO cycles */
 961                         ctx->pipe_index += 2;
 962
 963                         switch (ctx->last_branch_reason)
 964                         {
 965                                 case 0x0:       /* normal PC change */
 966                                         next_pc = ctx->last_branch;
 967                                         break;
 968                                 case 0x1:       /* tracing enabled */
 969                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 970                                         ctx->current_pc = ctx->last_branch;
 971                                         ctx->pipe_index++;
 972                                         continue;
 973                                         break;
 974                                 case 0x2:       /* trace restarted after FIFO overflow */
 975                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 976                                         ctx->current_pc = ctx->last_branch;
 977                                         ctx->pipe_index++;
 978                                         continue;
 979                                         break;
 980                                 case 0x3:       /* exit from debug state */
 981                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 982                                         ctx->current_pc = ctx->last_branch;
 983                                         ctx->pipe_index++;
 984                                         continue;
 985                                         break;
 986                                 case 0x4:       /* periodic synchronization point */
 987                                         next_pc = ctx->last_branch;
 988                                         /* if we had no valid PC prior to this synchronization point,
 989                                          * we have to move on with the next trace cycle
 990                                          */
 991                                         if (!current_pc_ok)
 992                                         {
 993                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 994                                                 ctx->current_pc = next_pc;
 995                                                 ctx->pipe_index++;
 996                                                 continue;
 997                                         }
 998                                         break;
 999                                 default:        /* reserved */
1000                                         LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
1001                                         return ERROR_FAIL;
1002                         }
1003
1004                         /* if we got here the branch was a normal PC change
1005                          * (or a periodic synchronization point, which means the same for that matter)
1006                          * if we didn't accquire a complete PC continue with the next cycle
1007                          */
1008                         if (!ctx->pc_ok)
1009                                 continue;
1010
1011                         /* indirect branch to the exception vector means an exception occured */
1012                         if ((ctx->last_branch <= 0x20)
1013                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1014                         {
1015                                 if ((ctx->last_branch & 0xff) == 0x10)
1016                                 {
1017                                         command_print(cmd_ctx, "data abort");
1018                                 }
1019                                 else
1020                                 {
1021                                         command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1022                                         ctx->current_pc = ctx->last_branch;
1023                                         ctx->pipe_index++;
1024                                         continue;
1025                                 }
1026                         }
1027                 }
1028
1029                 /* an instruction was executed (or not, depending on the condition flags)
1030                  * retrieve it from the image for displaying */
1031                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1032                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1033                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1034                 {
1035                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1036                         {
1037                                 /* can't continue tracing with no image available */
1038                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1039                                 {
1040                                         return retval;
1041                                 }
1042                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1043                                 {
1044                                         /* TODO: handle incomplete images
1045                                          * for now we just quit the analsysis*/
1046                                         return retval;
1047                                 }
1048                         }
1049
1050                         cycles = old_index - last_instruction;
1051                 }
1052
1053                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1054                 {
1055                         uint32_t new_data_index = ctx->data_index;
1056                         uint32_t new_data_half = ctx->data_half;
1057
1058                         /* in case of a branch with data, the branch target address was consumed before
1059                          * we temporarily go back to the saved data index */
1060                         if (pipestat == STAT_BD)
1061                         {
1062                                 ctx->data_index = old_data_index;
1063                                 ctx->data_half = old_data_half;
1064                         }
1065
1066                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
1067                         {
1068                                 uint8_t packet;
1069                                 int shift = 0;
1070
1071                                 do {
1072                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1073                                                 return ERROR_ETM_ANALYSIS_FAILED;
1074                                         ctx->last_ptr &= ~(0x7f << shift);
1075                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1076                                         shift += 7;
1077                                 } while ((packet & 0x80) && (shift < 32));
1078
1079                                 if (shift >= 32)
1080                                         ctx->ptr_ok = 1;
1081
1082                                 if (ctx->ptr_ok)
1083                                 {
1084                                         command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1085                                 }
1086                         }
1087
1088                         if (ctx->tracemode & ETMV1_TRACE_DATA)
1089                         {
1090                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1091                                 {
1092                                         int i;
1093                                         for (i = 0; i < 16; i++)
1094                                         {
1095                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
1096                                                 {
1097                                                         uint32_t data;
1098                                                         if (etmv1_data(ctx, 4, &data) != 0)
1099                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1100                                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1101                                                 }
1102                                         }
1103                                 }
1104                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1105                                 {
1106                                         uint32_t data;
1107                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1108                                                 return ERROR_ETM_ANALYSIS_FAILED;
1109                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1110                                 }
1111                         }
1112
1113                         /* restore data index after consuming BD address and data */
1114                         if (pipestat == STAT_BD)
1115                         {
1116                                 ctx->data_index = new_data_index;
1117                                 ctx->data_half = new_data_half;
1118                         }
1119                 }
1120
1121                 /* adjust PC */
1122                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1123                 {
1124                         if (((instruction.type == ARM_B) ||
1125                              (instruction.type == ARM_BL) ||
1126                              (instruction.type == ARM_BLX)) &&
1127                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1128                         {
1129                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1130                         }
1131                         else
1132                         {
1133                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1134                         }
1135                 }
1136                 else if (pipestat == STAT_IN)
1137                 {
1138                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1139                 }
1140
1141                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1142                 {
1143                         char cycles_text[32] = "";
1144
1145                         /* if the trace was captured with cycle accurate tracing enabled,
1146                          * output the number of cycles since the last executed instruction
1147                          */
1148                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1149                         {
1150                                 snprintf(cycles_text, 32, " (%i %s)",
1151                                          (int)cycles,
1152                                         (cycles == 1) ? "cycle" : "cycles");
1153                         }
1154
1155                         command_print(cmd_ctx, "%s%s%s",
1156                                 instruction.text,
1157                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1158                                 cycles_text);
1159
1160                         ctx->current_pc = next_pc;
1161
1162                         /* packets for an instruction don't start on or before the preceding
1163                          * functional pipestat (i.e. other than WT or TD)
1164                          */
1165                         if (ctx->data_index <= ctx->pipe_index)
1166                         {
1167                                 ctx->data_index = ctx->pipe_index + 1;
1168                                 ctx->data_half = 0;
1169                         }
1170                 }
1171
1172                 ctx->pipe_index += 1;
1173         }
1174
1175         return ERROR_OK;
1176 }
1177
1178 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1179                 etmv1_tracemode_t *mode)
1180 {
1181         etmv1_tracemode_t tracemode;
1182
1183         /* what parts of data access are traced? */
1184         if (strcmp(args[0], "none") == 0)
1185                 tracemode = ETMV1_TRACE_NONE;
1186         else if (strcmp(args[0], "data") == 0)
1187                 tracemode = ETMV1_TRACE_DATA;
1188         else if (strcmp(args[0], "address") == 0)
1189                 tracemode = ETMV1_TRACE_ADDR;
1190         else if (strcmp(args[0], "all") == 0)
1191                 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1192         else
1193         {
1194                 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1195                 return ERROR_INVALID_ARGUMENTS;
1196         }
1197
1198         uint8_t context_id;
1199         COMMAND_PARSE_NUMBER(u8, args[1], context_id);
1200         switch (context_id)
1201         {
1202         case 0:
1203                 tracemode |= ETMV1_CONTEXTID_NONE;
1204                 break;
1205         case 8:
1206                 tracemode |= ETMV1_CONTEXTID_8;
1207                 break;
1208         case 16:
1209                 tracemode |= ETMV1_CONTEXTID_16;
1210                 break;
1211         case 32:
1212                 tracemode |= ETMV1_CONTEXTID_32;
1213                 break;
1214         default:
1215                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1216                 return ERROR_INVALID_ARGUMENTS;
1217         }
1218
1219         if (strcmp(args[2], "enable") == 0)
1220                 tracemode |= ETMV1_CYCLE_ACCURATE;
1221         else if (strcmp(args[2], "disable") == 0)
1222                 tracemode |= 0;
1223         else
1224         {
1225                 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1226                 return ERROR_INVALID_ARGUMENTS;
1227         }
1228
1229         if (strcmp(args[3], "enable") == 0)
1230                 tracemode |= ETMV1_BRANCH_OUTPUT;
1231         else if (strcmp(args[3], "disable") == 0)
1232                 tracemode |= 0;
1233         else
1234         {
1235                 command_print(cmd_ctx, "invalid option '%s'", args[3]);
1236                 return ERROR_INVALID_ARGUMENTS;
1237         }
1238
1239         /* IGNORED:
1240          *  - CPRT tracing (coprocessor register transfers)
1241          *  - debug request (causes debug entry on trigger)
1242          *  - stall on FIFOFULL (preventing tracedata lossage)
1243          */
1244         *mode = tracemode;
1245
1246         return ERROR_OK;
1247 }
1248
1249 COMMAND_HANDLER(handle_etm_tracemode_command)
1250 {
1251         struct target *target = get_current_target(cmd_ctx);
1252         struct arm *arm = target_to_arm(target);
1253         struct etm_context *etm;
1254
1255         if (!is_arm(arm)) {
1256                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1257                 return ERROR_FAIL;
1258         }
1259
1260         etm = arm->etm;
1261         if (!etm) {
1262                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1263                 return ERROR_FAIL;
1264         }
1265
1266         etmv1_tracemode_t tracemode = etm->tracemode;
1267
1268         switch (argc)
1269         {
1270         case 0:
1271                 break;
1272         case 4:
1273                 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode);
1274                 break;
1275         default:
1276                 command_print(cmd_ctx, "usage: configure trace mode "
1277                                 "<none | data | address | all> "
1278                                 "<context id bits> <cycle accurate> <branch output>");
1279                 return ERROR_FAIL;
1280         }
1281
1282         /**
1283          * todo: fail if parameters were invalid for this hardware,
1284          * or couldn't be written; display actual hardware state...
1285          */
1286
1287         command_print(cmd_ctx, "current tracemode configuration:");
1288
1289         switch (tracemode & ETMV1_TRACE_MASK)
1290         {
1291                 case ETMV1_TRACE_NONE:
1292                         command_print(cmd_ctx, "data tracing: none");
1293                         break;
1294                 case ETMV1_TRACE_DATA:
1295                         command_print(cmd_ctx, "data tracing: data only");
1296                         break;
1297                 case ETMV1_TRACE_ADDR:
1298                         command_print(cmd_ctx, "data tracing: address only");
1299                         break;
1300                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1301                         command_print(cmd_ctx, "data tracing: address and data");
1302                         break;
1303         }
1304
1305         switch (tracemode & ETMV1_CONTEXTID_MASK)
1306         {
1307                 case ETMV1_CONTEXTID_NONE:
1308                         command_print(cmd_ctx, "contextid tracing: none");
1309                         break;
1310                 case ETMV1_CONTEXTID_8:
1311                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1312                         break;
1313                 case ETMV1_CONTEXTID_16:
1314                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1315                         break;
1316                 case ETMV1_CONTEXTID_32:
1317                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1318                         break;
1319         }
1320
1321         if (tracemode & ETMV1_CYCLE_ACCURATE)
1322         {
1323                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1324         }
1325         else
1326         {
1327                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1328         }
1329
1330         if (tracemode & ETMV1_BRANCH_OUTPUT)
1331         {
1332                 command_print(cmd_ctx, "full branch address output enabled");
1333         }
1334         else
1335         {
1336                 command_print(cmd_ctx, "full branch address output disabled");
1337         }
1338
1339         /* only update ETM_CTRL register if tracemode changed */
1340         if (etm->tracemode != tracemode)
1341         {
1342                 struct reg *etm_ctrl_reg;
1343
1344                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1345                 if (!etm_ctrl_reg)
1346                         return ERROR_FAIL;
1347
1348                 etm_get_reg(etm_ctrl_reg);
1349
1350                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1351                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1352                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1353                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1354                 etm_store_reg(etm_ctrl_reg);
1355
1356                 etm->tracemode = tracemode;
1357
1358                 /* invalidate old trace data */
1359                 etm->capture_status = TRACE_IDLE;
1360                 if (etm->trace_depth > 0)
1361                 {
1362                         free(etm->trace_data);
1363                         etm->trace_data = NULL;
1364                 }
1365                 etm->trace_depth = 0;
1366         }
1367
1368         return ERROR_OK;
1369 }
1370
1371 COMMAND_HANDLER(handle_etm_config_command)
1372 {
1373         struct target *target;
1374         struct arm *arm;
1375         etm_portmode_t portmode = 0x0;
1376         struct etm_context *etm_ctx;
1377         int i;
1378
1379         if (argc != 5)
1380                 return ERROR_COMMAND_SYNTAX_ERROR;
1381
1382         target = get_target(args[0]);
1383         if (!target)
1384         {
1385                 LOG_ERROR("target '%s' not defined", args[0]);
1386                 return ERROR_FAIL;
1387         }
1388
1389         arm = target_to_arm(target);
1390         if (!is_arm(arm)) {
1391                 command_print(cmd_ctx, "target '%s' is '%s'; not an ARM",
1392                                 target->cmd_name, target_get_name(target));
1393                 return ERROR_FAIL;
1394         }
1395
1396         /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1397          * version we'll be using!! -- so we can't know how to validate
1398          * params yet.  "etm config" should likely be *AFTER* hookup...
1399          *
1400          *  - Many more widths might be supported ... and we can easily
1401          *    check whether our setting "took".
1402          *
1403          *  - The "clock" and "mode" bits are interpreted differently.
1404          *    See ARM IHI 0014O table 2-17 for the old behavior, and
1405          *    table 2-18 for the new.  With ETB it's best to specify
1406          *    "normal full" ...
1407          */
1408         uint8_t port_width;
1409         COMMAND_PARSE_NUMBER(u8, args[1], port_width);
1410         switch (port_width)
1411         {
1412                 /* before ETMv3.0 */
1413                 case 4:
1414                         portmode |= ETM_PORT_4BIT;
1415                         break;
1416                 case 8:
1417                         portmode |= ETM_PORT_8BIT;
1418                         break;
1419                 case 16:
1420                         portmode |= ETM_PORT_16BIT;
1421                         break;
1422                 /* ETMv3.0 and later*/
1423                 case 24:
1424                         portmode |= ETM_PORT_24BIT;
1425                         break;
1426                 case 32:
1427                         portmode |= ETM_PORT_32BIT;
1428                         break;
1429                 case 48:
1430                         portmode |= ETM_PORT_48BIT;
1431                         break;
1432                 case 64:
1433                         portmode |= ETM_PORT_64BIT;
1434                         break;
1435                 case 1:
1436                         portmode |= ETM_PORT_1BIT;
1437                         break;
1438                 case 2:
1439                         portmode |= ETM_PORT_2BIT;
1440                         break;
1441                 default:
1442                         command_print(cmd_ctx,
1443                                 "unsupported ETM port width '%s'", args[1]);
1444                         return ERROR_FAIL;
1445         }
1446
1447         if (strcmp("normal", args[2]) == 0)
1448         {
1449                 portmode |= ETM_PORT_NORMAL;
1450         }
1451         else if (strcmp("multiplexed", args[2]) == 0)
1452         {
1453                 portmode |= ETM_PORT_MUXED;
1454         }
1455         else if (strcmp("demultiplexed", args[2]) == 0)
1456         {
1457                 portmode |= ETM_PORT_DEMUXED;
1458         }
1459         else
1460         {
1461                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1462                 return ERROR_FAIL;
1463         }
1464
1465         if (strcmp("half", args[3]) == 0)
1466         {
1467                 portmode |= ETM_PORT_HALF_CLOCK;
1468         }
1469         else if (strcmp("full", args[3]) == 0)
1470         {
1471                 portmode |= ETM_PORT_FULL_CLOCK;
1472         }
1473         else
1474         {
1475                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1476                 return ERROR_FAIL;
1477         }
1478
1479         etm_ctx = calloc(1, sizeof(struct etm_context));
1480         if (!etm_ctx) {
1481                 LOG_DEBUG("out of memory");
1482                 return ERROR_FAIL;
1483         }
1484
1485         for (i = 0; etm_capture_drivers[i]; i++)
1486         {
1487                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1488                 {
1489                         int retval;
1490                         if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1491                         {
1492                                 free(etm_ctx);
1493                                 return retval;
1494                         }
1495
1496                         etm_ctx->capture_driver = etm_capture_drivers[i];
1497
1498                         break;
1499                 }
1500         }
1501
1502         if (!etm_capture_drivers[i])
1503         {
1504                 /* no supported capture driver found, don't register an ETM */
1505                 free(etm_ctx);
1506                 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1507                 return ERROR_FAIL;
1508         }
1509
1510         etm_ctx->target = target;
1511         etm_ctx->trigger_percent = 50;
1512         etm_ctx->trace_data = NULL;
1513         etm_ctx->portmode = portmode;
1514         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1515
1516         arm->etm = etm_ctx;
1517
1518         return etm_register_user_commands(cmd_ctx);
1519 }
1520
1521 COMMAND_HANDLER(handle_etm_info_command)
1522 {
1523         struct target *target;
1524         struct arm *arm;
1525         struct etm_context *etm;
1526         struct reg *etm_sys_config_reg;
1527         int max_port_size;
1528         uint32_t config;
1529
1530         target = get_current_target(cmd_ctx);
1531         arm = target_to_arm(target);
1532         if (!is_arm(arm))
1533         {
1534                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1535                 return ERROR_FAIL;
1536         }
1537
1538         etm = arm->etm;
1539         if (!etm)
1540         {
1541                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1542                 return ERROR_FAIL;
1543         }
1544
1545         command_print(cmd_ctx, "ETM v%d.%d",
1546                         etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1547         command_print(cmd_ctx, "pairs of address comparators: %i",
1548                         (int) (etm->config >> 0) & 0x0f);
1549         command_print(cmd_ctx, "data comparators: %i",
1550                         (int) (etm->config >> 4) & 0x0f);
1551         command_print(cmd_ctx, "memory map decoders: %i",
1552                         (int) (etm->config >> 8) & 0x1f);
1553         command_print(cmd_ctx, "number of counters: %i",
1554                         (int) (etm->config >> 13) & 0x07);
1555         command_print(cmd_ctx, "sequencer %spresent",
1556                         (int) (etm->config & (1 << 16)) ? "" : "not ");
1557         command_print(cmd_ctx, "number of ext. inputs: %i",
1558                         (int) (etm->config >> 17) & 0x07);
1559         command_print(cmd_ctx, "number of ext. outputs: %i",
1560                         (int) (etm->config >> 20) & 0x07);
1561         command_print(cmd_ctx, "FIFO full %spresent",
1562                         (int) (etm->config & (1 << 23)) ? "" : "not ");
1563         if (etm->bcd_vers < 0x20)
1564                 command_print(cmd_ctx, "protocol version: %i",
1565                                 (int) (etm->config >> 28) & 0x07);
1566         else {
1567                 command_print(cmd_ctx,
1568                                 "coprocessor and memory access %ssupported",
1569                                 (etm->config & (1 << 26)) ? "" : "not ");
1570                 command_print(cmd_ctx, "trace start/stop %spresent",
1571                                 (etm->config & (1 << 26)) ? "" : "not ");
1572                 command_print(cmd_ctx, "number of context comparators: %i",
1573                                 (int) (etm->config >> 24) & 0x03);
1574         }
1575
1576         /* SYS_CONFIG isn't present before ETMv1.2 */
1577         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1578         if (!etm_sys_config_reg)
1579                 return ERROR_OK;
1580
1581         etm_get_reg(etm_sys_config_reg);
1582         config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1583
1584         LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1585
1586         max_port_size = config & 0x7;
1587         if (etm->bcd_vers >= 0x30)
1588                 max_port_size |= (config >> 6) & 0x08;
1589         switch (max_port_size)
1590         {
1591                 /* before ETMv3.0 */
1592                 case 0:
1593                         max_port_size = 4;
1594                         break;
1595                 case 1:
1596                         max_port_size = 8;
1597                         break;
1598                 case 2:
1599                         max_port_size = 16;
1600                         break;
1601                 /* ETMv3.0 and later*/
1602                 case 3:
1603                         max_port_size = 24;
1604                         break;
1605                 case 4:
1606                         max_port_size = 32;
1607                         break;
1608                 case 5:
1609                         max_port_size = 48;
1610                         break;
1611                 case 6:
1612                         max_port_size = 64;
1613                         break;
1614                 case 8:
1615                         max_port_size = 1;
1616                         break;
1617                 case 9:
1618                         max_port_size = 2;
1619                         break;
1620                 default:
1621                         LOG_ERROR("Illegal max_port_size");
1622                         return ERROR_FAIL;
1623         }
1624         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1625
1626         if (etm->bcd_vers < 0x30) {
1627                 command_print(cmd_ctx, "half-rate clocking %ssupported",
1628                                 (config & (1 << 3)) ? "" : "not ");
1629                 command_print(cmd_ctx, "full-rate clocking %ssupported",
1630                                 (config & (1 << 4)) ? "" : "not ");
1631                 command_print(cmd_ctx, "normal trace format %ssupported",
1632                                 (config & (1 << 5)) ? "" : "not ");
1633                 command_print(cmd_ctx, "multiplex trace format %ssupported",
1634                                 (config & (1 << 6)) ? "" : "not ");
1635                 command_print(cmd_ctx, "demultiplex trace format %ssupported",
1636                                 (config & (1 << 7)) ? "" : "not ");
1637         } else {
1638                 /* REVISIT show which size and format are selected ... */
1639                 command_print(cmd_ctx, "current port size %ssupported",
1640                                 (config & (1 << 10)) ? "" : "not ");
1641                 command_print(cmd_ctx, "current trace format %ssupported",
1642                                 (config & (1 << 11)) ? "" : "not ");
1643         }
1644         if (etm->bcd_vers >= 0x21)
1645                 command_print(cmd_ctx, "fetch comparisons %ssupported",
1646                                 (config & (1 << 17)) ? "not " : "");
1647         command_print(cmd_ctx, "FIFO full %ssupported",
1648                         (config & (1 << 8)) ? "" : "not ");
1649
1650         return ERROR_OK;
1651 }
1652
1653 COMMAND_HANDLER(handle_etm_status_command)
1654 {
1655         struct target *target;
1656         struct arm *arm;
1657         struct etm_context *etm;
1658         trace_status_t trace_status;
1659
1660         target = get_current_target(cmd_ctx);
1661         arm = target_to_arm(target);
1662         if (!is_arm(arm))
1663         {
1664                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1665                 return ERROR_FAIL;
1666         }
1667
1668         etm = arm->etm;
1669         if (!etm)
1670         {
1671                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1672                 return ERROR_FAIL;
1673         }
1674
1675         /* ETM status */
1676         if (etm->bcd_vers >= 0x11) {
1677                 struct reg *reg;
1678
1679                 reg = etm_reg_lookup(etm, ETM_STATUS);
1680                 if (!reg)
1681                         return ERROR_FAIL;
1682                 if (etm_get_reg(reg) == ERROR_OK) {
1683                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1684
1685                         command_print(cmd_ctx, "etm: %s%s%s%s",
1686                                 /* bit(1) == progbit */
1687                                 (etm->bcd_vers >= 0x12)
1688                                         ? ((s & (1 << 1))
1689                                                 ? "disabled" : "enabled")
1690                                         : "?",
1691                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1692                                         ? " triggered" : "",
1693                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1694                                         ? " start/stop" : "",
1695                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1696                                         ? " untraced-overflow" : "");
1697                 } /* else ignore and try showing trace port status */
1698         }
1699
1700         /* Trace Port Driver status */
1701         trace_status = etm->capture_driver->status(etm);
1702         if (trace_status == TRACE_IDLE)
1703         {
1704                 command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
1705         }
1706         else
1707         {
1708                 static char *completed = " completed";
1709                 static char *running = " is running";
1710                 static char *overflowed = ", overflowed";
1711                 static char *triggered = ", triggered";
1712
1713                 command_print(cmd_ctx, "%s: trace collection%s%s%s",
1714                         etm->capture_driver->name,
1715                         (trace_status & TRACE_RUNNING) ? running : completed,
1716                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1717                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1718
1719                 if (etm->trace_depth > 0)
1720                 {
1721                         command_print(cmd_ctx, "%i frames of trace data read",
1722                                         (int)(etm->trace_depth));
1723                 }
1724         }
1725
1726         return ERROR_OK;
1727 }
1728
1729 COMMAND_HANDLER(handle_etm_image_command)
1730 {
1731         struct target *target;
1732         struct arm *arm;
1733         struct etm_context *etm_ctx;
1734
1735         if (argc < 1)
1736         {
1737                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1738                 return ERROR_FAIL;
1739         }
1740
1741         target = get_current_target(cmd_ctx);
1742         arm = target_to_arm(target);
1743         if (!is_arm(arm))
1744         {
1745                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1746                 return ERROR_FAIL;
1747         }
1748
1749         etm_ctx = arm->etm;
1750         if (!etm_ctx)
1751         {
1752                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1753                 return ERROR_FAIL;
1754         }
1755
1756         if (etm_ctx->image)
1757         {
1758                 image_close(etm_ctx->image);
1759                 free(etm_ctx->image);
1760                 command_print(cmd_ctx, "previously loaded image found and closed");
1761         }
1762
1763         etm_ctx->image = malloc(sizeof(struct image));
1764         etm_ctx->image->base_address_set = 0;
1765         etm_ctx->image->start_address_set = 0;
1766
1767         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1768         if (argc >= 2)
1769         {
1770                 etm_ctx->image->base_address_set = 1;
1771                 COMMAND_PARSE_NUMBER(int, args[1], etm_ctx->image->base_address);
1772         }
1773         else
1774         {
1775                 etm_ctx->image->base_address_set = 0;
1776         }
1777
1778         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1779         {
1780                 free(etm_ctx->image);
1781                 etm_ctx->image = NULL;
1782                 return ERROR_FAIL;
1783         }
1784
1785         return ERROR_OK;
1786 }
1787
1788 COMMAND_HANDLER(handle_etm_dump_command)
1789 {
1790         struct fileio file;
1791         struct target *target;
1792         struct arm *arm;
1793         struct etm_context *etm_ctx;
1794         uint32_t i;
1795
1796         if (argc != 1)
1797         {
1798                 command_print(cmd_ctx, "usage: etm dump <file>");
1799                 return ERROR_FAIL;
1800         }
1801
1802         target = get_current_target(cmd_ctx);
1803         arm = target_to_arm(target);
1804         if (!is_arm(arm))
1805         {
1806                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1807                 return ERROR_FAIL;
1808         }
1809
1810         etm_ctx = arm->etm;
1811         if (!etm_ctx)
1812         {
1813                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1814                 return ERROR_FAIL;
1815         }
1816
1817         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1818         {
1819                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1820                 return ERROR_OK;
1821         }
1822
1823         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1824         {
1825                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1826                 command_print(cmd_ctx, "trace capture not completed");
1827                 return ERROR_FAIL;
1828         }
1829
1830         /* read the trace data if it wasn't read already */
1831         if (etm_ctx->trace_depth == 0)
1832                 etm_ctx->capture_driver->read_trace(etm_ctx);
1833
1834         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1835         {
1836                 return ERROR_FAIL;
1837         }
1838
1839         fileio_write_u32(&file, etm_ctx->capture_status);
1840         fileio_write_u32(&file, etm_ctx->portmode);
1841         fileio_write_u32(&file, etm_ctx->tracemode);
1842         fileio_write_u32(&file, etm_ctx->trace_depth);
1843
1844         for (i = 0; i < etm_ctx->trace_depth; i++)
1845         {
1846                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1847                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1848                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1849         }
1850
1851         fileio_close(&file);
1852
1853         return ERROR_OK;
1854 }
1855
1856 COMMAND_HANDLER(handle_etm_load_command)
1857 {
1858         struct fileio file;
1859         struct target *target;
1860         struct arm *arm;
1861         struct etm_context *etm_ctx;
1862         uint32_t i;
1863
1864         if (argc != 1)
1865         {
1866                 command_print(cmd_ctx, "usage: etm load <file>");
1867                 return ERROR_FAIL;
1868         }
1869
1870         target = get_current_target(cmd_ctx);
1871         arm = target_to_arm(target);
1872         if (!is_arm(arm))
1873         {
1874                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1875                 return ERROR_FAIL;
1876         }
1877
1878         etm_ctx = arm->etm;
1879         if (!etm_ctx)
1880         {
1881                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1882                 return ERROR_FAIL;
1883         }
1884
1885         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1886         {
1887                 command_print(cmd_ctx, "trace capture running, stop first");
1888                 return ERROR_FAIL;
1889         }
1890
1891         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1892         {
1893                 return ERROR_FAIL;
1894         }
1895
1896         if (file.size % 4)
1897         {
1898                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1899                 fileio_close(&file);
1900                 return ERROR_FAIL;
1901         }
1902
1903         if (etm_ctx->trace_depth > 0)
1904         {
1905                 free(etm_ctx->trace_data);
1906                 etm_ctx->trace_data = NULL;
1907         }
1908
1909         {
1910           uint32_t tmp;
1911           fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1912           fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1913           fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1914           fileio_read_u32(&file, &etm_ctx->trace_depth);
1915         }
1916         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1917         if (etm_ctx->trace_data == NULL)
1918         {
1919                 command_print(cmd_ctx, "not enough memory to perform operation");
1920                 fileio_close(&file);
1921                 return ERROR_FAIL;
1922         }
1923
1924         for (i = 0; i < etm_ctx->trace_depth; i++)
1925         {
1926                 uint32_t pipestat, packet, flags;
1927                 fileio_read_u32(&file, &pipestat);
1928                 fileio_read_u32(&file, &packet);
1929                 fileio_read_u32(&file, &flags);
1930                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1931                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1932                 etm_ctx->trace_data[i].flags = flags;
1933         }
1934
1935         fileio_close(&file);
1936
1937         return ERROR_OK;
1938 }
1939
1940 COMMAND_HANDLER(handle_etm_trigger_percent_command)
1941 {
1942         struct target *target;
1943         struct arm *arm;
1944         struct etm_context *etm_ctx;
1945
1946         target = get_current_target(cmd_ctx);
1947         arm = target_to_arm(target);
1948         if (!is_arm(arm))
1949         {
1950                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1951                 return ERROR_FAIL;
1952         }
1953
1954         etm_ctx = arm->etm;
1955         if (!etm_ctx)
1956         {
1957                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1958                 return ERROR_FAIL;
1959         }
1960
1961         if (argc > 0)
1962         {
1963                 uint32_t new_value;
1964                 COMMAND_PARSE_NUMBER(u32, args[0], new_value);
1965
1966                 if ((new_value < 2) || (new_value > 100))
1967                 {
1968                         command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1969                 }
1970                 else
1971                 {
1972                         etm_ctx->trigger_percent = new_value;
1973                 }
1974         }
1975
1976         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1977
1978         return ERROR_OK;
1979 }
1980
1981 COMMAND_HANDLER(handle_etm_start_command)
1982 {
1983         struct target *target;
1984         struct arm *arm;
1985         struct etm_context *etm_ctx;
1986         struct reg *etm_ctrl_reg;
1987
1988         target = get_current_target(cmd_ctx);
1989         arm = target_to_arm(target);
1990         if (!is_arm(arm))
1991         {
1992                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1993                 return ERROR_FAIL;
1994         }
1995
1996         etm_ctx = arm->etm;
1997         if (!etm_ctx)
1998         {
1999                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2000                 return ERROR_FAIL;
2001         }
2002
2003         /* invalidate old tracing data */
2004         etm_ctx->capture_status = TRACE_IDLE;
2005         if (etm_ctx->trace_depth > 0)
2006         {
2007                 free(etm_ctx->trace_data);
2008                 etm_ctx->trace_data = NULL;
2009         }
2010         etm_ctx->trace_depth = 0;
2011
2012         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2013         if (!etm_ctrl_reg)
2014                 return ERROR_FAIL;
2015
2016         etm_get_reg(etm_ctrl_reg);
2017
2018         /* Clear programming bit (10), set port selection bit (11) */
2019         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
2020
2021         etm_store_reg(etm_ctrl_reg);
2022         jtag_execute_queue();
2023
2024         etm_ctx->capture_driver->start_capture(etm_ctx);
2025
2026         return ERROR_OK;
2027 }
2028
2029 COMMAND_HANDLER(handle_etm_stop_command)
2030 {
2031         struct target *target;
2032         struct arm *arm;
2033         struct etm_context *etm_ctx;
2034         struct reg *etm_ctrl_reg;
2035
2036         target = get_current_target(cmd_ctx);
2037         arm = target_to_arm(target);
2038         if (!is_arm(arm))
2039         {
2040                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
2041                 return ERROR_FAIL;
2042         }
2043
2044         etm_ctx = arm->etm;
2045         if (!etm_ctx)
2046         {
2047                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2048                 return ERROR_FAIL;
2049         }
2050
2051         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2052         if (!etm_ctrl_reg)
2053                 return ERROR_FAIL;
2054
2055         etm_get_reg(etm_ctrl_reg);
2056
2057         /* Set programming bit (10), clear port selection bit (11) */
2058         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2059
2060         etm_store_reg(etm_ctrl_reg);
2061         jtag_execute_queue();
2062
2063         etm_ctx->capture_driver->stop_capture(etm_ctx);
2064
2065         return ERROR_OK;
2066 }
2067
2068 COMMAND_HANDLER(handle_etm_analyze_command)
2069 {
2070         struct target *target;
2071         struct arm *arm;
2072         struct etm_context *etm_ctx;
2073         int retval;
2074
2075         target = get_current_target(cmd_ctx);
2076         arm = target_to_arm(target);
2077         if (!is_arm(arm))
2078         {
2079                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
2080                 return ERROR_FAIL;
2081         }
2082
2083         etm_ctx = arm->etm;
2084         if (!etm_ctx)
2085         {
2086                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2087                 return ERROR_FAIL;
2088         }
2089
2090         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
2091         {
2092                 switch (retval)
2093                 {
2094                         case ERROR_ETM_ANALYSIS_FAILED:
2095                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
2096                                 break;
2097                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2098                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
2099                                 break;
2100                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
2101                                 command_print(cmd_ctx, "no image available for trace analysis");
2102                                 break;
2103                         default:
2104                                 command_print(cmd_ctx, "unknown error: %i", retval);
2105                 }
2106         }
2107
2108         return retval;
2109 }
2110
2111 int etm_register_commands(struct command_context *cmd_ctx)
2112 {
2113         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
2114
2115         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
2116                 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2117
2118         return ERROR_OK;
2119 }
2120
2121 static int etm_register_user_commands(struct command_context *cmd_ctx)
2122 {
2123         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2124                 COMMAND_EXEC, "configure/display trace mode: "
2125                         "<none | data | address | all> "
2126                         "<context_id_bits> <cycle_accurate> <branch_output>");
2127
2128         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2129                 COMMAND_EXEC, "display info about the current target's ETM");
2130
2131         register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2132                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2133         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2134                 COMMAND_EXEC, "display current target's ETM status");
2135         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2136                 COMMAND_EXEC, "start ETM trace collection");
2137         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2138                 COMMAND_EXEC, "stop ETM trace collection");
2139
2140         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2141                 COMMAND_EXEC, "anaylze collected ETM trace");
2142
2143         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2144                 COMMAND_EXEC, "load image from <file> [base address]");
2145
2146         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2147                 COMMAND_EXEC, "dump captured trace data <file>");
2148         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2149                 COMMAND_EXEC, "load trace data for analysis <file>");
2150
2151         return ERROR_OK;
2152 }