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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <string.h>
  25
  26 #include "etm.h"
  27 #include "etb.h"
  28
  29 #include "armv4_5.h"
  30 #include "arm7_9_common.h"
  31 #include "arm_disassembler.h"
  32 #include "arm_simulator.h"
  33
  34 #include "log.h"
  35 #include "arm_jtag.h"
  36 #include "types.h"
  37 #include "binarybuffer.h"
  38 #include "target.h"
  39 #include "register.h"
  40 #include "jtag.h"
  41 #include "fileio.h"
  42
  43 #include <stdlib.h>
  44
  45 /* ETM register access functionality
  46  *
  47  */
  48
  49 bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
  50 {
  51         {"R", 1},
  52         {"W", 1},
  53         {"reserved", 26},
  54         {"version", 4}
  55 };
  56
  57 int etm_reg_arch_info[] =
  58 {
  59         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  60         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  61         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
  62         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
  63         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
  64         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
  65         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
  66         0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
  67         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
  68         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
  69         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
  70         0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
  71         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
  72         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  73 };
  74
  75 int etm_reg_arch_size_info[] =
  76 {
  77         32, 32, 17, 8, 3, 9, 32, 16,
  78         17, 26, 25, 8, 17, 32, 32, 17,
  79         32, 32, 32, 32, 32, 32, 32, 32,
  80         32, 32, 32, 32, 32, 32, 32, 32,
  81         7, 7, 7, 7, 7, 7, 7, 7,
  82         7, 7, 7, 7, 7, 7, 7, 7,
  83         32, 32, 32, 32, 32, 32, 32, 32,
  84         32, 32, 32, 32, 32, 32, 32, 32,
  85         32, 32, 32, 32, 32, 32, 32, 32,
  86         32, 32, 32, 32, 32, 32, 32, 32,
  87         16, 16, 16, 16, 18, 18, 18, 18,
  88         17, 17, 17, 17, 16, 16, 16, 16,
  89         17, 17, 17, 17, 17, 17, 2,
  90         17, 17, 17, 17, 32, 32, 32, 32
  91 };
  92
  93 char* etm_reg_list[] =
  94 {
  95         "ETM_CTRL",
  96         "ETM_CONFIG",
  97         "ETM_TRIG_EVENT",
  98         "ETM_MMD_CTRL",
  99         "ETM_STATUS",
 100         "ETM_SYS_CONFIG",
 101         "ETM_TRACE_RESOURCE_CTRL",
 102         "ETM_TRACE_EN_CTRL2",
 103         "ETM_TRACE_EN_EVENT",
 104         "ETM_TRACE_EN_CTRL1",
 105         "ETM_FIFOFULL_REGION",
 106         "ETM_FIFOFULL_LEVEL",
 107         "ETM_VIEWDATA_EVENT",
 108         "ETM_VIEWDATA_CTRL1",
 109         "ETM_VIEWDATA_CTRL2",
 110         "ETM_VIEWDATA_CTRL3",
 111         "ETM_ADDR_COMPARATOR_VALUE1",
 112         "ETM_ADDR_COMPARATOR_VALUE2",
 113         "ETM_ADDR_COMPARATOR_VALUE3",
 114         "ETM_ADDR_COMPARATOR_VALUE4",
 115         "ETM_ADDR_COMPARATOR_VALUE5",
 116         "ETM_ADDR_COMPARATOR_VALUE6",
 117         "ETM_ADDR_COMPARATOR_VALUE7",
 118         "ETM_ADDR_COMPARATOR_VALUE8",
 119         "ETM_ADDR_COMPARATOR_VALUE9",
 120         "ETM_ADDR_COMPARATOR_VALUE10",
 121         "ETM_ADDR_COMPARATOR_VALUE11",
 122         "ETM_ADDR_COMPARATOR_VALUE12",
 123         "ETM_ADDR_COMPARATOR_VALUE13",
 124         "ETM_ADDR_COMPARATOR_VALUE14",
 125         "ETM_ADDR_COMPARATOR_VALUE15",
 126         "ETM_ADDR_COMPARATOR_VALUE16",
 127         "ETM_ADDR_ACCESS_TYPE1",
 128         "ETM_ADDR_ACCESS_TYPE2",
 129         "ETM_ADDR_ACCESS_TYPE3",
 130         "ETM_ADDR_ACCESS_TYPE4",
 131         "ETM_ADDR_ACCESS_TYPE5",
 132         "ETM_ADDR_ACCESS_TYPE6",
 133         "ETM_ADDR_ACCESS_TYPE7",
 134         "ETM_ADDR_ACCESS_TYPE8",
 135         "ETM_ADDR_ACCESS_TYPE9",
 136         "ETM_ADDR_ACCESS_TYPE10",
 137         "ETM_ADDR_ACCESS_TYPE11",
 138         "ETM_ADDR_ACCESS_TYPE12",
 139         "ETM_ADDR_ACCESS_TYPE13",
 140         "ETM_ADDR_ACCESS_TYPE14",
 141         "ETM_ADDR_ACCESS_TYPE15",
 142         "ETM_ADDR_ACCESS_TYPE16",
 143         "ETM_DATA_COMPARATOR_VALUE1",
 144         "ETM_DATA_COMPARATOR_VALUE2",
 145         "ETM_DATA_COMPARATOR_VALUE3",
 146         "ETM_DATA_COMPARATOR_VALUE4",
 147         "ETM_DATA_COMPARATOR_VALUE5",
 148         "ETM_DATA_COMPARATOR_VALUE6",
 149         "ETM_DATA_COMPARATOR_VALUE7",
 150         "ETM_DATA_COMPARATOR_VALUE8",
 151         "ETM_DATA_COMPARATOR_VALUE9",
 152         "ETM_DATA_COMPARATOR_VALUE10",
 153         "ETM_DATA_COMPARATOR_VALUE11",
 154         "ETM_DATA_COMPARATOR_VALUE12",
 155         "ETM_DATA_COMPARATOR_VALUE13",
 156         "ETM_DATA_COMPARATOR_VALUE14",
 157         "ETM_DATA_COMPARATOR_VALUE15",
 158         "ETM_DATA_COMPARATOR_VALUE16",
 159         "ETM_DATA_COMPARATOR_MASK1",
 160         "ETM_DATA_COMPARATOR_MASK2",
 161         "ETM_DATA_COMPARATOR_MASK3",
 162         "ETM_DATA_COMPARATOR_MASK4",
 163         "ETM_DATA_COMPARATOR_MASK5",
 164         "ETM_DATA_COMPARATOR_MASK6",
 165         "ETM_DATA_COMPARATOR_MASK7",
 166         "ETM_DATA_COMPARATOR_MASK8",
 167         "ETM_DATA_COMPARATOR_MASK9",
 168         "ETM_DATA_COMPARATOR_MASK10",
 169         "ETM_DATA_COMPARATOR_MASK11",
 170         "ETM_DATA_COMPARATOR_MASK12",
 171         "ETM_DATA_COMPARATOR_MASK13",
 172         "ETM_DATA_COMPARATOR_MASK14",
 173         "ETM_DATA_COMPARATOR_MASK15",
 174         "ETM_DATA_COMPARATOR_MASK16",
 175         "ETM_COUNTER_INITAL_VALUE1",
 176         "ETM_COUNTER_INITAL_VALUE2",
 177         "ETM_COUNTER_INITAL_VALUE3",
 178         "ETM_COUNTER_INITAL_VALUE4",
 179         "ETM_COUNTER_ENABLE1",
 180         "ETM_COUNTER_ENABLE2",
 181         "ETM_COUNTER_ENABLE3",
 182         "ETM_COUNTER_ENABLE4",
 183         "ETM_COUNTER_RELOAD_VALUE1",
 184         "ETM_COUNTER_RELOAD_VALUE2",
 185         "ETM_COUNTER_RELOAD_VALUE3",
 186         "ETM_COUNTER_RELOAD_VALUE4",
 187         "ETM_COUNTER_VALUE1",
 188         "ETM_COUNTER_VALUE2",
 189         "ETM_COUNTER_VALUE3",
 190         "ETM_COUNTER_VALUE4",
 191         "ETM_SEQUENCER_CTRL1",
 192         "ETM_SEQUENCER_CTRL2",
 193         "ETM_SEQUENCER_CTRL3",
 194         "ETM_SEQUENCER_CTRL4",
 195         "ETM_SEQUENCER_CTRL5",
 196         "ETM_SEQUENCER_CTRL6",
 197         "ETM_SEQUENCER_STATE",
 198         "ETM_EXTERNAL_OUTPUT1",
 199         "ETM_EXTERNAL_OUTPUT2",
 200         "ETM_EXTERNAL_OUTPUT3",
 201         "ETM_EXTERNAL_OUTPUT4",
 202         "ETM_CONTEXTID_COMPARATOR_VALUE1",
 203         "ETM_CONTEXTID_COMPARATOR_VALUE2",
 204         "ETM_CONTEXTID_COMPARATOR_VALUE3",
 205         "ETM_CONTEXTID_COMPARATOR_MASK"
 206 };
 207
 208 int etm_reg_arch_type = -1;
 209
 210 int etm_get_reg(reg_t *reg);
 211 int etm_set_reg(reg_t *reg, u32 value);
 212 int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
 213
 214 int etm_write_reg(reg_t *reg, u32 value);
 215 int etm_read_reg(reg_t *reg);
 216
 217 command_t *etm_cmd = NULL;
 218
 219 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 220 {
 221         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 222         reg_t *reg_list = NULL;
 223         etm_reg_t *arch_info = NULL;
 224         int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
 225         int i;
 226         u32 etm_ctrl_value;
 227
 228         /* register a register arch-type for etm registers only once */
 229         if (etm_reg_arch_type == -1)
 230                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
 231
 232         /* the actual registers are kept in two arrays */
 233         reg_list = calloc(num_regs, sizeof(reg_t));
 234         arch_info = calloc(num_regs, sizeof(etm_reg_t));
 235
 236         /* fill in values for the reg cache */
 237         reg_cache->name = "etm registers";
 238         reg_cache->next = NULL;
 239         reg_cache->reg_list = reg_list;
 240         reg_cache->num_regs = num_regs;
 241
 242         /* set up registers */
 243         for (i = 0; i < num_regs; i++)
 244         {
 245                 reg_list[i].name = etm_reg_list[i];
 246                 reg_list[i].size = 32;
 247                 reg_list[i].dirty = 0;
 248                 reg_list[i].valid = 0;
 249                 reg_list[i].bitfield_desc = NULL;
 250                 reg_list[i].num_bitfields = 0;
 251                 reg_list[i].value = calloc(1, 4);
 252                 reg_list[i].arch_info = &arch_info[i];
 253                 reg_list[i].arch_type = etm_reg_arch_type;
 254                 reg_list[i].size = etm_reg_arch_size_info[i];
 255                 arch_info[i].addr = etm_reg_arch_info[i];
 256                 arch_info[i].jtag_info = jtag_info;
 257         }
 258
 259         /* initialize some ETM control register settings */
 260         etm_get_reg(&reg_list[ETM_CTRL]);
 261         etm_ctrl_value = buf_get_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size);
 262
 263         /* clear the ETM powerdown bit (0) */
 264         etm_ctrl_value &= ~0x1;
 265
 266         /* configure port width (6:4), mode (17:16) and clocking (13) */
 267         etm_ctrl_value = (etm_ctrl_value &
 268                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 269                 | etm_ctx->portmode;
 270
 271         buf_set_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size, etm_ctrl_value);
 272         etm_store_reg(&reg_list[ETM_CTRL]);
 273
 274         /* the ETM might have an ETB connected */
 275         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 276         {
 277                 etb_t *etb = etm_ctx->capture_driver_priv;
 278
 279                 if (!etb)
 280                 {
 281                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 282                         return ERROR_OK;
 283                 }
 284
 285                 reg_cache->next = etb_build_reg_cache(etb);
 286
 287                 etb->reg_cache = reg_cache->next;
 288         }
 289
 290         if (etm_ctx->capture_driver->init(etm_ctx) != ERROR_OK)
 291         {
 292                 LOG_ERROR("ETM capture driver initialization failed");
 293                 exit(-1);
 294         }
 295
 296         return reg_cache;
 297 }
 298
 299 int etm_get_reg(reg_t *reg)
 300 {
 301         if (etm_read_reg(reg) != ERROR_OK)
 302         {
 303                 LOG_ERROR("BUG: error scheduling etm register read");
 304                 exit(-1);
 305         }
 306
 307         if (jtag_execute_queue() != ERROR_OK)
 308         {
 309                 LOG_ERROR("register read failed");
 310         }
 311
 312         return ERROR_OK;
 313 }
 314
 315 int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 316 {
 317         etm_reg_t *etm_reg = reg->arch_info;
 318         u8 reg_addr = etm_reg->addr & 0x7f;
 319         scan_field_t fields[3];
 320
 321         LOG_DEBUG("%i", etm_reg->addr);
 322
 323         jtag_add_end_state(TAP_RTI);
 324         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 325         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 326
 327         fields[0].device = etm_reg->jtag_info->chain_pos;
 328         fields[0].num_bits = 32;
 329         fields[0].out_value = reg->value;
 330         fields[0].out_mask = NULL;
 331         fields[0].in_value = NULL;
 332         fields[0].in_check_value = NULL;
 333         fields[0].in_check_mask = NULL;
 334         fields[0].in_handler = NULL;
 335         fields[0].in_handler_priv = NULL;
 336
 337         fields[1].device = etm_reg->jtag_info->chain_pos;
 338         fields[1].num_bits = 7;
 339         fields[1].out_value = malloc(1);
 340         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 341         fields[1].out_mask = NULL;
 342         fields[1].in_value = NULL;
 343         fields[1].in_check_value = NULL;
 344         fields[1].in_check_mask = NULL;
 345         fields[1].in_handler = NULL;
 346         fields[1].in_handler_priv = NULL;
 347
 348         fields[2].device = etm_reg->jtag_info->chain_pos;
 349         fields[2].num_bits = 1;
 350         fields[2].out_value = malloc(1);
 351         buf_set_u32(fields[2].out_value, 0, 1, 0);
 352         fields[2].out_mask = NULL;
 353         fields[2].in_value = NULL;
 354         fields[2].in_check_value = NULL;
 355         fields[2].in_check_mask = NULL;
 356         fields[2].in_handler = NULL;
 357         fields[2].in_handler_priv = NULL;
 358
 359         jtag_add_dr_scan(3, fields, -1);
 360
 361         fields[0].in_value = reg->value;
 362         jtag_set_check_value(fields+0, check_value, check_mask, NULL);
 363
 364         jtag_add_dr_scan(3, fields, -1);
 365
 366         free(fields[1].out_value);
 367         free(fields[2].out_value);
 368
 369         return ERROR_OK;
 370 }
 371
 372 int etm_read_reg(reg_t *reg)
 373 {
 374         return etm_read_reg_w_check(reg, NULL, NULL);
 375 }
 376
 377 int etm_set_reg(reg_t *reg, u32 value)
 378 {
 379         if (etm_write_reg(reg, value) != ERROR_OK)
 380         {
 381                 LOG_ERROR("BUG: error scheduling etm register write");
 382                 exit(-1);
 383         }
 384
 385         buf_set_u32(reg->value, 0, reg->size, value);
 386         reg->valid = 1;
 387         reg->dirty = 0;
 388
 389         return ERROR_OK;
 390 }
 391
 392 int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
 393 {
 394         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 395
 396         if (jtag_execute_queue() != ERROR_OK)
 397         {
 398                 LOG_ERROR("register write failed");
 399                 exit(-1);
 400         }
 401         return ERROR_OK;
 402 }
 403
 404 int etm_write_reg(reg_t *reg, u32 value)
 405 {
 406         etm_reg_t *etm_reg = reg->arch_info;
 407         u8 reg_addr = etm_reg->addr & 0x7f;
 408         scan_field_t fields[3];
 409
 410         LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
 411
 412         jtag_add_end_state(TAP_RTI);
 413         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 414         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 415
 416         fields[0].device = etm_reg->jtag_info->chain_pos;
 417         fields[0].num_bits = 32;
 418         fields[0].out_value = malloc(4);
 419         buf_set_u32(fields[0].out_value, 0, 32, value);
 420         fields[0].out_mask = NULL;
 421         fields[0].in_value = NULL;
 422         fields[0].in_check_value = NULL;
 423         fields[0].in_check_mask = NULL;
 424         fields[0].in_handler = NULL;
 425         fields[0].in_handler_priv = NULL;
 426
 427         fields[1].device = etm_reg->jtag_info->chain_pos;
 428         fields[1].num_bits = 7;
 429         fields[1].out_value = malloc(1);
 430         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 431         fields[1].out_mask = NULL;
 432         fields[1].in_value = NULL;
 433         fields[1].in_check_value = NULL;
 434         fields[1].in_check_mask = NULL;
 435         fields[1].in_handler = NULL;
 436         fields[1].in_handler_priv = NULL;
 437
 438         fields[2].device = etm_reg->jtag_info->chain_pos;
 439         fields[2].num_bits = 1;
 440         fields[2].out_value = malloc(1);
 441         buf_set_u32(fields[2].out_value, 0, 1, 1);
 442         fields[2].out_mask = NULL;
 443         fields[2].in_value = NULL;
 444         fields[2].in_check_value = NULL;
 445         fields[2].in_check_mask = NULL;
 446         fields[2].in_handler = NULL;
 447         fields[2].in_handler_priv = NULL;
 448
 449         jtag_add_dr_scan(3, fields, -1);
 450
 451         free(fields[0].out_value);
 452         free(fields[1].out_value);
 453         free(fields[2].out_value);
 454
 455         return ERROR_OK;
 456 }
 457
 458 int etm_store_reg(reg_t *reg)
 459 {
 460         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 461 }
 462
 463 /* ETM trace analysis functionality
 464  *
 465  */
 466 extern etm_capture_driver_t etb_capture_driver;
 467 extern etm_capture_driver_t etm_dummy_capture_driver;
 468 #if BUILD_OOCD_TRACE == 1
 469 extern etm_capture_driver_t oocd_trace_capture_driver;
 470 #endif
 471
 472 etm_capture_driver_t *etm_capture_drivers[] =
 473 {
 474         &etb_capture_driver,
 475         &etm_dummy_capture_driver,
 476 #if BUILD_OOCD_TRACE == 1
 477         &oocd_trace_capture_driver,
 478 #endif
 479         NULL
 480 };
 481
 482 char *etmv1v1_branch_reason_strings[] =
 483 {
 484         "normal PC change",
 485         "tracing enabled",
 486         "trace restarted after overflow",
 487         "exit from debug",
 488         "periodic synchronization",
 489         "reserved",
 490         "reserved",
 491         "reserved",
 492 };
 493
 494 int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 495 {
 496         int i;
 497         int section = -1;
 498         u32 size_read;
 499         u32 opcode;
 500         int retval;
 501
 502         if (!ctx->image)
 503                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 504
 505         /* search for the section the current instruction belongs to */
 506         for (i = 0; i < ctx->image->num_sections; i++)
 507         {
 508                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 509                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 510                 {
 511                         section = i;
 512                         break;
 513                 }
 514         }
 515
 516         if (section == -1)
 517         {
 518                 /* current instruction couldn't be found in the image */
 519                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 520         }
 521
 522         if (ctx->core_state == ARMV4_5_STATE_ARM)
 523         {
 524                 u8 buf[4];
 525                 if ((retval = image_read_section(ctx->image, section,
 526                         ctx->current_pc - ctx->image->sections[section].base_address,
 527                         4, buf, &size_read)) != ERROR_OK)
 528                 {
 529                         LOG_ERROR("error while reading instruction: %i", retval);
 530                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 531                 }
 532                 opcode = target_buffer_get_u32(ctx->target, buf);
 533                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 534         }
 535         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 536         {
 537                 u8 buf[2];
 538                 if ((retval = image_read_section(ctx->image, section,
 539                         ctx->current_pc - ctx->image->sections[section].base_address,
 540                         2, buf, &size_read)) != ERROR_OK)
 541                 {
 542                         LOG_ERROR("error while reading instruction: %i", retval);
 543                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 544                 }
 545                 opcode = target_buffer_get_u16(ctx->target, buf);
 546                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 547         }
 548         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 549         {
 550                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 551                 exit(-1);
 552         }
 553         else
 554         {
 555                 LOG_ERROR("BUG: unknown core state encountered");
 556                 exit(-1);
 557         }
 558
 559         return ERROR_OK;
 560 }
 561
 562 int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
 563 {
 564         while (ctx->data_index < ctx->trace_depth)
 565         {
 566                 /* if the caller specified an address packet offset, skip until the
 567                  * we reach the n-th cycle marked with tracesync */
 568                 if (apo > 0)
 569                 {
 570                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 571                                 apo--;
 572
 573                         if (apo > 0)
 574                         {
 575                                 ctx->data_index++;
 576                                 ctx->data_half = 0;
 577                         }
 578                         continue;
 579                 }
 580
 581                 /* no tracedata output during a TD cycle
 582                  * or in a trigger cycle */
 583                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 584                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 585                 {
 586                         ctx->data_index++;
 587                         ctx->data_half = 0;
 588                         continue;
 589                 }
 590
 591                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 592                 {
 593                         if (ctx->data_half == 0)
 594                         {
 595                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 596                                 ctx->data_half = 1;
 597                         }
 598                         else
 599                         {
 600                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 601                                 ctx->data_half = 0;
 602                                 ctx->data_index++;
 603                         }
 604                 }
 605                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 606                 {
 607                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 608                         ctx->data_index++;
 609                 }
 610                 else
 611                 {
 612                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 613                         if (ctx->data_index > (ctx->trace_depth - 2))
 614                                 return -1;
 615
 616                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 617                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 618                         ctx->data_index += 2;
 619                 }
 620
 621                 return 0;
 622         }
 623
 624         return -1;
 625 }
 626
 627 int etmv1_branch_address(etm_context_t *ctx)
 628 {
 629         int retval;
 630         u8 packet;
 631         int shift = 0;
 632         int apo;
 633         int i;
 634
 635         /* quit analysis if less than two cycles are left in the trace
 636          * because we can't extract the APO */
 637         if (ctx->data_index > (ctx->trace_depth - 2))
 638                 return -1;
 639
 640         /* a BE could be output during an APO cycle, skip the current
 641          * and continue with the new one */
 642         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 643                 return 1;
 644         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 645                 return 2;
 646
 647         /* address packet offset encoded in the next two cycles' pipestat bits */
 648         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 649         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 650
 651         /* count number of tracesync cycles between current pipe_index and data_index
 652          * i.e. the number of tracesyncs that data_index already passed by
 653          * to subtract them from the APO */
 654         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 655         {
 656                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 657                         apo--;
 658         }
 659
 660         /* extract up to four 7-bit packets */
 661         do {
 662                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 663                         return -1;
 664                 ctx->last_branch &= ~(0x7f << shift);
 665                 ctx->last_branch |= (packet & 0x7f) << shift;
 666                 shift += 7;
 667         } while ((packet & 0x80) && (shift < 28));
 668
 669         /* one last packet holding 4 bits of the address, plus the branch reason code */
 670         if ((shift == 28) && (packet & 0x80))
 671         {
 672                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 673                         return -1;
 674                 ctx->last_branch &= 0x0fffffff;
 675                 ctx->last_branch |= (packet & 0x0f) << 28;
 676                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 677                 shift += 4;
 678         }
 679         else
 680         {
 681                 ctx->last_branch_reason = 0;
 682         }
 683
 684         if (shift == 32)
 685         {
 686                 ctx->pc_ok = 1;
 687         }
 688
 689         /* if a full address was output, we might have branched into Jazelle state */
 690         if ((shift == 32) && (packet & 0x80))
 691         {
 692                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 693         }
 694         else
 695         {
 696                 /* if we didn't branch into Jazelle state, the current processor state is
 697                  * encoded in bit 0 of the branch target address */
 698                 if (ctx->last_branch & 0x1)
 699                 {
 700                         ctx->core_state = ARMV4_5_STATE_THUMB;
 701                         ctx->last_branch &= ~0x1;
 702                 }
 703                 else
 704                 {
 705                         ctx->core_state = ARMV4_5_STATE_ARM;
 706                         ctx->last_branch &= ~0x3;
 707                 }
 708         }
 709
 710         return 0;
 711 }
 712
 713 int etmv1_data(etm_context_t *ctx, int size, u32 *data)
 714 {
 715         int j;
 716         u8 buf[4];
 717         int retval;
 718
 719         for (j = 0; j < size; j++)
 720         {
 721                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 722                         return -1;
 723         }
 724
 725         if (size == 8)
 726         {
 727                 LOG_ERROR("TODO: add support for 64-bit values");
 728                 return -1;
 729         }
 730         else if (size == 4)
 731                 *data = target_buffer_get_u32(ctx->target, buf);
 732         else if (size == 2)
 733                 *data = target_buffer_get_u16(ctx->target, buf);
 734         else if (size == 1)
 735                 *data = buf[0];
 736         else
 737                 return -1;
 738
 739         return 0;
 740 }
 741
 742 int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 743 {
 744         int retval;
 745         arm_instruction_t instruction;
 746
 747         /* read the trace data if it wasn't read already */
 748         if (ctx->trace_depth == 0)
 749                 ctx->capture_driver->read_trace(ctx);
 750
 751         /* start at the beginning of the captured trace */
 752         ctx->pipe_index = 0;
 753         ctx->data_index = 0;
 754         ctx->data_half = 0;
 755
 756         /* neither the PC nor the data pointer are valid */
 757         ctx->pc_ok = 0;
 758         ctx->ptr_ok = 0;
 759
 760         while (ctx->pipe_index < ctx->trace_depth)
 761         {
 762                 u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 763                 u32 next_pc = ctx->current_pc;
 764                 u32 old_data_index = ctx->data_index;
 765                 u32 old_data_half = ctx->data_half;
 766                 u32 old_index = ctx->pipe_index;
 767                 u32 last_instruction = ctx->last_instruction;
 768                 u32 cycles = 0;
 769                 int current_pc_ok = ctx->pc_ok;
 770
 771                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 772                 {
 773                         command_print(cmd_ctx, "--- trigger ---");
 774                 }
 775
 776                 /* instructions execute in IE/D or BE/D cycles */
 777                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 778                         ctx->last_instruction = ctx->pipe_index;
 779
 780                 /* if we don't have a valid pc skip until we reach an indirect branch */
 781                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 782                 {
 783                         ctx->pipe_index++;
 784                         continue;
 785                 }
 786
 787                 /* any indirect branch could have interrupted instruction flow
 788                  * - the branch reason code could indicate a trace discontinuity
 789                  * - a branch to the exception vectors indicates an exception
 790                  */
 791                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 792                 {
 793                         /* backup current data index, to be able to consume the branch address
 794                          * before examining data address and values
 795                          */
 796                         old_data_index = ctx->data_index;
 797                         old_data_half = ctx->data_half;
 798
 799                         ctx->last_instruction = ctx->pipe_index;
 800
 801                         if ((retval = etmv1_branch_address(ctx)) != 0)
 802                         {
 803                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 804                                  * quit analysing the trace */
 805                                 if (retval < 0)
 806                                         break;
 807
 808                                 /* a positive return values means the current branch was abandoned,
 809                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 810                                  */
 811                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 812                                 ctx->pipe_index += retval;
 813                                 continue;
 814                         }
 815
 816                         /* skip over APO cycles */
 817                         ctx->pipe_index += 2;
 818
 819                         switch (ctx->last_branch_reason)
 820                         {
 821                                 case 0x0:       /* normal PC change */
 822                                         next_pc = ctx->last_branch;
 823                                         break;
 824                                 case 0x1:       /* tracing enabled */
 825                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
 826                                         ctx->current_pc = ctx->last_branch;
 827                                         ctx->pipe_index++;
 828                                         continue;
 829                                         break;
 830                                 case 0x2:       /* trace restarted after FIFO overflow */
 831                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
 832                                         ctx->current_pc = ctx->last_branch;
 833                                         ctx->pipe_index++;
 834                                         continue;
 835                                         break;
 836                                 case 0x3:       /* exit from debug state */
 837                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
 838                                         ctx->current_pc = ctx->last_branch;
 839                                         ctx->pipe_index++;
 840                                         continue;
 841                                         break;
 842                                 case 0x4:       /* periodic synchronization point */
 843                                         next_pc = ctx->last_branch;
 844                                         /* if we had no valid PC prior to this synchronization point,
 845                                          * we have to move on with the next trace cycle
 846                                          */
 847                                         if (!current_pc_ok)
 848                                         {
 849                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
 850                                                 ctx->current_pc = next_pc;
 851                                                 ctx->pipe_index++;
 852                                                 continue;
 853                                         }
 854                                         break;
 855                                 default:        /* reserved */
 856                                         LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
 857                                         exit(-1);
 858                                         break;
 859                         }
 860
 861                         /* if we got here the branch was a normal PC change
 862                          * (or a periodic synchronization point, which means the same for that matter)
 863                          * if we didn't accquire a complete PC continue with the next cycle
 864                          */
 865                         if (!ctx->pc_ok)
 866                                 continue;
 867
 868                         /* indirect branch to the exception vector means an exception occured */
 869                         if (((ctx->last_branch >= 0x0) && (ctx->last_branch <= 0x20))
 870                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 871                         {
 872                                 if ((ctx->last_branch & 0xff) == 0x10)
 873                                 {
 874                                         command_print(cmd_ctx, "data abort");
 875                                 }
 876                                 else
 877                                 {
 878                                         command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
 879                                         ctx->current_pc = ctx->last_branch;
 880                                         ctx->pipe_index++;
 881                                         continue;
 882                                 }
 883                         }
 884                 }
 885
 886                 /* an instruction was executed (or not, depending on the condition flags)
 887                  * retrieve it from the image for displaying */
 888                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
 889                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
 890                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
 891                 {
 892                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
 893                         {
 894                                 /* can't continue tracing with no image available */
 895                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
 896                                 {
 897                                         return retval;
 898                                 }
 899                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
 900                                 {
 901                                         /* TODO: handle incomplete images
 902                                          * for now we just quit the analsysis*/
 903                                         return retval;
 904                                 }
 905                         }
 906
 907                         cycles = old_index - last_instruction;
 908                 }
 909
 910                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
 911                 {
 912                         u32 new_data_index = ctx->data_index;
 913                         u32 new_data_half = ctx->data_half;
 914
 915                         /* in case of a branch with data, the branch target address was consumed before
 916                          * we temporarily go back to the saved data index */
 917                         if (pipestat == STAT_BD)
 918                         {
 919                                 ctx->data_index = old_data_index;
 920                                 ctx->data_half = old_data_half;
 921                         }
 922
 923                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
 924                         {
 925                                 u8 packet;
 926                                 int shift = 0;
 927
 928                                 do {
 929                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 930                                                 return ERROR_ETM_ANALYSIS_FAILED;
 931                                         ctx->last_ptr &= ~(0x7f << shift);
 932                                         ctx->last_ptr |= (packet & 0x7f) << shift;
 933                                         shift += 7;
 934                                 } while ((packet & 0x80) && (shift < 32));
 935
 936                                 if (shift >= 32)
 937                                         ctx->ptr_ok = 1;
 938
 939                                 if (ctx->ptr_ok)
 940                                 {
 941                                         command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
 942                                 }
 943                         }
 944
 945                         if (ctx->tracemode & ETMV1_TRACE_DATA)
 946                         {
 947                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
 948                                 {
 949                                         int i;
 950                                         for (i = 0; i < 16; i++)
 951                                         {
 952                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
 953                                                 {
 954                                                         u32 data;
 955                                                         if (etmv1_data(ctx, 4, &data) != 0)
 956                                                                 return ERROR_ETM_ANALYSIS_FAILED;
 957                                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 958                                                 }
 959                                         }
 960                                 }
 961                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
 962                                 {
 963                                         u32 data;
 964                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
 965                                                 return ERROR_ETM_ANALYSIS_FAILED;
 966                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 967                                 }
 968                         }
 969
 970                         /* restore data index after consuming BD address and data */
 971                         if (pipestat == STAT_BD)
 972                         {
 973                                 ctx->data_index = new_data_index;
 974                                 ctx->data_half = new_data_half;
 975                         }
 976                 }
 977
 978                 /* adjust PC */
 979                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 980                 {
 981                         if (((instruction.type == ARM_B) ||
 982                                 (instruction.type == ARM_BL) ||
 983                                 (instruction.type == ARM_BLX)) &&
 984                                 (instruction.info.b_bl_bx_blx.target_address != -1))
 985                         {
 986                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
 987                         }
 988                         else
 989                         {
 990                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 991                         }
 992                 }
 993                 else if (pipestat == STAT_IN)
 994                 {
 995                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 996                 }
 997
 998                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
 999                 {
1000                         char cycles_text[32] = "";
1001
1002                         /* if the trace was captured with cycle accurate tracing enabled,
1003                          * output the number of cycles since the last executed instruction
1004                          */
1005                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1006                         {
1007                                 snprintf(cycles_text, 32, " (%i %s)",
1008                                         cycles,
1009                                         (cycles == 1) ? "cycle" : "cycles");
1010                         }
1011
1012                         command_print(cmd_ctx, "%s%s%s",
1013                                 instruction.text,
1014                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1015                                 cycles_text);
1016
1017                         ctx->current_pc = next_pc;
1018
1019                         /* packets for an instruction don't start on or before the preceding
1020                          * functional pipestat (i.e. other than WT or TD)
1021                          */
1022                         if (ctx->data_index <= ctx->pipe_index)
1023                         {
1024                                 ctx->data_index = ctx->pipe_index + 1;
1025                                 ctx->data_half = 0;
1026                         }
1027                 }
1028
1029                 ctx->pipe_index += 1;
1030         }
1031
1032         return ERROR_OK;
1033 }
1034
1035 int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1036 {
1037         target_t *target;
1038         armv4_5_common_t *armv4_5;
1039         arm7_9_common_t *arm7_9;
1040         etmv1_tracemode_t tracemode;
1041
1042         target = get_current_target(cmd_ctx);
1043
1044         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1045         {
1046                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1047                 return ERROR_OK;
1048         }
1049
1050         if (!arm7_9->etm_ctx)
1051         {
1052                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1053                 return ERROR_OK;
1054         }
1055
1056         tracemode = arm7_9->etm_ctx->tracemode;
1057
1058         if (argc == 4)
1059         {
1060                 if (strcmp(args[0], "none") == 0)
1061                 {
1062                         tracemode = ETMV1_TRACE_NONE;
1063                 }
1064                 else if (strcmp(args[0], "data") == 0)
1065                 {
1066                         tracemode = ETMV1_TRACE_DATA;
1067                 }
1068                 else if (strcmp(args[0], "address") == 0)
1069                 {
1070                         tracemode = ETMV1_TRACE_ADDR;
1071                 }
1072                 else if (strcmp(args[0], "all") == 0)
1073                 {
1074                         tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1075                 }
1076                 else
1077                 {
1078                         command_print(cmd_ctx, "invalid option '%s'", args[0]);
1079                         return ERROR_OK;
1080                 }
1081
1082                 switch (strtol(args[1], NULL, 0))
1083                 {
1084                         case 0:
1085                                 tracemode |= ETMV1_CONTEXTID_NONE;
1086                                 break;
1087                         case 8:
1088                                 tracemode |= ETMV1_CONTEXTID_8;
1089                                 break;
1090                         case 16:
1091                                 tracemode |= ETMV1_CONTEXTID_16;
1092                                 break;
1093                         case 32:
1094                                 tracemode |= ETMV1_CONTEXTID_32;
1095                                 break;
1096                         default:
1097                                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1098                                 return ERROR_OK;
1099                 }
1100
1101                 if (strcmp(args[2], "enable") == 0)
1102                 {
1103                         tracemode |= ETMV1_CYCLE_ACCURATE;
1104                 }
1105                 else if (strcmp(args[2], "disable") == 0)
1106                 {
1107                         tracemode |= 0;
1108                 }
1109                 else
1110                 {
1111                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1112                         return ERROR_OK;
1113                 }
1114
1115                 if (strcmp(args[3], "enable") == 0)
1116                 {
1117                         tracemode |= ETMV1_BRANCH_OUTPUT;
1118                 }
1119                 else if (strcmp(args[3], "disable") == 0)
1120                 {
1121                         tracemode |= 0;
1122                 }
1123                 else
1124                 {
1125                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1126                         return ERROR_OK;
1127                 }
1128         }
1129         else if (argc != 0)
1130         {
1131                 command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1132                 return ERROR_OK;
1133         }
1134
1135         command_print(cmd_ctx, "current tracemode configuration:");
1136
1137         switch (tracemode & ETMV1_TRACE_MASK)
1138         {
1139                 case ETMV1_TRACE_NONE:
1140                         command_print(cmd_ctx, "data tracing: none");
1141                         break;
1142                 case ETMV1_TRACE_DATA:
1143                         command_print(cmd_ctx, "data tracing: data only");
1144                         break;
1145                 case ETMV1_TRACE_ADDR:
1146                         command_print(cmd_ctx, "data tracing: address only");
1147                         break;
1148                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1149                         command_print(cmd_ctx, "data tracing: address and data");
1150                         break;
1151         }
1152
1153         switch (tracemode & ETMV1_CONTEXTID_MASK)
1154         {
1155                 case ETMV1_CONTEXTID_NONE:
1156                         command_print(cmd_ctx, "contextid tracing: none");
1157                         break;
1158                 case ETMV1_CONTEXTID_8:
1159                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1160                         break;
1161                 case ETMV1_CONTEXTID_16:
1162                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1163                         break;
1164                 case ETMV1_CONTEXTID_32:
1165                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1166                         break;
1167         }
1168
1169         if (tracemode & ETMV1_CYCLE_ACCURATE)
1170         {
1171                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1172         }
1173         else
1174         {
1175                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1176         }
1177
1178         if (tracemode & ETMV1_BRANCH_OUTPUT)
1179         {
1180                 command_print(cmd_ctx, "full branch address output enabled");
1181         }
1182         else
1183         {
1184                 command_print(cmd_ctx, "full branch address output disabled");
1185         }
1186
1187         /* only update ETM_CTRL register if tracemode changed */
1188         if (arm7_9->etm_ctx->tracemode != tracemode)
1189         {
1190                 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1191
1192                 etm_get_reg(etm_ctrl_reg);
1193
1194                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1195                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1196                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1197                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1198                 etm_store_reg(etm_ctrl_reg);
1199
1200                 arm7_9->etm_ctx->tracemode = tracemode;
1201
1202                 /* invalidate old trace data */
1203                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1204                 if (arm7_9->etm_ctx->trace_depth > 0)
1205                 {
1206                         free(arm7_9->etm_ctx->trace_data);
1207                         arm7_9->etm_ctx->trace_data = NULL;
1208                 }
1209                 arm7_9->etm_ctx->trace_depth = 0;
1210         }
1211
1212         return ERROR_OK;
1213 }
1214
1215 int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1216 {
1217         target_t *target;
1218         armv4_5_common_t *armv4_5;
1219         arm7_9_common_t *arm7_9;
1220         etm_portmode_t portmode = 0x0;
1221         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1222         int i;
1223
1224         if (argc != 5)
1225         {
1226                 LOG_ERROR("incomplete 'etm config <target> <port_width> <port_mode> <clocking> <capture_driver>' command");
1227                 exit(-1);
1228         }
1229
1230         target = get_target_by_num(strtoul(args[0], NULL, 0));
1231
1232         if (!target)
1233         {
1234                 LOG_ERROR("target number '%s' not defined", args[0]);
1235                 exit(-1);
1236         }
1237
1238         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1239         {
1240                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1241                 return ERROR_OK;
1242         }
1243
1244         switch (strtoul(args[1], NULL, 0))
1245         {
1246                 case 4:
1247                         portmode |= ETM_PORT_4BIT;
1248                         break;
1249                 case 8:
1250                         portmode |= ETM_PORT_8BIT;
1251                         break;
1252                 case 16:
1253                         portmode |= ETM_PORT_16BIT;
1254                         break;
1255                 default:
1256                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1257                         return ERROR_OK;
1258         }
1259
1260         if (strcmp("normal", args[2]) == 0)
1261         {
1262                 portmode |= ETM_PORT_NORMAL;
1263         }
1264         else if (strcmp("multiplexed", args[2]) == 0)
1265         {
1266                 portmode |= ETM_PORT_MUXED;
1267         }
1268         else if (strcmp("demultiplexed", args[2]) == 0)
1269         {
1270                 portmode |= ETM_PORT_DEMUXED;
1271         }
1272         else
1273         {
1274                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1275                 return ERROR_OK;
1276         }
1277
1278         if (strcmp("half", args[3]) == 0)
1279         {
1280                 portmode |= ETM_PORT_HALF_CLOCK;
1281         }
1282         else if (strcmp("full", args[3]) == 0)
1283         {
1284                 portmode |= ETM_PORT_FULL_CLOCK;
1285         }
1286         else
1287         {
1288                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1289                 return ERROR_OK;
1290         }
1291
1292         for (i=0; etm_capture_drivers[i]; i++)
1293         {
1294                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1295                 {
1296                         if (etm_capture_drivers[i]->register_commands(cmd_ctx) != ERROR_OK)
1297                         {
1298                                 free(etm_ctx);
1299                                 exit(-1);
1300                         }
1301
1302                         etm_ctx->capture_driver = etm_capture_drivers[i];
1303
1304                         break;
1305                 }
1306         }
1307
1308         if (!etm_capture_drivers[i])
1309         {
1310                 /* no supported capture driver found, don't register an ETM */
1311                 free(etm_ctx);
1312                 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1313                 return ERROR_OK;
1314         }
1315
1316         etm_ctx->target = target;
1317         etm_ctx->trigger_percent = 50;
1318         etm_ctx->trace_data = NULL;
1319         etm_ctx->trace_depth = 0;
1320         etm_ctx->portmode = portmode;
1321         etm_ctx->tracemode = 0x0;
1322         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1323         etm_ctx->image = NULL;
1324         etm_ctx->pipe_index = 0;
1325         etm_ctx->data_index = 0;
1326         etm_ctx->current_pc = 0x0;
1327         etm_ctx->pc_ok = 0;
1328         etm_ctx->last_branch = 0x0;
1329         etm_ctx->last_branch_reason = 0x0;
1330         etm_ctx->last_ptr = 0x0;
1331         etm_ctx->ptr_ok = 0x0;
1332         etm_ctx->context_id = 0x0;
1333         etm_ctx->last_instruction = 0;
1334
1335         arm7_9->etm_ctx = etm_ctx;
1336
1337         etm_register_user_commands(cmd_ctx);
1338
1339         return ERROR_OK;
1340 }
1341
1342 int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1343 {
1344         target_t *target;
1345         armv4_5_common_t *armv4_5;
1346         arm7_9_common_t *arm7_9;
1347         reg_t *etm_config_reg;
1348         reg_t *etm_sys_config_reg;
1349
1350         int max_port_size;
1351
1352         target = get_current_target(cmd_ctx);
1353
1354         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1355         {
1356                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1357                 return ERROR_OK;
1358         }
1359
1360         if (!arm7_9->etm_ctx)
1361         {
1362                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1363                 return ERROR_OK;
1364         }
1365
1366         etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
1367         etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
1368
1369         etm_get_reg(etm_config_reg);
1370         command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
1371         command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
1372         command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
1373         command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
1374         command_print(cmd_ctx, "sequencer %spresent",
1375                         (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
1376         command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
1377         command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
1378         command_print(cmd_ctx, "FIFO full %spresent",
1379                         (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
1380         command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
1381
1382         etm_get_reg(etm_sys_config_reg);
1383
1384         switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1385         {
1386                 case 0:
1387                         max_port_size = 4;
1388                         break;
1389                 case 1:
1390                         max_port_size = 8;
1391                         break;
1392                 case 2:
1393                         max_port_size = 16;
1394                         break;
1395                 default:
1396                         LOG_ERROR("Illegal max_port_size");
1397                         exit(-1);
1398         }
1399         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1400
1401         command_print(cmd_ctx, "half-rate clocking %ssupported",
1402                         (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1403         command_print(cmd_ctx, "full-rate clocking %ssupported",
1404                         (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1405         command_print(cmd_ctx, "normal trace format %ssupported",
1406                         (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1407         command_print(cmd_ctx, "multiplex trace format %ssupported",
1408                         (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1409         command_print(cmd_ctx, "demultiplex trace format %ssupported",
1410                         (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1411         command_print(cmd_ctx, "FIFO full %ssupported",
1412                         (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1413
1414         return ERROR_OK;
1415 }
1416
1417 int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1418 {
1419         target_t *target;
1420         armv4_5_common_t *armv4_5;
1421         arm7_9_common_t *arm7_9;
1422         trace_status_t trace_status;
1423
1424         target = get_current_target(cmd_ctx);
1425
1426         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1427         {
1428                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1429                 return ERROR_OK;
1430         }
1431
1432         if (!arm7_9->etm_ctx)
1433         {
1434                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1435                 return ERROR_OK;
1436         }
1437
1438         trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1439
1440         if (trace_status == TRACE_IDLE)
1441         {
1442                 command_print(cmd_ctx, "tracing is idle");
1443         }
1444         else
1445         {
1446                 static char *completed = " completed";
1447                 static char *running = " is running";
1448                 static char *overflowed = ", trace overflowed";
1449                 static char *triggered = ", trace triggered";
1450
1451                 command_print(cmd_ctx, "trace collection%s%s%s",
1452                         (trace_status & TRACE_RUNNING) ? running : completed,
1453                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1454                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1455
1456                 if (arm7_9->etm_ctx->trace_depth > 0)
1457                 {
1458                         command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
1459                 }
1460         }
1461
1462         return ERROR_OK;
1463 }
1464
1465 int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1466 {
1467         target_t *target;
1468         armv4_5_common_t *armv4_5;
1469         arm7_9_common_t *arm7_9;
1470         etm_context_t *etm_ctx;
1471
1472         if (argc < 1)
1473         {
1474                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1475                 return ERROR_OK;
1476         }
1477
1478         target = get_current_target(cmd_ctx);
1479
1480         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1481         {
1482                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1483                 return ERROR_OK;
1484         }
1485
1486         if (!(etm_ctx = arm7_9->etm_ctx))
1487         {
1488                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1489                 return ERROR_OK;
1490         }
1491
1492         if (etm_ctx->image)
1493         {
1494                 image_close(etm_ctx->image);
1495                 free(etm_ctx->image);
1496                 command_print(cmd_ctx, "previously loaded image found and closed");
1497         }
1498
1499         etm_ctx->image = malloc(sizeof(image_t));
1500         etm_ctx->image->base_address_set = 0;
1501         etm_ctx->image->start_address_set = 0;
1502
1503         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1504         if (argc >= 2)
1505         {
1506                 etm_ctx->image->base_address_set = 1;
1507                 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1508         }
1509         else
1510         {
1511                 etm_ctx->image->base_address_set = 0;
1512         }
1513
1514         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1515         {
1516                 free(etm_ctx->image);
1517                 etm_ctx->image = NULL;
1518                 return ERROR_OK;
1519         }
1520
1521         return ERROR_OK;
1522 }
1523
1524 int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1525 {
1526         fileio_t file;
1527         target_t *target;
1528         armv4_5_common_t *armv4_5;
1529         arm7_9_common_t *arm7_9;
1530         etm_context_t *etm_ctx;
1531         int i;
1532
1533         if (argc != 1)
1534         {
1535                 command_print(cmd_ctx, "usage: etm dump <file>");
1536                 return ERROR_OK;
1537         }
1538
1539         target = get_current_target(cmd_ctx);
1540
1541         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1542         {
1543                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1544                 return ERROR_OK;
1545         }
1546
1547         if (!(etm_ctx = arm7_9->etm_ctx))
1548         {
1549                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1550                 return ERROR_OK;
1551         }
1552
1553         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1554         {
1555                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1556                 return ERROR_OK;
1557         }
1558
1559         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1560         {
1561                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1562                 command_print(cmd_ctx, "trace capture not completed");
1563                 return ERROR_OK;
1564         }
1565
1566         /* read the trace data if it wasn't read already */
1567         if (etm_ctx->trace_depth == 0)
1568                 etm_ctx->capture_driver->read_trace(etm_ctx);
1569
1570         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1571         {
1572                 return ERROR_OK;
1573         }
1574
1575         fileio_write_u32(&file, etm_ctx->capture_status);
1576         fileio_write_u32(&file, etm_ctx->portmode);
1577         fileio_write_u32(&file, etm_ctx->tracemode);
1578         fileio_write_u32(&file, etm_ctx->trace_depth);
1579
1580         for (i = 0; i < etm_ctx->trace_depth; i++)
1581         {
1582                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1583                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1584                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1585         }
1586
1587         fileio_close(&file);
1588
1589         return ERROR_OK;
1590 }
1591
1592 int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1593 {
1594         fileio_t file;
1595         target_t *target;
1596         armv4_5_common_t *armv4_5;
1597         arm7_9_common_t *arm7_9;
1598         etm_context_t *etm_ctx;
1599         int i;
1600
1601         if (argc != 1)
1602         {
1603                 command_print(cmd_ctx, "usage: etm load <file>");
1604                 return ERROR_OK;
1605         }
1606
1607         target = get_current_target(cmd_ctx);
1608
1609         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1610         {
1611                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1612                 return ERROR_OK;
1613         }
1614
1615         if (!(etm_ctx = arm7_9->etm_ctx))
1616         {
1617                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1618                 return ERROR_OK;
1619         }
1620
1621         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1622         {
1623                 command_print(cmd_ctx, "trace capture running, stop first");
1624                 return ERROR_OK;
1625         }
1626
1627         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1628         {
1629                 return ERROR_OK;
1630         }
1631
1632         if (file.size % 4)
1633         {
1634                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1635                 return ERROR_OK;
1636         }
1637
1638         if (etm_ctx->trace_depth > 0)
1639         {
1640                 free(etm_ctx->trace_data);
1641         }
1642
1643         fileio_read_u32(&file, &etm_ctx->capture_status);
1644         fileio_read_u32(&file, &etm_ctx->portmode);
1645         fileio_read_u32(&file, &etm_ctx->tracemode);
1646         fileio_read_u32(&file, &etm_ctx->trace_depth);
1647
1648         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1649
1650         for (i = 0; i < etm_ctx->trace_depth; i++)
1651         {
1652                 u32 pipestat, packet, flags;
1653                 fileio_read_u32(&file, &pipestat);
1654                 fileio_read_u32(&file, &packet);
1655                 fileio_read_u32(&file, &flags);
1656                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1657                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1658                 etm_ctx->trace_data[i].flags = flags;
1659         }
1660
1661         fileio_close(&file);
1662
1663         return ERROR_OK;
1664 }
1665
1666 int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1667 {
1668         target_t *target;
1669         armv4_5_common_t *armv4_5;
1670         arm7_9_common_t *arm7_9;
1671         etm_context_t *etm_ctx;
1672
1673         target = get_current_target(cmd_ctx);
1674
1675         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1676         {
1677                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1678                 return ERROR_OK;
1679         }
1680
1681         if (!(etm_ctx = arm7_9->etm_ctx))
1682         {
1683                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1684                 return ERROR_OK;
1685         }
1686
1687         if (argc > 0)
1688         {
1689                 u32 new_value = strtoul(args[0], NULL, 0);
1690
1691                 if ((new_value < 2) || (new_value > 100))
1692                 {
1693                         command_print(cmd_ctx, "valid settings are 2% to 100%");
1694                 }
1695                 else
1696                 {
1697                         etm_ctx->trigger_percent = new_value;
1698                 }
1699         }
1700
1701         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
1702
1703         return ERROR_OK;
1704 }
1705
1706 int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1707 {
1708         target_t *target;
1709         armv4_5_common_t *armv4_5;
1710         arm7_9_common_t *arm7_9;
1711         etm_context_t *etm_ctx;
1712         reg_t *etm_ctrl_reg;
1713
1714         target = get_current_target(cmd_ctx);
1715
1716         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1717         {
1718                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1719                 return ERROR_OK;
1720         }
1721
1722         if (!(etm_ctx = arm7_9->etm_ctx))
1723         {
1724                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1725                 return ERROR_OK;
1726         }
1727
1728         /* invalidate old tracing data */
1729         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1730         if (arm7_9->etm_ctx->trace_depth > 0)
1731         {
1732                 free(arm7_9->etm_ctx->trace_data);
1733                 arm7_9->etm_ctx->trace_data = NULL;
1734         }
1735         arm7_9->etm_ctx->trace_depth = 0;
1736
1737         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1738         etm_get_reg(etm_ctrl_reg);
1739
1740         /* Clear programming bit (10), set port selection bit (11) */
1741         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1742
1743         etm_store_reg(etm_ctrl_reg);
1744         jtag_execute_queue();
1745
1746         etm_ctx->capture_driver->start_capture(etm_ctx);
1747
1748         return ERROR_OK;
1749 }
1750
1751 int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1752 {
1753         target_t *target;
1754         armv4_5_common_t *armv4_5;
1755         arm7_9_common_t *arm7_9;
1756         etm_context_t *etm_ctx;
1757         reg_t *etm_ctrl_reg;
1758
1759         target = get_current_target(cmd_ctx);
1760
1761         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1762         {
1763                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1764                 return ERROR_OK;
1765         }
1766
1767         if (!(etm_ctx = arm7_9->etm_ctx))
1768         {
1769                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1770                 return ERROR_OK;
1771         }
1772
1773         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1774         etm_get_reg(etm_ctrl_reg);
1775
1776         /* Set programming bit (10), clear port selection bit (11) */
1777         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1778
1779         etm_store_reg(etm_ctrl_reg);
1780         jtag_execute_queue();
1781
1782         etm_ctx->capture_driver->stop_capture(etm_ctx);
1783
1784         return ERROR_OK;
1785 }
1786
1787 int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1788 {
1789         target_t *target;
1790         armv4_5_common_t *armv4_5;
1791         arm7_9_common_t *arm7_9;
1792         etm_context_t *etm_ctx;
1793         int retval;
1794
1795         target = get_current_target(cmd_ctx);
1796
1797         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1798         {
1799                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1800                 return ERROR_OK;
1801         }
1802
1803         if (!(etm_ctx = arm7_9->etm_ctx))
1804         {
1805                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1806                 return ERROR_OK;
1807         }
1808
1809         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1810         {
1811                 switch(retval)
1812                 {
1813                         case ERROR_ETM_ANALYSIS_FAILED:
1814                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1815                                 break;
1816                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1817                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1818                                 break;
1819                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
1820                                 command_print(cmd_ctx, "no image available for trace analysis");
1821                                 break;
1822                         default:
1823                                 command_print(cmd_ctx, "unknown error: %i", retval);
1824                 }
1825         }
1826
1827         return ERROR_OK;
1828 }
1829
1830 int etm_register_commands(struct command_context_s *cmd_ctx)
1831 {
1832         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1833
1834         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, NULL);
1835
1836         return ERROR_OK;
1837 }
1838
1839 int etm_register_user_commands(struct command_context_s *cmd_ctx)
1840 {
1841         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1842                 COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
1843
1844         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
1845                 COMMAND_EXEC, "display info about the current target's ETM");
1846
1847         register_command(cmd_ctx, etm_cmd, "trigger_percent <percent>", handle_etm_trigger_percent_command,
1848                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1849         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1850                 COMMAND_EXEC, "display current target's ETM status");
1851         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1852                 COMMAND_EXEC, "start ETM trace collection");
1853         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1854                 COMMAND_EXEC, "stop ETM trace collection");
1855
1856         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1857                 COMMAND_EXEC, "anaylze collected ETM trace");
1858
1859         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1860                 COMMAND_EXEC, "load image from <file> [base address]");
1861
1862         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1863                 COMMAND_EXEC, "dump captured trace data <file>");
1864         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1865                 COMMAND_EXEC, "load trace data for analysis <file>");
1866
1867         return ERROR_OK;
1868 }