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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm.h"
  25 #include "etm.h"
  26 #include "etb.h"
  27 #include "image.h"
  28 #include "arm_disassembler.h"
  29 #include "register.h"
  30 #include "etm_dummy.h"
  31 #include "oocd_trace.h"
  32
  33
  34 /*
  35  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  36  *
  37  * ETM modules collect instruction and/or data trace information, compress
  38  * it, and transfer it to a debugging host through either a (buffered) trace
  39  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  40  *
  41  * There are several generations of these modules.  Original versions have
  42  * JTAG access through a dedicated scan chain.  Recent versions have added
  43  * access via coprocessor instructions, memory addressing, and the ARM Debug
  44  * Interface v5 (ADIv5); and phased out direct JTAG access.
  45  *
  46  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  47  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  48  * implying non-JTAG connectivity options.
  49  *
  50  * Relevant documentation includes:
  51  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  52  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  53  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  54  */
  55
  56 enum {
  57         RO,                             /* read/only */
  58         WO,                             /* write/only */
  59         RW,                             /* read/write */
  60 };
  61
  62 struct etm_reg_info {
  63         uint8_t         addr;
  64         uint8_t         size;           /* low-N of 32 bits */
  65         uint8_t         mode;           /* RO, WO, RW */
  66         uint8_t         bcd_vers;       /* 1.0, 2.0, etc */
  67         char            *name;
  68 };
  69
  70 /*
  71  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  72  * (Or on some processors, through coprocessor operations.)
  73  * Newer versions of ETM make some W/O registers R/W, and
  74  * provide definitions for some previously-unused bits.
  75  */
  76
  77 /* core registers used to version/configure the ETM */
  78 static const struct etm_reg_info etm_core[] = {
  79         /* NOTE: we "know" the order here ... */
  80         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  81         { ETM_ID, 32, RO, 0x20, "ETM_id", },
  82 };
  83
  84 /* basic registers that are always there given the right ETM version */
  85 static const struct etm_reg_info etm_basic[] = {
  86         /* ETM Trace Registers */
  87         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  88         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  89         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
  90         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
  91         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
  92
  93         /* TraceEnable configuration */
  94         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  95         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  96         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
  97         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
  98
  99         /* ViewData configuration (data trace) */
 100         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
 101         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
 102         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
 103         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
 104
 105         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 106
 107         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
 108         { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
 109         { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
 110         { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
 111         { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
 112 };
 113
 114 static const struct etm_reg_info etm_fifofull[] = {
 115         /* FIFOFULL configuration */
 116         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
 117         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
 118 };
 119
 120 static const struct etm_reg_info etm_addr_comp[] = {
 121         /* Address comparator register pairs */
 122 #define ADDR_COMPARATOR(i) \
 123                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
 124                                 "ETM_addr_" #i "_comparator_value", }, \
 125                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
 126                                 "ETM_addr_" #i "_access_type", }
 127         ADDR_COMPARATOR(1),
 128         ADDR_COMPARATOR(2),
 129         ADDR_COMPARATOR(3),
 130         ADDR_COMPARATOR(4),
 131         ADDR_COMPARATOR(5),
 132         ADDR_COMPARATOR(6),
 133         ADDR_COMPARATOR(7),
 134         ADDR_COMPARATOR(8),
 135
 136         ADDR_COMPARATOR(9),
 137         ADDR_COMPARATOR(10),
 138         ADDR_COMPARATOR(11),
 139         ADDR_COMPARATOR(12),
 140         ADDR_COMPARATOR(13),
 141         ADDR_COMPARATOR(14),
 142         ADDR_COMPARATOR(15),
 143         ADDR_COMPARATOR(16),
 144 #undef ADDR_COMPARATOR
 145 };
 146
 147 static const struct etm_reg_info etm_data_comp[] = {
 148         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 149 #define DATA_COMPARATOR(i) \
 150                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
 151                                 "ETM_data_" #i "_comparator_value", }, \
 152                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
 153                                 "ETM_data_" #i "_comparator_mask", }
 154         DATA_COMPARATOR(1),
 155         DATA_COMPARATOR(2),
 156         DATA_COMPARATOR(3),
 157         DATA_COMPARATOR(4),
 158         DATA_COMPARATOR(5),
 159         DATA_COMPARATOR(6),
 160         DATA_COMPARATOR(7),
 161         DATA_COMPARATOR(8),
 162 #undef DATA_COMPARATOR
 163 };
 164
 165 static const struct etm_reg_info etm_counters[] = {
 166 #define ETM_COUNTER(i) \
 167                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
 168                                 "ETM_counter_" #i "_reload_value", }, \
 169                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
 170                                 "ETM_counter_" #i "_enable", }, \
 171                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
 172                                 "ETM_counter_" #i "_reload_event", }, \
 173                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
 174                                 "ETM_counter_" #i "_value", }
 175         ETM_COUNTER(1),
 176         ETM_COUNTER(2),
 177         ETM_COUNTER(3),
 178         ETM_COUNTER(4),
 179 #undef ETM_COUNTER
 180 };
 181
 182 static const struct etm_reg_info etm_sequencer[] = {
 183 #define ETM_SEQ(i) \
 184                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 185                                 "ETM_sequencer_event" #i, }
 186         ETM_SEQ(0),                             /* 1->2 */
 187         ETM_SEQ(1),                             /* 2->1 */
 188         ETM_SEQ(2),                             /* 2->3 */
 189         ETM_SEQ(3),                             /* 3->1 */
 190         ETM_SEQ(4),                             /* 3->2 */
 191         ETM_SEQ(5),                             /* 1->3 */
 192 #undef ETM_SEQ
 193         /* 0x66 reserved */
 194         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
 195 };
 196
 197 static const struct etm_reg_info etm_outputs[] = {
 198 #define ETM_OUTPUT(i) \
 199                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
 200                                 "ETM_external_output" #i, }
 201
 202         ETM_OUTPUT(1),
 203         ETM_OUTPUT(2),
 204         ETM_OUTPUT(3),
 205         ETM_OUTPUT(4),
 206 #undef ETM_OUTPUT
 207 };
 208
 209 #if 0
 210         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 211
 212         /* Context ID Comparators */
 213         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
 214         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
 215         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
 216         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
 217 #endif
 218
 219 static int etm_get_reg(struct reg *reg);
 220 static int etm_read_reg_w_check(struct reg *reg,
 221                 uint8_t* check_value, uint8_t* check_mask);
 222 static int etm_register_user_commands(struct command_context *cmd_ctx);
 223 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
 224 static int etm_write_reg(struct reg *reg, uint32_t value);
 225
 226 static const struct reg_arch_type etm_scan6_type = {
 227         .get = etm_get_reg,
 228         .set = etm_set_reg_w_exec,
 229 };
 230
 231 /* Look up register by ID ... most ETM instances only
 232  * support a subset of the possible registers.
 233  */
 234 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
 235 {
 236         struct reg_cache *cache = etm_ctx->reg_cache;
 237         unsigned i;
 238
 239         for (i = 0; i < cache->num_regs; i++) {
 240                 struct etm_reg *reg = cache->reg_list[i].arch_info;
 241
 242                 if (reg->reg_info->addr == id)
 243                         return &cache->reg_list[i];
 244         }
 245
 246         /* caller asking for nonexistent register is a bug! */
 247         /* REVISIT say which of the N targets was involved */
 248         LOG_ERROR("ETM: register 0x%02x not available", id);
 249         return NULL;
 250 }
 251
 252 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
 253                 struct reg_cache *cache, struct etm_reg *ereg,
 254                 const struct etm_reg_info *r, unsigned nreg)
 255 {
 256         struct reg *reg = cache->reg_list;
 257
 258         reg += cache->num_regs;
 259         ereg += cache->num_regs;
 260
 261         /* add up to "nreg" registers from "r", if supported by this
 262          * version of the ETM, to the specified cache.
 263          */
 264         for (; nreg--; r++) {
 265
 266                 /* this ETM may be too old to have some registers */
 267                 if (r->bcd_vers > bcd_vers)
 268                         continue;
 269
 270                 reg->name = r->name;
 271                 reg->size = r->size;
 272                 reg->value = &ereg->value;
 273                 reg->arch_info = ereg;
 274                 reg->type = &etm_scan6_type;
 275                 reg++;
 276                 cache->num_regs++;
 277
 278                 ereg->reg_info = r;
 279                 ereg->jtag_info = jtag_info;
 280                 ereg++;
 281         }
 282 }
 283
 284 struct reg_cache *etm_build_reg_cache(struct target *target,
 285                 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
 286 {
 287         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 288         struct reg *reg_list = NULL;
 289         struct etm_reg *arch_info = NULL;
 290         unsigned bcd_vers, config;
 291
 292         /* the actual registers are kept in two arrays */
 293         reg_list = calloc(128, sizeof(struct reg));
 294         arch_info = calloc(128, sizeof(struct etm_reg));
 295
 296         /* fill in values for the reg cache */
 297         reg_cache->name = "etm registers";
 298         reg_cache->next = NULL;
 299         reg_cache->reg_list = reg_list;
 300         reg_cache->num_regs = 0;
 301
 302         /* add ETM_CONFIG, then parse its values to see
 303          * which other registers exist in this ETM
 304          */
 305         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 306                         etm_core, 1);
 307
 308         etm_get_reg(reg_list);
 309         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 310         config = etm_ctx->config;
 311
 312         /* figure ETM version then add base registers */
 313         if (config & (1 << 31)) {
 314                 bcd_vers = 0x20;
 315                 LOG_WARNING("ETMv2+ support is incomplete");
 316
 317                 /* REVISIT more registers may exist; they may now be
 318                  * readable; more register bits have defined meanings;
 319                  * don't presume trace start/stop support is present;
 320                  * and include any context ID comparator registers.
 321                  */
 322                 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
 323                                 etm_core + 1, 1);
 324                 etm_get_reg(reg_list + 1);
 325                 etm_ctx->id = buf_get_u32(
 326                                 (void *)&arch_info[1].value, 0, 32);
 327                 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
 328                 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
 329
 330         } else {
 331                 switch (config >> 28) {
 332                 case 7:
 333                 case 5:
 334                 case 3:
 335                         bcd_vers = 0x13;
 336                         break;
 337                 case 4:
 338                 case 2:
 339                         bcd_vers = 0x12;
 340                         break;
 341                 case 1:
 342                         bcd_vers = 0x11;
 343                         break;
 344                 case 0:
 345                         bcd_vers = 0x10;
 346                         break;
 347                 default:
 348                         LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 349                         goto fail;
 350                 }
 351         }
 352         etm_ctx->bcd_vers = bcd_vers;
 353         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 354
 355         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 356                         etm_basic, ARRAY_SIZE(etm_basic));
 357
 358         /* address and data comparators; counters; outputs */
 359         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 360                         etm_addr_comp, 4 * (0x0f & (config >> 0)));
 361         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 362                         etm_data_comp, 2 * (0x0f & (config >> 4)));
 363         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 364                         etm_counters, 4 * (0x07 & (config >> 13)));
 365         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 366                         etm_outputs, (0x07 & (config >> 20)));
 367
 368         /* FIFOFULL presence is optional
 369          * REVISIT for ETMv1.2 and later, don't bother adding this
 370          * unless ETM_SYS_CONFIG says it's also *supported* ...
 371          */
 372         if (config & (1 << 23))
 373                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 374                                 etm_fifofull, ARRAY_SIZE(etm_fifofull));
 375
 376         /* sequencer is optional (for state-dependant triggering) */
 377         if (config & (1 << 16))
 378                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 379                                 etm_sequencer, ARRAY_SIZE(etm_sequencer));
 380
 381         /* REVISIT could realloc and likely save half the memory
 382          * in the two chunks we allocated...
 383          */
 384
 385         /* the ETM might have an ETB connected */
 386         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 387         {
 388                 struct etb *etb = etm_ctx->capture_driver_priv;
 389
 390                 if (!etb)
 391                 {
 392                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 393                         goto fail;
 394                 }
 395
 396                 reg_cache->next = etb_build_reg_cache(etb);
 397
 398                 etb->reg_cache = reg_cache->next;
 399         }
 400
 401         etm_ctx->reg_cache = reg_cache;
 402         return reg_cache;
 403
 404 fail:
 405         free(reg_cache);
 406         free(reg_list);
 407         free(arch_info);
 408         return NULL;
 409 }
 410
 411 static int etm_read_reg(struct reg *reg)
 412 {
 413         return etm_read_reg_w_check(reg, NULL, NULL);
 414 }
 415
 416 static int etm_store_reg(struct reg *reg)
 417 {
 418         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 419 }
 420
 421 int etm_setup(struct target *target)
 422 {
 423         int retval;
 424         uint32_t etm_ctrl_value;
 425         struct arm *arm = target_to_arm(target);
 426         struct etm_context *etm_ctx = arm->etm;
 427         struct reg *etm_ctrl_reg;
 428
 429         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 430         if (!etm_ctrl_reg)
 431                 return ERROR_OK;
 432
 433         /* initialize some ETM control register settings */
 434         etm_get_reg(etm_ctrl_reg);
 435         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
 436
 437         /* clear the ETM powerdown bit (0) */
 438         etm_ctrl_value &= ~0x1;
 439
 440         /* configure port width (21,6:4), mode (13,17:16) and
 441          * for older modules clocking (13)
 442          */
 443         etm_ctrl_value = (etm_ctrl_value
 444                         & ~ETM_PORT_WIDTH_MASK
 445                         & ~ETM_PORT_MODE_MASK
 446                         & ~ETM_PORT_CLOCK_MASK)
 447                 | etm_ctx->portmode;
 448
 449         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 450         etm_store_reg(etm_ctrl_reg);
 451
 452         if ((retval = jtag_execute_queue()) != ERROR_OK)
 453                 return retval;
 454
 455         /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
 456          * verify that those width and mode settings are OK ...
 457          */
 458
 459         if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 460         {
 461                 LOG_ERROR("ETM capture driver initialization failed");
 462                 return retval;
 463         }
 464         return ERROR_OK;
 465 }
 466
 467 static int etm_get_reg(struct reg *reg)
 468 {
 469         int retval;
 470
 471         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 472         {
 473                 LOG_ERROR("BUG: error scheduling etm register read");
 474                 return retval;
 475         }
 476
 477         if ((retval = jtag_execute_queue()) != ERROR_OK)
 478         {
 479                 LOG_ERROR("register read failed");
 480                 return retval;
 481         }
 482
 483         return ERROR_OK;
 484 }
 485
 486 static int etm_read_reg_w_check(struct reg *reg,
 487                 uint8_t* check_value, uint8_t* check_mask)
 488 {
 489         struct etm_reg *etm_reg = reg->arch_info;
 490         const struct etm_reg_info *r = etm_reg->reg_info;
 491         uint8_t reg_addr = r->addr & 0x7f;
 492         struct scan_field fields[3];
 493
 494         if (etm_reg->reg_info->mode == WO) {
 495                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 496                 return ERROR_INVALID_ARGUMENTS;
 497         }
 498
 499         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 500
 501         jtag_set_end_state(TAP_IDLE);
 502         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 503         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 504
 505         fields[0].tap = etm_reg->jtag_info->tap;
 506         fields[0].num_bits = 32;
 507         fields[0].out_value = reg->value;
 508         fields[0].in_value = NULL;
 509         fields[0].check_value = NULL;
 510         fields[0].check_mask = NULL;
 511
 512         fields[1].tap = etm_reg->jtag_info->tap;
 513         fields[1].num_bits = 7;
 514         fields[1].out_value = malloc(1);
 515         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 516         fields[1].in_value = NULL;
 517         fields[1].check_value = NULL;
 518         fields[1].check_mask = NULL;
 519
 520         fields[2].tap = etm_reg->jtag_info->tap;
 521         fields[2].num_bits = 1;
 522         fields[2].out_value = malloc(1);
 523         buf_set_u32(fields[2].out_value, 0, 1, 0);
 524         fields[2].in_value = NULL;
 525         fields[2].check_value = NULL;
 526         fields[2].check_mask = NULL;
 527
 528         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 529
 530         fields[0].in_value = reg->value;
 531         fields[0].check_value = check_value;
 532         fields[0].check_mask = check_mask;
 533
 534         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 535
 536         free(fields[1].out_value);
 537         free(fields[2].out_value);
 538
 539         return ERROR_OK;
 540 }
 541
 542 static int etm_set_reg(struct reg *reg, uint32_t value)
 543 {
 544         int retval;
 545
 546         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 547         {
 548                 LOG_ERROR("BUG: error scheduling etm register write");
 549                 return retval;
 550         }
 551
 552         buf_set_u32(reg->value, 0, reg->size, value);
 553         reg->valid = 1;
 554         reg->dirty = 0;
 555
 556         return ERROR_OK;
 557 }
 558
 559 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 560 {
 561         int retval;
 562
 563         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 564
 565         if ((retval = jtag_execute_queue()) != ERROR_OK)
 566         {
 567                 LOG_ERROR("register write failed");
 568                 return retval;
 569         }
 570         return ERROR_OK;
 571 }
 572
 573 static int etm_write_reg(struct reg *reg, uint32_t value)
 574 {
 575         struct etm_reg *etm_reg = reg->arch_info;
 576         const struct etm_reg_info *r = etm_reg->reg_info;
 577         uint8_t reg_addr = r->addr & 0x7f;
 578         struct scan_field fields[3];
 579
 580         if (etm_reg->reg_info->mode == RO) {
 581                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 582                 return ERROR_INVALID_ARGUMENTS;
 583         }
 584
 585         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 586
 587         jtag_set_end_state(TAP_IDLE);
 588         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 589         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 590
 591         fields[0].tap = etm_reg->jtag_info->tap;
 592         fields[0].num_bits = 32;
 593         uint8_t tmp1[4];
 594         fields[0].out_value = tmp1;
 595         buf_set_u32(fields[0].out_value, 0, 32, value);
 596         fields[0].in_value = NULL;
 597
 598         fields[1].tap = etm_reg->jtag_info->tap;
 599         fields[1].num_bits = 7;
 600         uint8_t tmp2;
 601         fields[1].out_value = &tmp2;
 602         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 603         fields[1].in_value = NULL;
 604
 605         fields[2].tap = etm_reg->jtag_info->tap;
 606         fields[2].num_bits = 1;
 607         uint8_t tmp3;
 608         fields[2].out_value = &tmp3;
 609         buf_set_u32(fields[2].out_value, 0, 1, 1);
 610         fields[2].in_value = NULL;
 611
 612         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 613
 614         return ERROR_OK;
 615 }
 616
 617
 618 /* ETM trace analysis functionality */
 619
 620 static struct etm_capture_driver *etm_capture_drivers[] =
 621 {
 622         &etb_capture_driver,
 623         &etm_dummy_capture_driver,
 624 #if BUILD_OOCD_TRACE == 1
 625         &oocd_trace_capture_driver,
 626 #endif
 627         NULL
 628 };
 629
 630 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
 631 {
 632         int i;
 633         int section = -1;
 634         size_t size_read;
 635         uint32_t opcode;
 636         int retval;
 637
 638         if (!ctx->image)
 639                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 640
 641         /* search for the section the current instruction belongs to */
 642         for (i = 0; i < ctx->image->num_sections; i++)
 643         {
 644                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 645                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 646                 {
 647                         section = i;
 648                         break;
 649                 }
 650         }
 651
 652         if (section == -1)
 653         {
 654                 /* current instruction couldn't be found in the image */
 655                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 656         }
 657
 658         if (ctx->core_state == ARM_STATE_ARM)
 659         {
 660                 uint8_t buf[4];
 661                 if ((retval = image_read_section(ctx->image, section,
 662                         ctx->current_pc - ctx->image->sections[section].base_address,
 663                         4, buf, &size_read)) != ERROR_OK)
 664                 {
 665                         LOG_ERROR("error while reading instruction: %i", retval);
 666                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 667                 }
 668                 opcode = target_buffer_get_u32(ctx->target, buf);
 669                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 670         }
 671         else if (ctx->core_state == ARM_STATE_THUMB)
 672         {
 673                 uint8_t buf[2];
 674                 if ((retval = image_read_section(ctx->image, section,
 675                         ctx->current_pc - ctx->image->sections[section].base_address,
 676                         2, buf, &size_read)) != ERROR_OK)
 677                 {
 678                         LOG_ERROR("error while reading instruction: %i", retval);
 679                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 680                 }
 681                 opcode = target_buffer_get_u16(ctx->target, buf);
 682                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 683         }
 684         else if (ctx->core_state == ARM_STATE_JAZELLE)
 685         {
 686                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 687                 return ERROR_FAIL;
 688         }
 689         else
 690         {
 691                 LOG_ERROR("BUG: unknown core state encountered");
 692                 return ERROR_FAIL;
 693         }
 694
 695         return ERROR_OK;
 696 }
 697
 698 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
 699 {
 700         while (ctx->data_index < ctx->trace_depth)
 701         {
 702                 /* if the caller specified an address packet offset, skip until the
 703                  * we reach the n-th cycle marked with tracesync */
 704                 if (apo > 0)
 705                 {
 706                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 707                                 apo--;
 708
 709                         if (apo > 0)
 710                         {
 711                                 ctx->data_index++;
 712                                 ctx->data_half = 0;
 713                         }
 714                         continue;
 715                 }
 716
 717                 /* no tracedata output during a TD cycle
 718                  * or in a trigger cycle */
 719                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 720                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 721                 {
 722                         ctx->data_index++;
 723                         ctx->data_half = 0;
 724                         continue;
 725                 }
 726
 727                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 728                 {
 729                         if (ctx->data_half == 0)
 730                         {
 731                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 732                                 ctx->data_half = 1;
 733                         }
 734                         else
 735                         {
 736                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 737                                 ctx->data_half = 0;
 738                                 ctx->data_index++;
 739                         }
 740                 }
 741                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 742                 {
 743                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 744                         ctx->data_index++;
 745                 }
 746                 else
 747                 {
 748                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 749                         if (ctx->data_index > (ctx->trace_depth - 2))
 750                                 return -1;
 751
 752                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 753                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 754                         ctx->data_index += 2;
 755                 }
 756
 757                 return 0;
 758         }
 759
 760         return -1;
 761 }
 762
 763 static int etmv1_branch_address(struct etm_context *ctx)
 764 {
 765         int retval;
 766         uint8_t packet;
 767         int shift = 0;
 768         int apo;
 769         uint32_t i;
 770
 771         /* quit analysis if less than two cycles are left in the trace
 772          * because we can't extract the APO */
 773         if (ctx->data_index > (ctx->trace_depth - 2))
 774                 return -1;
 775
 776         /* a BE could be output during an APO cycle, skip the current
 777          * and continue with the new one */
 778         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 779                 return 1;
 780         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 781                 return 2;
 782
 783         /* address packet offset encoded in the next two cycles' pipestat bits */
 784         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 785         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 786
 787         /* count number of tracesync cycles between current pipe_index and data_index
 788          * i.e. the number of tracesyncs that data_index already passed by
 789          * to subtract them from the APO */
 790         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 791         {
 792                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 793                         apo--;
 794         }
 795
 796         /* extract up to four 7-bit packets */
 797         do {
 798                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 799                         return -1;
 800                 ctx->last_branch &= ~(0x7f << shift);
 801                 ctx->last_branch |= (packet & 0x7f) << shift;
 802                 shift += 7;
 803         } while ((packet & 0x80) && (shift < 28));
 804
 805         /* one last packet holding 4 bits of the address, plus the branch reason code */
 806         if ((shift == 28) && (packet & 0x80))
 807         {
 808                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 809                         return -1;
 810                 ctx->last_branch &= 0x0fffffff;
 811                 ctx->last_branch |= (packet & 0x0f) << 28;
 812                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 813                 shift += 4;
 814         }
 815         else
 816         {
 817                 ctx->last_branch_reason = 0;
 818         }
 819
 820         if (shift == 32)
 821         {
 822                 ctx->pc_ok = 1;
 823         }
 824
 825         /* if a full address was output, we might have branched into Jazelle state */
 826         if ((shift == 32) && (packet & 0x80))
 827         {
 828                 ctx->core_state = ARM_STATE_JAZELLE;
 829         }
 830         else
 831         {
 832                 /* if we didn't branch into Jazelle state, the current processor state is
 833                  * encoded in bit 0 of the branch target address */
 834                 if (ctx->last_branch & 0x1)
 835                 {
 836                         ctx->core_state = ARM_STATE_THUMB;
 837                         ctx->last_branch &= ~0x1;
 838                 }
 839                 else
 840                 {
 841                         ctx->core_state = ARM_STATE_ARM;
 842                         ctx->last_branch &= ~0x3;
 843                 }
 844         }
 845
 846         return 0;
 847 }
 848
 849 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
 850 {
 851         int j;
 852         uint8_t buf[4];
 853         int retval;
 854
 855         for (j = 0; j < size; j++)
 856         {
 857                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 858                         return -1;
 859         }
 860
 861         if (size == 8)
 862         {
 863                 LOG_ERROR("TODO: add support for 64-bit values");
 864                 return -1;
 865         }
 866         else if (size == 4)
 867                 *data = target_buffer_get_u32(ctx->target, buf);
 868         else if (size == 2)
 869                 *data = target_buffer_get_u16(ctx->target, buf);
 870         else if (size == 1)
 871                 *data = buf[0];
 872         else
 873                 return -1;
 874
 875         return 0;
 876 }
 877
 878 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
 879 {
 880         int retval;
 881         struct arm_instruction instruction;
 882
 883         /* read the trace data if it wasn't read already */
 884         if (ctx->trace_depth == 0)
 885                 ctx->capture_driver->read_trace(ctx);
 886
 887         /* start at the beginning of the captured trace */
 888         ctx->pipe_index = 0;
 889         ctx->data_index = 0;
 890         ctx->data_half = 0;
 891
 892         /* neither the PC nor the data pointer are valid */
 893         ctx->pc_ok = 0;
 894         ctx->ptr_ok = 0;
 895
 896         while (ctx->pipe_index < ctx->trace_depth)
 897         {
 898                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 899                 uint32_t next_pc = ctx->current_pc;
 900                 uint32_t old_data_index = ctx->data_index;
 901                 uint32_t old_data_half = ctx->data_half;
 902                 uint32_t old_index = ctx->pipe_index;
 903                 uint32_t last_instruction = ctx->last_instruction;
 904                 uint32_t cycles = 0;
 905                 int current_pc_ok = ctx->pc_ok;
 906
 907                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 908                 {
 909                         command_print(cmd_ctx, "--- trigger ---");
 910                 }
 911
 912                 /* instructions execute in IE/D or BE/D cycles */
 913                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 914                         ctx->last_instruction = ctx->pipe_index;
 915
 916                 /* if we don't have a valid pc skip until we reach an indirect branch */
 917                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 918                 {
 919                         ctx->pipe_index++;
 920                         continue;
 921                 }
 922
 923                 /* any indirect branch could have interrupted instruction flow
 924                  * - the branch reason code could indicate a trace discontinuity
 925                  * - a branch to the exception vectors indicates an exception
 926                  */
 927                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 928                 {
 929                         /* backup current data index, to be able to consume the branch address
 930                          * before examining data address and values
 931                          */
 932                         old_data_index = ctx->data_index;
 933                         old_data_half = ctx->data_half;
 934
 935                         ctx->last_instruction = ctx->pipe_index;
 936
 937                         if ((retval = etmv1_branch_address(ctx)) != 0)
 938                         {
 939                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 940                                  * quit analysing the trace */
 941                                 if (retval < 0)
 942                                         break;
 943
 944                                 /* a positive return values means the current branch was abandoned,
 945                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 946                                  */
 947                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 948                                 ctx->pipe_index += retval;
 949                                 continue;
 950                         }
 951
 952                         /* skip over APO cycles */
 953                         ctx->pipe_index += 2;
 954
 955                         switch (ctx->last_branch_reason)
 956                         {
 957                                 case 0x0:       /* normal PC change */
 958                                         next_pc = ctx->last_branch;
 959                                         break;
 960                                 case 0x1:       /* tracing enabled */
 961                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 962                                         ctx->current_pc = ctx->last_branch;
 963                                         ctx->pipe_index++;
 964                                         continue;
 965                                         break;
 966                                 case 0x2:       /* trace restarted after FIFO overflow */
 967                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 968                                         ctx->current_pc = ctx->last_branch;
 969                                         ctx->pipe_index++;
 970                                         continue;
 971                                         break;
 972                                 case 0x3:       /* exit from debug state */
 973                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 974                                         ctx->current_pc = ctx->last_branch;
 975                                         ctx->pipe_index++;
 976                                         continue;
 977                                         break;
 978                                 case 0x4:       /* periodic synchronization point */
 979                                         next_pc = ctx->last_branch;
 980                                         /* if we had no valid PC prior to this synchronization point,
 981                                          * we have to move on with the next trace cycle
 982                                          */
 983                                         if (!current_pc_ok)
 984                                         {
 985                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 986                                                 ctx->current_pc = next_pc;
 987                                                 ctx->pipe_index++;
 988                                                 continue;
 989                                         }
 990                                         break;
 991                                 default:        /* reserved */
 992                                         LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
 993                                         return ERROR_FAIL;
 994                         }
 995
 996                         /* if we got here the branch was a normal PC change
 997                          * (or a periodic synchronization point, which means the same for that matter)
 998                          * if we didn't accquire a complete PC continue with the next cycle
 999                          */
1000                         if (!ctx->pc_ok)
1001                                 continue;
1002
1003                         /* indirect branch to the exception vector means an exception occured */
1004                         if ((ctx->last_branch <= 0x20)
1005                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1006                         {
1007                                 if ((ctx->last_branch & 0xff) == 0x10)
1008                                 {
1009                                         command_print(cmd_ctx, "data abort");
1010                                 }
1011                                 else
1012                                 {
1013                                         command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1014                                         ctx->current_pc = ctx->last_branch;
1015                                         ctx->pipe_index++;
1016                                         continue;
1017                                 }
1018                         }
1019                 }
1020
1021                 /* an instruction was executed (or not, depending on the condition flags)
1022                  * retrieve it from the image for displaying */
1023                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1024                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1025                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1026                 {
1027                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1028                         {
1029                                 /* can't continue tracing with no image available */
1030                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1031                                 {
1032                                         return retval;
1033                                 }
1034                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1035                                 {
1036                                         /* TODO: handle incomplete images
1037                                          * for now we just quit the analsysis*/
1038                                         return retval;
1039                                 }
1040                         }
1041
1042                         cycles = old_index - last_instruction;
1043                 }
1044
1045                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1046                 {
1047                         uint32_t new_data_index = ctx->data_index;
1048                         uint32_t new_data_half = ctx->data_half;
1049
1050                         /* in case of a branch with data, the branch target address was consumed before
1051                          * we temporarily go back to the saved data index */
1052                         if (pipestat == STAT_BD)
1053                         {
1054                                 ctx->data_index = old_data_index;
1055                                 ctx->data_half = old_data_half;
1056                         }
1057
1058                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
1059                         {
1060                                 uint8_t packet;
1061                                 int shift = 0;
1062
1063                                 do {
1064                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1065                                                 return ERROR_ETM_ANALYSIS_FAILED;
1066                                         ctx->last_ptr &= ~(0x7f << shift);
1067                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1068                                         shift += 7;
1069                                 } while ((packet & 0x80) && (shift < 32));
1070
1071                                 if (shift >= 32)
1072                                         ctx->ptr_ok = 1;
1073
1074                                 if (ctx->ptr_ok)
1075                                 {
1076                                         command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1077                                 }
1078                         }
1079
1080                         if (ctx->tracemode & ETMV1_TRACE_DATA)
1081                         {
1082                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1083                                 {
1084                                         int i;
1085                                         for (i = 0; i < 16; i++)
1086                                         {
1087                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
1088                                                 {
1089                                                         uint32_t data;
1090                                                         if (etmv1_data(ctx, 4, &data) != 0)
1091                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1092                                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1093                                                 }
1094                                         }
1095                                 }
1096                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1097                                 {
1098                                         uint32_t data;
1099                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1100                                                 return ERROR_ETM_ANALYSIS_FAILED;
1101                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1102                                 }
1103                         }
1104
1105                         /* restore data index after consuming BD address and data */
1106                         if (pipestat == STAT_BD)
1107                         {
1108                                 ctx->data_index = new_data_index;
1109                                 ctx->data_half = new_data_half;
1110                         }
1111                 }
1112
1113                 /* adjust PC */
1114                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1115                 {
1116                         if (((instruction.type == ARM_B) ||
1117                              (instruction.type == ARM_BL) ||
1118                              (instruction.type == ARM_BLX)) &&
1119                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1120                         {
1121                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1122                         }
1123                         else
1124                         {
1125                                 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1126                         }
1127                 }
1128                 else if (pipestat == STAT_IN)
1129                 {
1130                         next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1131                 }
1132
1133                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1134                 {
1135                         char cycles_text[32] = "";
1136
1137                         /* if the trace was captured with cycle accurate tracing enabled,
1138                          * output the number of cycles since the last executed instruction
1139                          */
1140                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1141                         {
1142                                 snprintf(cycles_text, 32, " (%i %s)",
1143                                          (int)cycles,
1144                                         (cycles == 1) ? "cycle" : "cycles");
1145                         }
1146
1147                         command_print(cmd_ctx, "%s%s%s",
1148                                 instruction.text,
1149                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1150                                 cycles_text);
1151
1152                         ctx->current_pc = next_pc;
1153
1154                         /* packets for an instruction don't start on or before the preceding
1155                          * functional pipestat (i.e. other than WT or TD)
1156                          */
1157                         if (ctx->data_index <= ctx->pipe_index)
1158                         {
1159                                 ctx->data_index = ctx->pipe_index + 1;
1160                                 ctx->data_half = 0;
1161                         }
1162                 }
1163
1164                 ctx->pipe_index += 1;
1165         }
1166
1167         return ERROR_OK;
1168 }
1169
1170 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1171                 etmv1_tracemode_t *mode)
1172 {
1173         etmv1_tracemode_t tracemode;
1174
1175         /* what parts of data access are traced? */
1176         if (strcmp(CMD_ARGV[0], "none") == 0)
1177                 tracemode = ETMV1_TRACE_NONE;
1178         else if (strcmp(CMD_ARGV[0], "data") == 0)
1179                 tracemode = ETMV1_TRACE_DATA;
1180         else if (strcmp(CMD_ARGV[0], "address") == 0)
1181                 tracemode = ETMV1_TRACE_ADDR;
1182         else if (strcmp(CMD_ARGV[0], "all") == 0)
1183                 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1184         else
1185         {
1186                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1187                 return ERROR_INVALID_ARGUMENTS;
1188         }
1189
1190         uint8_t context_id;
1191         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1192         switch (context_id)
1193         {
1194         case 0:
1195                 tracemode |= ETMV1_CONTEXTID_NONE;
1196                 break;
1197         case 8:
1198                 tracemode |= ETMV1_CONTEXTID_8;
1199                 break;
1200         case 16:
1201                 tracemode |= ETMV1_CONTEXTID_16;
1202                 break;
1203         case 32:
1204                 tracemode |= ETMV1_CONTEXTID_32;
1205                 break;
1206         default:
1207                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1208                 return ERROR_INVALID_ARGUMENTS;
1209         }
1210
1211         bool etmv1_cycle_accurate;
1212         COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1213         if (etmv1_cycle_accurate)
1214                 tracemode |= ETMV1_CYCLE_ACCURATE;
1215
1216         bool etmv1_branch_output;
1217         COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1218                 tracemode |= ETMV1_BRANCH_OUTPUT;
1219
1220         /* IGNORED:
1221          *  - CPRT tracing (coprocessor register transfers)
1222          *  - debug request (causes debug entry on trigger)
1223          *  - stall on FIFOFULL (preventing tracedata lossage)
1224          */
1225         *mode = tracemode;
1226
1227         return ERROR_OK;
1228 }
1229
1230 COMMAND_HANDLER(handle_etm_tracemode_command)
1231 {
1232         struct target *target = get_current_target(CMD_CTX);
1233         struct arm *arm = target_to_arm(target);
1234         struct etm_context *etm;
1235
1236         if (!is_arm(arm)) {
1237                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1238                 return ERROR_FAIL;
1239         }
1240
1241         etm = arm->etm;
1242         if (!etm) {
1243                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1244                 return ERROR_FAIL;
1245         }
1246
1247         etmv1_tracemode_t tracemode = etm->tracemode;
1248
1249         switch (CMD_ARGC)
1250         {
1251         case 0:
1252                 break;
1253         case 4:
1254                 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode);
1255                 break;
1256         default:
1257                 command_print(CMD_CTX, "usage: configure trace mode "
1258                                 "<none | data | address | all> "
1259                                 "<context id bits> <cycle accurate> <branch output>");
1260                 return ERROR_FAIL;
1261         }
1262
1263         /**
1264          * todo: fail if parameters were invalid for this hardware,
1265          * or couldn't be written; display actual hardware state...
1266          */
1267
1268         command_print(CMD_CTX, "current tracemode configuration:");
1269
1270         switch (tracemode & ETMV1_TRACE_MASK)
1271         {
1272                 case ETMV1_TRACE_NONE:
1273                         command_print(CMD_CTX, "data tracing: none");
1274                         break;
1275                 case ETMV1_TRACE_DATA:
1276                         command_print(CMD_CTX, "data tracing: data only");
1277                         break;
1278                 case ETMV1_TRACE_ADDR:
1279                         command_print(CMD_CTX, "data tracing: address only");
1280                         break;
1281                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1282                         command_print(CMD_CTX, "data tracing: address and data");
1283                         break;
1284         }
1285
1286         switch (tracemode & ETMV1_CONTEXTID_MASK)
1287         {
1288                 case ETMV1_CONTEXTID_NONE:
1289                         command_print(CMD_CTX, "contextid tracing: none");
1290                         break;
1291                 case ETMV1_CONTEXTID_8:
1292                         command_print(CMD_CTX, "contextid tracing: 8 bit");
1293                         break;
1294                 case ETMV1_CONTEXTID_16:
1295                         command_print(CMD_CTX, "contextid tracing: 16 bit");
1296                         break;
1297                 case ETMV1_CONTEXTID_32:
1298                         command_print(CMD_CTX, "contextid tracing: 32 bit");
1299                         break;
1300         }
1301
1302         if (tracemode & ETMV1_CYCLE_ACCURATE)
1303         {
1304                 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1305         }
1306         else
1307         {
1308                 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1309         }
1310
1311         if (tracemode & ETMV1_BRANCH_OUTPUT)
1312         {
1313                 command_print(CMD_CTX, "full branch address output enabled");
1314         }
1315         else
1316         {
1317                 command_print(CMD_CTX, "full branch address output disabled");
1318         }
1319
1320         /* only update ETM_CTRL register if tracemode changed */
1321         if (etm->tracemode != tracemode)
1322         {
1323                 struct reg *etm_ctrl_reg;
1324
1325                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1326                 if (!etm_ctrl_reg)
1327                         return ERROR_FAIL;
1328
1329                 etm_get_reg(etm_ctrl_reg);
1330
1331                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1332                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1333                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1334                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1335                 etm_store_reg(etm_ctrl_reg);
1336
1337                 etm->tracemode = tracemode;
1338
1339                 /* invalidate old trace data */
1340                 etm->capture_status = TRACE_IDLE;
1341                 if (etm->trace_depth > 0)
1342                 {
1343                         free(etm->trace_data);
1344                         etm->trace_data = NULL;
1345                 }
1346                 etm->trace_depth = 0;
1347         }
1348
1349         return ERROR_OK;
1350 }
1351
1352 COMMAND_HANDLER(handle_etm_config_command)
1353 {
1354         struct target *target;
1355         struct arm *arm;
1356         etm_portmode_t portmode = 0x0;
1357         struct etm_context *etm_ctx;
1358         int i;
1359
1360         if (CMD_ARGC != 5)
1361                 return ERROR_COMMAND_SYNTAX_ERROR;
1362
1363         target = get_target(CMD_ARGV[0]);
1364         if (!target)
1365         {
1366                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1367                 return ERROR_FAIL;
1368         }
1369
1370         arm = target_to_arm(target);
1371         if (!is_arm(arm)) {
1372                 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1373                                 target_name(target),
1374                                 target_type_name(target));
1375                 return ERROR_FAIL;
1376         }
1377
1378         /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1379          * version we'll be using!! -- so we can't know how to validate
1380          * params yet.  "etm config" should likely be *AFTER* hookup...
1381          *
1382          *  - Many more widths might be supported ... and we can easily
1383          *    check whether our setting "took".
1384          *
1385          *  - The "clock" and "mode" bits are interpreted differently.
1386          *    See ARM IHI 0014O table 2-17 for the old behavior, and
1387          *    table 2-18 for the new.  With ETB it's best to specify
1388          *    "normal full" ...
1389          */
1390         uint8_t port_width;
1391         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1392         switch (port_width)
1393         {
1394                 /* before ETMv3.0 */
1395                 case 4:
1396                         portmode |= ETM_PORT_4BIT;
1397                         break;
1398                 case 8:
1399                         portmode |= ETM_PORT_8BIT;
1400                         break;
1401                 case 16:
1402                         portmode |= ETM_PORT_16BIT;
1403                         break;
1404                 /* ETMv3.0 and later*/
1405                 case 24:
1406                         portmode |= ETM_PORT_24BIT;
1407                         break;
1408                 case 32:
1409                         portmode |= ETM_PORT_32BIT;
1410                         break;
1411                 case 48:
1412                         portmode |= ETM_PORT_48BIT;
1413                         break;
1414                 case 64:
1415                         portmode |= ETM_PORT_64BIT;
1416                         break;
1417                 case 1:
1418                         portmode |= ETM_PORT_1BIT;
1419                         break;
1420                 case 2:
1421                         portmode |= ETM_PORT_2BIT;
1422                         break;
1423                 default:
1424                         command_print(CMD_CTX,
1425                                 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1426                         return ERROR_FAIL;
1427         }
1428
1429         if (strcmp("normal", CMD_ARGV[2]) == 0)
1430         {
1431                 portmode |= ETM_PORT_NORMAL;
1432         }
1433         else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1434         {
1435                 portmode |= ETM_PORT_MUXED;
1436         }
1437         else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1438         {
1439                 portmode |= ETM_PORT_DEMUXED;
1440         }
1441         else
1442         {
1443                 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1444                 return ERROR_FAIL;
1445         }
1446
1447         if (strcmp("half", CMD_ARGV[3]) == 0)
1448         {
1449                 portmode |= ETM_PORT_HALF_CLOCK;
1450         }
1451         else if (strcmp("full", CMD_ARGV[3]) == 0)
1452         {
1453                 portmode |= ETM_PORT_FULL_CLOCK;
1454         }
1455         else
1456         {
1457                 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1458                 return ERROR_FAIL;
1459         }
1460
1461         etm_ctx = calloc(1, sizeof(struct etm_context));
1462         if (!etm_ctx) {
1463                 LOG_DEBUG("out of memory");
1464                 return ERROR_FAIL;
1465         }
1466
1467         for (i = 0; etm_capture_drivers[i]; i++)
1468         {
1469                 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1470                 {
1471                         int retval = register_commands(CMD_CTX, NULL,
1472                                         etm_capture_drivers[i]->commands);
1473                         if (ERROR_OK != retval)
1474                         {
1475                                 free(etm_ctx);
1476                                 return retval;
1477                         }
1478
1479                         etm_ctx->capture_driver = etm_capture_drivers[i];
1480
1481                         break;
1482                 }
1483         }
1484
1485         if (!etm_capture_drivers[i])
1486         {
1487                 /* no supported capture driver found, don't register an ETM */
1488                 free(etm_ctx);
1489                 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1490                 return ERROR_FAIL;
1491         }
1492
1493         etm_ctx->target = target;
1494         etm_ctx->trigger_percent = 50;
1495         etm_ctx->trace_data = NULL;
1496         etm_ctx->portmode = portmode;
1497         etm_ctx->core_state = ARM_STATE_ARM;
1498
1499         arm->etm = etm_ctx;
1500
1501         return etm_register_user_commands(CMD_CTX);
1502 }
1503
1504 COMMAND_HANDLER(handle_etm_info_command)
1505 {
1506         struct target *target;
1507         struct arm *arm;
1508         struct etm_context *etm;
1509         struct reg *etm_sys_config_reg;
1510         int max_port_size;
1511         uint32_t config;
1512
1513         target = get_current_target(CMD_CTX);
1514         arm = target_to_arm(target);
1515         if (!is_arm(arm))
1516         {
1517                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1518                 return ERROR_FAIL;
1519         }
1520
1521         etm = arm->etm;
1522         if (!etm)
1523         {
1524                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1525                 return ERROR_FAIL;
1526         }
1527
1528         command_print(CMD_CTX, "ETM v%d.%d",
1529                         etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1530         command_print(CMD_CTX, "pairs of address comparators: %i",
1531                         (int) (etm->config >> 0) & 0x0f);
1532         command_print(CMD_CTX, "data comparators: %i",
1533                         (int) (etm->config >> 4) & 0x0f);
1534         command_print(CMD_CTX, "memory map decoders: %i",
1535                         (int) (etm->config >> 8) & 0x1f);
1536         command_print(CMD_CTX, "number of counters: %i",
1537                         (int) (etm->config >> 13) & 0x07);
1538         command_print(CMD_CTX, "sequencer %spresent",
1539                         (int) (etm->config & (1 << 16)) ? "" : "not ");
1540         command_print(CMD_CTX, "number of ext. inputs: %i",
1541                         (int) (etm->config >> 17) & 0x07);
1542         command_print(CMD_CTX, "number of ext. outputs: %i",
1543                         (int) (etm->config >> 20) & 0x07);
1544         command_print(CMD_CTX, "FIFO full %spresent",
1545                         (int) (etm->config & (1 << 23)) ? "" : "not ");
1546         if (etm->bcd_vers < 0x20)
1547                 command_print(CMD_CTX, "protocol version: %i",
1548                                 (int) (etm->config >> 28) & 0x07);
1549         else {
1550                 command_print(CMD_CTX,
1551                                 "coprocessor and memory access %ssupported",
1552                                 (etm->config & (1 << 26)) ? "" : "not ");
1553                 command_print(CMD_CTX, "trace start/stop %spresent",
1554                                 (etm->config & (1 << 26)) ? "" : "not ");
1555                 command_print(CMD_CTX, "number of context comparators: %i",
1556                                 (int) (etm->config >> 24) & 0x03);
1557         }
1558
1559         /* SYS_CONFIG isn't present before ETMv1.2 */
1560         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1561         if (!etm_sys_config_reg)
1562                 return ERROR_OK;
1563
1564         etm_get_reg(etm_sys_config_reg);
1565         config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1566
1567         LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1568
1569         max_port_size = config & 0x7;
1570         if (etm->bcd_vers >= 0x30)
1571                 max_port_size |= (config >> 6) & 0x08;
1572         switch (max_port_size)
1573         {
1574                 /* before ETMv3.0 */
1575                 case 0:
1576                         max_port_size = 4;
1577                         break;
1578                 case 1:
1579                         max_port_size = 8;
1580                         break;
1581                 case 2:
1582                         max_port_size = 16;
1583                         break;
1584                 /* ETMv3.0 and later*/
1585                 case 3:
1586                         max_port_size = 24;
1587                         break;
1588                 case 4:
1589                         max_port_size = 32;
1590                         break;
1591                 case 5:
1592                         max_port_size = 48;
1593                         break;
1594                 case 6:
1595                         max_port_size = 64;
1596                         break;
1597                 case 8:
1598                         max_port_size = 1;
1599                         break;
1600                 case 9:
1601                         max_port_size = 2;
1602                         break;
1603                 default:
1604                         LOG_ERROR("Illegal max_port_size");
1605                         return ERROR_FAIL;
1606         }
1607         command_print(CMD_CTX, "max. port size: %i", max_port_size);
1608
1609         if (etm->bcd_vers < 0x30) {
1610                 command_print(CMD_CTX, "half-rate clocking %ssupported",
1611                                 (config & (1 << 3)) ? "" : "not ");
1612                 command_print(CMD_CTX, "full-rate clocking %ssupported",
1613                                 (config & (1 << 4)) ? "" : "not ");
1614                 command_print(CMD_CTX, "normal trace format %ssupported",
1615                                 (config & (1 << 5)) ? "" : "not ");
1616                 command_print(CMD_CTX, "multiplex trace format %ssupported",
1617                                 (config & (1 << 6)) ? "" : "not ");
1618                 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1619                                 (config & (1 << 7)) ? "" : "not ");
1620         } else {
1621                 /* REVISIT show which size and format are selected ... */
1622                 command_print(CMD_CTX, "current port size %ssupported",
1623                                 (config & (1 << 10)) ? "" : "not ");
1624                 command_print(CMD_CTX, "current trace format %ssupported",
1625                                 (config & (1 << 11)) ? "" : "not ");
1626         }
1627         if (etm->bcd_vers >= 0x21)
1628                 command_print(CMD_CTX, "fetch comparisons %ssupported",
1629                                 (config & (1 << 17)) ? "not " : "");
1630         command_print(CMD_CTX, "FIFO full %ssupported",
1631                         (config & (1 << 8)) ? "" : "not ");
1632
1633         return ERROR_OK;
1634 }
1635
1636 COMMAND_HANDLER(handle_etm_status_command)
1637 {
1638         struct target *target;
1639         struct arm *arm;
1640         struct etm_context *etm;
1641         trace_status_t trace_status;
1642
1643         target = get_current_target(CMD_CTX);
1644         arm = target_to_arm(target);
1645         if (!is_arm(arm))
1646         {
1647                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1648                 return ERROR_FAIL;
1649         }
1650
1651         etm = arm->etm;
1652         if (!etm)
1653         {
1654                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1655                 return ERROR_FAIL;
1656         }
1657
1658         /* ETM status */
1659         if (etm->bcd_vers >= 0x11) {
1660                 struct reg *reg;
1661
1662                 reg = etm_reg_lookup(etm, ETM_STATUS);
1663                 if (!reg)
1664                         return ERROR_FAIL;
1665                 if (etm_get_reg(reg) == ERROR_OK) {
1666                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1667
1668                         command_print(CMD_CTX, "etm: %s%s%s%s",
1669                                 /* bit(1) == progbit */
1670                                 (etm->bcd_vers >= 0x12)
1671                                         ? ((s & (1 << 1))
1672                                                 ? "disabled" : "enabled")
1673                                         : "?",
1674                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1675                                         ? " triggered" : "",
1676                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1677                                         ? " start/stop" : "",
1678                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1679                                         ? " untraced-overflow" : "");
1680                 } /* else ignore and try showing trace port status */
1681         }
1682
1683         /* Trace Port Driver status */
1684         trace_status = etm->capture_driver->status(etm);
1685         if (trace_status == TRACE_IDLE)
1686         {
1687                 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1688         }
1689         else
1690         {
1691                 static char *completed = " completed";
1692                 static char *running = " is running";
1693                 static char *overflowed = ", overflowed";
1694                 static char *triggered = ", triggered";
1695
1696                 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1697                         etm->capture_driver->name,
1698                         (trace_status & TRACE_RUNNING) ? running : completed,
1699                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1700                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1701
1702                 if (etm->trace_depth > 0)
1703                 {
1704                         command_print(CMD_CTX, "%i frames of trace data read",
1705                                         (int)(etm->trace_depth));
1706                 }
1707         }
1708
1709         return ERROR_OK;
1710 }
1711
1712 COMMAND_HANDLER(handle_etm_image_command)
1713 {
1714         struct target *target;
1715         struct arm *arm;
1716         struct etm_context *etm_ctx;
1717
1718         if (CMD_ARGC < 1)
1719         {
1720                 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1721                 return ERROR_FAIL;
1722         }
1723
1724         target = get_current_target(CMD_CTX);
1725         arm = target_to_arm(target);
1726         if (!is_arm(arm))
1727         {
1728                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1729                 return ERROR_FAIL;
1730         }
1731
1732         etm_ctx = arm->etm;
1733         if (!etm_ctx)
1734         {
1735                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1736                 return ERROR_FAIL;
1737         }
1738
1739         if (etm_ctx->image)
1740         {
1741                 image_close(etm_ctx->image);
1742                 free(etm_ctx->image);
1743                 command_print(CMD_CTX, "previously loaded image found and closed");
1744         }
1745
1746         etm_ctx->image = malloc(sizeof(struct image));
1747         etm_ctx->image->base_address_set = 0;
1748         etm_ctx->image->start_address_set = 0;
1749
1750         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1751         if (CMD_ARGC >= 2)
1752         {
1753                 etm_ctx->image->base_address_set = 1;
1754                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], etm_ctx->image->base_address);
1755         }
1756         else
1757         {
1758                 etm_ctx->image->base_address_set = 0;
1759         }
1760
1761         if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1762         {
1763                 free(etm_ctx->image);
1764                 etm_ctx->image = NULL;
1765                 return ERROR_FAIL;
1766         }
1767
1768         return ERROR_OK;
1769 }
1770
1771 COMMAND_HANDLER(handle_etm_dump_command)
1772 {
1773         struct fileio file;
1774         struct target *target;
1775         struct arm *arm;
1776         struct etm_context *etm_ctx;
1777         uint32_t i;
1778
1779         if (CMD_ARGC != 1)
1780         {
1781                 command_print(CMD_CTX, "usage: etm dump <file>");
1782                 return ERROR_FAIL;
1783         }
1784
1785         target = get_current_target(CMD_CTX);
1786         arm = target_to_arm(target);
1787         if (!is_arm(arm))
1788         {
1789                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1790                 return ERROR_FAIL;
1791         }
1792
1793         etm_ctx = arm->etm;
1794         if (!etm_ctx)
1795         {
1796                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1797                 return ERROR_FAIL;
1798         }
1799
1800         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1801         {
1802                 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1803                 return ERROR_OK;
1804         }
1805
1806         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1807         {
1808                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1809                 command_print(CMD_CTX, "trace capture not completed");
1810                 return ERROR_FAIL;
1811         }
1812
1813         /* read the trace data if it wasn't read already */
1814         if (etm_ctx->trace_depth == 0)
1815                 etm_ctx->capture_driver->read_trace(etm_ctx);
1816
1817         if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1818         {
1819                 return ERROR_FAIL;
1820         }
1821
1822         fileio_write_u32(&file, etm_ctx->capture_status);
1823         fileio_write_u32(&file, etm_ctx->portmode);
1824         fileio_write_u32(&file, etm_ctx->tracemode);
1825         fileio_write_u32(&file, etm_ctx->trace_depth);
1826
1827         for (i = 0; i < etm_ctx->trace_depth; i++)
1828         {
1829                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1830                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1831                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1832         }
1833
1834         fileio_close(&file);
1835
1836         return ERROR_OK;
1837 }
1838
1839 COMMAND_HANDLER(handle_etm_load_command)
1840 {
1841         struct fileio file;
1842         struct target *target;
1843         struct arm *arm;
1844         struct etm_context *etm_ctx;
1845         uint32_t i;
1846
1847         if (CMD_ARGC != 1)
1848         {
1849                 command_print(CMD_CTX, "usage: etm load <file>");
1850                 return ERROR_FAIL;
1851         }
1852
1853         target = get_current_target(CMD_CTX);
1854         arm = target_to_arm(target);
1855         if (!is_arm(arm))
1856         {
1857                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1858                 return ERROR_FAIL;
1859         }
1860
1861         etm_ctx = arm->etm;
1862         if (!etm_ctx)
1863         {
1864                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1865                 return ERROR_FAIL;
1866         }
1867
1868         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1869         {
1870                 command_print(CMD_CTX, "trace capture running, stop first");
1871                 return ERROR_FAIL;
1872         }
1873
1874         if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1875         {
1876                 return ERROR_FAIL;
1877         }
1878
1879         if (file.size % 4)
1880         {
1881                 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1882                 fileio_close(&file);
1883                 return ERROR_FAIL;
1884         }
1885
1886         if (etm_ctx->trace_depth > 0)
1887         {
1888                 free(etm_ctx->trace_data);
1889                 etm_ctx->trace_data = NULL;
1890         }
1891
1892         {
1893           uint32_t tmp;
1894           fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1895           fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1896           fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1897           fileio_read_u32(&file, &etm_ctx->trace_depth);
1898         }
1899         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1900         if (etm_ctx->trace_data == NULL)
1901         {
1902                 command_print(CMD_CTX, "not enough memory to perform operation");
1903                 fileio_close(&file);
1904                 return ERROR_FAIL;
1905         }
1906
1907         for (i = 0; i < etm_ctx->trace_depth; i++)
1908         {
1909                 uint32_t pipestat, packet, flags;
1910                 fileio_read_u32(&file, &pipestat);
1911                 fileio_read_u32(&file, &packet);
1912                 fileio_read_u32(&file, &flags);
1913                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1914                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1915                 etm_ctx->trace_data[i].flags = flags;
1916         }
1917
1918         fileio_close(&file);
1919
1920         return ERROR_OK;
1921 }
1922
1923 COMMAND_HANDLER(handle_etm_trigger_percent_command)
1924 {
1925         struct target *target;
1926         struct arm *arm;
1927         struct etm_context *etm_ctx;
1928
1929         target = get_current_target(CMD_CTX);
1930         arm = target_to_arm(target);
1931         if (!is_arm(arm))
1932         {
1933                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1934                 return ERROR_FAIL;
1935         }
1936
1937         etm_ctx = arm->etm;
1938         if (!etm_ctx)
1939         {
1940                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1941                 return ERROR_FAIL;
1942         }
1943
1944         if (CMD_ARGC > 0)
1945         {
1946                 uint32_t new_value;
1947                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
1948
1949                 if ((new_value < 2) || (new_value > 100))
1950                 {
1951                         command_print(CMD_CTX, "valid settings are 2%% to 100%%");
1952                 }
1953                 else
1954                 {
1955                         etm_ctx->trigger_percent = new_value;
1956                 }
1957         }
1958
1959         command_print(CMD_CTX, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1960
1961         return ERROR_OK;
1962 }
1963
1964 COMMAND_HANDLER(handle_etm_start_command)
1965 {
1966         struct target *target;
1967         struct arm *arm;
1968         struct etm_context *etm_ctx;
1969         struct reg *etm_ctrl_reg;
1970
1971         target = get_current_target(CMD_CTX);
1972         arm = target_to_arm(target);
1973         if (!is_arm(arm))
1974         {
1975                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1976                 return ERROR_FAIL;
1977         }
1978
1979         etm_ctx = arm->etm;
1980         if (!etm_ctx)
1981         {
1982                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1983                 return ERROR_FAIL;
1984         }
1985
1986         /* invalidate old tracing data */
1987         etm_ctx->capture_status = TRACE_IDLE;
1988         if (etm_ctx->trace_depth > 0)
1989         {
1990                 free(etm_ctx->trace_data);
1991                 etm_ctx->trace_data = NULL;
1992         }
1993         etm_ctx->trace_depth = 0;
1994
1995         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1996         if (!etm_ctrl_reg)
1997                 return ERROR_FAIL;
1998
1999         etm_get_reg(etm_ctrl_reg);
2000
2001         /* Clear programming bit (10), set port selection bit (11) */
2002         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
2003
2004         etm_store_reg(etm_ctrl_reg);
2005         jtag_execute_queue();
2006
2007         etm_ctx->capture_driver->start_capture(etm_ctx);
2008
2009         return ERROR_OK;
2010 }
2011
2012 COMMAND_HANDLER(handle_etm_stop_command)
2013 {
2014         struct target *target;
2015         struct arm *arm;
2016         struct etm_context *etm_ctx;
2017         struct reg *etm_ctrl_reg;
2018
2019         target = get_current_target(CMD_CTX);
2020         arm = target_to_arm(target);
2021         if (!is_arm(arm))
2022         {
2023                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2024                 return ERROR_FAIL;
2025         }
2026
2027         etm_ctx = arm->etm;
2028         if (!etm_ctx)
2029         {
2030                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2031                 return ERROR_FAIL;
2032         }
2033
2034         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2035         if (!etm_ctrl_reg)
2036                 return ERROR_FAIL;
2037
2038         etm_get_reg(etm_ctrl_reg);
2039
2040         /* Set programming bit (10), clear port selection bit (11) */
2041         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2042
2043         etm_store_reg(etm_ctrl_reg);
2044         jtag_execute_queue();
2045
2046         etm_ctx->capture_driver->stop_capture(etm_ctx);
2047
2048         return ERROR_OK;
2049 }
2050
2051 COMMAND_HANDLER(handle_etm_analyze_command)
2052 {
2053         struct target *target;
2054         struct arm *arm;
2055         struct etm_context *etm_ctx;
2056         int retval;
2057
2058         target = get_current_target(CMD_CTX);
2059         arm = target_to_arm(target);
2060         if (!is_arm(arm))
2061         {
2062                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2063                 return ERROR_FAIL;
2064         }
2065
2066         etm_ctx = arm->etm;
2067         if (!etm_ctx)
2068         {
2069                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2070                 return ERROR_FAIL;
2071         }
2072
2073         if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2074         {
2075                 switch (retval)
2076                 {
2077                         case ERROR_ETM_ANALYSIS_FAILED:
2078                                 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2079                                 break;
2080                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2081                                 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2082                                 break;
2083                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
2084                                 command_print(CMD_CTX, "no image available for trace analysis");
2085                                 break;
2086                         default:
2087                                 command_print(CMD_CTX, "unknown error: %i", retval);
2088                 }
2089         }
2090
2091         return retval;
2092 }
2093
2094 static const struct command_registration etm_config_command_handlers[] = {
2095         {
2096                 .name = "config",
2097                 .handler = &handle_etm_config_command,
2098                 .mode = COMMAND_CONFIG,
2099                 .usage = "<target> <port_width> <port_mode> "
2100                         "<clocking> <capture_driver>",
2101         },
2102         COMMAND_REGISTRATION_DONE
2103 };
2104 const struct command_registration etm_command_handlers[] = {
2105         {
2106                 .name = "etm",
2107                 .mode = COMMAND_ANY,
2108                 .help = "Emebdded Trace Macrocell command group",
2109                 .chain = etm_config_command_handlers,
2110         },
2111         COMMAND_REGISTRATION_DONE
2112 };
2113
2114 static const struct command_registration etm_exec_command_handlers[] = {
2115         {
2116                 .name = "tracemode", handle_etm_tracemode_command,
2117                 .mode = COMMAND_EXEC,
2118                 .help = "configure/display trace mode",
2119                 .usage = "<none | data | address | all> "
2120                         "<context_id_bits> <cycle_accurate> <branch_output>",
2121         },
2122         {
2123                 .name = "info",
2124                 .handler = &handle_etm_info_command,
2125                 .mode = COMMAND_EXEC,
2126                 .help = "display info about the current target's ETM",
2127         },
2128         {
2129                 .name = "trigger_percent",
2130                 .handler = &handle_etm_trigger_percent_command,
2131                 .mode = COMMAND_EXEC,
2132                 .help = "amount (<percent>) of trace buffer "
2133                         "to be filled after the trigger occured",
2134         },
2135         {
2136                 .name = "status",
2137                 .handler = &handle_etm_status_command,
2138                 .mode = COMMAND_EXEC,
2139                 .help = "display current target's ETM status",
2140         },
2141         {
2142                 .name = "start",
2143                 .handler = &handle_etm_start_command,
2144                 .mode = COMMAND_EXEC,
2145                 .help = "start ETM trace collection",
2146         },
2147         {
2148                 .name = "stop",
2149                 .handler = &handle_etm_stop_command,
2150                 .mode = COMMAND_EXEC,
2151                 .help = "stop ETM trace collection",
2152         },
2153         {
2154                 .name = "analyze",
2155                 .handler = &handle_etm_analyze_command,
2156                 .mode = COMMAND_EXEC,
2157                 .help = "anaylze collected ETM trace",
2158         },
2159         {
2160                 .name = "image",
2161                 .handler = &handle_etm_image_command,
2162                 .mode = COMMAND_EXEC,
2163                 .help = "load image from <file> [base address]",
2164         },
2165         {
2166                 .name = "dump",
2167                 .handler = &handle_etm_dump_command,
2168                 .mode = COMMAND_EXEC,
2169                 .help = "dump captured trace data <file>",
2170         },
2171         {
2172                 .name = "load",
2173                 .handler = &handle_etm_load_command,
2174                 .mode = COMMAND_EXEC,
2175                 .help = "load trace data for analysis <file>",
2176         },
2177         COMMAND_REGISTRATION_DONE
2178 };
2179
2180 static int etm_register_user_commands(struct command_context *cmd_ctx)
2181 {
2182         struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2183         return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2184 }