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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <string.h>
  25
  26 #include "etm.h"
  27 #include "etb.h"
  28
  29 #include "armv4_5.h"
  30 #include "arm7_9_common.h"
  31 #include "arm_disassembler.h"
  32 #include "arm_simulator.h"
  33
  34 #include "log.h"
  35 #include "arm_jtag.h"
  36 #include "types.h"
  37 #include "binarybuffer.h"
  38 #include "target.h"
  39 #include "register.h"
  40 #include "jtag.h"
  41 #include "fileio.h"
  42
  43 #include <stdlib.h>
  44
  45 /* ETM register access functionality
  46  *
  47  */
  48
  49 #if 0
  50 static bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
  51 {
  52         {"R", 1},
  53         {"W", 1},
  54         {"reserved", 26},
  55         {"version", 4}
  56 };
  57 #endif
  58
  59 static int etm_reg_arch_info[] =
  60 {
  61         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  62         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  63         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
  64         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
  65         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
  66         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
  67         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
  68         0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
  69         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
  70         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
  71         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
  72         0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
  73         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
  74         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  75 };
  76
  77 static int etm_reg_arch_size_info[] =
  78 {
  79         32, 32, 17, 8, 3, 9, 32, 16,
  80         17, 26, 25, 8, 17, 32, 32, 17,
  81         32, 32, 32, 32, 32, 32, 32, 32,
  82         32, 32, 32, 32, 32, 32, 32, 32,
  83         7, 7, 7, 7, 7, 7, 7, 7,
  84         7, 7, 7, 7, 7, 7, 7, 7,
  85         32, 32, 32, 32, 32, 32, 32, 32,
  86         32, 32, 32, 32, 32, 32, 32, 32,
  87         32, 32, 32, 32, 32, 32, 32, 32,
  88         32, 32, 32, 32, 32, 32, 32, 32,
  89         16, 16, 16, 16, 18, 18, 18, 18,
  90         17, 17, 17, 17, 16, 16, 16, 16,
  91         17, 17, 17, 17, 17, 17, 2,
  92         17, 17, 17, 17, 32, 32, 32, 32
  93 };
  94
  95 static char* etm_reg_list[] =
  96 {
  97         "ETM_CTRL",
  98         "ETM_CONFIG",
  99         "ETM_TRIG_EVENT",
 100         "ETM_MMD_CTRL",
 101         "ETM_STATUS",
 102         "ETM_SYS_CONFIG",
 103         "ETM_TRACE_RESOURCE_CTRL",
 104         "ETM_TRACE_EN_CTRL2",
 105         "ETM_TRACE_EN_EVENT",
 106         "ETM_TRACE_EN_CTRL1",
 107         "ETM_FIFOFULL_REGION",
 108         "ETM_FIFOFULL_LEVEL",
 109         "ETM_VIEWDATA_EVENT",
 110         "ETM_VIEWDATA_CTRL1",
 111         "ETM_VIEWDATA_CTRL2",
 112         "ETM_VIEWDATA_CTRL3",
 113         "ETM_ADDR_COMPARATOR_VALUE1",
 114         "ETM_ADDR_COMPARATOR_VALUE2",
 115         "ETM_ADDR_COMPARATOR_VALUE3",
 116         "ETM_ADDR_COMPARATOR_VALUE4",
 117         "ETM_ADDR_COMPARATOR_VALUE5",
 118         "ETM_ADDR_COMPARATOR_VALUE6",
 119         "ETM_ADDR_COMPARATOR_VALUE7",
 120         "ETM_ADDR_COMPARATOR_VALUE8",
 121         "ETM_ADDR_COMPARATOR_VALUE9",
 122         "ETM_ADDR_COMPARATOR_VALUE10",
 123         "ETM_ADDR_COMPARATOR_VALUE11",
 124         "ETM_ADDR_COMPARATOR_VALUE12",
 125         "ETM_ADDR_COMPARATOR_VALUE13",
 126         "ETM_ADDR_COMPARATOR_VALUE14",
 127         "ETM_ADDR_COMPARATOR_VALUE15",
 128         "ETM_ADDR_COMPARATOR_VALUE16",
 129         "ETM_ADDR_ACCESS_TYPE1",
 130         "ETM_ADDR_ACCESS_TYPE2",
 131         "ETM_ADDR_ACCESS_TYPE3",
 132         "ETM_ADDR_ACCESS_TYPE4",
 133         "ETM_ADDR_ACCESS_TYPE5",
 134         "ETM_ADDR_ACCESS_TYPE6",
 135         "ETM_ADDR_ACCESS_TYPE7",
 136         "ETM_ADDR_ACCESS_TYPE8",
 137         "ETM_ADDR_ACCESS_TYPE9",
 138         "ETM_ADDR_ACCESS_TYPE10",
 139         "ETM_ADDR_ACCESS_TYPE11",
 140         "ETM_ADDR_ACCESS_TYPE12",
 141         "ETM_ADDR_ACCESS_TYPE13",
 142         "ETM_ADDR_ACCESS_TYPE14",
 143         "ETM_ADDR_ACCESS_TYPE15",
 144         "ETM_ADDR_ACCESS_TYPE16",
 145         "ETM_DATA_COMPARATOR_VALUE1",
 146         "ETM_DATA_COMPARATOR_VALUE2",
 147         "ETM_DATA_COMPARATOR_VALUE3",
 148         "ETM_DATA_COMPARATOR_VALUE4",
 149         "ETM_DATA_COMPARATOR_VALUE5",
 150         "ETM_DATA_COMPARATOR_VALUE6",
 151         "ETM_DATA_COMPARATOR_VALUE7",
 152         "ETM_DATA_COMPARATOR_VALUE8",
 153         "ETM_DATA_COMPARATOR_VALUE9",
 154         "ETM_DATA_COMPARATOR_VALUE10",
 155         "ETM_DATA_COMPARATOR_VALUE11",
 156         "ETM_DATA_COMPARATOR_VALUE12",
 157         "ETM_DATA_COMPARATOR_VALUE13",
 158         "ETM_DATA_COMPARATOR_VALUE14",
 159         "ETM_DATA_COMPARATOR_VALUE15",
 160         "ETM_DATA_COMPARATOR_VALUE16",
 161         "ETM_DATA_COMPARATOR_MASK1",
 162         "ETM_DATA_COMPARATOR_MASK2",
 163         "ETM_DATA_COMPARATOR_MASK3",
 164         "ETM_DATA_COMPARATOR_MASK4",
 165         "ETM_DATA_COMPARATOR_MASK5",
 166         "ETM_DATA_COMPARATOR_MASK6",
 167         "ETM_DATA_COMPARATOR_MASK7",
 168         "ETM_DATA_COMPARATOR_MASK8",
 169         "ETM_DATA_COMPARATOR_MASK9",
 170         "ETM_DATA_COMPARATOR_MASK10",
 171         "ETM_DATA_COMPARATOR_MASK11",
 172         "ETM_DATA_COMPARATOR_MASK12",
 173         "ETM_DATA_COMPARATOR_MASK13",
 174         "ETM_DATA_COMPARATOR_MASK14",
 175         "ETM_DATA_COMPARATOR_MASK15",
 176         "ETM_DATA_COMPARATOR_MASK16",
 177         "ETM_COUNTER_INITAL_VALUE1",
 178         "ETM_COUNTER_INITAL_VALUE2",
 179         "ETM_COUNTER_INITAL_VALUE3",
 180         "ETM_COUNTER_INITAL_VALUE4",
 181         "ETM_COUNTER_ENABLE1",
 182         "ETM_COUNTER_ENABLE2",
 183         "ETM_COUNTER_ENABLE3",
 184         "ETM_COUNTER_ENABLE4",
 185         "ETM_COUNTER_RELOAD_VALUE1",
 186         "ETM_COUNTER_RELOAD_VALUE2",
 187         "ETM_COUNTER_RELOAD_VALUE3",
 188         "ETM_COUNTER_RELOAD_VALUE4",
 189         "ETM_COUNTER_VALUE1",
 190         "ETM_COUNTER_VALUE2",
 191         "ETM_COUNTER_VALUE3",
 192         "ETM_COUNTER_VALUE4",
 193         "ETM_SEQUENCER_CTRL1",
 194         "ETM_SEQUENCER_CTRL2",
 195         "ETM_SEQUENCER_CTRL3",
 196         "ETM_SEQUENCER_CTRL4",
 197         "ETM_SEQUENCER_CTRL5",
 198         "ETM_SEQUENCER_CTRL6",
 199         "ETM_SEQUENCER_STATE",
 200         "ETM_EXTERNAL_OUTPUT1",
 201         "ETM_EXTERNAL_OUTPUT2",
 202         "ETM_EXTERNAL_OUTPUT3",
 203         "ETM_EXTERNAL_OUTPUT4",
 204         "ETM_CONTEXTID_COMPARATOR_VALUE1",
 205         "ETM_CONTEXTID_COMPARATOR_VALUE2",
 206         "ETM_CONTEXTID_COMPARATOR_VALUE3",
 207         "ETM_CONTEXTID_COMPARATOR_MASK"
 208 };
 209
 210 static int etm_reg_arch_type = -1;
 211
 212 static int etm_get_reg(reg_t *reg);
 213
 214 static command_t *etm_cmd = NULL;
 215
 216 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 217 {
 218         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 219         reg_t *reg_list = NULL;
 220         etm_reg_t *arch_info = NULL;
 221         int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
 222         int i;
 223
 224         /* register a register arch-type for etm registers only once */
 225         if (etm_reg_arch_type == -1)
 226                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
 227
 228         /* the actual registers are kept in two arrays */
 229         reg_list = calloc(num_regs, sizeof(reg_t));
 230         arch_info = calloc(num_regs, sizeof(etm_reg_t));
 231
 232         /* fill in values for the reg cache */
 233         reg_cache->name = "etm registers";
 234         reg_cache->next = NULL;
 235         reg_cache->reg_list = reg_list;
 236         reg_cache->num_regs = num_regs;
 237
 238         /* set up registers */
 239         for (i = 0; i < num_regs; i++)
 240         {
 241                 reg_list[i].name = etm_reg_list[i];
 242                 reg_list[i].size = 32;
 243                 reg_list[i].dirty = 0;
 244                 reg_list[i].valid = 0;
 245                 reg_list[i].bitfield_desc = NULL;
 246                 reg_list[i].num_bitfields = 0;
 247                 reg_list[i].value = calloc(1, 4);
 248                 reg_list[i].arch_info = &arch_info[i];
 249                 reg_list[i].arch_type = etm_reg_arch_type;
 250                 reg_list[i].size = etm_reg_arch_size_info[i];
 251                 arch_info[i].addr = etm_reg_arch_info[i];
 252                 arch_info[i].jtag_info = jtag_info;
 253         }
 254
 255         /* the ETM might have an ETB connected */
 256         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 257         {
 258                 etb_t *etb = etm_ctx->capture_driver_priv;
 259
 260                 if (!etb)
 261                 {
 262                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 263                         return ERROR_OK;
 264                 }
 265
 266                 reg_cache->next = etb_build_reg_cache(etb);
 267
 268                 etb->reg_cache = reg_cache->next;
 269         }
 270
 271
 272         return reg_cache;
 273 }
 274
 275 int etm_setup(target_t *target)
 276 {
 277         int retval;
 278         u32 etm_ctrl_value;
 279         armv4_5_common_t *armv4_5 = target->arch_info;
 280         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 281         etm_context_t *etm_ctx = arm7_9->etm_ctx;
 282         reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
 283         /* initialize some ETM control register settings */
 284         etm_get_reg(etm_ctrl_reg);
 285         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
 286
 287         /* clear the ETM powerdown bit (0) */
 288         etm_ctrl_value &= ~0x1;
 289
 290         /* configure port width (6:4), mode (17:16) and clocking (13) */
 291         etm_ctrl_value = (etm_ctrl_value &
 292                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 293                 | etm_ctx->portmode;
 294
 295         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 296         etm_store_reg(etm_ctrl_reg);
 297
 298         if ((retval=jtag_execute_queue())!=ERROR_OK)
 299                 return retval;
 300
 301         if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 302         {
 303                 LOG_ERROR("ETM capture driver initialization failed");
 304                 return retval;
 305         }
 306         return ERROR_OK;
 307 }
 308
 309 int etm_get_reg(reg_t *reg)
 310 {
 311         int retval;
 312         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 313         {
 314                 LOG_ERROR("BUG: error scheduling etm register read");
 315                 return retval;
 316         }
 317
 318         if ((retval = jtag_execute_queue()) != ERROR_OK)
 319         {
 320                 LOG_ERROR("register read failed");
 321                 return retval;
 322         }
 323
 324         return ERROR_OK;
 325 }
 326
 327 int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 328 {
 329         etm_reg_t *etm_reg = reg->arch_info;
 330         u8 reg_addr = etm_reg->addr & 0x7f;
 331         scan_field_t fields[3];
 332
 333         LOG_DEBUG("%i", etm_reg->addr);
 334
 335         jtag_add_end_state(TAP_IDLE);
 336         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 337         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 338
 339         fields[0].tap = etm_reg->jtag_info->tap;
 340         fields[0].num_bits = 32;
 341         fields[0].out_value = reg->value;
 342         fields[0].in_value = NULL;
 343
 344
 345         fields[1].tap = etm_reg->jtag_info->tap;
 346         fields[1].num_bits = 7;
 347         fields[1].out_value = malloc(1);
 348         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 349         fields[1].in_value = NULL;
 350
 351
 352         fields[2].tap = etm_reg->jtag_info->tap;
 353         fields[2].num_bits = 1;
 354         fields[2].out_value = malloc(1);
 355         buf_set_u32(fields[2].out_value, 0, 1, 0);
 356         fields[2].in_value = NULL;
 357
 358
 359         jtag_add_dr_scan(3, fields, TAP_INVALID);
 360
 361         fields[0].in_value = reg->value;
 362
 363         jtag_add_dr_scan(3, fields, TAP_INVALID);
 364
 365         jtag_check_value_mask(fields+0, check_value, check_mask);
 366
 367         free(fields[1].out_value);
 368         free(fields[2].out_value);
 369
 370         return ERROR_OK;
 371 }
 372
 373 int etm_read_reg(reg_t *reg)
 374 {
 375         return etm_read_reg_w_check(reg, NULL, NULL);
 376 }
 377
 378 int etm_set_reg(reg_t *reg, u32 value)
 379 {
 380         int retval;
 381         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 382         {
 383                 LOG_ERROR("BUG: error scheduling etm register write");
 384                 return retval;
 385         }
 386
 387         buf_set_u32(reg->value, 0, reg->size, value);
 388         reg->valid = 1;
 389         reg->dirty = 0;
 390
 391         return ERROR_OK;
 392 }
 393
 394 int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
 395 {
 396         int retval;
 397         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 398
 399         if ((retval = jtag_execute_queue()) != ERROR_OK)
 400         {
 401                 LOG_ERROR("register write failed");
 402                 return retval;
 403         }
 404         return ERROR_OK;
 405 }
 406
 407 int etm_write_reg(reg_t *reg, u32 value)
 408 {
 409         etm_reg_t *etm_reg = reg->arch_info;
 410         u8 reg_addr = etm_reg->addr & 0x7f;
 411         scan_field_t fields[3];
 412
 413         LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
 414
 415         jtag_add_end_state(TAP_IDLE);
 416         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 417         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 418
 419         fields[0].tap = etm_reg->jtag_info->tap;
 420         fields[0].num_bits = 32;
 421         fields[0].out_value = malloc(4);
 422         buf_set_u32(fields[0].out_value, 0, 32, value);
 423
 424         fields[0].in_value = NULL;
 425
 426
 427
 428
 429
 430         fields[1].tap = etm_reg->jtag_info->tap;
 431         fields[1].num_bits = 7;
 432         fields[1].out_value = malloc(1);
 433         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 434
 435         fields[1].in_value = NULL;
 436
 437
 438
 439
 440
 441         fields[2].tap = etm_reg->jtag_info->tap;
 442         fields[2].num_bits = 1;
 443         fields[2].out_value = malloc(1);
 444         buf_set_u32(fields[2].out_value, 0, 1, 1);
 445
 446         fields[2].in_value = NULL;
 447
 448
 449
 450
 451
 452         jtag_add_dr_scan(3, fields, TAP_INVALID);
 453
 454         free(fields[0].out_value);
 455         free(fields[1].out_value);
 456         free(fields[2].out_value);
 457
 458         return ERROR_OK;
 459 }
 460
 461 int etm_store_reg(reg_t *reg)
 462 {
 463         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 464 }
 465
 466 /* ETM trace analysis functionality
 467  *
 468  */
 469 extern etm_capture_driver_t etm_dummy_capture_driver;
 470 #if BUILD_OOCD_TRACE == 1
 471 extern etm_capture_driver_t oocd_trace_capture_driver;
 472 #endif
 473
 474 static etm_capture_driver_t *etm_capture_drivers[] =
 475 {
 476         &etb_capture_driver,
 477         &etm_dummy_capture_driver,
 478 #if BUILD_OOCD_TRACE == 1
 479         &oocd_trace_capture_driver,
 480 #endif
 481         NULL
 482 };
 483
 484 char *etmv1v1_branch_reason_strings[] =
 485 {
 486         "normal PC change",
 487         "tracing enabled",
 488         "trace restarted after overflow",
 489         "exit from debug",
 490         "periodic synchronization",
 491         "reserved",
 492         "reserved",
 493         "reserved",
 494 };
 495
 496 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 497 {
 498         int i;
 499         int section = -1;
 500         u32 size_read;
 501         u32 opcode;
 502         int retval;
 503
 504         if (!ctx->image)
 505                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 506
 507         /* search for the section the current instruction belongs to */
 508         for (i = 0; i < ctx->image->num_sections; i++)
 509         {
 510                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 511                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 512                 {
 513                         section = i;
 514                         break;
 515                 }
 516         }
 517
 518         if (section == -1)
 519         {
 520                 /* current instruction couldn't be found in the image */
 521                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 522         }
 523
 524         if (ctx->core_state == ARMV4_5_STATE_ARM)
 525         {
 526                 u8 buf[4];
 527                 if ((retval = image_read_section(ctx->image, section,
 528                         ctx->current_pc - ctx->image->sections[section].base_address,
 529                         4, buf, &size_read)) != ERROR_OK)
 530                 {
 531                         LOG_ERROR("error while reading instruction: %i", retval);
 532                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 533                 }
 534                 opcode = target_buffer_get_u32(ctx->target, buf);
 535                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 536         }
 537         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 538         {
 539                 u8 buf[2];
 540                 if ((retval = image_read_section(ctx->image, section,
 541                         ctx->current_pc - ctx->image->sections[section].base_address,
 542                         2, buf, &size_read)) != ERROR_OK)
 543                 {
 544                         LOG_ERROR("error while reading instruction: %i", retval);
 545                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 546                 }
 547                 opcode = target_buffer_get_u16(ctx->target, buf);
 548                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 549         }
 550         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 551         {
 552                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 553                 exit(-1);
 554         }
 555         else
 556         {
 557                 LOG_ERROR("BUG: unknown core state encountered");
 558                 exit(-1);
 559         }
 560
 561         return ERROR_OK;
 562 }
 563
 564 static int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
 565 {
 566         while (ctx->data_index < ctx->trace_depth)
 567         {
 568                 /* if the caller specified an address packet offset, skip until the
 569                  * we reach the n-th cycle marked with tracesync */
 570                 if (apo > 0)
 571                 {
 572                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 573                                 apo--;
 574
 575                         if (apo > 0)
 576                         {
 577                                 ctx->data_index++;
 578                                 ctx->data_half = 0;
 579                         }
 580                         continue;
 581                 }
 582
 583                 /* no tracedata output during a TD cycle
 584                  * or in a trigger cycle */
 585                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 586                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 587                 {
 588                         ctx->data_index++;
 589                         ctx->data_half = 0;
 590                         continue;
 591                 }
 592
 593                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 594                 {
 595                         if (ctx->data_half == 0)
 596                         {
 597                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 598                                 ctx->data_half = 1;
 599                         }
 600                         else
 601                         {
 602                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 603                                 ctx->data_half = 0;
 604                                 ctx->data_index++;
 605                         }
 606                 }
 607                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 608                 {
 609                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 610                         ctx->data_index++;
 611                 }
 612                 else
 613                 {
 614                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 615                         if (ctx->data_index > (ctx->trace_depth - 2))
 616                                 return -1;
 617
 618                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 619                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 620                         ctx->data_index += 2;
 621                 }
 622
 623                 return 0;
 624         }
 625
 626         return -1;
 627 }
 628
 629 static int etmv1_branch_address(etm_context_t *ctx)
 630 {
 631         int retval;
 632         u8 packet;
 633         int shift = 0;
 634         int apo;
 635         u32 i;
 636
 637         /* quit analysis if less than two cycles are left in the trace
 638          * because we can't extract the APO */
 639         if (ctx->data_index > (ctx->trace_depth - 2))
 640                 return -1;
 641
 642         /* a BE could be output during an APO cycle, skip the current
 643          * and continue with the new one */
 644         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 645                 return 1;
 646         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 647                 return 2;
 648
 649         /* address packet offset encoded in the next two cycles' pipestat bits */
 650         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 651         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 652
 653         /* count number of tracesync cycles between current pipe_index and data_index
 654          * i.e. the number of tracesyncs that data_index already passed by
 655          * to subtract them from the APO */
 656         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 657         {
 658                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 659                         apo--;
 660         }
 661
 662         /* extract up to four 7-bit packets */
 663         do {
 664                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 665                         return -1;
 666                 ctx->last_branch &= ~(0x7f << shift);
 667                 ctx->last_branch |= (packet & 0x7f) << shift;
 668                 shift += 7;
 669         } while ((packet & 0x80) && (shift < 28));
 670
 671         /* one last packet holding 4 bits of the address, plus the branch reason code */
 672         if ((shift == 28) && (packet & 0x80))
 673         {
 674                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 675                         return -1;
 676                 ctx->last_branch &= 0x0fffffff;
 677                 ctx->last_branch |= (packet & 0x0f) << 28;
 678                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 679                 shift += 4;
 680         }
 681         else
 682         {
 683                 ctx->last_branch_reason = 0;
 684         }
 685
 686         if (shift == 32)
 687         {
 688                 ctx->pc_ok = 1;
 689         }
 690
 691         /* if a full address was output, we might have branched into Jazelle state */
 692         if ((shift == 32) && (packet & 0x80))
 693         {
 694                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 695         }
 696         else
 697         {
 698                 /* if we didn't branch into Jazelle state, the current processor state is
 699                  * encoded in bit 0 of the branch target address */
 700                 if (ctx->last_branch & 0x1)
 701                 {
 702                         ctx->core_state = ARMV4_5_STATE_THUMB;
 703                         ctx->last_branch &= ~0x1;
 704                 }
 705                 else
 706                 {
 707                         ctx->core_state = ARMV4_5_STATE_ARM;
 708                         ctx->last_branch &= ~0x3;
 709                 }
 710         }
 711
 712         return 0;
 713 }
 714
 715 static int etmv1_data(etm_context_t *ctx, int size, u32 *data)
 716 {
 717         int j;
 718         u8 buf[4];
 719         int retval;
 720
 721         for (j = 0; j < size; j++)
 722         {
 723                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 724                         return -1;
 725         }
 726
 727         if (size == 8)
 728         {
 729                 LOG_ERROR("TODO: add support for 64-bit values");
 730                 return -1;
 731         }
 732         else if (size == 4)
 733                 *data = target_buffer_get_u32(ctx->target, buf);
 734         else if (size == 2)
 735                 *data = target_buffer_get_u16(ctx->target, buf);
 736         else if (size == 1)
 737                 *data = buf[0];
 738         else
 739                 return -1;
 740
 741         return 0;
 742 }
 743
 744 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 745 {
 746         int retval;
 747         arm_instruction_t instruction;
 748
 749         /* read the trace data if it wasn't read already */
 750         if (ctx->trace_depth == 0)
 751                 ctx->capture_driver->read_trace(ctx);
 752
 753         /* start at the beginning of the captured trace */
 754         ctx->pipe_index = 0;
 755         ctx->data_index = 0;
 756         ctx->data_half = 0;
 757
 758         /* neither the PC nor the data pointer are valid */
 759         ctx->pc_ok = 0;
 760         ctx->ptr_ok = 0;
 761
 762         while (ctx->pipe_index < ctx->trace_depth)
 763         {
 764                 u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 765                 u32 next_pc = ctx->current_pc;
 766                 u32 old_data_index = ctx->data_index;
 767                 u32 old_data_half = ctx->data_half;
 768                 u32 old_index = ctx->pipe_index;
 769                 u32 last_instruction = ctx->last_instruction;
 770                 u32 cycles = 0;
 771                 int current_pc_ok = ctx->pc_ok;
 772
 773                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 774                 {
 775                         command_print(cmd_ctx, "--- trigger ---");
 776                 }
 777
 778                 /* instructions execute in IE/D or BE/D cycles */
 779                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 780                         ctx->last_instruction = ctx->pipe_index;
 781
 782                 /* if we don't have a valid pc skip until we reach an indirect branch */
 783                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 784                 {
 785                         ctx->pipe_index++;
 786                         continue;
 787                 }
 788
 789                 /* any indirect branch could have interrupted instruction flow
 790                  * - the branch reason code could indicate a trace discontinuity
 791                  * - a branch to the exception vectors indicates an exception
 792                  */
 793                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 794                 {
 795                         /* backup current data index, to be able to consume the branch address
 796                          * before examining data address and values
 797                          */
 798                         old_data_index = ctx->data_index;
 799                         old_data_half = ctx->data_half;
 800
 801                         ctx->last_instruction = ctx->pipe_index;
 802
 803                         if ((retval = etmv1_branch_address(ctx)) != 0)
 804                         {
 805                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 806                                  * quit analysing the trace */
 807                                 if (retval < 0)
 808                                         break;
 809
 810                                 /* a positive return values means the current branch was abandoned,
 811                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 812                                  */
 813                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 814                                 ctx->pipe_index += retval;
 815                                 continue;
 816                         }
 817
 818                         /* skip over APO cycles */
 819                         ctx->pipe_index += 2;
 820
 821                         switch (ctx->last_branch_reason)
 822                         {
 823                                 case 0x0:       /* normal PC change */
 824                                         next_pc = ctx->last_branch;
 825                                         break;
 826                                 case 0x1:       /* tracing enabled */
 827                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
 828                                         ctx->current_pc = ctx->last_branch;
 829                                         ctx->pipe_index++;
 830                                         continue;
 831                                         break;
 832                                 case 0x2:       /* trace restarted after FIFO overflow */
 833                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
 834                                         ctx->current_pc = ctx->last_branch;
 835                                         ctx->pipe_index++;
 836                                         continue;
 837                                         break;
 838                                 case 0x3:       /* exit from debug state */
 839                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
 840                                         ctx->current_pc = ctx->last_branch;
 841                                         ctx->pipe_index++;
 842                                         continue;
 843                                         break;
 844                                 case 0x4:       /* periodic synchronization point */
 845                                         next_pc = ctx->last_branch;
 846                                         /* if we had no valid PC prior to this synchronization point,
 847                                          * we have to move on with the next trace cycle
 848                                          */
 849                                         if (!current_pc_ok)
 850                                         {
 851                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
 852                                                 ctx->current_pc = next_pc;
 853                                                 ctx->pipe_index++;
 854                                                 continue;
 855                                         }
 856                                         break;
 857                                 default:        /* reserved */
 858                                         LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
 859                                         exit(-1);
 860                                         break;
 861                         }
 862
 863                         /* if we got here the branch was a normal PC change
 864                          * (or a periodic synchronization point, which means the same for that matter)
 865                          * if we didn't accquire a complete PC continue with the next cycle
 866                          */
 867                         if (!ctx->pc_ok)
 868                                 continue;
 869
 870                         /* indirect branch to the exception vector means an exception occured */
 871                         if ((ctx->last_branch <= 0x20)
 872                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 873                         {
 874                                 if ((ctx->last_branch & 0xff) == 0x10)
 875                                 {
 876                                         command_print(cmd_ctx, "data abort");
 877                                 }
 878                                 else
 879                                 {
 880                                         command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
 881                                         ctx->current_pc = ctx->last_branch;
 882                                         ctx->pipe_index++;
 883                                         continue;
 884                                 }
 885                         }
 886                 }
 887
 888                 /* an instruction was executed (or not, depending on the condition flags)
 889                  * retrieve it from the image for displaying */
 890                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
 891                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
 892                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
 893                 {
 894                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
 895                         {
 896                                 /* can't continue tracing with no image available */
 897                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
 898                                 {
 899                                         return retval;
 900                                 }
 901                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
 902                                 {
 903                                         /* TODO: handle incomplete images
 904                                          * for now we just quit the analsysis*/
 905                                         return retval;
 906                                 }
 907                         }
 908
 909                         cycles = old_index - last_instruction;
 910                 }
 911
 912                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
 913                 {
 914                         u32 new_data_index = ctx->data_index;
 915                         u32 new_data_half = ctx->data_half;
 916
 917                         /* in case of a branch with data, the branch target address was consumed before
 918                          * we temporarily go back to the saved data index */
 919                         if (pipestat == STAT_BD)
 920                         {
 921                                 ctx->data_index = old_data_index;
 922                                 ctx->data_half = old_data_half;
 923                         }
 924
 925                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
 926                         {
 927                                 u8 packet;
 928                                 int shift = 0;
 929
 930                                 do {
 931                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 932                                                 return ERROR_ETM_ANALYSIS_FAILED;
 933                                         ctx->last_ptr &= ~(0x7f << shift);
 934                                         ctx->last_ptr |= (packet & 0x7f) << shift;
 935                                         shift += 7;
 936                                 } while ((packet & 0x80) && (shift < 32));
 937
 938                                 if (shift >= 32)
 939                                         ctx->ptr_ok = 1;
 940
 941                                 if (ctx->ptr_ok)
 942                                 {
 943                                         command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
 944                                 }
 945                         }
 946
 947                         if (ctx->tracemode & ETMV1_TRACE_DATA)
 948                         {
 949                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
 950                                 {
 951                                         int i;
 952                                         for (i = 0; i < 16; i++)
 953                                         {
 954                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
 955                                                 {
 956                                                         u32 data;
 957                                                         if (etmv1_data(ctx, 4, &data) != 0)
 958                                                                 return ERROR_ETM_ANALYSIS_FAILED;
 959                                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 960                                                 }
 961                                         }
 962                                 }
 963                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
 964                                 {
 965                                         u32 data;
 966                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
 967                                                 return ERROR_ETM_ANALYSIS_FAILED;
 968                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 969                                 }
 970                         }
 971
 972                         /* restore data index after consuming BD address and data */
 973                         if (pipestat == STAT_BD)
 974                         {
 975                                 ctx->data_index = new_data_index;
 976                                 ctx->data_half = new_data_half;
 977                         }
 978                 }
 979
 980                 /* adjust PC */
 981                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 982                 {
 983                         if (((instruction.type == ARM_B) ||
 984                              (instruction.type == ARM_BL) ||
 985                              (instruction.type == ARM_BLX)) &&
 986                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
 987                         {
 988                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
 989                         }
 990                         else
 991                         {
 992                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 993                         }
 994                 }
 995                 else if (pipestat == STAT_IN)
 996                 {
 997                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 998                 }
 999
1000                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1001                 {
1002                         char cycles_text[32] = "";
1003
1004                         /* if the trace was captured with cycle accurate tracing enabled,
1005                          * output the number of cycles since the last executed instruction
1006                          */
1007                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1008                         {
1009                                 snprintf(cycles_text, 32, " (%i %s)",
1010                                         cycles,
1011                                         (cycles == 1) ? "cycle" : "cycles");
1012                         }
1013
1014                         command_print(cmd_ctx, "%s%s%s",
1015                                 instruction.text,
1016                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1017                                 cycles_text);
1018
1019                         ctx->current_pc = next_pc;
1020
1021                         /* packets for an instruction don't start on or before the preceding
1022                          * functional pipestat (i.e. other than WT or TD)
1023                          */
1024                         if (ctx->data_index <= ctx->pipe_index)
1025                         {
1026                                 ctx->data_index = ctx->pipe_index + 1;
1027                                 ctx->data_half = 0;
1028                         }
1029                 }
1030
1031                 ctx->pipe_index += 1;
1032         }
1033
1034         return ERROR_OK;
1035 }
1036
1037 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1038 {
1039         target_t *target;
1040         armv4_5_common_t *armv4_5;
1041         arm7_9_common_t *arm7_9;
1042         etmv1_tracemode_t tracemode;
1043
1044         target = get_current_target(cmd_ctx);
1045
1046         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1047         {
1048                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1049                 return ERROR_OK;
1050         }
1051
1052         if (!arm7_9->etm_ctx)
1053         {
1054                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1055                 return ERROR_OK;
1056         }
1057
1058         tracemode = arm7_9->etm_ctx->tracemode;
1059
1060         if (argc == 4)
1061         {
1062                 if (strcmp(args[0], "none") == 0)
1063                 {
1064                         tracemode = ETMV1_TRACE_NONE;
1065                 }
1066                 else if (strcmp(args[0], "data") == 0)
1067                 {
1068                         tracemode = ETMV1_TRACE_DATA;
1069                 }
1070                 else if (strcmp(args[0], "address") == 0)
1071                 {
1072                         tracemode = ETMV1_TRACE_ADDR;
1073                 }
1074                 else if (strcmp(args[0], "all") == 0)
1075                 {
1076                         tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1077                 }
1078                 else
1079                 {
1080                         command_print(cmd_ctx, "invalid option '%s'", args[0]);
1081                         return ERROR_OK;
1082                 }
1083
1084                 switch (strtol(args[1], NULL, 0))
1085                 {
1086                         case 0:
1087                                 tracemode |= ETMV1_CONTEXTID_NONE;
1088                                 break;
1089                         case 8:
1090                                 tracemode |= ETMV1_CONTEXTID_8;
1091                                 break;
1092                         case 16:
1093                                 tracemode |= ETMV1_CONTEXTID_16;
1094                                 break;
1095                         case 32:
1096                                 tracemode |= ETMV1_CONTEXTID_32;
1097                                 break;
1098                         default:
1099                                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1100                                 return ERROR_OK;
1101                 }
1102
1103                 if (strcmp(args[2], "enable") == 0)
1104                 {
1105                         tracemode |= ETMV1_CYCLE_ACCURATE;
1106                 }
1107                 else if (strcmp(args[2], "disable") == 0)
1108                 {
1109                         tracemode |= 0;
1110                 }
1111                 else
1112                 {
1113                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1114                         return ERROR_OK;
1115                 }
1116
1117                 if (strcmp(args[3], "enable") == 0)
1118                 {
1119                         tracemode |= ETMV1_BRANCH_OUTPUT;
1120                 }
1121                 else if (strcmp(args[3], "disable") == 0)
1122                 {
1123                         tracemode |= 0;
1124                 }
1125                 else
1126                 {
1127                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1128                         return ERROR_OK;
1129                 }
1130         }
1131         else if (argc != 0)
1132         {
1133                 command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1134                 return ERROR_OK;
1135         }
1136
1137         command_print(cmd_ctx, "current tracemode configuration:");
1138
1139         switch (tracemode & ETMV1_TRACE_MASK)
1140         {
1141                 case ETMV1_TRACE_NONE:
1142                         command_print(cmd_ctx, "data tracing: none");
1143                         break;
1144                 case ETMV1_TRACE_DATA:
1145                         command_print(cmd_ctx, "data tracing: data only");
1146                         break;
1147                 case ETMV1_TRACE_ADDR:
1148                         command_print(cmd_ctx, "data tracing: address only");
1149                         break;
1150                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1151                         command_print(cmd_ctx, "data tracing: address and data");
1152                         break;
1153         }
1154
1155         switch (tracemode & ETMV1_CONTEXTID_MASK)
1156         {
1157                 case ETMV1_CONTEXTID_NONE:
1158                         command_print(cmd_ctx, "contextid tracing: none");
1159                         break;
1160                 case ETMV1_CONTEXTID_8:
1161                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1162                         break;
1163                 case ETMV1_CONTEXTID_16:
1164                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1165                         break;
1166                 case ETMV1_CONTEXTID_32:
1167                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1168                         break;
1169         }
1170
1171         if (tracemode & ETMV1_CYCLE_ACCURATE)
1172         {
1173                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1174         }
1175         else
1176         {
1177                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1178         }
1179
1180         if (tracemode & ETMV1_BRANCH_OUTPUT)
1181         {
1182                 command_print(cmd_ctx, "full branch address output enabled");
1183         }
1184         else
1185         {
1186                 command_print(cmd_ctx, "full branch address output disabled");
1187         }
1188
1189         /* only update ETM_CTRL register if tracemode changed */
1190         if (arm7_9->etm_ctx->tracemode != tracemode)
1191         {
1192                 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1193
1194                 etm_get_reg(etm_ctrl_reg);
1195
1196                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1197                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1198                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1199                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1200                 etm_store_reg(etm_ctrl_reg);
1201
1202                 arm7_9->etm_ctx->tracemode = tracemode;
1203
1204                 /* invalidate old trace data */
1205                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1206                 if (arm7_9->etm_ctx->trace_depth > 0)
1207                 {
1208                         free(arm7_9->etm_ctx->trace_data);
1209                         arm7_9->etm_ctx->trace_data = NULL;
1210                 }
1211                 arm7_9->etm_ctx->trace_depth = 0;
1212         }
1213
1214         return ERROR_OK;
1215 }
1216
1217 static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1218 {
1219         target_t *target;
1220         armv4_5_common_t *armv4_5;
1221         arm7_9_common_t *arm7_9;
1222         etm_portmode_t portmode = 0x0;
1223         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1224         int i;
1225
1226         if (argc != 5)
1227         {
1228                 return ERROR_COMMAND_SYNTAX_ERROR;
1229         }
1230
1231         target = get_target_by_num(strtoul(args[0], NULL, 0));
1232
1233         if (!target)
1234         {
1235                 LOG_ERROR("target number '%s' not defined", args[0]);
1236                 return ERROR_FAIL;
1237         }
1238
1239         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1240         {
1241                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1242                 return ERROR_FAIL;
1243         }
1244
1245         switch (strtoul(args[1], NULL, 0))
1246         {
1247                 case 4:
1248                         portmode |= ETM_PORT_4BIT;
1249                         break;
1250                 case 8:
1251                         portmode |= ETM_PORT_8BIT;
1252                         break;
1253                 case 16:
1254                         portmode |= ETM_PORT_16BIT;
1255                         break;
1256                 default:
1257                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1258                         return ERROR_FAIL;
1259         }
1260
1261         if (strcmp("normal", args[2]) == 0)
1262         {
1263                 portmode |= ETM_PORT_NORMAL;
1264         }
1265         else if (strcmp("multiplexed", args[2]) == 0)
1266         {
1267                 portmode |= ETM_PORT_MUXED;
1268         }
1269         else if (strcmp("demultiplexed", args[2]) == 0)
1270         {
1271                 portmode |= ETM_PORT_DEMUXED;
1272         }
1273         else
1274         {
1275                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1276                 return ERROR_FAIL;
1277         }
1278
1279         if (strcmp("half", args[3]) == 0)
1280         {
1281                 portmode |= ETM_PORT_HALF_CLOCK;
1282         }
1283         else if (strcmp("full", args[3]) == 0)
1284         {
1285                 portmode |= ETM_PORT_FULL_CLOCK;
1286         }
1287         else
1288         {
1289                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1290                 return ERROR_FAIL;
1291         }
1292
1293         for (i=0; etm_capture_drivers[i]; i++)
1294         {
1295                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1296                 {
1297                         int retval;
1298                         if ((retval=etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1299                         {
1300                                 free(etm_ctx);
1301                                 return retval;
1302                         }
1303
1304                         etm_ctx->capture_driver = etm_capture_drivers[i];
1305
1306                         break;
1307                 }
1308         }
1309
1310         if (!etm_capture_drivers[i])
1311         {
1312                 /* no supported capture driver found, don't register an ETM */
1313                 free(etm_ctx);
1314                 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1315                 return ERROR_FAIL;
1316         }
1317
1318         etm_ctx->target = target;
1319         etm_ctx->trigger_percent = 50;
1320         etm_ctx->trace_data = NULL;
1321         etm_ctx->trace_depth = 0;
1322         etm_ctx->portmode = portmode;
1323         etm_ctx->tracemode = 0x0;
1324         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1325         etm_ctx->image = NULL;
1326         etm_ctx->pipe_index = 0;
1327         etm_ctx->data_index = 0;
1328         etm_ctx->current_pc = 0x0;
1329         etm_ctx->pc_ok = 0;
1330         etm_ctx->last_branch = 0x0;
1331         etm_ctx->last_branch_reason = 0x0;
1332         etm_ctx->last_ptr = 0x0;
1333         etm_ctx->ptr_ok = 0x0;
1334         etm_ctx->context_id = 0x0;
1335         etm_ctx->last_instruction = 0;
1336
1337         arm7_9->etm_ctx = etm_ctx;
1338
1339         return etm_register_user_commands(cmd_ctx);
1340 }
1341
1342 int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1343 {
1344         target_t *target;
1345         armv4_5_common_t *armv4_5;
1346         arm7_9_common_t *arm7_9;
1347         reg_t *etm_config_reg;
1348         reg_t *etm_sys_config_reg;
1349
1350         int max_port_size;
1351
1352         target = get_current_target(cmd_ctx);
1353
1354         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1355         {
1356                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1357                 return ERROR_OK;
1358         }
1359
1360         if (!arm7_9->etm_ctx)
1361         {
1362                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1363                 return ERROR_OK;
1364         }
1365
1366         etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
1367         etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
1368
1369         etm_get_reg(etm_config_reg);
1370         command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
1371         command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
1372         command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
1373         command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
1374         command_print(cmd_ctx, "sequencer %spresent",
1375                         (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
1376         command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
1377         command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
1378         command_print(cmd_ctx, "FIFO full %spresent",
1379                         (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
1380         command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
1381
1382         etm_get_reg(etm_sys_config_reg);
1383
1384         switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1385         {
1386                 case 0:
1387                         max_port_size = 4;
1388                         break;
1389                 case 1:
1390                         max_port_size = 8;
1391                         break;
1392                 case 2:
1393                         max_port_size = 16;
1394                         break;
1395                 default:
1396                         LOG_ERROR("Illegal max_port_size");
1397                         exit(-1);
1398         }
1399         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1400
1401         command_print(cmd_ctx, "half-rate clocking %ssupported",
1402                         (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1403         command_print(cmd_ctx, "full-rate clocking %ssupported",
1404                         (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1405         command_print(cmd_ctx, "normal trace format %ssupported",
1406                         (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1407         command_print(cmd_ctx, "multiplex trace format %ssupported",
1408                         (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1409         command_print(cmd_ctx, "demultiplex trace format %ssupported",
1410                         (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1411         command_print(cmd_ctx, "FIFO full %ssupported",
1412                         (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1413
1414         return ERROR_OK;
1415 }
1416
1417 static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1418 {
1419         target_t *target;
1420         armv4_5_common_t *armv4_5;
1421         arm7_9_common_t *arm7_9;
1422         trace_status_t trace_status;
1423
1424         target = get_current_target(cmd_ctx);
1425
1426         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1427         {
1428                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1429                 return ERROR_OK;
1430         }
1431
1432         if (!arm7_9->etm_ctx)
1433         {
1434                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1435                 return ERROR_OK;
1436         }
1437
1438         trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1439
1440         if (trace_status == TRACE_IDLE)
1441         {
1442                 command_print(cmd_ctx, "tracing is idle");
1443         }
1444         else
1445         {
1446                 static char *completed = " completed";
1447                 static char *running = " is running";
1448                 static char *overflowed = ", trace overflowed";
1449                 static char *triggered = ", trace triggered";
1450
1451                 command_print(cmd_ctx, "trace collection%s%s%s",
1452                         (trace_status & TRACE_RUNNING) ? running : completed,
1453                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1454                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1455
1456                 if (arm7_9->etm_ctx->trace_depth > 0)
1457                 {
1458                         command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
1459                 }
1460         }
1461
1462         return ERROR_OK;
1463 }
1464
1465 static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1466 {
1467         target_t *target;
1468         armv4_5_common_t *armv4_5;
1469         arm7_9_common_t *arm7_9;
1470         etm_context_t *etm_ctx;
1471
1472         if (argc < 1)
1473         {
1474                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1475                 return ERROR_OK;
1476         }
1477
1478         target = get_current_target(cmd_ctx);
1479
1480         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1481         {
1482                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1483                 return ERROR_OK;
1484         }
1485
1486         if (!(etm_ctx = arm7_9->etm_ctx))
1487         {
1488                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1489                 return ERROR_OK;
1490         }
1491
1492         if (etm_ctx->image)
1493         {
1494                 image_close(etm_ctx->image);
1495                 free(etm_ctx->image);
1496                 command_print(cmd_ctx, "previously loaded image found and closed");
1497         }
1498
1499         etm_ctx->image = malloc(sizeof(image_t));
1500         etm_ctx->image->base_address_set = 0;
1501         etm_ctx->image->start_address_set = 0;
1502
1503         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1504         if (argc >= 2)
1505         {
1506                 etm_ctx->image->base_address_set = 1;
1507                 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1508         }
1509         else
1510         {
1511                 etm_ctx->image->base_address_set = 0;
1512         }
1513
1514         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1515         {
1516                 free(etm_ctx->image);
1517                 etm_ctx->image = NULL;
1518                 return ERROR_OK;
1519         }
1520
1521         return ERROR_OK;
1522 }
1523
1524 static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1525 {
1526         fileio_t file;
1527         target_t *target;
1528         armv4_5_common_t *armv4_5;
1529         arm7_9_common_t *arm7_9;
1530         etm_context_t *etm_ctx;
1531         u32 i;
1532
1533         if (argc != 1)
1534         {
1535                 command_print(cmd_ctx, "usage: etm dump <file>");
1536                 return ERROR_OK;
1537         }
1538
1539         target = get_current_target(cmd_ctx);
1540
1541         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1542         {
1543                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1544                 return ERROR_OK;
1545         }
1546
1547         if (!(etm_ctx = arm7_9->etm_ctx))
1548         {
1549                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1550                 return ERROR_OK;
1551         }
1552
1553         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1554         {
1555                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1556                 return ERROR_OK;
1557         }
1558
1559         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1560         {
1561                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1562                 command_print(cmd_ctx, "trace capture not completed");
1563                 return ERROR_OK;
1564         }
1565
1566         /* read the trace data if it wasn't read already */
1567         if (etm_ctx->trace_depth == 0)
1568                 etm_ctx->capture_driver->read_trace(etm_ctx);
1569
1570         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1571         {
1572                 return ERROR_OK;
1573         }
1574
1575         fileio_write_u32(&file, etm_ctx->capture_status);
1576         fileio_write_u32(&file, etm_ctx->portmode);
1577         fileio_write_u32(&file, etm_ctx->tracemode);
1578         fileio_write_u32(&file, etm_ctx->trace_depth);
1579
1580         for (i = 0; i < etm_ctx->trace_depth; i++)
1581         {
1582                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1583                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1584                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1585         }
1586
1587         fileio_close(&file);
1588
1589         return ERROR_OK;
1590 }
1591
1592 static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1593 {
1594         fileio_t file;
1595         target_t *target;
1596         armv4_5_common_t *armv4_5;
1597         arm7_9_common_t *arm7_9;
1598         etm_context_t *etm_ctx;
1599         u32 i;
1600
1601         if (argc != 1)
1602         {
1603                 command_print(cmd_ctx, "usage: etm load <file>");
1604                 return ERROR_OK;
1605         }
1606
1607         target = get_current_target(cmd_ctx);
1608
1609         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1610         {
1611                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1612                 return ERROR_OK;
1613         }
1614
1615         if (!(etm_ctx = arm7_9->etm_ctx))
1616         {
1617                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1618                 return ERROR_OK;
1619         }
1620
1621         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1622         {
1623                 command_print(cmd_ctx, "trace capture running, stop first");
1624                 return ERROR_OK;
1625         }
1626
1627         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1628         {
1629                 return ERROR_OK;
1630         }
1631
1632         if (file.size % 4)
1633         {
1634                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1635                 fileio_close(&file);
1636                 return ERROR_OK;
1637         }
1638
1639         if (etm_ctx->trace_depth > 0)
1640         {
1641                 free(etm_ctx->trace_data);
1642                 etm_ctx->trace_data = NULL;
1643         }
1644
1645         fileio_read_u32(&file, &etm_ctx->capture_status);
1646         fileio_read_u32(&file, &etm_ctx->portmode);
1647         fileio_read_u32(&file, &etm_ctx->tracemode);
1648         fileio_read_u32(&file, &etm_ctx->trace_depth);
1649
1650         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1651         if(etm_ctx->trace_data == NULL)
1652         {
1653                 command_print(cmd_ctx, "not enough memory to perform operation");
1654                 fileio_close(&file);
1655                 return ERROR_OK;
1656         }
1657
1658         for (i = 0; i < etm_ctx->trace_depth; i++)
1659         {
1660                 u32 pipestat, packet, flags;
1661                 fileio_read_u32(&file, &pipestat);
1662                 fileio_read_u32(&file, &packet);
1663                 fileio_read_u32(&file, &flags);
1664                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1665                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1666                 etm_ctx->trace_data[i].flags = flags;
1667         }
1668
1669         fileio_close(&file);
1670
1671         return ERROR_OK;
1672 }
1673
1674 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1675 {
1676         target_t *target;
1677         armv4_5_common_t *armv4_5;
1678         arm7_9_common_t *arm7_9;
1679         etm_context_t *etm_ctx;
1680
1681         target = get_current_target(cmd_ctx);
1682
1683         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1684         {
1685                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1686                 return ERROR_OK;
1687         }
1688
1689         if (!(etm_ctx = arm7_9->etm_ctx))
1690         {
1691                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1692                 return ERROR_OK;
1693         }
1694
1695         if (argc > 0)
1696         {
1697                 u32 new_value = strtoul(args[0], NULL, 0);
1698
1699                 if ((new_value < 2) || (new_value > 100))
1700                 {
1701                         command_print(cmd_ctx, "valid settings are 2% to 100%");
1702                 }
1703                 else
1704                 {
1705                         etm_ctx->trigger_percent = new_value;
1706                 }
1707         }
1708
1709         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
1710
1711         return ERROR_OK;
1712 }
1713
1714 static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1715 {
1716         target_t *target;
1717         armv4_5_common_t *armv4_5;
1718         arm7_9_common_t *arm7_9;
1719         etm_context_t *etm_ctx;
1720         reg_t *etm_ctrl_reg;
1721
1722         target = get_current_target(cmd_ctx);
1723
1724         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1725         {
1726                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1727                 return ERROR_OK;
1728         }
1729
1730         if (!(etm_ctx = arm7_9->etm_ctx))
1731         {
1732                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1733                 return ERROR_OK;
1734         }
1735
1736         /* invalidate old tracing data */
1737         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1738         if (arm7_9->etm_ctx->trace_depth > 0)
1739         {
1740                 free(arm7_9->etm_ctx->trace_data);
1741                 arm7_9->etm_ctx->trace_data = NULL;
1742         }
1743         arm7_9->etm_ctx->trace_depth = 0;
1744
1745         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1746         etm_get_reg(etm_ctrl_reg);
1747
1748         /* Clear programming bit (10), set port selection bit (11) */
1749         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1750
1751         etm_store_reg(etm_ctrl_reg);
1752         jtag_execute_queue();
1753
1754         etm_ctx->capture_driver->start_capture(etm_ctx);
1755
1756         return ERROR_OK;
1757 }
1758
1759 static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1760 {
1761         target_t *target;
1762         armv4_5_common_t *armv4_5;
1763         arm7_9_common_t *arm7_9;
1764         etm_context_t *etm_ctx;
1765         reg_t *etm_ctrl_reg;
1766
1767         target = get_current_target(cmd_ctx);
1768
1769         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1770         {
1771                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1772                 return ERROR_OK;
1773         }
1774
1775         if (!(etm_ctx = arm7_9->etm_ctx))
1776         {
1777                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1778                 return ERROR_OK;
1779         }
1780
1781         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1782         etm_get_reg(etm_ctrl_reg);
1783
1784         /* Set programming bit (10), clear port selection bit (11) */
1785         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1786
1787         etm_store_reg(etm_ctrl_reg);
1788         jtag_execute_queue();
1789
1790         etm_ctx->capture_driver->stop_capture(etm_ctx);
1791
1792         return ERROR_OK;
1793 }
1794
1795 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1796 {
1797         target_t *target;
1798         armv4_5_common_t *armv4_5;
1799         arm7_9_common_t *arm7_9;
1800         etm_context_t *etm_ctx;
1801         int retval;
1802
1803         target = get_current_target(cmd_ctx);
1804
1805         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1806         {
1807                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1808                 return ERROR_OK;
1809         }
1810
1811         if (!(etm_ctx = arm7_9->etm_ctx))
1812         {
1813                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1814                 return ERROR_OK;
1815         }
1816
1817         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1818         {
1819                 switch(retval)
1820                 {
1821                         case ERROR_ETM_ANALYSIS_FAILED:
1822                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1823                                 break;
1824                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1825                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1826                                 break;
1827                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
1828                                 command_print(cmd_ctx, "no image available for trace analysis");
1829                                 break;
1830                         default:
1831                                 command_print(cmd_ctx, "unknown error: %i", retval);
1832                 }
1833         }
1834
1835         return ERROR_OK;
1836 }
1837
1838 int etm_register_commands(struct command_context_s *cmd_ctx)
1839 {
1840         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1841
1842         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1843
1844         return ERROR_OK;
1845 }
1846
1847 int etm_register_user_commands(struct command_context_s *cmd_ctx)
1848 {
1849         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1850                 COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
1851
1852         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
1853                 COMMAND_EXEC, "display info about the current target's ETM");
1854
1855         register_command(cmd_ctx, etm_cmd, "trigger_percent <percent>", handle_etm_trigger_percent_command,
1856                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1857         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1858                 COMMAND_EXEC, "display current target's ETM status");
1859         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1860                 COMMAND_EXEC, "start ETM trace collection");
1861         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1862                 COMMAND_EXEC, "stop ETM trace collection");
1863
1864         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1865                 COMMAND_EXEC, "anaylze collected ETM trace");
1866
1867         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1868                 COMMAND_EXEC, "load image from <file> [base address]");
1869
1870         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1871                 COMMAND_EXEC, "dump captured trace data <file>");
1872         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1873                 COMMAND_EXEC, "load trace data for analysis <file>");
1874
1875         return ERROR_OK;
1876 }