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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "armv4_5.h"
  25 #include "etb.h"
  26 #include "image.h"
  27 #include "arm_disassembler.h"
  28
  29
  30 /*
  31  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  32  *
  33  * ETM modules collect instruction and/or data trace information, compress
  34  * it, and transfer it to a debugging host through either a (buffered) trace
  35  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  36  *
  37  * There are several generations of these modules.  Original versions have
  38  * JTAG access through a dedicated scan chain.  Recent versions have added
  39  * access via coprocessor instructions, memory addressing, and the ARM Debug
  40  * Interface v5 (ADIv5); and phased out direct JTAG access.
  41  *
  42  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  43  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  44  * implying non-JTAG connectivity options.
  45  *
  46  * Relevant documentation includes:
  47  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  48  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  49  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  50  */
  51
  52 #define ARRAY_SIZE(x)   ((int)(sizeof(x)/sizeof((x)[0])))
  53
  54 enum {
  55         RO,                             /* read/only */
  56         WO,                             /* write/only */
  57         RW,                             /* read/write */
  58 };
  59
  60 struct etm_reg_info {
  61         uint8_t         addr;
  62         uint8_t         size;           /* low-N of 32 bits */
  63         uint8_t         mode;           /* RO, WO, RW */
  64         uint8_t         bcd_vers;       /* 1.0, 2.0, etc */
  65         char            *name;
  66 };
  67
  68 /*
  69  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  70  * (Or on some processors, through coprocessor operations.)
  71  * Newer versions of ETM make some W/O registers R/W, and
  72  * provide definitions for some previously-unused bits.
  73  */
  74
  75 /* basic registers that are always there given the right ETM version */
  76 static const struct etm_reg_info etm_core[] = {
  77         /* NOTE: we "know" ETM_CONFIG is listed first */
  78         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  79
  80         /* ETM Trace Registers */
  81         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  82         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  83         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
  84         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
  85         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
  86
  87         /* TraceEnable configuration */
  88         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  89         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  90         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
  91         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
  92
  93         /* ViewData configuration (data trace) */
  94         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
  95         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
  96         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
  97         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
  98
  99         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 100
 101         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
 102         { 0x79, 32, RO, 0x20, "ETM_id", },
 103 };
 104
 105 static const struct etm_reg_info etm_fifofull[] = {
 106         /* FIFOFULL configuration */
 107         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
 108         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
 109 };
 110
 111 static const struct etm_reg_info etm_addr_comp[] = {
 112         /* Address comparator register pairs */
 113 #define ADDR_COMPARATOR(i) \
 114                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
 115                                 "ETM_addr_" #i "_comparator_value", }, \
 116                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
 117                                 "ETM_addr_" #i "_access_type", }
 118         ADDR_COMPARATOR(1),
 119         ADDR_COMPARATOR(2),
 120         ADDR_COMPARATOR(3),
 121         ADDR_COMPARATOR(4),
 122         ADDR_COMPARATOR(5),
 123         ADDR_COMPARATOR(6),
 124         ADDR_COMPARATOR(7),
 125         ADDR_COMPARATOR(8),
 126
 127         ADDR_COMPARATOR(9),
 128         ADDR_COMPARATOR(10),
 129         ADDR_COMPARATOR(11),
 130         ADDR_COMPARATOR(12),
 131         ADDR_COMPARATOR(13),
 132         ADDR_COMPARATOR(14),
 133         ADDR_COMPARATOR(15),
 134         ADDR_COMPARATOR(16),
 135 #undef ADDR_COMPARATOR
 136 };
 137
 138 static const struct etm_reg_info etm_data_comp[] = {
 139         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 140 #define DATA_COMPARATOR(i) \
 141                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
 142                                 "ETM_data_" #i "_comparator_value", }, \
 143                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
 144                                 "ETM_data_" #i "_comparator_mask", }
 145         DATA_COMPARATOR(1),
 146         DATA_COMPARATOR(2),
 147         DATA_COMPARATOR(3),
 148         DATA_COMPARATOR(4),
 149         DATA_COMPARATOR(5),
 150         DATA_COMPARATOR(6),
 151         DATA_COMPARATOR(7),
 152         DATA_COMPARATOR(8),
 153 #undef DATA_COMPARATOR
 154 };
 155
 156 static const struct etm_reg_info etm_counters[] = {
 157 #define ETM_COUNTER(i) \
 158                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
 159                                 "ETM_counter_" #i "_reload_value", }, \
 160                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
 161                                 "ETM_counter_" #i "_enable", }, \
 162                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
 163                                 "ETM_counter_" #i "_reload_event", }, \
 164                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
 165                                 "ETM_counter_" #i "_value", }
 166         ETM_COUNTER(1),
 167         ETM_COUNTER(2),
 168         ETM_COUNTER(3),
 169         ETM_COUNTER(4),
 170 #undef ETM_COUNTER
 171 };
 172
 173 static const struct etm_reg_info etm_sequencer[] = {
 174 #define ETM_SEQ(i) \
 175                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 176                                 "ETM_sequencer_event" #i, }
 177         ETM_SEQ(0),                             /* 1->2 */
 178         ETM_SEQ(1),                             /* 2->1 */
 179         ETM_SEQ(2),                             /* 2->3 */
 180         ETM_SEQ(3),                             /* 3->1 */
 181         ETM_SEQ(4),                             /* 3->2 */
 182         ETM_SEQ(5),                             /* 1->3 */
 183 #undef ETM_SEQ
 184         /* 0x66 reserved */
 185         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
 186 };
 187
 188 static const struct etm_reg_info etm_outputs[] = {
 189 #define ETM_OUTPUT(i) \
 190                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
 191                                 "ETM_external_output" #i, }
 192
 193         ETM_OUTPUT(1),
 194         ETM_OUTPUT(2),
 195         ETM_OUTPUT(3),
 196         ETM_OUTPUT(4),
 197 #undef ETM_OUTPUT
 198 };
 199
 200 #if 0
 201         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 202
 203         /* Context ID Comparators */
 204         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
 205         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
 206         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
 207         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
 208 #endif
 209
 210 static int etm_reg_arch_type = -1;
 211
 212 static int etm_get_reg(reg_t *reg);
 213 static int etm_read_reg_w_check(reg_t *reg,
 214                 uint8_t* check_value, uint8_t* check_mask);
 215 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
 216 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
 217 static int etm_write_reg(reg_t *reg, uint32_t value);
 218
 219 static command_t *etm_cmd;
 220
 221
 222 /* Look up register by ID ... most ETM instances only
 223  * support a subset of the possible registers.
 224  */
 225 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
 226 {
 227         reg_cache_t *cache = etm_ctx->reg_cache;
 228         int i;
 229
 230         for (i = 0; i < cache->num_regs; i++) {
 231                 struct etm_reg_s *reg = cache->reg_list[i].arch_info;
 232
 233                 if (reg->reg_info->addr == id)
 234                         return &cache->reg_list[i];
 235         }
 236
 237         /* caller asking for nonexistent register is a bug! */
 238         /* REVISIT say which of the N targets was involved */
 239         LOG_ERROR("ETM: register 0x%02x not available", id);
 240         return NULL;
 241 }
 242
 243 static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
 244                 reg_cache_t *cache, etm_reg_t *ereg,
 245                 const struct etm_reg_info *r, unsigned nreg)
 246 {
 247         reg_t *reg = cache->reg_list;
 248
 249         reg += cache->num_regs;
 250         ereg += cache->num_regs;
 251
 252         /* add up to "nreg" registers from "r", if supported by this
 253          * version of the ETM, to the specified cache.
 254          */
 255         for (; nreg--; r++) {
 256
 257                 /* this ETM may be too old to have some registers */
 258                 if (r->bcd_vers > bcd_vers)
 259                         continue;
 260
 261                 reg->name = r->name;
 262                 reg->size = r->size;
 263                 reg->value = &ereg->value;
 264                 reg->arch_info = ereg;
 265                 reg->arch_type = etm_reg_arch_type;
 266                 reg++;
 267                 cache->num_regs++;
 268
 269                 ereg->reg_info = r;
 270                 ereg->jtag_info = jtag_info;
 271                 ereg++;
 272         }
 273 }
 274
 275 reg_cache_t *etm_build_reg_cache(target_t *target,
 276                 arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 277 {
 278         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 279         reg_t *reg_list = NULL;
 280         etm_reg_t *arch_info = NULL;
 281         unsigned bcd_vers, config;
 282
 283         /* register a register arch-type for etm registers only once */
 284         if (etm_reg_arch_type == -1)
 285                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
 286                                 etm_set_reg_w_exec);
 287
 288         /* the actual registers are kept in two arrays */
 289         reg_list = calloc(128, sizeof(reg_t));
 290         arch_info = calloc(128, sizeof(etm_reg_t));
 291
 292         /* fill in values for the reg cache */
 293         reg_cache->name = "etm registers";
 294         reg_cache->next = NULL;
 295         reg_cache->reg_list = reg_list;
 296         reg_cache->num_regs = 0;
 297
 298         /* add ETM_CONFIG, then parse its values to see
 299          * which other registers exist in this ETM
 300          */
 301         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 302                         etm_core, 1);
 303
 304         etm_get_reg(reg_list);
 305         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 306         config = etm_ctx->config;
 307
 308         /* figure ETM version then add base registers */
 309         if (config & (1 << 31)) {
 310                 bcd_vers = 0x20;
 311                 LOG_WARNING("ETMv2+ support is incomplete");
 312
 313                 /* REVISIT read ID register, distinguish ETMv3.3 etc;
 314                  * don't presume trace start/stop support is present;
 315                  * and include any context ID comparator registers.
 316                  */
 317         } else {
 318                 switch (config >> 28) {
 319                 case 7:
 320                 case 5:
 321                 case 3:
 322                         bcd_vers = 0x13;
 323                         break;
 324                 case 4:
 325                 case 2:
 326                         bcd_vers = 0x12;
 327                         break;
 328                 case 1:
 329                         bcd_vers = 0x11;
 330                         break;
 331                 case 0:
 332                         bcd_vers = 0x10;
 333                         break;
 334                 default:
 335                         LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 336                         free(reg_cache);
 337                         free(reg_list);
 338                         free(arch_info);
 339                         return ERROR_OK;
 340                 }
 341         }
 342         etm_ctx->bcd_vers = bcd_vers;
 343         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 344
 345         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 346                         etm_core + 1, ARRAY_SIZE(etm_core) - 1);
 347
 348         /* address and data comparators; counters; outputs */
 349         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 350                         etm_addr_comp, 4 * (0x0f & (config >> 0)));
 351         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 352                         etm_data_comp, 2 * (0x0f & (config >> 4)));
 353         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 354                         etm_counters, 4 * (0x07 & (config >> 13)));
 355         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 356                         etm_outputs, (0x07 & (config >> 20)));
 357
 358         /* FIFOFULL presence is optional
 359          * REVISIT for ETMv1.2 and later, don't bother adding this
 360          * unless ETM_SYS_CONFIG says it's also *supported* ...
 361          */
 362         if (config & (1 << 23))
 363                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 364                                 etm_fifofull, ARRAY_SIZE(etm_fifofull));
 365
 366         /* sequencer is optional (for state-dependant triggering) */
 367         if (config & (1 << 16))
 368                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 369                                 etm_sequencer, ARRAY_SIZE(etm_sequencer));
 370
 371         /* REVISIT could realloc and likely save half the memory
 372          * in the two chunks we allocated...
 373          */
 374
 375         /* the ETM might have an ETB connected */
 376         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 377         {
 378                 etb_t *etb = etm_ctx->capture_driver_priv;
 379
 380                 if (!etb)
 381                 {
 382                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 383                         free(reg_cache);
 384                         free(reg_list);
 385                         free(arch_info);
 386                         return ERROR_OK;
 387                 }
 388
 389                 reg_cache->next = etb_build_reg_cache(etb);
 390
 391                 etb->reg_cache = reg_cache->next;
 392         }
 393
 394
 395         return reg_cache;
 396 }
 397
 398 static int etm_read_reg(reg_t *reg)
 399 {
 400         return etm_read_reg_w_check(reg, NULL, NULL);
 401 }
 402
 403 static int etm_store_reg(reg_t *reg)
 404 {
 405         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 406 }
 407
 408 int etm_setup(target_t *target)
 409 {
 410         int retval;
 411         uint32_t etm_ctrl_value;
 412         struct arm *arm = target_to_arm(target);
 413         etm_context_t *etm_ctx = arm->etm;
 414         reg_t *etm_ctrl_reg;
 415
 416         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 417         if (!etm_ctrl_reg)
 418                 return ERROR_OK;
 419
 420         /* initialize some ETM control register settings */
 421         etm_get_reg(etm_ctrl_reg);
 422         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
 423
 424         /* clear the ETM powerdown bit (0) */
 425         etm_ctrl_value &= ~0x1;
 426
 427         /* configure port width (6:4), mode (17:16) and clocking (13) */
 428         etm_ctrl_value = (etm_ctrl_value &
 429                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 430                 | etm_ctx->portmode;
 431
 432         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 433         etm_store_reg(etm_ctrl_reg);
 434
 435         if ((retval = jtag_execute_queue()) != ERROR_OK)
 436                 return retval;
 437
 438         if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 439         {
 440                 LOG_ERROR("ETM capture driver initialization failed");
 441                 return retval;
 442         }
 443         return ERROR_OK;
 444 }
 445
 446 static int etm_get_reg(reg_t *reg)
 447 {
 448         int retval;
 449
 450         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 451         {
 452                 LOG_ERROR("BUG: error scheduling etm register read");
 453                 return retval;
 454         }
 455
 456         if ((retval = jtag_execute_queue()) != ERROR_OK)
 457         {
 458                 LOG_ERROR("register read failed");
 459                 return retval;
 460         }
 461
 462         return ERROR_OK;
 463 }
 464
 465 static int etm_read_reg_w_check(reg_t *reg,
 466                 uint8_t* check_value, uint8_t* check_mask)
 467 {
 468         etm_reg_t *etm_reg = reg->arch_info;
 469         const struct etm_reg_info *r = etm_reg->reg_info;
 470         uint8_t reg_addr = r->addr & 0x7f;
 471         scan_field_t fields[3];
 472
 473         if (etm_reg->reg_info->mode == WO) {
 474                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 475                 return ERROR_INVALID_ARGUMENTS;
 476         }
 477
 478         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 479
 480         jtag_set_end_state(TAP_IDLE);
 481         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 482         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 483
 484         fields[0].tap = etm_reg->jtag_info->tap;
 485         fields[0].num_bits = 32;
 486         fields[0].out_value = reg->value;
 487         fields[0].in_value = NULL;
 488         fields[0].check_value = NULL;
 489         fields[0].check_mask = NULL;
 490
 491         fields[1].tap = etm_reg->jtag_info->tap;
 492         fields[1].num_bits = 7;
 493         fields[1].out_value = malloc(1);
 494         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 495         fields[1].in_value = NULL;
 496         fields[1].check_value = NULL;
 497         fields[1].check_mask = NULL;
 498
 499         fields[2].tap = etm_reg->jtag_info->tap;
 500         fields[2].num_bits = 1;
 501         fields[2].out_value = malloc(1);
 502         buf_set_u32(fields[2].out_value, 0, 1, 0);
 503         fields[2].in_value = NULL;
 504         fields[2].check_value = NULL;
 505         fields[2].check_mask = NULL;
 506
 507         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 508
 509         fields[0].in_value = reg->value;
 510         fields[0].check_value = check_value;
 511         fields[0].check_mask = check_mask;
 512
 513         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 514
 515         free(fields[1].out_value);
 516         free(fields[2].out_value);
 517
 518         return ERROR_OK;
 519 }
 520
 521 static int etm_set_reg(reg_t *reg, uint32_t value)
 522 {
 523         int retval;
 524
 525         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 526         {
 527                 LOG_ERROR("BUG: error scheduling etm register write");
 528                 return retval;
 529         }
 530
 531         buf_set_u32(reg->value, 0, reg->size, value);
 532         reg->valid = 1;
 533         reg->dirty = 0;
 534
 535         return ERROR_OK;
 536 }
 537
 538 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 539 {
 540         int retval;
 541
 542         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 543
 544         if ((retval = jtag_execute_queue()) != ERROR_OK)
 545         {
 546                 LOG_ERROR("register write failed");
 547                 return retval;
 548         }
 549         return ERROR_OK;
 550 }
 551
 552 static int etm_write_reg(reg_t *reg, uint32_t value)
 553 {
 554         etm_reg_t *etm_reg = reg->arch_info;
 555         const struct etm_reg_info *r = etm_reg->reg_info;
 556         uint8_t reg_addr = r->addr & 0x7f;
 557         scan_field_t fields[3];
 558
 559         if (etm_reg->reg_info->mode == RO) {
 560                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 561                 return ERROR_INVALID_ARGUMENTS;
 562         }
 563
 564         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 565
 566         jtag_set_end_state(TAP_IDLE);
 567         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 568         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 569
 570         fields[0].tap = etm_reg->jtag_info->tap;
 571         fields[0].num_bits = 32;
 572         uint8_t tmp1[4];
 573         fields[0].out_value = tmp1;
 574         buf_set_u32(fields[0].out_value, 0, 32, value);
 575         fields[0].in_value = NULL;
 576
 577         fields[1].tap = etm_reg->jtag_info->tap;
 578         fields[1].num_bits = 7;
 579         uint8_t tmp2;
 580         fields[1].out_value = &tmp2;
 581         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 582         fields[1].in_value = NULL;
 583
 584         fields[2].tap = etm_reg->jtag_info->tap;
 585         fields[2].num_bits = 1;
 586         uint8_t tmp3;
 587         fields[2].out_value = &tmp3;
 588         buf_set_u32(fields[2].out_value, 0, 1, 1);
 589         fields[2].in_value = NULL;
 590
 591         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 592
 593         return ERROR_OK;
 594 }
 595
 596
 597 /* ETM trace analysis functionality
 598  *
 599  */
 600 extern etm_capture_driver_t etm_dummy_capture_driver;
 601 #if BUILD_OOCD_TRACE == 1
 602 extern etm_capture_driver_t oocd_trace_capture_driver;
 603 #endif
 604
 605 static etm_capture_driver_t *etm_capture_drivers[] =
 606 {
 607         &etb_capture_driver,
 608         &etm_dummy_capture_driver,
 609 #if BUILD_OOCD_TRACE == 1
 610         &oocd_trace_capture_driver,
 611 #endif
 612         NULL
 613 };
 614
 615 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 616 {
 617         int i;
 618         int section = -1;
 619         uint32_t size_read;
 620         uint32_t opcode;
 621         int retval;
 622
 623         if (!ctx->image)
 624                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 625
 626         /* search for the section the current instruction belongs to */
 627         for (i = 0; i < ctx->image->num_sections; i++)
 628         {
 629                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 630                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 631                 {
 632                         section = i;
 633                         break;
 634                 }
 635         }
 636
 637         if (section == -1)
 638         {
 639                 /* current instruction couldn't be found in the image */
 640                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 641         }
 642
 643         if (ctx->core_state == ARMV4_5_STATE_ARM)
 644         {
 645                 uint8_t buf[4];
 646                 if ((retval = image_read_section(ctx->image, section,
 647                         ctx->current_pc - ctx->image->sections[section].base_address,
 648                         4, buf, &size_read)) != ERROR_OK)
 649                 {
 650                         LOG_ERROR("error while reading instruction: %i", retval);
 651                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 652                 }
 653                 opcode = target_buffer_get_u32(ctx->target, buf);
 654                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 655         }
 656         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 657         {
 658                 uint8_t buf[2];
 659                 if ((retval = image_read_section(ctx->image, section,
 660                         ctx->current_pc - ctx->image->sections[section].base_address,
 661                         2, buf, &size_read)) != ERROR_OK)
 662                 {
 663                         LOG_ERROR("error while reading instruction: %i", retval);
 664                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 665                 }
 666                 opcode = target_buffer_get_u16(ctx->target, buf);
 667                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 668         }
 669         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 670         {
 671                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 672                 return ERROR_FAIL;
 673         }
 674         else
 675         {
 676                 LOG_ERROR("BUG: unknown core state encountered");
 677                 return ERROR_FAIL;
 678         }
 679
 680         return ERROR_OK;
 681 }
 682
 683 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
 684 {
 685         while (ctx->data_index < ctx->trace_depth)
 686         {
 687                 /* if the caller specified an address packet offset, skip until the
 688                  * we reach the n-th cycle marked with tracesync */
 689                 if (apo > 0)
 690                 {
 691                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 692                                 apo--;
 693
 694                         if (apo > 0)
 695                         {
 696                                 ctx->data_index++;
 697                                 ctx->data_half = 0;
 698                         }
 699                         continue;
 700                 }
 701
 702                 /* no tracedata output during a TD cycle
 703                  * or in a trigger cycle */
 704                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 705                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 706                 {
 707                         ctx->data_index++;
 708                         ctx->data_half = 0;
 709                         continue;
 710                 }
 711
 712                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 713                 {
 714                         if (ctx->data_half == 0)
 715                         {
 716                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 717                                 ctx->data_half = 1;
 718                         }
 719                         else
 720                         {
 721                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 722                                 ctx->data_half = 0;
 723                                 ctx->data_index++;
 724                         }
 725                 }
 726                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 727                 {
 728                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 729                         ctx->data_index++;
 730                 }
 731                 else
 732                 {
 733                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 734                         if (ctx->data_index > (ctx->trace_depth - 2))
 735                                 return -1;
 736
 737                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 738                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 739                         ctx->data_index += 2;
 740                 }
 741
 742                 return 0;
 743         }
 744
 745         return -1;
 746 }
 747
 748 static int etmv1_branch_address(etm_context_t *ctx)
 749 {
 750         int retval;
 751         uint8_t packet;
 752         int shift = 0;
 753         int apo;
 754         uint32_t i;
 755
 756         /* quit analysis if less than two cycles are left in the trace
 757          * because we can't extract the APO */
 758         if (ctx->data_index > (ctx->trace_depth - 2))
 759                 return -1;
 760
 761         /* a BE could be output during an APO cycle, skip the current
 762          * and continue with the new one */
 763         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 764                 return 1;
 765         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 766                 return 2;
 767
 768         /* address packet offset encoded in the next two cycles' pipestat bits */
 769         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 770         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 771
 772         /* count number of tracesync cycles between current pipe_index and data_index
 773          * i.e. the number of tracesyncs that data_index already passed by
 774          * to subtract them from the APO */
 775         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 776         {
 777                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 778                         apo--;
 779         }
 780
 781         /* extract up to four 7-bit packets */
 782         do {
 783                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 784                         return -1;
 785                 ctx->last_branch &= ~(0x7f << shift);
 786                 ctx->last_branch |= (packet & 0x7f) << shift;
 787                 shift += 7;
 788         } while ((packet & 0x80) && (shift < 28));
 789
 790         /* one last packet holding 4 bits of the address, plus the branch reason code */
 791         if ((shift == 28) && (packet & 0x80))
 792         {
 793                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 794                         return -1;
 795                 ctx->last_branch &= 0x0fffffff;
 796                 ctx->last_branch |= (packet & 0x0f) << 28;
 797                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 798                 shift += 4;
 799         }
 800         else
 801         {
 802                 ctx->last_branch_reason = 0;
 803         }
 804
 805         if (shift == 32)
 806         {
 807                 ctx->pc_ok = 1;
 808         }
 809
 810         /* if a full address was output, we might have branched into Jazelle state */
 811         if ((shift == 32) && (packet & 0x80))
 812         {
 813                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 814         }
 815         else
 816         {
 817                 /* if we didn't branch into Jazelle state, the current processor state is
 818                  * encoded in bit 0 of the branch target address */
 819                 if (ctx->last_branch & 0x1)
 820                 {
 821                         ctx->core_state = ARMV4_5_STATE_THUMB;
 822                         ctx->last_branch &= ~0x1;
 823                 }
 824                 else
 825                 {
 826                         ctx->core_state = ARMV4_5_STATE_ARM;
 827                         ctx->last_branch &= ~0x3;
 828                 }
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
 835 {
 836         int j;
 837         uint8_t buf[4];
 838         int retval;
 839
 840         for (j = 0; j < size; j++)
 841         {
 842                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 843                         return -1;
 844         }
 845
 846         if (size == 8)
 847         {
 848                 LOG_ERROR("TODO: add support for 64-bit values");
 849                 return -1;
 850         }
 851         else if (size == 4)
 852                 *data = target_buffer_get_u32(ctx->target, buf);
 853         else if (size == 2)
 854                 *data = target_buffer_get_u16(ctx->target, buf);
 855         else if (size == 1)
 856                 *data = buf[0];
 857         else
 858                 return -1;
 859
 860         return 0;
 861 }
 862
 863 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 864 {
 865         int retval;
 866         arm_instruction_t instruction;
 867
 868         /* read the trace data if it wasn't read already */
 869         if (ctx->trace_depth == 0)
 870                 ctx->capture_driver->read_trace(ctx);
 871
 872         /* start at the beginning of the captured trace */
 873         ctx->pipe_index = 0;
 874         ctx->data_index = 0;
 875         ctx->data_half = 0;
 876
 877         /* neither the PC nor the data pointer are valid */
 878         ctx->pc_ok = 0;
 879         ctx->ptr_ok = 0;
 880
 881         while (ctx->pipe_index < ctx->trace_depth)
 882         {
 883                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 884                 uint32_t next_pc = ctx->current_pc;
 885                 uint32_t old_data_index = ctx->data_index;
 886                 uint32_t old_data_half = ctx->data_half;
 887                 uint32_t old_index = ctx->pipe_index;
 888                 uint32_t last_instruction = ctx->last_instruction;
 889                 uint32_t cycles = 0;
 890                 int current_pc_ok = ctx->pc_ok;
 891
 892                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 893                 {
 894                         command_print(cmd_ctx, "--- trigger ---");
 895                 }
 896
 897                 /* instructions execute in IE/D or BE/D cycles */
 898                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 899                         ctx->last_instruction = ctx->pipe_index;
 900
 901                 /* if we don't have a valid pc skip until we reach an indirect branch */
 902                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 903                 {
 904                         ctx->pipe_index++;
 905                         continue;
 906                 }
 907
 908                 /* any indirect branch could have interrupted instruction flow
 909                  * - the branch reason code could indicate a trace discontinuity
 910                  * - a branch to the exception vectors indicates an exception
 911                  */
 912                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 913                 {
 914                         /* backup current data index, to be able to consume the branch address
 915                          * before examining data address and values
 916                          */
 917                         old_data_index = ctx->data_index;
 918                         old_data_half = ctx->data_half;
 919
 920                         ctx->last_instruction = ctx->pipe_index;
 921
 922                         if ((retval = etmv1_branch_address(ctx)) != 0)
 923                         {
 924                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 925                                  * quit analysing the trace */
 926                                 if (retval < 0)
 927                                         break;
 928
 929                                 /* a positive return values means the current branch was abandoned,
 930                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 931                                  */
 932                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 933                                 ctx->pipe_index += retval;
 934                                 continue;
 935                         }
 936
 937                         /* skip over APO cycles */
 938                         ctx->pipe_index += 2;
 939
 940                         switch (ctx->last_branch_reason)
 941                         {
 942                                 case 0x0:       /* normal PC change */
 943                                         next_pc = ctx->last_branch;
 944                                         break;
 945                                 case 0x1:       /* tracing enabled */
 946                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 947                                         ctx->current_pc = ctx->last_branch;
 948                                         ctx->pipe_index++;
 949                                         continue;
 950                                         break;
 951                                 case 0x2:       /* trace restarted after FIFO overflow */
 952                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 953                                         ctx->current_pc = ctx->last_branch;
 954                                         ctx->pipe_index++;
 955                                         continue;
 956                                         break;
 957                                 case 0x3:       /* exit from debug state */
 958                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 959                                         ctx->current_pc = ctx->last_branch;
 960                                         ctx->pipe_index++;
 961                                         continue;
 962                                         break;
 963                                 case 0x4:       /* periodic synchronization point */
 964                                         next_pc = ctx->last_branch;
 965                                         /* if we had no valid PC prior to this synchronization point,
 966                                          * we have to move on with the next trace cycle
 967                                          */
 968                                         if (!current_pc_ok)
 969                                         {
 970                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 971                                                 ctx->current_pc = next_pc;
 972                                                 ctx->pipe_index++;
 973                                                 continue;
 974                                         }
 975                                         break;
 976                                 default:        /* reserved */
 977                                         LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
 978                                         return ERROR_FAIL;
 979                         }
 980
 981                         /* if we got here the branch was a normal PC change
 982                          * (or a periodic synchronization point, which means the same for that matter)
 983                          * if we didn't accquire a complete PC continue with the next cycle
 984                          */
 985                         if (!ctx->pc_ok)
 986                                 continue;
 987
 988                         /* indirect branch to the exception vector means an exception occured */
 989                         if ((ctx->last_branch <= 0x20)
 990                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 991                         {
 992                                 if ((ctx->last_branch & 0xff) == 0x10)
 993                                 {
 994                                         command_print(cmd_ctx, "data abort");
 995                                 }
 996                                 else
 997                                 {
 998                                         command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
 999                                         ctx->current_pc = ctx->last_branch;
1000                                         ctx->pipe_index++;
1001                                         continue;
1002                                 }
1003                         }
1004                 }
1005
1006                 /* an instruction was executed (or not, depending on the condition flags)
1007                  * retrieve it from the image for displaying */
1008                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1009                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1010                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1011                 {
1012                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1013                         {
1014                                 /* can't continue tracing with no image available */
1015                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1016                                 {
1017                                         return retval;
1018                                 }
1019                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1020                                 {
1021                                         /* TODO: handle incomplete images
1022                                          * for now we just quit the analsysis*/
1023                                         return retval;
1024                                 }
1025                         }
1026
1027                         cycles = old_index - last_instruction;
1028                 }
1029
1030                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1031                 {
1032                         uint32_t new_data_index = ctx->data_index;
1033                         uint32_t new_data_half = ctx->data_half;
1034
1035                         /* in case of a branch with data, the branch target address was consumed before
1036                          * we temporarily go back to the saved data index */
1037                         if (pipestat == STAT_BD)
1038                         {
1039                                 ctx->data_index = old_data_index;
1040                                 ctx->data_half = old_data_half;
1041                         }
1042
1043                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
1044                         {
1045                                 uint8_t packet;
1046                                 int shift = 0;
1047
1048                                 do {
1049                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1050                                                 return ERROR_ETM_ANALYSIS_FAILED;
1051                                         ctx->last_ptr &= ~(0x7f << shift);
1052                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1053                                         shift += 7;
1054                                 } while ((packet & 0x80) && (shift < 32));
1055
1056                                 if (shift >= 32)
1057                                         ctx->ptr_ok = 1;
1058
1059                                 if (ctx->ptr_ok)
1060                                 {
1061                                         command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1062                                 }
1063                         }
1064
1065                         if (ctx->tracemode & ETMV1_TRACE_DATA)
1066                         {
1067                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1068                                 {
1069                                         int i;
1070                                         for (i = 0; i < 16; i++)
1071                                         {
1072                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
1073                                                 {
1074                                                         uint32_t data;
1075                                                         if (etmv1_data(ctx, 4, &data) != 0)
1076                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1077                                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1078                                                 }
1079                                         }
1080                                 }
1081                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1082                                 {
1083                                         uint32_t data;
1084                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1085                                                 return ERROR_ETM_ANALYSIS_FAILED;
1086                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1087                                 }
1088                         }
1089
1090                         /* restore data index after consuming BD address and data */
1091                         if (pipestat == STAT_BD)
1092                         {
1093                                 ctx->data_index = new_data_index;
1094                                 ctx->data_half = new_data_half;
1095                         }
1096                 }
1097
1098                 /* adjust PC */
1099                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1100                 {
1101                         if (((instruction.type == ARM_B) ||
1102                              (instruction.type == ARM_BL) ||
1103                              (instruction.type == ARM_BLX)) &&
1104                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1105                         {
1106                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1107                         }
1108                         else
1109                         {
1110                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1111                         }
1112                 }
1113                 else if (pipestat == STAT_IN)
1114                 {
1115                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1116                 }
1117
1118                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1119                 {
1120                         char cycles_text[32] = "";
1121
1122                         /* if the trace was captured with cycle accurate tracing enabled,
1123                          * output the number of cycles since the last executed instruction
1124                          */
1125                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1126                         {
1127                                 snprintf(cycles_text, 32, " (%i %s)",
1128                                          (int)cycles,
1129                                         (cycles == 1) ? "cycle" : "cycles");
1130                         }
1131
1132                         command_print(cmd_ctx, "%s%s%s",
1133                                 instruction.text,
1134                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1135                                 cycles_text);
1136
1137                         ctx->current_pc = next_pc;
1138
1139                         /* packets for an instruction don't start on or before the preceding
1140                          * functional pipestat (i.e. other than WT or TD)
1141                          */
1142                         if (ctx->data_index <= ctx->pipe_index)
1143                         {
1144                                 ctx->data_index = ctx->pipe_index + 1;
1145                                 ctx->data_half = 0;
1146                         }
1147                 }
1148
1149                 ctx->pipe_index += 1;
1150         }
1151
1152         return ERROR_OK;
1153 }
1154
1155 static int handle_etm_tracemode_command_update(
1156                 struct command_context_s *cmd_ctx,
1157                 char **args, etmv1_tracemode_t *mode)
1158 {
1159         etmv1_tracemode_t tracemode;
1160
1161         /* what parts of data access are traced? */
1162         if (strcmp(args[0], "none") == 0)
1163                 tracemode = ETMV1_TRACE_NONE;
1164         else if (strcmp(args[0], "data") == 0)
1165                 tracemode = ETMV1_TRACE_DATA;
1166         else if (strcmp(args[0], "address") == 0)
1167                 tracemode = ETMV1_TRACE_ADDR;
1168         else if (strcmp(args[0], "all") == 0)
1169                 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1170         else
1171         {
1172                 command_print(cmd_ctx, "invalid option '%s'", args[0]);
1173                 return ERROR_INVALID_ARGUMENTS;
1174         }
1175
1176         uint8_t context_id;
1177         COMMAND_PARSE_NUMBER(u8, args[1], context_id);
1178         switch (context_id)
1179         {
1180         case 0:
1181                 tracemode |= ETMV1_CONTEXTID_NONE;
1182                 break;
1183         case 8:
1184                 tracemode |= ETMV1_CONTEXTID_8;
1185                 break;
1186         case 16:
1187                 tracemode |= ETMV1_CONTEXTID_16;
1188                 break;
1189         case 32:
1190                 tracemode |= ETMV1_CONTEXTID_32;
1191                 break;
1192         default:
1193                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1194                 return ERROR_INVALID_ARGUMENTS;
1195         }
1196
1197         if (strcmp(args[2], "enable") == 0)
1198                 tracemode |= ETMV1_CYCLE_ACCURATE;
1199         else if (strcmp(args[2], "disable") == 0)
1200                 tracemode |= 0;
1201         else
1202         {
1203                 command_print(cmd_ctx, "invalid option '%s'", args[2]);
1204                 return ERROR_INVALID_ARGUMENTS;
1205         }
1206
1207         if (strcmp(args[3], "enable") == 0)
1208                 tracemode |= ETMV1_BRANCH_OUTPUT;
1209         else if (strcmp(args[3], "disable") == 0)
1210                 tracemode |= 0;
1211         else
1212         {
1213                 command_print(cmd_ctx, "invalid option '%s'", args[3]);
1214                 return ERROR_INVALID_ARGUMENTS;
1215         }
1216
1217         /* IGNORED:
1218          *  - CPRT tracing (coprocessor register transfers)
1219          *  - debug request (causes debug entry on trigger)
1220          *  - stall on FIFOFULL (preventing tracedata lossage)
1221          */
1222         *mode = tracemode;
1223
1224         return ERROR_OK;
1225 }
1226
1227 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx,
1228                 char *cmd, char **args, int argc)
1229 {
1230         target_t *target = get_current_target(cmd_ctx);
1231         struct arm *arm = target_to_arm(target);
1232         struct etm *etm;
1233
1234         if (!is_arm(arm)) {
1235                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1236                 return ERROR_FAIL;
1237         }
1238
1239         etm = arm->etm;
1240         if (!etm) {
1241                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1242                 return ERROR_FAIL;
1243         }
1244
1245         etmv1_tracemode_t tracemode = etm->tracemode;
1246
1247         switch (argc)
1248         {
1249         case 0:
1250                 break;
1251         case 4:
1252                 handle_etm_tracemode_command_update(cmd_ctx, args, &tracemode);
1253                 break;
1254         default:
1255                 command_print(cmd_ctx, "usage: configure trace mode "
1256                                 "<none | data | address | all> "
1257                                 "<context id bits> <cycle accurate> <branch output>");
1258                 return ERROR_FAIL;
1259         }
1260
1261         /**
1262          * todo: fail if parameters were invalid for this hardware,
1263          * or couldn't be written; display actual hardware state...
1264          */
1265
1266         command_print(cmd_ctx, "current tracemode configuration:");
1267
1268         switch (tracemode & ETMV1_TRACE_MASK)
1269         {
1270                 case ETMV1_TRACE_NONE:
1271                         command_print(cmd_ctx, "data tracing: none");
1272                         break;
1273                 case ETMV1_TRACE_DATA:
1274                         command_print(cmd_ctx, "data tracing: data only");
1275                         break;
1276                 case ETMV1_TRACE_ADDR:
1277                         command_print(cmd_ctx, "data tracing: address only");
1278                         break;
1279                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1280                         command_print(cmd_ctx, "data tracing: address and data");
1281                         break;
1282         }
1283
1284         switch (tracemode & ETMV1_CONTEXTID_MASK)
1285         {
1286                 case ETMV1_CONTEXTID_NONE:
1287                         command_print(cmd_ctx, "contextid tracing: none");
1288                         break;
1289                 case ETMV1_CONTEXTID_8:
1290                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1291                         break;
1292                 case ETMV1_CONTEXTID_16:
1293                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1294                         break;
1295                 case ETMV1_CONTEXTID_32:
1296                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1297                         break;
1298         }
1299
1300         if (tracemode & ETMV1_CYCLE_ACCURATE)
1301         {
1302                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1303         }
1304         else
1305         {
1306                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1307         }
1308
1309         if (tracemode & ETMV1_BRANCH_OUTPUT)
1310         {
1311                 command_print(cmd_ctx, "full branch address output enabled");
1312         }
1313         else
1314         {
1315                 command_print(cmd_ctx, "full branch address output disabled");
1316         }
1317
1318         /* only update ETM_CTRL register if tracemode changed */
1319         if (etm->tracemode != tracemode)
1320         {
1321                 reg_t *etm_ctrl_reg;
1322
1323                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1324                 if (!etm_ctrl_reg)
1325                         return ERROR_FAIL;
1326
1327                 etm_get_reg(etm_ctrl_reg);
1328
1329                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1330                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1331                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1332                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1333                 etm_store_reg(etm_ctrl_reg);
1334
1335                 etm->tracemode = tracemode;
1336
1337                 /* invalidate old trace data */
1338                 etm->capture_status = TRACE_IDLE;
1339                 if (etm->trace_depth > 0)
1340                 {
1341                         free(etm->trace_data);
1342                         etm->trace_data = NULL;
1343                 }
1344                 etm->trace_depth = 0;
1345         }
1346
1347         return ERROR_OK;
1348 }
1349
1350 static int handle_etm_config_command(struct command_context_s *cmd_ctx,
1351                 char *cmd, char **args, int argc)
1352 {
1353         target_t *target;
1354         struct arm *arm;
1355         etm_portmode_t portmode = 0x0;
1356         struct etm *etm_ctx;
1357         int i;
1358
1359         if (argc != 5)
1360                 return ERROR_COMMAND_SYNTAX_ERROR;
1361
1362         target = get_target(args[0]);
1363         if (!target)
1364         {
1365                 LOG_ERROR("target '%s' not defined", args[0]);
1366                 return ERROR_FAIL;
1367         }
1368
1369         arm = target_to_arm(target);
1370         if (!is_arm(arm)) {
1371                 command_print(cmd_ctx, "target '%s' is '%s'; not an ARM",
1372                                 target->cmd_name, target_get_name(target));
1373                 return ERROR_FAIL;
1374         }
1375
1376         uint8_t port_width;
1377         COMMAND_PARSE_NUMBER(u8, args[1], port_width);
1378         switch (port_width)
1379         {
1380                 case 4:
1381                         portmode |= ETM_PORT_4BIT;
1382                         break;
1383                 case 8:
1384                         portmode |= ETM_PORT_8BIT;
1385                         break;
1386                 case 16:
1387                         portmode |= ETM_PORT_16BIT;
1388                         break;
1389                 default:
1390                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1391                         return ERROR_FAIL;
1392         }
1393
1394         if (strcmp("normal", args[2]) == 0)
1395         {
1396                 portmode |= ETM_PORT_NORMAL;
1397         }
1398         else if (strcmp("multiplexed", args[2]) == 0)
1399         {
1400                 portmode |= ETM_PORT_MUXED;
1401         }
1402         else if (strcmp("demultiplexed", args[2]) == 0)
1403         {
1404                 portmode |= ETM_PORT_DEMUXED;
1405         }
1406         else
1407         {
1408                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1409                 return ERROR_FAIL;
1410         }
1411
1412         if (strcmp("half", args[3]) == 0)
1413         {
1414                 portmode |= ETM_PORT_HALF_CLOCK;
1415         }
1416         else if (strcmp("full", args[3]) == 0)
1417         {
1418                 portmode |= ETM_PORT_FULL_CLOCK;
1419         }
1420         else
1421         {
1422                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1423                 return ERROR_FAIL;
1424         }
1425
1426         etm_ctx = calloc(1, sizeof(etm_context_t));
1427         if (!etm_ctx) {
1428                 LOG_DEBUG("out of memory");
1429                 return ERROR_FAIL;
1430         }
1431
1432         for (i = 0; etm_capture_drivers[i]; i++)
1433         {
1434                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1435                 {
1436                         int retval;
1437                         if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1438                         {
1439                                 free(etm_ctx);
1440                                 return retval;
1441                         }
1442
1443                         etm_ctx->capture_driver = etm_capture_drivers[i];
1444
1445                         break;
1446                 }
1447         }
1448
1449         if (!etm_capture_drivers[i])
1450         {
1451                 /* no supported capture driver found, don't register an ETM */
1452                 free(etm_ctx);
1453                 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1454                 return ERROR_FAIL;
1455         }
1456
1457         etm_ctx->target = target;
1458         etm_ctx->trigger_percent = 50;
1459         etm_ctx->trace_data = NULL;
1460         etm_ctx->portmode = portmode;
1461         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1462
1463         arm->etm = etm_ctx;
1464
1465         return etm_register_user_commands(cmd_ctx);
1466 }
1467
1468 static int handle_etm_info_command(struct command_context_s *cmd_ctx,
1469                 char *cmd, char **args, int argc)
1470 {
1471         target_t *target;
1472         struct arm *arm;
1473         etm_context_t *etm;
1474         reg_t *etm_sys_config_reg;
1475         int max_port_size;
1476
1477         target = get_current_target(cmd_ctx);
1478         arm = target_to_arm(target);
1479         if (!is_arm(arm))
1480         {
1481                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1482                 return ERROR_FAIL;
1483         }
1484
1485         etm = arm->etm;
1486         if (!etm)
1487         {
1488                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1489                 return ERROR_FAIL;
1490         }
1491
1492         command_print(cmd_ctx, "ETM v%d.%d",
1493                         etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1494         command_print(cmd_ctx, "pairs of address comparators: %i",
1495                         (int) (etm->config >> 0) & 0x0f);
1496         command_print(cmd_ctx, "data comparators: %i",
1497                         (int) (etm->config >> 4) & 0x0f);
1498         command_print(cmd_ctx, "memory map decoders: %i",
1499                         (int) (etm->config >> 8) & 0x1f);
1500         command_print(cmd_ctx, "number of counters: %i",
1501                         (int) (etm->config >> 13) & 0x07);
1502         command_print(cmd_ctx, "sequencer %spresent",
1503                         (int) (etm->config & (1 << 16)) ? "" : "not ");
1504         command_print(cmd_ctx, "number of ext. inputs: %i",
1505                         (int) (etm->config >> 17) & 0x07);
1506         command_print(cmd_ctx, "number of ext. outputs: %i",
1507                         (int) (etm->config >> 20) & 0x07);
1508         command_print(cmd_ctx, "FIFO full %spresent",
1509                         (int) (etm->config & (1 << 23)) ? "" : "not ");
1510         if (etm->bcd_vers < 0x20)
1511                 command_print(cmd_ctx, "protocol version: %i",
1512                                 (int) (etm->config >> 28) & 0x07);
1513         else {
1514                 command_print(cmd_ctx, "trace start/stop %spresent",
1515                                 (etm->config & (1 << 26)) ? "" : "not ");
1516                 command_print(cmd_ctx, "number of context comparators: %i",
1517                                 (int) (etm->config >> 24) & 0x03);
1518         }
1519
1520         /* SYS_CONFIG isn't present before ETMv1.2 */
1521         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1522         if (!etm_sys_config_reg)
1523                 return ERROR_OK;
1524
1525         etm_get_reg(etm_sys_config_reg);
1526
1527         switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1528         {
1529                 case 0:
1530                         max_port_size = 4;
1531                         break;
1532                 case 1:
1533                         max_port_size = 8;
1534                         break;
1535                 case 2:
1536                         max_port_size = 16;
1537                         break;
1538                 default:
1539                         LOG_ERROR("Illegal max_port_size");
1540                         return ERROR_FAIL;
1541         }
1542         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1543
1544         command_print(cmd_ctx, "half-rate clocking %ssupported",
1545                         (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1546         command_print(cmd_ctx, "full-rate clocking %ssupported",
1547                         (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1548         command_print(cmd_ctx, "normal trace format %ssupported",
1549                         (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1550         command_print(cmd_ctx, "multiplex trace format %ssupported",
1551                         (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1552         command_print(cmd_ctx, "demultiplex trace format %ssupported",
1553                         (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1554         command_print(cmd_ctx, "FIFO full %ssupported",
1555                         (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1556
1557         return ERROR_OK;
1558 }
1559
1560 static int handle_etm_status_command(struct command_context_s *cmd_ctx,
1561                 char *cmd, char **args, int argc)
1562 {
1563         target_t *target;
1564         struct arm *arm;
1565         etm_context_t *etm;
1566         trace_status_t trace_status;
1567
1568         target = get_current_target(cmd_ctx);
1569         arm = target_to_arm(target);
1570         if (!is_arm(arm))
1571         {
1572                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1573                 return ERROR_FAIL;
1574         }
1575
1576         etm = arm->etm;
1577         if (!etm)
1578         {
1579                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1580                 return ERROR_FAIL;
1581         }
1582
1583         /* ETM status */
1584         if (etm->bcd_vers >= 0x11) {
1585                 reg_t *reg;
1586
1587                 reg = etm_reg_lookup(etm, ETM_STATUS);
1588                 if (!reg)
1589                         return ERROR_FAIL;
1590                 if (etm_get_reg(reg) == ERROR_OK) {
1591                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1592
1593                         command_print(cmd_ctx, "etm: %s%s%s%s",
1594                                 /* bit(1) == progbit */
1595                                 (etm->bcd_vers >= 0x12)
1596                                         ? ((s & (1 << 1))
1597                                                 ? "disabled" : "enabled")
1598                                         : "?",
1599                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1600                                         ? " triggered" : "",
1601                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1602                                         ? " start/stop" : "",
1603                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1604                                         ? " untraced-overflow" : "");
1605                 } /* else ignore and try showing trace port status */
1606         }
1607
1608         /* Trace Port Driver status */
1609         trace_status = etm->capture_driver->status(etm);
1610         if (trace_status == TRACE_IDLE)
1611         {
1612                 command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
1613         }
1614         else
1615         {
1616                 static char *completed = " completed";
1617                 static char *running = " is running";
1618                 static char *overflowed = ", overflowed";
1619                 static char *triggered = ", triggered";
1620
1621                 command_print(cmd_ctx, "%s: trace collection%s%s%s",
1622                         etm->capture_driver->name,
1623                         (trace_status & TRACE_RUNNING) ? running : completed,
1624                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1625                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1626
1627                 if (etm->trace_depth > 0)
1628                 {
1629                         command_print(cmd_ctx, "%i frames of trace data read",
1630                                         (int)(etm->trace_depth));
1631                 }
1632         }
1633
1634         return ERROR_OK;
1635 }
1636
1637 static int handle_etm_image_command(struct command_context_s *cmd_ctx,
1638                 char *cmd, char **args, int argc)
1639 {
1640         target_t *target;
1641         struct arm *arm;
1642         etm_context_t *etm_ctx;
1643
1644         if (argc < 1)
1645         {
1646                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1647                 return ERROR_FAIL;
1648         }
1649
1650         target = get_current_target(cmd_ctx);
1651         arm = target_to_arm(target);
1652         if (!is_arm(arm))
1653         {
1654                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1655                 return ERROR_FAIL;
1656         }
1657
1658         etm_ctx = arm->etm;
1659         if (!etm_ctx)
1660         {
1661                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1662                 return ERROR_FAIL;
1663         }
1664
1665         if (etm_ctx->image)
1666         {
1667                 image_close(etm_ctx->image);
1668                 free(etm_ctx->image);
1669                 command_print(cmd_ctx, "previously loaded image found and closed");
1670         }
1671
1672         etm_ctx->image = malloc(sizeof(image_t));
1673         etm_ctx->image->base_address_set = 0;
1674         etm_ctx->image->start_address_set = 0;
1675
1676         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1677         if (argc >= 2)
1678         {
1679                 etm_ctx->image->base_address_set = 1;
1680                 COMMAND_PARSE_NUMBER(int, args[1], etm_ctx->image->base_address);
1681         }
1682         else
1683         {
1684                 etm_ctx->image->base_address_set = 0;
1685         }
1686
1687         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1688         {
1689                 free(etm_ctx->image);
1690                 etm_ctx->image = NULL;
1691                 return ERROR_FAIL;
1692         }
1693
1694         return ERROR_OK;
1695 }
1696
1697 static int handle_etm_dump_command(struct command_context_s *cmd_ctx,
1698                 char *cmd, char **args, int argc)
1699 {
1700         fileio_t file;
1701         target_t *target;
1702         struct arm *arm;
1703         etm_context_t *etm_ctx;
1704         uint32_t i;
1705
1706         if (argc != 1)
1707         {
1708                 command_print(cmd_ctx, "usage: etm dump <file>");
1709                 return ERROR_FAIL;
1710         }
1711
1712         target = get_current_target(cmd_ctx);
1713         arm = target_to_arm(target);
1714         if (!is_arm(arm))
1715         {
1716                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1717                 return ERROR_FAIL;
1718         }
1719
1720         etm_ctx = arm->etm;
1721         if (!etm_ctx)
1722         {
1723                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1724                 return ERROR_FAIL;
1725         }
1726
1727         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1728         {
1729                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1730                 return ERROR_OK;
1731         }
1732
1733         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1734         {
1735                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1736                 command_print(cmd_ctx, "trace capture not completed");
1737                 return ERROR_FAIL;
1738         }
1739
1740         /* read the trace data if it wasn't read already */
1741         if (etm_ctx->trace_depth == 0)
1742                 etm_ctx->capture_driver->read_trace(etm_ctx);
1743
1744         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1745         {
1746                 return ERROR_FAIL;
1747         }
1748
1749         fileio_write_u32(&file, etm_ctx->capture_status);
1750         fileio_write_u32(&file, etm_ctx->portmode);
1751         fileio_write_u32(&file, etm_ctx->tracemode);
1752         fileio_write_u32(&file, etm_ctx->trace_depth);
1753
1754         for (i = 0; i < etm_ctx->trace_depth; i++)
1755         {
1756                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1757                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1758                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1759         }
1760
1761         fileio_close(&file);
1762
1763         return ERROR_OK;
1764 }
1765
1766 static int handle_etm_load_command(struct command_context_s *cmd_ctx,
1767                 char *cmd, char **args, int argc)
1768 {
1769         fileio_t file;
1770         target_t *target;
1771         struct arm *arm;
1772         etm_context_t *etm_ctx;
1773         uint32_t i;
1774
1775         if (argc != 1)
1776         {
1777                 command_print(cmd_ctx, "usage: etm load <file>");
1778                 return ERROR_FAIL;
1779         }
1780
1781         target = get_current_target(cmd_ctx);
1782         arm = target_to_arm(target);
1783         if (!is_arm(arm))
1784         {
1785                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1786                 return ERROR_FAIL;
1787         }
1788
1789         etm_ctx = arm->etm;
1790         if (!etm_ctx)
1791         {
1792                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1793                 return ERROR_FAIL;
1794         }
1795
1796         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1797         {
1798                 command_print(cmd_ctx, "trace capture running, stop first");
1799                 return ERROR_FAIL;
1800         }
1801
1802         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1803         {
1804                 return ERROR_FAIL;
1805         }
1806
1807         if (file.size % 4)
1808         {
1809                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1810                 fileio_close(&file);
1811                 return ERROR_FAIL;
1812         }
1813
1814         if (etm_ctx->trace_depth > 0)
1815         {
1816                 free(etm_ctx->trace_data);
1817                 etm_ctx->trace_data = NULL;
1818         }
1819
1820         {
1821           uint32_t tmp;
1822           fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1823           fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1824           fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1825           fileio_read_u32(&file, &etm_ctx->trace_depth);
1826         }
1827         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1828         if (etm_ctx->trace_data == NULL)
1829         {
1830                 command_print(cmd_ctx, "not enough memory to perform operation");
1831                 fileio_close(&file);
1832                 return ERROR_FAIL;
1833         }
1834
1835         for (i = 0; i < etm_ctx->trace_depth; i++)
1836         {
1837                 uint32_t pipestat, packet, flags;
1838                 fileio_read_u32(&file, &pipestat);
1839                 fileio_read_u32(&file, &packet);
1840                 fileio_read_u32(&file, &flags);
1841                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1842                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1843                 etm_ctx->trace_data[i].flags = flags;
1844         }
1845
1846         fileio_close(&file);
1847
1848         return ERROR_OK;
1849 }
1850
1851 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx,
1852                 char *cmd, char **args, int argc)
1853 {
1854         target_t *target;
1855         struct arm *arm;
1856         etm_context_t *etm_ctx;
1857
1858         target = get_current_target(cmd_ctx);
1859         arm = target_to_arm(target);
1860         if (!is_arm(arm))
1861         {
1862                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1863                 return ERROR_FAIL;
1864         }
1865
1866         etm_ctx = arm->etm;
1867         if (!etm_ctx)
1868         {
1869                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1870                 return ERROR_FAIL;
1871         }
1872
1873         if (argc > 0)
1874         {
1875                 uint32_t new_value;
1876                 COMMAND_PARSE_NUMBER(u32, args[0], new_value);
1877
1878                 if ((new_value < 2) || (new_value > 100))
1879                 {
1880                         command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1881                 }
1882                 else
1883                 {
1884                         etm_ctx->trigger_percent = new_value;
1885                 }
1886         }
1887
1888         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1889
1890         return ERROR_OK;
1891 }
1892
1893 static int handle_etm_start_command(struct command_context_s *cmd_ctx,
1894                 char *cmd, char **args, int argc)
1895 {
1896         target_t *target;
1897         struct arm *arm;
1898         etm_context_t *etm_ctx;
1899         reg_t *etm_ctrl_reg;
1900
1901         target = get_current_target(cmd_ctx);
1902         arm = target_to_arm(target);
1903         if (!is_arm(arm))
1904         {
1905                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1906                 return ERROR_FAIL;
1907         }
1908
1909         etm_ctx = arm->etm;
1910         if (!etm_ctx)
1911         {
1912                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1913                 return ERROR_FAIL;
1914         }
1915
1916         /* invalidate old tracing data */
1917         etm_ctx->capture_status = TRACE_IDLE;
1918         if (etm_ctx->trace_depth > 0)
1919         {
1920                 free(etm_ctx->trace_data);
1921                 etm_ctx->trace_data = NULL;
1922         }
1923         etm_ctx->trace_depth = 0;
1924
1925         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1926         if (!etm_ctrl_reg)
1927                 return ERROR_FAIL;
1928
1929         etm_get_reg(etm_ctrl_reg);
1930
1931         /* Clear programming bit (10), set port selection bit (11) */
1932         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1933
1934         etm_store_reg(etm_ctrl_reg);
1935         jtag_execute_queue();
1936
1937         etm_ctx->capture_driver->start_capture(etm_ctx);
1938
1939         return ERROR_OK;
1940 }
1941
1942 static int handle_etm_stop_command(struct command_context_s *cmd_ctx,
1943                 char *cmd, char **args, int argc)
1944 {
1945         target_t *target;
1946         struct arm *arm;
1947         etm_context_t *etm_ctx;
1948         reg_t *etm_ctrl_reg;
1949
1950         target = get_current_target(cmd_ctx);
1951         arm = target_to_arm(target);
1952         if (!is_arm(arm))
1953         {
1954                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1955                 return ERROR_FAIL;
1956         }
1957
1958         etm_ctx = arm->etm;
1959         if (!etm_ctx)
1960         {
1961                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1962                 return ERROR_FAIL;
1963         }
1964
1965         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1966         if (!etm_ctrl_reg)
1967                 return ERROR_FAIL;
1968
1969         etm_get_reg(etm_ctrl_reg);
1970
1971         /* Set programming bit (10), clear port selection bit (11) */
1972         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1973
1974         etm_store_reg(etm_ctrl_reg);
1975         jtag_execute_queue();
1976
1977         etm_ctx->capture_driver->stop_capture(etm_ctx);
1978
1979         return ERROR_OK;
1980 }
1981
1982 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx,
1983                 char *cmd, char **args, int argc)
1984 {
1985         target_t *target;
1986         struct arm *arm;
1987         etm_context_t *etm_ctx;
1988         int retval;
1989
1990         target = get_current_target(cmd_ctx);
1991         arm = target_to_arm(target);
1992         if (!is_arm(arm))
1993         {
1994                 command_print(cmd_ctx, "ETM: current target isn't an ARM");
1995                 return ERROR_FAIL;
1996         }
1997
1998         etm_ctx = arm->etm;
1999         if (!etm_ctx)
2000         {
2001                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
2002                 return ERROR_FAIL;
2003         }
2004
2005         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
2006         {
2007                 switch (retval)
2008                 {
2009                         case ERROR_ETM_ANALYSIS_FAILED:
2010                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
2011                                 break;
2012                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2013                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
2014                                 break;
2015                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
2016                                 command_print(cmd_ctx, "no image available for trace analysis");
2017                                 break;
2018                         default:
2019                                 command_print(cmd_ctx, "unknown error: %i", retval);
2020                 }
2021         }
2022
2023         return retval;
2024 }
2025
2026 int etm_register_commands(struct command_context_s *cmd_ctx)
2027 {
2028         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
2029
2030         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
2031                 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2032
2033         return ERROR_OK;
2034 }
2035
2036 static int etm_register_user_commands(struct command_context_s *cmd_ctx)
2037 {
2038         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2039                 COMMAND_EXEC, "configure/display trace mode: "
2040                         "<none | data | address | all> "
2041                         "<context_id_bits> <cycle_accurate> <branch_output>");
2042
2043         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2044                 COMMAND_EXEC, "display info about the current target's ETM");
2045
2046         register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2047                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2048         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2049                 COMMAND_EXEC, "display current target's ETM status");
2050         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2051                 COMMAND_EXEC, "start ETM trace collection");
2052         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2053                 COMMAND_EXEC, "stop ETM trace collection");
2054
2055         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2056                 COMMAND_EXEC, "anaylze collected ETM trace");
2057
2058         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2059                 COMMAND_EXEC, "load image from <file> [base address]");
2060
2061         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2062                 COMMAND_EXEC, "dump captured trace data <file>");
2063         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2064                 COMMAND_EXEC, "load trace data for analysis <file>");
2065
2066         return ERROR_OK;
2067 }