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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "etm.h"
  25 #include "etb.h"
  26 #include "image.h"
  27 #include "arm7_9_common.h"
  28 #include "arm_disassembler.h"
  29
  30
  31 /*
  32  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  33  *
  34  * ETM modules collect instruction and/or data trace information, compress
  35  * it, and transfer it to a debugging host through either a (buffered) trace
  36  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  37  *
  38  * There are several generations of these modules.  Original versions have
  39  * JTAG access through a dedicated scan chain.  Recent versions have added
  40  * access via coprocessor instructions, memory addressing, and the ARM Debug
  41  * Interface v5 (ADIv5); and phased out direct JTAG access.
  42  *
  43  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  44  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  45  * implying non-JTAG connectivity options.
  46  *
  47  * Relevant documentation includes:
  48  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  49  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  50  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  51  */
  52
  53 #define ARRAY_SIZE(x)   ((int)(sizeof(x)/sizeof((x)[0])))
  54
  55 enum {
  56         RO,                             /* read/only */
  57         WO,                             /* write/only */
  58         RW,                             /* read/write */
  59 };
  60
  61 struct etm_reg_info {
  62         uint8_t         addr;
  63         uint8_t         size;           /* low-N of 32 bits */
  64         uint8_t         mode;           /* RO, WO, RW */
  65         uint8_t         bcd_vers;       /* 1.0, 2.0, etc */
  66         char            *name;
  67 };
  68
  69 /*
  70  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  71  * Newer versions of ETM make some W/O registers R/W, and
  72  * provide definitions for some previously-unused bits.
  73  */
  74
  75 /* basic registers that are always there given the right ETM version */
  76 static const struct etm_reg_info etm_core[] = {
  77         /* NOTE: we "know" ETM_CONFIG is listed first */
  78         { ETM_CONFIG, 32, RO, 0x10, "ETM_CONFIG", },
  79
  80         /* ETM Trace Registers */
  81         { ETM_CTRL, 32, RW, 0x10, "ETM_CTRL", },
  82         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_TRIG_EVENT", },
  83         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_ASIC_CTRL", },
  84         { ETM_STATUS,  3, RO, 0x11, "ETM_STATUS", },
  85         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_SYS_CONFIG", },
  86
  87         /* TraceEnable configuration */
  88         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_TRACE_RESOURCE_CTRL", },
  89         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_TRACE_EN_CTRL2", },
  90         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_TRACE_EN_EVENT", },
  91         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_TRACE_EN_CTRL1", },
  92
  93         /* ViewData configuration (data trace) */
  94         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_VIEWDATA_EVENT", },
  95         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_VIEWDATA_CTRL1", },
  96         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_VIEWDATA_CTRL2", },
  97         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_VIEWDATA_CTRL3", },
  98
  99         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 100
 101         { 0x78, 12, WO, 0x20, "ETM_SYNC_FREQ", },
 102         { 0x79, 32, RO, 0x20, "ETM_ID", },
 103 };
 104
 105 static const struct etm_reg_info etm_fifofull[] = {
 106         /* FIFOFULL configuration */
 107         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_FIFOFULL_REGION", },
 108         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_FIFOFULL_LEVEL", },
 109 };
 110
 111 static const struct etm_reg_info etm_addr_comp[] = {
 112         /* Address comparator register pairs */
 113 #define ADDR_COMPARATOR(i) \
 114                 { ETM_ADDR_COMPARATOR_VALUE + (i), 32, WO, 0x10, \
 115                                 "ETM_ADDR_COMPARATOR_VALUE" #i, }, \
 116                 { ETM_ADDR_ACCESS_TYPE + (i),  7, WO, 0x10, \
 117                                 "ETM_ADDR_ACCESS_TYPE" #i, }
 118         ADDR_COMPARATOR(0),
 119         ADDR_COMPARATOR(1),
 120         ADDR_COMPARATOR(2),
 121         ADDR_COMPARATOR(3),
 122         ADDR_COMPARATOR(4),
 123         ADDR_COMPARATOR(5),
 124         ADDR_COMPARATOR(6),
 125         ADDR_COMPARATOR(7),
 126
 127         ADDR_COMPARATOR(8),
 128         ADDR_COMPARATOR(9),
 129         ADDR_COMPARATOR(10),
 130         ADDR_COMPARATOR(11),
 131         ADDR_COMPARATOR(12),
 132         ADDR_COMPARATOR(13),
 133         ADDR_COMPARATOR(14),
 134         ADDR_COMPARATOR(15),
 135 #undef ADDR_COMPARATOR
 136 };
 137
 138 static const struct etm_reg_info etm_data_comp[] = {
 139         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 140 #define DATA_COMPARATOR(i) \
 141                 { ETM_DATA_COMPARATOR_VALUE + 2*(i), 32, WO, 0x10, \
 142                                 "ETM_DATA_COMPARATOR_VALUE" #i, }, \
 143                 { ETM_DATA_COMPARATOR_MASK + 2*(i), 32, WO, 0x10, \
 144                                 "ETM_DATA_COMPARATOR_MASK" #i, }
 145         DATA_COMPARATOR(0),
 146         DATA_COMPARATOR(1),
 147         DATA_COMPARATOR(2),
 148         DATA_COMPARATOR(3),
 149         DATA_COMPARATOR(4),
 150         DATA_COMPARATOR(5),
 151         DATA_COMPARATOR(6),
 152         DATA_COMPARATOR(7),
 153 #undef DATA_COMPARATOR
 154 };
 155
 156 static const struct etm_reg_info etm_counters[] = {
 157 #define COUNTER(i) \
 158                 { ETM_COUNTER_RELOAD_VALUE + (i), 16, WO, 0x10, \
 159                                 "ETM_COUNTER_RELOAD_VALUE" #i, }, \
 160                 { ETM_COUNTER_ENABLE + (i), 18, WO, 0x10, \
 161                                 "ETM_COUNTER_ENABLE" #i, }, \
 162                 { ETM_COUNTER_RELOAD_EVENT + (i), 17, WO, 0x10, \
 163                                 "ETM_COUNTER_RELOAD_EVENT" #i, }, \
 164                 { ETM_COUNTER_VALUE + (i), 16, RO, 0x10, \
 165                                 "ETM_COUNTER_VALUE" #i, }
 166         COUNTER(0),
 167         COUNTER(1),
 168         COUNTER(2),
 169         COUNTER(3),
 170 #undef COUNTER
 171 };
 172
 173 static const struct etm_reg_info etm_sequencer[] = {
 174 #define SEQ(i) \
 175                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 176                                 "ETM_SEQUENCER_EVENT" #i, }
 177         SEQ(0),                         /* 1->2 */
 178         SEQ(1),                         /* 2->1 */
 179         SEQ(2),                         /* 2->3 */
 180         SEQ(3),                         /* 3->1 */
 181         SEQ(4),                         /* 3->2 */
 182         SEQ(5),                         /* 1->3 */
 183 #undef SEQ
 184         /* 0x66 reserved */
 185         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_SEQUENCER_STATE", },
 186 };
 187
 188 static const struct etm_reg_info etm_outputs[] = {
 189 #define OUT(i) \
 190                 { ETM_EXTERNAL_OUTPUT + (i), 17, WO, 0x10, \
 191                                 "ETM_EXTERNAL_OUTPUT" #i, }
 192
 193         OUT(0),
 194         OUT(1),
 195         OUT(2),
 196         OUT(3),
 197 #undef OUT
 198 };
 199
 200 #if 0
 201         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 202
 203         /* Context ID Comparators */
 204         { 0x6c, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
 205         { 0x6d, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
 206         { 0x6e, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
 207         { 0x6f, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_MASK", }
 208 #endif
 209
 210 static int etm_reg_arch_type = -1;
 211
 212 static int etm_get_reg(reg_t *reg);
 213 static int etm_read_reg_w_check(reg_t *reg,
 214                 uint8_t* check_value, uint8_t* check_mask);
 215 static int etm_register_user_commands(struct command_context_s *cmd_ctx);
 216 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
 217 static int etm_write_reg(reg_t *reg, uint32_t value);
 218
 219 static command_t *etm_cmd;
 220
 221
 222 /* Look up register by ID ... most ETM instances only
 223  * support a subset of the possible registers.
 224  */
 225 static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
 226 {
 227         reg_cache_t *cache = etm_ctx->reg_cache;
 228         int i;
 229
 230         for (i = 0; i < cache->num_regs; i++) {
 231                 struct etm_reg_s *reg = cache->reg_list[i].arch_info;
 232
 233                 if (reg->reg_info->addr == id)
 234                         return &cache->reg_list[i];
 235         }
 236
 237         /* caller asking for nonexistent register is a bug! */
 238         /* REVISIT say which of the N targets was involved */
 239         LOG_ERROR("ETM: register 0x%02x not available", id);
 240         return NULL;
 241 }
 242
 243 static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
 244                 reg_cache_t *cache, etm_reg_t *ereg,
 245                 const struct etm_reg_info *r, unsigned nreg)
 246 {
 247         reg_t *reg = cache->reg_list;
 248
 249         reg += cache->num_regs;
 250         ereg += cache->num_regs;
 251
 252         /* add up to "nreg" registers from "r", if supported by this
 253          * version of the ETM, to the specified cache.
 254          */
 255         for (; nreg--; r++) {
 256
 257                 /* this ETM may be too old to have some registers */
 258                 if (r->bcd_vers > bcd_vers)
 259                         continue;
 260
 261                 reg->name = r->name;
 262                 reg->size = r->size;
 263                 reg->value = &ereg->value;
 264                 reg->arch_info = ereg;
 265                 reg->arch_type = etm_reg_arch_type;
 266                 reg++;
 267                 cache->num_regs++;
 268
 269                 ereg->reg_info = r;
 270                 ereg->jtag_info = jtag_info;
 271                 ereg++;
 272         }
 273 }
 274
 275 reg_cache_t *etm_build_reg_cache(target_t *target,
 276                 arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 277 {
 278         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 279         reg_t *reg_list = NULL;
 280         etm_reg_t *arch_info = NULL;
 281         unsigned bcd_vers, config;
 282
 283         /* register a register arch-type for etm registers only once */
 284         if (etm_reg_arch_type == -1)
 285                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
 286                                 etm_set_reg_w_exec);
 287
 288         /* the actual registers are kept in two arrays */
 289         reg_list = calloc(128, sizeof(reg_t));
 290         arch_info = calloc(128, sizeof(etm_reg_t));
 291
 292         /* fill in values for the reg cache */
 293         reg_cache->name = "etm registers";
 294         reg_cache->next = NULL;
 295         reg_cache->reg_list = reg_list;
 296         reg_cache->num_regs = 0;
 297
 298         /* add ETM_CONFIG, then parse its values to see
 299          * which other registers exist in this ETM
 300          */
 301         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 302                         etm_core, 1);
 303
 304         etm_get_reg(reg_list);
 305         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 306         config = etm_ctx->config;
 307
 308         /* figure ETM version then add base registers */
 309         if (config & (1 << 31)) {
 310                 bcd_vers = 0x20;
 311                 LOG_WARNING("ETMv2+ support is incomplete");
 312
 313                 /* REVISIT read ID register, distinguish ETMv3.3 etc;
 314                  * don't presume trace start/stop support is present;
 315                  * and include any context ID comparator registers.
 316                  */
 317         } else {
 318                 switch (config >> 28) {
 319                 case 7:
 320                 case 5:
 321                 case 3:
 322                         bcd_vers = 0x13;
 323                         break;
 324                 case 4:
 325                 case 2:
 326                         bcd_vers = 0x12;
 327                         break;
 328                 case 1:
 329                         bcd_vers = 0x11;
 330                         break;
 331                 case 0:
 332                         bcd_vers = 0x10;
 333                         break;
 334                 default:
 335                         LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 336                         free(reg_cache);
 337                         free(reg_list);
 338                         free(arch_info);
 339                         return ERROR_OK;
 340                 }
 341         }
 342         etm_ctx->bcd_vers = bcd_vers;
 343         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 344
 345         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 346                         etm_core + 1, ARRAY_SIZE(etm_core) - 1);
 347
 348         /* address and data comparators; counters; outputs */
 349         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 350                         etm_addr_comp, 4 * (0x0f & (config >> 0)));
 351         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 352                         etm_data_comp, 2 * (0x0f & (config >> 4)));
 353         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 354                         etm_counters, 4 * (0x07 & (config >> 13)));
 355         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 356                         etm_outputs, (0x07 & (config >> 20)));
 357
 358         /* FIFOFULL presence is optional
 359          * REVISIT for ETMv1.2 and later, don't bother adding this
 360          * unless ETM_SYS_CONFIG says it's also *supported* ...
 361          */
 362         if (config & (1 << 23))
 363                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 364                                 etm_fifofull, ARRAY_SIZE(etm_fifofull));
 365
 366         /* sequencer is optional (for state-dependant triggering) */
 367         if (config & (1 << 16))
 368                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 369                                 etm_sequencer, ARRAY_SIZE(etm_sequencer));
 370
 371         /* REVISIT could realloc and likely save half the memory
 372          * in the two chunks we allocated...
 373          */
 374
 375         /* the ETM might have an ETB connected */
 376         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 377         {
 378                 etb_t *etb = etm_ctx->capture_driver_priv;
 379
 380                 if (!etb)
 381                 {
 382                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 383                         free(reg_cache);
 384                         free(reg_list);
 385                         free(arch_info);
 386                         return ERROR_OK;
 387                 }
 388
 389                 reg_cache->next = etb_build_reg_cache(etb);
 390
 391                 etb->reg_cache = reg_cache->next;
 392         }
 393
 394
 395         return reg_cache;
 396 }
 397
 398 static int etm_read_reg(reg_t *reg)
 399 {
 400         return etm_read_reg_w_check(reg, NULL, NULL);
 401 }
 402
 403 static int etm_store_reg(reg_t *reg)
 404 {
 405         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 406 }
 407
 408 int etm_setup(target_t *target)
 409 {
 410         int retval;
 411         uint32_t etm_ctrl_value;
 412         armv4_5_common_t *armv4_5 = target->arch_info;
 413         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 414         etm_context_t *etm_ctx = arm7_9->etm_ctx;
 415         reg_t *etm_ctrl_reg;
 416
 417         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 418         if (!etm_ctrl_reg)
 419                 return ERROR_OK;
 420
 421         /* initialize some ETM control register settings */
 422         etm_get_reg(etm_ctrl_reg);
 423         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
 424
 425         /* clear the ETM powerdown bit (0) */
 426         etm_ctrl_value &= ~0x1;
 427
 428         /* configure port width (6:4), mode (17:16) and clocking (13) */
 429         etm_ctrl_value = (etm_ctrl_value &
 430                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 431                 | etm_ctx->portmode;
 432
 433         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 434         etm_store_reg(etm_ctrl_reg);
 435
 436         if ((retval = jtag_execute_queue()) != ERROR_OK)
 437                 return retval;
 438
 439         if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 440         {
 441                 LOG_ERROR("ETM capture driver initialization failed");
 442                 return retval;
 443         }
 444         return ERROR_OK;
 445 }
 446
 447 static int etm_get_reg(reg_t *reg)
 448 {
 449         int retval;
 450
 451         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 452         {
 453                 LOG_ERROR("BUG: error scheduling etm register read");
 454                 return retval;
 455         }
 456
 457         if ((retval = jtag_execute_queue()) != ERROR_OK)
 458         {
 459                 LOG_ERROR("register read failed");
 460                 return retval;
 461         }
 462
 463         return ERROR_OK;
 464 }
 465
 466 static int etm_read_reg_w_check(reg_t *reg,
 467                 uint8_t* check_value, uint8_t* check_mask)
 468 {
 469         etm_reg_t *etm_reg = reg->arch_info;
 470         const struct etm_reg_info *r = etm_reg->reg_info;
 471         uint8_t reg_addr = r->addr & 0x7f;
 472         scan_field_t fields[3];
 473
 474         if (etm_reg->reg_info->mode == WO) {
 475                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 476                 return ERROR_INVALID_ARGUMENTS;
 477         }
 478
 479         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 480
 481         jtag_set_end_state(TAP_IDLE);
 482         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 483         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 484
 485         fields[0].tap = etm_reg->jtag_info->tap;
 486         fields[0].num_bits = 32;
 487         fields[0].out_value = reg->value;
 488         fields[0].in_value = NULL;
 489         fields[0].check_value = NULL;
 490         fields[0].check_mask = NULL;
 491
 492         fields[1].tap = etm_reg->jtag_info->tap;
 493         fields[1].num_bits = 7;
 494         fields[1].out_value = malloc(1);
 495         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 496         fields[1].in_value = NULL;
 497         fields[1].check_value = NULL;
 498         fields[1].check_mask = NULL;
 499
 500         fields[2].tap = etm_reg->jtag_info->tap;
 501         fields[2].num_bits = 1;
 502         fields[2].out_value = malloc(1);
 503         buf_set_u32(fields[2].out_value, 0, 1, 0);
 504         fields[2].in_value = NULL;
 505         fields[2].check_value = NULL;
 506         fields[2].check_mask = NULL;
 507
 508         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 509
 510         fields[0].in_value = reg->value;
 511         fields[0].check_value = check_value;
 512         fields[0].check_mask = check_mask;
 513
 514         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 515
 516         free(fields[1].out_value);
 517         free(fields[2].out_value);
 518
 519         return ERROR_OK;
 520 }
 521
 522 static int etm_set_reg(reg_t *reg, uint32_t value)
 523 {
 524         int retval;
 525
 526         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 527         {
 528                 LOG_ERROR("BUG: error scheduling etm register write");
 529                 return retval;
 530         }
 531
 532         buf_set_u32(reg->value, 0, reg->size, value);
 533         reg->valid = 1;
 534         reg->dirty = 0;
 535
 536         return ERROR_OK;
 537 }
 538
 539 static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 540 {
 541         int retval;
 542
 543         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 544
 545         if ((retval = jtag_execute_queue()) != ERROR_OK)
 546         {
 547                 LOG_ERROR("register write failed");
 548                 return retval;
 549         }
 550         return ERROR_OK;
 551 }
 552
 553 static int etm_write_reg(reg_t *reg, uint32_t value)
 554 {
 555         etm_reg_t *etm_reg = reg->arch_info;
 556         const struct etm_reg_info *r = etm_reg->reg_info;
 557         uint8_t reg_addr = r->addr & 0x7f;
 558         scan_field_t fields[3];
 559
 560         if (etm_reg->reg_info->mode == RO) {
 561                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 562                 return ERROR_INVALID_ARGUMENTS;
 563         }
 564
 565         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 566
 567         jtag_set_end_state(TAP_IDLE);
 568         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 569         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 570
 571         fields[0].tap = etm_reg->jtag_info->tap;
 572         fields[0].num_bits = 32;
 573         uint8_t tmp1[4];
 574         fields[0].out_value = tmp1;
 575         buf_set_u32(fields[0].out_value, 0, 32, value);
 576         fields[0].in_value = NULL;
 577
 578         fields[1].tap = etm_reg->jtag_info->tap;
 579         fields[1].num_bits = 7;
 580         uint8_t tmp2;
 581         fields[1].out_value = &tmp2;
 582         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 583         fields[1].in_value = NULL;
 584
 585         fields[2].tap = etm_reg->jtag_info->tap;
 586         fields[2].num_bits = 1;
 587         uint8_t tmp3;
 588         fields[2].out_value = &tmp3;
 589         buf_set_u32(fields[2].out_value, 0, 1, 1);
 590         fields[2].in_value = NULL;
 591
 592         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 593
 594         return ERROR_OK;
 595 }
 596
 597
 598 /* ETM trace analysis functionality
 599  *
 600  */
 601 extern etm_capture_driver_t etm_dummy_capture_driver;
 602 #if BUILD_OOCD_TRACE == 1
 603 extern etm_capture_driver_t oocd_trace_capture_driver;
 604 #endif
 605
 606 static etm_capture_driver_t *etm_capture_drivers[] =
 607 {
 608         &etb_capture_driver,
 609         &etm_dummy_capture_driver,
 610 #if BUILD_OOCD_TRACE == 1
 611         &oocd_trace_capture_driver,
 612 #endif
 613         NULL
 614 };
 615
 616 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 617 {
 618         int i;
 619         int section = -1;
 620         uint32_t size_read;
 621         uint32_t opcode;
 622         int retval;
 623
 624         if (!ctx->image)
 625                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 626
 627         /* search for the section the current instruction belongs to */
 628         for (i = 0; i < ctx->image->num_sections; i++)
 629         {
 630                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 631                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 632                 {
 633                         section = i;
 634                         break;
 635                 }
 636         }
 637
 638         if (section == -1)
 639         {
 640                 /* current instruction couldn't be found in the image */
 641                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 642         }
 643
 644         if (ctx->core_state == ARMV4_5_STATE_ARM)
 645         {
 646                 uint8_t buf[4];
 647                 if ((retval = image_read_section(ctx->image, section,
 648                         ctx->current_pc - ctx->image->sections[section].base_address,
 649                         4, buf, &size_read)) != ERROR_OK)
 650                 {
 651                         LOG_ERROR("error while reading instruction: %i", retval);
 652                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 653                 }
 654                 opcode = target_buffer_get_u32(ctx->target, buf);
 655                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 656         }
 657         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 658         {
 659                 uint8_t buf[2];
 660                 if ((retval = image_read_section(ctx->image, section,
 661                         ctx->current_pc - ctx->image->sections[section].base_address,
 662                         2, buf, &size_read)) != ERROR_OK)
 663                 {
 664                         LOG_ERROR("error while reading instruction: %i", retval);
 665                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 666                 }
 667                 opcode = target_buffer_get_u16(ctx->target, buf);
 668                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 669         }
 670         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 671         {
 672                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 673                 exit(-1);
 674         }
 675         else
 676         {
 677                 LOG_ERROR("BUG: unknown core state encountered");
 678                 exit(-1);
 679         }
 680
 681         return ERROR_OK;
 682 }
 683
 684 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
 685 {
 686         while (ctx->data_index < ctx->trace_depth)
 687         {
 688                 /* if the caller specified an address packet offset, skip until the
 689                  * we reach the n-th cycle marked with tracesync */
 690                 if (apo > 0)
 691                 {
 692                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 693                                 apo--;
 694
 695                         if (apo > 0)
 696                         {
 697                                 ctx->data_index++;
 698                                 ctx->data_half = 0;
 699                         }
 700                         continue;
 701                 }
 702
 703                 /* no tracedata output during a TD cycle
 704                  * or in a trigger cycle */
 705                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 706                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 707                 {
 708                         ctx->data_index++;
 709                         ctx->data_half = 0;
 710                         continue;
 711                 }
 712
 713                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 714                 {
 715                         if (ctx->data_half == 0)
 716                         {
 717                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 718                                 ctx->data_half = 1;
 719                         }
 720                         else
 721                         {
 722                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 723                                 ctx->data_half = 0;
 724                                 ctx->data_index++;
 725                         }
 726                 }
 727                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 728                 {
 729                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 730                         ctx->data_index++;
 731                 }
 732                 else
 733                 {
 734                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 735                         if (ctx->data_index > (ctx->trace_depth - 2))
 736                                 return -1;
 737
 738                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 739                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 740                         ctx->data_index += 2;
 741                 }
 742
 743                 return 0;
 744         }
 745
 746         return -1;
 747 }
 748
 749 static int etmv1_branch_address(etm_context_t *ctx)
 750 {
 751         int retval;
 752         uint8_t packet;
 753         int shift = 0;
 754         int apo;
 755         uint32_t i;
 756
 757         /* quit analysis if less than two cycles are left in the trace
 758          * because we can't extract the APO */
 759         if (ctx->data_index > (ctx->trace_depth - 2))
 760                 return -1;
 761
 762         /* a BE could be output during an APO cycle, skip the current
 763          * and continue with the new one */
 764         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 765                 return 1;
 766         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 767                 return 2;
 768
 769         /* address packet offset encoded in the next two cycles' pipestat bits */
 770         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 771         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 772
 773         /* count number of tracesync cycles between current pipe_index and data_index
 774          * i.e. the number of tracesyncs that data_index already passed by
 775          * to subtract them from the APO */
 776         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 777         {
 778                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 779                         apo--;
 780         }
 781
 782         /* extract up to four 7-bit packets */
 783         do {
 784                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 785                         return -1;
 786                 ctx->last_branch &= ~(0x7f << shift);
 787                 ctx->last_branch |= (packet & 0x7f) << shift;
 788                 shift += 7;
 789         } while ((packet & 0x80) && (shift < 28));
 790
 791         /* one last packet holding 4 bits of the address, plus the branch reason code */
 792         if ((shift == 28) && (packet & 0x80))
 793         {
 794                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 795                         return -1;
 796                 ctx->last_branch &= 0x0fffffff;
 797                 ctx->last_branch |= (packet & 0x0f) << 28;
 798                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 799                 shift += 4;
 800         }
 801         else
 802         {
 803                 ctx->last_branch_reason = 0;
 804         }
 805
 806         if (shift == 32)
 807         {
 808                 ctx->pc_ok = 1;
 809         }
 810
 811         /* if a full address was output, we might have branched into Jazelle state */
 812         if ((shift == 32) && (packet & 0x80))
 813         {
 814                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 815         }
 816         else
 817         {
 818                 /* if we didn't branch into Jazelle state, the current processor state is
 819                  * encoded in bit 0 of the branch target address */
 820                 if (ctx->last_branch & 0x1)
 821                 {
 822                         ctx->core_state = ARMV4_5_STATE_THUMB;
 823                         ctx->last_branch &= ~0x1;
 824                 }
 825                 else
 826                 {
 827                         ctx->core_state = ARMV4_5_STATE_ARM;
 828                         ctx->last_branch &= ~0x3;
 829                 }
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data)
 836 {
 837         int j;
 838         uint8_t buf[4];
 839         int retval;
 840
 841         for (j = 0; j < size; j++)
 842         {
 843                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 844                         return -1;
 845         }
 846
 847         if (size == 8)
 848         {
 849                 LOG_ERROR("TODO: add support for 64-bit values");
 850                 return -1;
 851         }
 852         else if (size == 4)
 853                 *data = target_buffer_get_u32(ctx->target, buf);
 854         else if (size == 2)
 855                 *data = target_buffer_get_u16(ctx->target, buf);
 856         else if (size == 1)
 857                 *data = buf[0];
 858         else
 859                 return -1;
 860
 861         return 0;
 862 }
 863
 864 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 865 {
 866         int retval;
 867         arm_instruction_t instruction;
 868
 869         /* read the trace data if it wasn't read already */
 870         if (ctx->trace_depth == 0)
 871                 ctx->capture_driver->read_trace(ctx);
 872
 873         /* start at the beginning of the captured trace */
 874         ctx->pipe_index = 0;
 875         ctx->data_index = 0;
 876         ctx->data_half = 0;
 877
 878         /* neither the PC nor the data pointer are valid */
 879         ctx->pc_ok = 0;
 880         ctx->ptr_ok = 0;
 881
 882         while (ctx->pipe_index < ctx->trace_depth)
 883         {
 884                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 885                 uint32_t next_pc = ctx->current_pc;
 886                 uint32_t old_data_index = ctx->data_index;
 887                 uint32_t old_data_half = ctx->data_half;
 888                 uint32_t old_index = ctx->pipe_index;
 889                 uint32_t last_instruction = ctx->last_instruction;
 890                 uint32_t cycles = 0;
 891                 int current_pc_ok = ctx->pc_ok;
 892
 893                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 894                 {
 895                         command_print(cmd_ctx, "--- trigger ---");
 896                 }
 897
 898                 /* instructions execute in IE/D or BE/D cycles */
 899                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 900                         ctx->last_instruction = ctx->pipe_index;
 901
 902                 /* if we don't have a valid pc skip until we reach an indirect branch */
 903                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 904                 {
 905                         ctx->pipe_index++;
 906                         continue;
 907                 }
 908
 909                 /* any indirect branch could have interrupted instruction flow
 910                  * - the branch reason code could indicate a trace discontinuity
 911                  * - a branch to the exception vectors indicates an exception
 912                  */
 913                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 914                 {
 915                         /* backup current data index, to be able to consume the branch address
 916                          * before examining data address and values
 917                          */
 918                         old_data_index = ctx->data_index;
 919                         old_data_half = ctx->data_half;
 920
 921                         ctx->last_instruction = ctx->pipe_index;
 922
 923                         if ((retval = etmv1_branch_address(ctx)) != 0)
 924                         {
 925                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 926                                  * quit analysing the trace */
 927                                 if (retval < 0)
 928                                         break;
 929
 930                                 /* a positive return values means the current branch was abandoned,
 931                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 932                                  */
 933                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 934                                 ctx->pipe_index += retval;
 935                                 continue;
 936                         }
 937
 938                         /* skip over APO cycles */
 939                         ctx->pipe_index += 2;
 940
 941                         switch (ctx->last_branch_reason)
 942                         {
 943                                 case 0x0:       /* normal PC change */
 944                                         next_pc = ctx->last_branch;
 945                                         break;
 946                                 case 0x1:       /* tracing enabled */
 947                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 948                                         ctx->current_pc = ctx->last_branch;
 949                                         ctx->pipe_index++;
 950                                         continue;
 951                                         break;
 952                                 case 0x2:       /* trace restarted after FIFO overflow */
 953                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 954                                         ctx->current_pc = ctx->last_branch;
 955                                         ctx->pipe_index++;
 956                                         continue;
 957                                         break;
 958                                 case 0x3:       /* exit from debug state */
 959                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 960                                         ctx->current_pc = ctx->last_branch;
 961                                         ctx->pipe_index++;
 962                                         continue;
 963                                         break;
 964                                 case 0x4:       /* periodic synchronization point */
 965                                         next_pc = ctx->last_branch;
 966                                         /* if we had no valid PC prior to this synchronization point,
 967                                          * we have to move on with the next trace cycle
 968                                          */
 969                                         if (!current_pc_ok)
 970                                         {
 971                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 972                                                 ctx->current_pc = next_pc;
 973                                                 ctx->pipe_index++;
 974                                                 continue;
 975                                         }
 976                                         break;
 977                                 default:        /* reserved */
 978                                         LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
 979                                         exit(-1);
 980                                         break;
 981                         }
 982
 983                         /* if we got here the branch was a normal PC change
 984                          * (or a periodic synchronization point, which means the same for that matter)
 985                          * if we didn't accquire a complete PC continue with the next cycle
 986                          */
 987                         if (!ctx->pc_ok)
 988                                 continue;
 989
 990                         /* indirect branch to the exception vector means an exception occured */
 991                         if ((ctx->last_branch <= 0x20)
 992                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 993                         {
 994                                 if ((ctx->last_branch & 0xff) == 0x10)
 995                                 {
 996                                         command_print(cmd_ctx, "data abort");
 997                                 }
 998                                 else
 999                                 {
1000                                         command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1001                                         ctx->current_pc = ctx->last_branch;
1002                                         ctx->pipe_index++;
1003                                         continue;
1004                                 }
1005                         }
1006                 }
1007
1008                 /* an instruction was executed (or not, depending on the condition flags)
1009                  * retrieve it from the image for displaying */
1010                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1011                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1012                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1013                 {
1014                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1015                         {
1016                                 /* can't continue tracing with no image available */
1017                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1018                                 {
1019                                         return retval;
1020                                 }
1021                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1022                                 {
1023                                         /* TODO: handle incomplete images
1024                                          * for now we just quit the analsysis*/
1025                                         return retval;
1026                                 }
1027                         }
1028
1029                         cycles = old_index - last_instruction;
1030                 }
1031
1032                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1033                 {
1034                         uint32_t new_data_index = ctx->data_index;
1035                         uint32_t new_data_half = ctx->data_half;
1036
1037                         /* in case of a branch with data, the branch target address was consumed before
1038                          * we temporarily go back to the saved data index */
1039                         if (pipestat == STAT_BD)
1040                         {
1041                                 ctx->data_index = old_data_index;
1042                                 ctx->data_half = old_data_half;
1043                         }
1044
1045                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
1046                         {
1047                                 uint8_t packet;
1048                                 int shift = 0;
1049
1050                                 do {
1051                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1052                                                 return ERROR_ETM_ANALYSIS_FAILED;
1053                                         ctx->last_ptr &= ~(0x7f << shift);
1054                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1055                                         shift += 7;
1056                                 } while ((packet & 0x80) && (shift < 32));
1057
1058                                 if (shift >= 32)
1059                                         ctx->ptr_ok = 1;
1060
1061                                 if (ctx->ptr_ok)
1062                                 {
1063                                         command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1064                                 }
1065                         }
1066
1067                         if (ctx->tracemode & ETMV1_TRACE_DATA)
1068                         {
1069                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1070                                 {
1071                                         int i;
1072                                         for (i = 0; i < 16; i++)
1073                                         {
1074                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
1075                                                 {
1076                                                         uint32_t data;
1077                                                         if (etmv1_data(ctx, 4, &data) != 0)
1078                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1079                                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1080                                                 }
1081                                         }
1082                                 }
1083                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1084                                 {
1085                                         uint32_t data;
1086                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1087                                                 return ERROR_ETM_ANALYSIS_FAILED;
1088                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1089                                 }
1090                         }
1091
1092                         /* restore data index after consuming BD address and data */
1093                         if (pipestat == STAT_BD)
1094                         {
1095                                 ctx->data_index = new_data_index;
1096                                 ctx->data_half = new_data_half;
1097                         }
1098                 }
1099
1100                 /* adjust PC */
1101                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1102                 {
1103                         if (((instruction.type == ARM_B) ||
1104                              (instruction.type == ARM_BL) ||
1105                              (instruction.type == ARM_BLX)) &&
1106                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1107                         {
1108                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1109                         }
1110                         else
1111                         {
1112                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1113                         }
1114                 }
1115                 else if (pipestat == STAT_IN)
1116                 {
1117                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1118                 }
1119
1120                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1121                 {
1122                         char cycles_text[32] = "";
1123
1124                         /* if the trace was captured with cycle accurate tracing enabled,
1125                          * output the number of cycles since the last executed instruction
1126                          */
1127                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1128                         {
1129                                 snprintf(cycles_text, 32, " (%i %s)",
1130                                          (int)cycles,
1131                                         (cycles == 1) ? "cycle" : "cycles");
1132                         }
1133
1134                         command_print(cmd_ctx, "%s%s%s",
1135                                 instruction.text,
1136                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1137                                 cycles_text);
1138
1139                         ctx->current_pc = next_pc;
1140
1141                         /* packets for an instruction don't start on or before the preceding
1142                          * functional pipestat (i.e. other than WT or TD)
1143                          */
1144                         if (ctx->data_index <= ctx->pipe_index)
1145                         {
1146                                 ctx->data_index = ctx->pipe_index + 1;
1147                                 ctx->data_half = 0;
1148                         }
1149                 }
1150
1151                 ctx->pipe_index += 1;
1152         }
1153
1154         return ERROR_OK;
1155 }
1156
1157 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1158 {
1159         target_t *target;
1160         armv4_5_common_t *armv4_5;
1161         arm7_9_common_t *arm7_9;
1162         etmv1_tracemode_t tracemode;
1163
1164         target = get_current_target(cmd_ctx);
1165
1166         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1167         {
1168                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1169                 return ERROR_OK;
1170         }
1171
1172         if (!arm7_9->etm_ctx)
1173         {
1174                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1175                 return ERROR_OK;
1176         }
1177
1178         tracemode = arm7_9->etm_ctx->tracemode;
1179
1180         if (argc == 4)
1181         {
1182                 if (strcmp(args[0], "none") == 0)
1183                 {
1184                         tracemode = ETMV1_TRACE_NONE;
1185                 }
1186                 else if (strcmp(args[0], "data") == 0)
1187                 {
1188                         tracemode = ETMV1_TRACE_DATA;
1189                 }
1190                 else if (strcmp(args[0], "address") == 0)
1191                 {
1192                         tracemode = ETMV1_TRACE_ADDR;
1193                 }
1194                 else if (strcmp(args[0], "all") == 0)
1195                 {
1196                         tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1197                 }
1198                 else
1199                 {
1200                         command_print(cmd_ctx, "invalid option '%s'", args[0]);
1201                         return ERROR_OK;
1202                 }
1203
1204                 switch (strtol(args[1], NULL, 0))
1205                 {
1206                         case 0:
1207                                 tracemode |= ETMV1_CONTEXTID_NONE;
1208                                 break;
1209                         case 8:
1210                                 tracemode |= ETMV1_CONTEXTID_8;
1211                                 break;
1212                         case 16:
1213                                 tracemode |= ETMV1_CONTEXTID_16;
1214                                 break;
1215                         case 32:
1216                                 tracemode |= ETMV1_CONTEXTID_32;
1217                                 break;
1218                         default:
1219                                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1220                                 return ERROR_OK;
1221                 }
1222
1223                 if (strcmp(args[2], "enable") == 0)
1224                 {
1225                         tracemode |= ETMV1_CYCLE_ACCURATE;
1226                 }
1227                 else if (strcmp(args[2], "disable") == 0)
1228                 {
1229                         tracemode |= 0;
1230                 }
1231                 else
1232                 {
1233                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1234                         return ERROR_OK;
1235                 }
1236
1237                 if (strcmp(args[3], "enable") == 0)
1238                 {
1239                         tracemode |= ETMV1_BRANCH_OUTPUT;
1240                 }
1241                 else if (strcmp(args[3], "disable") == 0)
1242                 {
1243                         tracemode |= 0;
1244                 }
1245                 else
1246                 {
1247                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1248                         return ERROR_OK;
1249                 }
1250         }
1251         else if (argc != 0)
1252         {
1253                 command_print(cmd_ctx, "usage: configure trace mode <none | data | address | all> <context id bits> <cycle accurate> <branch output>");
1254                 return ERROR_OK;
1255         }
1256
1257         command_print(cmd_ctx, "current tracemode configuration:");
1258
1259         switch (tracemode & ETMV1_TRACE_MASK)
1260         {
1261                 case ETMV1_TRACE_NONE:
1262                         command_print(cmd_ctx, "data tracing: none");
1263                         break;
1264                 case ETMV1_TRACE_DATA:
1265                         command_print(cmd_ctx, "data tracing: data only");
1266                         break;
1267                 case ETMV1_TRACE_ADDR:
1268                         command_print(cmd_ctx, "data tracing: address only");
1269                         break;
1270                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1271                         command_print(cmd_ctx, "data tracing: address and data");
1272                         break;
1273         }
1274
1275         switch (tracemode & ETMV1_CONTEXTID_MASK)
1276         {
1277                 case ETMV1_CONTEXTID_NONE:
1278                         command_print(cmd_ctx, "contextid tracing: none");
1279                         break;
1280                 case ETMV1_CONTEXTID_8:
1281                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1282                         break;
1283                 case ETMV1_CONTEXTID_16:
1284                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1285                         break;
1286                 case ETMV1_CONTEXTID_32:
1287                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1288                         break;
1289         }
1290
1291         if (tracemode & ETMV1_CYCLE_ACCURATE)
1292         {
1293                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1294         }
1295         else
1296         {
1297                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1298         }
1299
1300         if (tracemode & ETMV1_BRANCH_OUTPUT)
1301         {
1302                 command_print(cmd_ctx, "full branch address output enabled");
1303         }
1304         else
1305         {
1306                 command_print(cmd_ctx, "full branch address output disabled");
1307         }
1308
1309         /* only update ETM_CTRL register if tracemode changed */
1310         if (arm7_9->etm_ctx->tracemode != tracemode)
1311         {
1312                 reg_t *etm_ctrl_reg;
1313
1314                 etm_ctrl_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CTRL);
1315                 if (!etm_ctrl_reg)
1316                         return ERROR_OK;
1317
1318                 etm_get_reg(etm_ctrl_reg);
1319
1320                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1321                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1322                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1323                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1324                 etm_store_reg(etm_ctrl_reg);
1325
1326                 arm7_9->etm_ctx->tracemode = tracemode;
1327
1328                 /* invalidate old trace data */
1329                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1330                 if (arm7_9->etm_ctx->trace_depth > 0)
1331                 {
1332                         free(arm7_9->etm_ctx->trace_data);
1333                         arm7_9->etm_ctx->trace_data = NULL;
1334                 }
1335                 arm7_9->etm_ctx->trace_depth = 0;
1336         }
1337
1338         return ERROR_OK;
1339 }
1340
1341 static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1342 {
1343         target_t *target;
1344         armv4_5_common_t *armv4_5;
1345         arm7_9_common_t *arm7_9;
1346         etm_portmode_t portmode = 0x0;
1347         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1348         int i;
1349
1350         if (argc != 5)
1351         {
1352                 free(etm_ctx);
1353                 return ERROR_COMMAND_SYNTAX_ERROR;
1354         }
1355
1356         target = get_target(args[0]);
1357         if (!target)
1358         {
1359                 LOG_ERROR("target '%s' not defined", args[0]);
1360                 free(etm_ctx);
1361                 return ERROR_FAIL;
1362         }
1363
1364         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1365         {
1366                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1367                 free(etm_ctx);
1368                 return ERROR_FAIL;
1369         }
1370
1371         switch (strtoul(args[1], NULL, 0))
1372         {
1373                 case 4:
1374                         portmode |= ETM_PORT_4BIT;
1375                         break;
1376                 case 8:
1377                         portmode |= ETM_PORT_8BIT;
1378                         break;
1379                 case 16:
1380                         portmode |= ETM_PORT_16BIT;
1381                         break;
1382                 default:
1383                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1384                         free(etm_ctx);
1385                         return ERROR_FAIL;
1386         }
1387
1388         if (strcmp("normal", args[2]) == 0)
1389         {
1390                 portmode |= ETM_PORT_NORMAL;
1391         }
1392         else if (strcmp("multiplexed", args[2]) == 0)
1393         {
1394                 portmode |= ETM_PORT_MUXED;
1395         }
1396         else if (strcmp("demultiplexed", args[2]) == 0)
1397         {
1398                 portmode |= ETM_PORT_DEMUXED;
1399         }
1400         else
1401         {
1402                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1403                 free(etm_ctx);
1404                 return ERROR_FAIL;
1405         }
1406
1407         if (strcmp("half", args[3]) == 0)
1408         {
1409                 portmode |= ETM_PORT_HALF_CLOCK;
1410         }
1411         else if (strcmp("full", args[3]) == 0)
1412         {
1413                 portmode |= ETM_PORT_FULL_CLOCK;
1414         }
1415         else
1416         {
1417                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1418                 free(etm_ctx);
1419                 return ERROR_FAIL;
1420         }
1421
1422         for (i = 0; etm_capture_drivers[i]; i++)
1423         {
1424                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1425                 {
1426                         int retval;
1427                         if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1428                         {
1429                                 free(etm_ctx);
1430                                 return retval;
1431                         }
1432
1433                         etm_ctx->capture_driver = etm_capture_drivers[i];
1434
1435                         break;
1436                 }
1437         }
1438
1439         if (!etm_capture_drivers[i])
1440         {
1441                 /* no supported capture driver found, don't register an ETM */
1442                 free(etm_ctx);
1443                 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1444                 return ERROR_FAIL;
1445         }
1446
1447         etm_ctx->target = target;
1448         etm_ctx->trigger_percent = 50;
1449         etm_ctx->trace_data = NULL;
1450         etm_ctx->trace_depth = 0;
1451         etm_ctx->portmode = portmode;
1452         etm_ctx->tracemode = 0x0;
1453         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1454         etm_ctx->image = NULL;
1455         etm_ctx->pipe_index = 0;
1456         etm_ctx->data_index = 0;
1457         etm_ctx->current_pc = 0x0;
1458         etm_ctx->pc_ok = 0;
1459         etm_ctx->last_branch = 0x0;
1460         etm_ctx->last_branch_reason = 0x0;
1461         etm_ctx->last_ptr = 0x0;
1462         etm_ctx->ptr_ok = 0x0;
1463         etm_ctx->last_instruction = 0;
1464
1465         arm7_9->etm_ctx = etm_ctx;
1466
1467         return etm_register_user_commands(cmd_ctx);
1468 }
1469
1470 static int handle_etm_info_command(struct command_context_s *cmd_ctx,
1471                 char *cmd, char **args, int argc)
1472 {
1473         target_t *target;
1474         armv4_5_common_t *armv4_5;
1475         arm7_9_common_t *arm7_9;
1476         etm_context_t *etm;
1477         reg_t *etm_sys_config_reg;
1478
1479         int max_port_size;
1480
1481         target = get_current_target(cmd_ctx);
1482
1483         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1484         {
1485                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1486                 return ERROR_OK;
1487         }
1488
1489         etm = arm7_9->etm_ctx;
1490         if (!etm)
1491         {
1492                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1493                 return ERROR_OK;
1494         }
1495
1496         command_print(cmd_ctx, "ETM v%d.%d",
1497                         etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1498         command_print(cmd_ctx, "pairs of address comparators: %i",
1499                         (etm->config >> 0) & 0x0f);
1500         command_print(cmd_ctx, "data comparators: %i",
1501                         (etm->config >> 4) & 0x0f);
1502         command_print(cmd_ctx, "memory map decoders: %i",
1503                         (etm->config >> 8) & 0x1f);
1504         command_print(cmd_ctx, "number of counters: %i",
1505                         (etm->config >> 13) & 0x07);
1506         command_print(cmd_ctx, "sequencer %spresent",
1507                         (etm->config & (1 << 16)) ? "" : "not ");
1508         command_print(cmd_ctx, "number of ext. inputs: %i",
1509                         (etm->config >> 17) & 0x07);
1510         command_print(cmd_ctx, "number of ext. outputs: %i",
1511                         (etm->config >> 20) & 0x07);
1512         command_print(cmd_ctx, "FIFO full %spresent",
1513                         (etm->config & (1 << 23)) ? "" : "not ");
1514         if (etm->bcd_vers < 0x20)
1515                 command_print(cmd_ctx, "protocol version: %i",
1516                                 (etm->config >> 28) & 0x07);
1517         else {
1518                 command_print(cmd_ctx, "trace start/stop %spresent",
1519                                 (etm->config & (1 << 26)) ? "" : "not ");
1520                 command_print(cmd_ctx, "number of context comparators: %i",
1521                                 (etm->config >> 24) & 0x03);
1522         }
1523
1524         /* SYS_CONFIG isn't present before ETMv1.2 */
1525         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1526         if (!etm_sys_config_reg)
1527                 return ERROR_OK;
1528
1529         etm_get_reg(etm_sys_config_reg);
1530
1531         switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1532         {
1533                 case 0:
1534                         max_port_size = 4;
1535                         break;
1536                 case 1:
1537                         max_port_size = 8;
1538                         break;
1539                 case 2:
1540                         max_port_size = 16;
1541                         break;
1542                 default:
1543                         LOG_ERROR("Illegal max_port_size");
1544                         exit(-1);
1545         }
1546         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1547
1548         command_print(cmd_ctx, "half-rate clocking %ssupported",
1549                         (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1550         command_print(cmd_ctx, "full-rate clocking %ssupported",
1551                         (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1552         command_print(cmd_ctx, "normal trace format %ssupported",
1553                         (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1554         command_print(cmd_ctx, "multiplex trace format %ssupported",
1555                         (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1556         command_print(cmd_ctx, "demultiplex trace format %ssupported",
1557                         (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1558         command_print(cmd_ctx, "FIFO full %ssupported",
1559                         (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1560
1561         return ERROR_OK;
1562 }
1563
1564 static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1565 {
1566         target_t *target;
1567         armv4_5_common_t *armv4_5;
1568         arm7_9_common_t *arm7_9;
1569         trace_status_t trace_status;
1570
1571         target = get_current_target(cmd_ctx);
1572
1573         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1574         {
1575                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1576                 return ERROR_OK;
1577         }
1578
1579         if (!arm7_9->etm_ctx)
1580         {
1581                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1582                 return ERROR_OK;
1583         }
1584
1585         trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1586
1587         if (trace_status == TRACE_IDLE)
1588         {
1589                 command_print(cmd_ctx, "tracing is idle");
1590         }
1591         else
1592         {
1593                 static char *completed = " completed";
1594                 static char *running = " is running";
1595                 static char *overflowed = ", trace overflowed";
1596                 static char *triggered = ", trace triggered";
1597
1598                 command_print(cmd_ctx, "trace collection%s%s%s",
1599                         (trace_status & TRACE_RUNNING) ? running : completed,
1600                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1601                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1602
1603                 if (arm7_9->etm_ctx->trace_depth > 0)
1604                 {
1605                         command_print(cmd_ctx, "%i frames of trace data read", (int)(arm7_9->etm_ctx->trace_depth));
1606                 }
1607         }
1608
1609         return ERROR_OK;
1610 }
1611
1612 static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1613 {
1614         target_t *target;
1615         armv4_5_common_t *armv4_5;
1616         arm7_9_common_t *arm7_9;
1617         etm_context_t *etm_ctx;
1618
1619         if (argc < 1)
1620         {
1621                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1622                 return ERROR_OK;
1623         }
1624
1625         target = get_current_target(cmd_ctx);
1626
1627         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1628         {
1629                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1630                 return ERROR_OK;
1631         }
1632
1633         if (!(etm_ctx = arm7_9->etm_ctx))
1634         {
1635                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1636                 return ERROR_OK;
1637         }
1638
1639         if (etm_ctx->image)
1640         {
1641                 image_close(etm_ctx->image);
1642                 free(etm_ctx->image);
1643                 command_print(cmd_ctx, "previously loaded image found and closed");
1644         }
1645
1646         etm_ctx->image = malloc(sizeof(image_t));
1647         etm_ctx->image->base_address_set = 0;
1648         etm_ctx->image->start_address_set = 0;
1649
1650         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1651         if (argc >= 2)
1652         {
1653                 etm_ctx->image->base_address_set = 1;
1654                 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1655         }
1656         else
1657         {
1658                 etm_ctx->image->base_address_set = 0;
1659         }
1660
1661         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1662         {
1663                 free(etm_ctx->image);
1664                 etm_ctx->image = NULL;
1665                 return ERROR_OK;
1666         }
1667
1668         return ERROR_OK;
1669 }
1670
1671 static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1672 {
1673         fileio_t file;
1674         target_t *target;
1675         armv4_5_common_t *armv4_5;
1676         arm7_9_common_t *arm7_9;
1677         etm_context_t *etm_ctx;
1678         uint32_t i;
1679
1680         if (argc != 1)
1681         {
1682                 command_print(cmd_ctx, "usage: etm dump <file>");
1683                 return ERROR_OK;
1684         }
1685
1686         target = get_current_target(cmd_ctx);
1687
1688         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1689         {
1690                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1691                 return ERROR_OK;
1692         }
1693
1694         if (!(etm_ctx = arm7_9->etm_ctx))
1695         {
1696                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1697                 return ERROR_OK;
1698         }
1699
1700         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1701         {
1702                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1703                 return ERROR_OK;
1704         }
1705
1706         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1707         {
1708                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1709                 command_print(cmd_ctx, "trace capture not completed");
1710                 return ERROR_OK;
1711         }
1712
1713         /* read the trace data if it wasn't read already */
1714         if (etm_ctx->trace_depth == 0)
1715                 etm_ctx->capture_driver->read_trace(etm_ctx);
1716
1717         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1718         {
1719                 return ERROR_OK;
1720         }
1721
1722         fileio_write_u32(&file, etm_ctx->capture_status);
1723         fileio_write_u32(&file, etm_ctx->portmode);
1724         fileio_write_u32(&file, etm_ctx->tracemode);
1725         fileio_write_u32(&file, etm_ctx->trace_depth);
1726
1727         for (i = 0; i < etm_ctx->trace_depth; i++)
1728         {
1729                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1730                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1731                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1732         }
1733
1734         fileio_close(&file);
1735
1736         return ERROR_OK;
1737 }
1738
1739 static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1740 {
1741         fileio_t file;
1742         target_t *target;
1743         armv4_5_common_t *armv4_5;
1744         arm7_9_common_t *arm7_9;
1745         etm_context_t *etm_ctx;
1746         uint32_t i;
1747
1748         if (argc != 1)
1749         {
1750                 command_print(cmd_ctx, "usage: etm load <file>");
1751                 return ERROR_OK;
1752         }
1753
1754         target = get_current_target(cmd_ctx);
1755
1756         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1757         {
1758                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1759                 return ERROR_OK;
1760         }
1761
1762         if (!(etm_ctx = arm7_9->etm_ctx))
1763         {
1764                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1765                 return ERROR_OK;
1766         }
1767
1768         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1769         {
1770                 command_print(cmd_ctx, "trace capture running, stop first");
1771                 return ERROR_OK;
1772         }
1773
1774         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1775         {
1776                 return ERROR_OK;
1777         }
1778
1779         if (file.size % 4)
1780         {
1781                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1782                 fileio_close(&file);
1783                 return ERROR_OK;
1784         }
1785
1786         if (etm_ctx->trace_depth > 0)
1787         {
1788                 free(etm_ctx->trace_data);
1789                 etm_ctx->trace_data = NULL;
1790         }
1791
1792         {
1793           uint32_t tmp;
1794           fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1795           fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1796           fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1797           fileio_read_u32(&file, &etm_ctx->trace_depth);
1798         }
1799         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1800         if (etm_ctx->trace_data == NULL)
1801         {
1802                 command_print(cmd_ctx, "not enough memory to perform operation");
1803                 fileio_close(&file);
1804                 return ERROR_OK;
1805         }
1806
1807         for (i = 0; i < etm_ctx->trace_depth; i++)
1808         {
1809                 uint32_t pipestat, packet, flags;
1810                 fileio_read_u32(&file, &pipestat);
1811                 fileio_read_u32(&file, &packet);
1812                 fileio_read_u32(&file, &flags);
1813                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1814                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1815                 etm_ctx->trace_data[i].flags = flags;
1816         }
1817
1818         fileio_close(&file);
1819
1820         return ERROR_OK;
1821 }
1822
1823 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1824 {
1825         target_t *target;
1826         armv4_5_common_t *armv4_5;
1827         arm7_9_common_t *arm7_9;
1828         etm_context_t *etm_ctx;
1829
1830         target = get_current_target(cmd_ctx);
1831
1832         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1833         {
1834                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1835                 return ERROR_OK;
1836         }
1837
1838         if (!(etm_ctx = arm7_9->etm_ctx))
1839         {
1840                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1841                 return ERROR_OK;
1842         }
1843
1844         if (argc > 0)
1845         {
1846                 uint32_t new_value = strtoul(args[0], NULL, 0);
1847
1848                 if ((new_value < 2) || (new_value > 100))
1849                 {
1850                         command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1851                 }
1852                 else
1853                 {
1854                         etm_ctx->trigger_percent = new_value;
1855                 }
1856         }
1857
1858         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1859
1860         return ERROR_OK;
1861 }
1862
1863 static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1864 {
1865         target_t *target;
1866         armv4_5_common_t *armv4_5;
1867         arm7_9_common_t *arm7_9;
1868         etm_context_t *etm_ctx;
1869         reg_t *etm_ctrl_reg;
1870
1871         target = get_current_target(cmd_ctx);
1872
1873         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1874         {
1875                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1876                 return ERROR_OK;
1877         }
1878
1879         if (!(etm_ctx = arm7_9->etm_ctx))
1880         {
1881                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1882                 return ERROR_OK;
1883         }
1884
1885         /* invalidate old tracing data */
1886         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1887         if (arm7_9->etm_ctx->trace_depth > 0)
1888         {
1889                 free(arm7_9->etm_ctx->trace_data);
1890                 arm7_9->etm_ctx->trace_data = NULL;
1891         }
1892         arm7_9->etm_ctx->trace_depth = 0;
1893
1894         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1895         if (!etm_ctrl_reg)
1896                 return ERROR_OK;
1897
1898         etm_get_reg(etm_ctrl_reg);
1899
1900         /* Clear programming bit (10), set port selection bit (11) */
1901         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1902
1903         etm_store_reg(etm_ctrl_reg);
1904         jtag_execute_queue();
1905
1906         etm_ctx->capture_driver->start_capture(etm_ctx);
1907
1908         return ERROR_OK;
1909 }
1910
1911 static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1912 {
1913         target_t *target;
1914         armv4_5_common_t *armv4_5;
1915         arm7_9_common_t *arm7_9;
1916         etm_context_t *etm_ctx;
1917         reg_t *etm_ctrl_reg;
1918
1919         target = get_current_target(cmd_ctx);
1920
1921         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1922         {
1923                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1924                 return ERROR_OK;
1925         }
1926
1927         if (!(etm_ctx = arm7_9->etm_ctx))
1928         {
1929                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1930                 return ERROR_OK;
1931         }
1932
1933         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1934         if (!etm_ctrl_reg)
1935                 return ERROR_OK;
1936
1937         etm_get_reg(etm_ctrl_reg);
1938
1939         /* Set programming bit (10), clear port selection bit (11) */
1940         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1941
1942         etm_store_reg(etm_ctrl_reg);
1943         jtag_execute_queue();
1944
1945         etm_ctx->capture_driver->stop_capture(etm_ctx);
1946
1947         return ERROR_OK;
1948 }
1949
1950 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1951 {
1952         target_t *target;
1953         armv4_5_common_t *armv4_5;
1954         arm7_9_common_t *arm7_9;
1955         etm_context_t *etm_ctx;
1956         int retval;
1957
1958         target = get_current_target(cmd_ctx);
1959
1960         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1961         {
1962                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1963                 return ERROR_OK;
1964         }
1965
1966         if (!(etm_ctx = arm7_9->etm_ctx))
1967         {
1968                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1969                 return ERROR_OK;
1970         }
1971
1972         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1973         {
1974                 switch (retval)
1975                 {
1976                         case ERROR_ETM_ANALYSIS_FAILED:
1977                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1978                                 break;
1979                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1980                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1981                                 break;
1982                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
1983                                 command_print(cmd_ctx, "no image available for trace analysis");
1984                                 break;
1985                         default:
1986                                 command_print(cmd_ctx, "unknown error: %i", retval);
1987                 }
1988         }
1989
1990         return ERROR_OK;
1991 }
1992
1993 int etm_register_commands(struct command_context_s *cmd_ctx)
1994 {
1995         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1996
1997         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
1998                 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1999
2000         return ERROR_OK;
2001 }
2002
2003 static int etm_register_user_commands(struct command_context_s *cmd_ctx)
2004 {
2005         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2006                 COMMAND_EXEC, "configure/display trace mode: "
2007                         "<none | data | address | all> "
2008                         "<context_id_bits> <cycle_accurate> <branch_output>");
2009
2010         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2011                 COMMAND_EXEC, "display info about the current target's ETM");
2012
2013         register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2014                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2015         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2016                 COMMAND_EXEC, "display current target's ETM status");
2017         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2018                 COMMAND_EXEC, "start ETM trace collection");
2019         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2020                 COMMAND_EXEC, "stop ETM trace collection");
2021
2022         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2023                 COMMAND_EXEC, "anaylze collected ETM trace");
2024
2025         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2026                 COMMAND_EXEC, "load image from <file> [base address]");
2027
2028         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2029                 COMMAND_EXEC, "dump captured trace data <file>");
2030         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2031                 COMMAND_EXEC, "load trace data for analysis <file>");
2032
2033         return ERROR_OK;
2034 }