git.gag.com Git - fw/openocd/blob - src/target/etm.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <string.h>
  25
  26 #include "etm.h"
  27 #include "etb.h"
  28
  29 #include "armv4_5.h"
  30 #include "arm7_9_common.h"
  31 #include "arm_disassembler.h"
  32 #include "arm_simulator.h"
  33
  34 #include "log.h"
  35 #include "arm_jtag.h"
  36 #include "types.h"
  37 #include "binarybuffer.h"
  38 #include "target.h"
  39 #include "register.h"
  40 #include "jtag.h"
  41 #include "fileio.h"
  42
  43 #include <stdlib.h>
  44
  45 /* ETM register access functionality
  46  *
  47  */
  48
  49 bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
  50 {
  51         {"R", 1},
  52         {"W", 1},
  53         {"reserved", 26},
  54         {"version", 4}
  55 };
  56
  57 int etm_reg_arch_info[] =
  58 {
  59         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  60         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  61         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
  62         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
  63         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
  64         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
  65         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
  66         0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
  67         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
  68         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
  69         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
  70         0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
  71         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
  72         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  73 };
  74
  75 int etm_reg_arch_size_info[] =
  76 {
  77         32, 32, 17, 8, 3, 9, 32, 16,
  78         17, 26, 25, 8, 17, 32, 32, 17,
  79         32, 32, 32, 32, 32, 32, 32, 32,
  80         32, 32, 32, 32, 32, 32, 32, 32,
  81         7, 7, 7, 7, 7, 7, 7, 7,
  82         7, 7, 7, 7, 7, 7, 7, 7,
  83         32, 32, 32, 32, 32, 32, 32, 32,
  84         32, 32, 32, 32, 32, 32, 32, 32,
  85         32, 32, 32, 32, 32, 32, 32, 32,
  86         32, 32, 32, 32, 32, 32, 32, 32,
  87         16, 16, 16, 16, 18, 18, 18, 18,
  88         17, 17, 17, 17, 16, 16, 16, 16,
  89         17, 17, 17, 17, 17, 17, 2,
  90         17, 17, 17, 17, 32, 32, 32, 32
  91 };
  92
  93 char* etm_reg_list[] =
  94 {
  95         "ETM_CTRL",
  96         "ETM_CONFIG",
  97         "ETM_TRIG_EVENT",
  98         "ETM_MMD_CTRL",
  99         "ETM_STATUS",
 100         "ETM_SYS_CONFIG",
 101         "ETM_TRACE_RESOURCE_CTRL",
 102         "ETM_TRACE_EN_CTRL2",
 103         "ETM_TRACE_EN_EVENT",
 104         "ETM_TRACE_EN_CTRL1",
 105         "ETM_FIFOFULL_REGION",
 106         "ETM_FIFOFULL_LEVEL",
 107         "ETM_VIEWDATA_EVENT",
 108         "ETM_VIEWDATA_CTRL1",
 109         "ETM_VIEWDATA_CTRL2",
 110         "ETM_VIEWDATA_CTRL3",
 111         "ETM_ADDR_COMPARATOR_VALUE1",
 112         "ETM_ADDR_COMPARATOR_VALUE2",
 113         "ETM_ADDR_COMPARATOR_VALUE3",
 114         "ETM_ADDR_COMPARATOR_VALUE4",
 115         "ETM_ADDR_COMPARATOR_VALUE5",
 116         "ETM_ADDR_COMPARATOR_VALUE6",
 117         "ETM_ADDR_COMPARATOR_VALUE7",
 118         "ETM_ADDR_COMPARATOR_VALUE8",
 119         "ETM_ADDR_COMPARATOR_VALUE9",
 120         "ETM_ADDR_COMPARATOR_VALUE10",
 121         "ETM_ADDR_COMPARATOR_VALUE11",
 122         "ETM_ADDR_COMPARATOR_VALUE12",
 123         "ETM_ADDR_COMPARATOR_VALUE13",
 124         "ETM_ADDR_COMPARATOR_VALUE14",
 125         "ETM_ADDR_COMPARATOR_VALUE15",
 126         "ETM_ADDR_COMPARATOR_VALUE16",
 127         "ETM_ADDR_ACCESS_TYPE1",
 128         "ETM_ADDR_ACCESS_TYPE2",
 129         "ETM_ADDR_ACCESS_TYPE3",
 130         "ETM_ADDR_ACCESS_TYPE4",
 131         "ETM_ADDR_ACCESS_TYPE5",
 132         "ETM_ADDR_ACCESS_TYPE6",
 133         "ETM_ADDR_ACCESS_TYPE7",
 134         "ETM_ADDR_ACCESS_TYPE8",
 135         "ETM_ADDR_ACCESS_TYPE9",
 136         "ETM_ADDR_ACCESS_TYPE10",
 137         "ETM_ADDR_ACCESS_TYPE11",
 138         "ETM_ADDR_ACCESS_TYPE12",
 139         "ETM_ADDR_ACCESS_TYPE13",
 140         "ETM_ADDR_ACCESS_TYPE14",
 141         "ETM_ADDR_ACCESS_TYPE15",
 142         "ETM_ADDR_ACCESS_TYPE16",
 143         "ETM_DATA_COMPARATOR_VALUE1",
 144         "ETM_DATA_COMPARATOR_VALUE2",
 145         "ETM_DATA_COMPARATOR_VALUE3",
 146         "ETM_DATA_COMPARATOR_VALUE4",
 147         "ETM_DATA_COMPARATOR_VALUE5",
 148         "ETM_DATA_COMPARATOR_VALUE6",
 149         "ETM_DATA_COMPARATOR_VALUE7",
 150         "ETM_DATA_COMPARATOR_VALUE8",
 151         "ETM_DATA_COMPARATOR_VALUE9",
 152         "ETM_DATA_COMPARATOR_VALUE10",
 153         "ETM_DATA_COMPARATOR_VALUE11",
 154         "ETM_DATA_COMPARATOR_VALUE12",
 155         "ETM_DATA_COMPARATOR_VALUE13",
 156         "ETM_DATA_COMPARATOR_VALUE14",
 157         "ETM_DATA_COMPARATOR_VALUE15",
 158         "ETM_DATA_COMPARATOR_VALUE16",
 159         "ETM_DATA_COMPARATOR_MASK1",
 160         "ETM_DATA_COMPARATOR_MASK2",
 161         "ETM_DATA_COMPARATOR_MASK3",
 162         "ETM_DATA_COMPARATOR_MASK4",
 163         "ETM_DATA_COMPARATOR_MASK5",
 164         "ETM_DATA_COMPARATOR_MASK6",
 165         "ETM_DATA_COMPARATOR_MASK7",
 166         "ETM_DATA_COMPARATOR_MASK8",
 167         "ETM_DATA_COMPARATOR_MASK9",
 168         "ETM_DATA_COMPARATOR_MASK10",
 169         "ETM_DATA_COMPARATOR_MASK11",
 170         "ETM_DATA_COMPARATOR_MASK12",
 171         "ETM_DATA_COMPARATOR_MASK13",
 172         "ETM_DATA_COMPARATOR_MASK14",
 173         "ETM_DATA_COMPARATOR_MASK15",
 174         "ETM_DATA_COMPARATOR_MASK16",
 175         "ETM_COUNTER_INITAL_VALUE1",
 176         "ETM_COUNTER_INITAL_VALUE2",
 177         "ETM_COUNTER_INITAL_VALUE3",
 178         "ETM_COUNTER_INITAL_VALUE4",
 179         "ETM_COUNTER_ENABLE1",
 180         "ETM_COUNTER_ENABLE2",
 181         "ETM_COUNTER_ENABLE3",
 182         "ETM_COUNTER_ENABLE4",
 183         "ETM_COUNTER_RELOAD_VALUE1",
 184         "ETM_COUNTER_RELOAD_VALUE2",
 185         "ETM_COUNTER_RELOAD_VALUE3",
 186         "ETM_COUNTER_RELOAD_VALUE4",
 187         "ETM_COUNTER_VALUE1",
 188         "ETM_COUNTER_VALUE2",
 189         "ETM_COUNTER_VALUE3",
 190         "ETM_COUNTER_VALUE4",
 191         "ETM_SEQUENCER_CTRL1",
 192         "ETM_SEQUENCER_CTRL2",
 193         "ETM_SEQUENCER_CTRL3",
 194         "ETM_SEQUENCER_CTRL4",
 195         "ETM_SEQUENCER_CTRL5",
 196         "ETM_SEQUENCER_CTRL6",
 197         "ETM_SEQUENCER_STATE",
 198         "ETM_EXTERNAL_OUTPUT1",
 199         "ETM_EXTERNAL_OUTPUT2",
 200         "ETM_EXTERNAL_OUTPUT3",
 201         "ETM_EXTERNAL_OUTPUT4",
 202         "ETM_CONTEXTID_COMPARATOR_VALUE1",
 203         "ETM_CONTEXTID_COMPARATOR_VALUE2",
 204         "ETM_CONTEXTID_COMPARATOR_VALUE3",
 205         "ETM_CONTEXTID_COMPARATOR_MASK"
 206 };
 207
 208 int etm_reg_arch_type = -1;
 209
 210 int etm_get_reg(reg_t *reg);
 211 int etm_set_reg(reg_t *reg, u32 value);
 212 int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
 213
 214 int etm_write_reg(reg_t *reg, u32 value);
 215 int etm_read_reg(reg_t *reg);
 216
 217 command_t *etm_cmd = NULL;
 218
 219 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 220 {
 221         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 222         reg_t *reg_list = NULL;
 223         etm_reg_t *arch_info = NULL;
 224         int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
 225         int i;
 226         u32 etm_ctrl_value;
 227
 228         /* register a register arch-type for etm registers only once */
 229         if (etm_reg_arch_type == -1)
 230                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
 231
 232         /* the actual registers are kept in two arrays */
 233         reg_list = calloc(num_regs, sizeof(reg_t));
 234         arch_info = calloc(num_regs, sizeof(etm_reg_t));
 235
 236         /* fill in values for the reg cache */
 237         reg_cache->name = "etm registers";
 238         reg_cache->next = NULL;
 239         reg_cache->reg_list = reg_list;
 240         reg_cache->num_regs = num_regs;
 241
 242         /* set up registers */
 243         for (i = 0; i < num_regs; i++)
 244         {
 245                 reg_list[i].name = etm_reg_list[i];
 246                 reg_list[i].size = 32;
 247                 reg_list[i].dirty = 0;
 248                 reg_list[i].valid = 0;
 249                 reg_list[i].bitfield_desc = NULL;
 250                 reg_list[i].num_bitfields = 0;
 251                 reg_list[i].value = calloc(1, 4);
 252                 reg_list[i].arch_info = &arch_info[i];
 253                 reg_list[i].arch_type = etm_reg_arch_type;
 254                 reg_list[i].size = etm_reg_arch_size_info[i];
 255                 arch_info[i].addr = etm_reg_arch_info[i];
 256                 arch_info[i].jtag_info = jtag_info;
 257         }
 258
 259         /* initialize some ETM control register settings */
 260         etm_get_reg(&reg_list[ETM_CTRL]);
 261         etm_ctrl_value = buf_get_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size);
 262
 263         /* clear the ETM powerdown bit (0) */
 264         etm_ctrl_value &= ~0x1;
 265
 266         /* configure port width (6:4), mode (17:16) and clocking (13) */
 267         etm_ctrl_value = (etm_ctrl_value &
 268                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 269                 | etm_ctx->portmode;
 270
 271         buf_set_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size, etm_ctrl_value);
 272         etm_store_reg(&reg_list[ETM_CTRL]);
 273
 274         /* the ETM might have an ETB connected */
 275         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 276         {
 277                 etb_t *etb = etm_ctx->capture_driver_priv;
 278
 279                 if (!etb)
 280                 {
 281                         ERROR("etb selected as etm capture driver, but no ETB configured");
 282                         return ERROR_OK;
 283                 }
 284
 285                 reg_cache->next = etb_build_reg_cache(etb);
 286
 287                 etb->reg_cache = reg_cache->next;
 288         }
 289
 290         if (etm_ctx->capture_driver->init(etm_ctx) != ERROR_OK)
 291         {
 292                 ERROR("ETM capture driver initialization failed");
 293                 exit(-1);
 294         }
 295
 296         return reg_cache;
 297 }
 298
 299 int etm_get_reg(reg_t *reg)
 300 {
 301         if (etm_read_reg(reg) != ERROR_OK)
 302         {
 303                 ERROR("BUG: error scheduling etm register read");
 304                 exit(-1);
 305         }
 306
 307         if (jtag_execute_queue() != ERROR_OK)
 308         {
 309                 ERROR("register read failed");
 310         }
 311
 312         return ERROR_OK;
 313 }
 314
 315 int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 316 {
 317         etm_reg_t *etm_reg = reg->arch_info;
 318         u8 reg_addr = etm_reg->addr & 0x7f;
 319         scan_field_t fields[3];
 320
 321         DEBUG("%i", etm_reg->addr);
 322
 323         jtag_add_end_state(TAP_RTI);
 324         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 325         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 326
 327         fields[0].device = etm_reg->jtag_info->chain_pos;
 328         fields[0].num_bits = 32;
 329         fields[0].out_value = reg->value;
 330         fields[0].out_mask = NULL;
 331         fields[0].in_value = NULL;
 332         fields[0].in_check_value = NULL;
 333         fields[0].in_check_mask = NULL;
 334         fields[0].in_handler = NULL;
 335         fields[0].in_handler_priv = NULL;
 336
 337         fields[1].device = etm_reg->jtag_info->chain_pos;
 338         fields[1].num_bits = 7;
 339         fields[1].out_value = malloc(1);
 340         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 341         fields[1].out_mask = NULL;
 342         fields[1].in_value = NULL;
 343         fields[1].in_check_value = NULL;
 344         fields[1].in_check_mask = NULL;
 345         fields[1].in_handler = NULL;
 346         fields[1].in_handler_priv = NULL;
 347
 348         fields[2].device = etm_reg->jtag_info->chain_pos;
 349         fields[2].num_bits = 1;
 350         fields[2].out_value = malloc(1);
 351         buf_set_u32(fields[2].out_value, 0, 1, 0);
 352         fields[2].out_mask = NULL;
 353         fields[2].in_value = NULL;
 354         fields[2].in_check_value = NULL;
 355         fields[2].in_check_mask = NULL;
 356         fields[2].in_handler = NULL;
 357         fields[2].in_handler_priv = NULL;
 358
 359         jtag_add_dr_scan(3, fields, -1);
 360
 361         fields[0].in_value = reg->value;
 362         jtag_set_check_value(fields+0, check_value, check_mask, NULL);
 363
 364         jtag_add_dr_scan(3, fields, -1);
 365
 366         free(fields[1].out_value);
 367         free(fields[2].out_value);
 368
 369         return ERROR_OK;
 370 }
 371
 372 int etm_read_reg(reg_t *reg)
 373 {
 374         return etm_read_reg_w_check(reg, NULL, NULL);
 375 }
 376
 377 int etm_set_reg(reg_t *reg, u32 value)
 378 {
 379         if (etm_write_reg(reg, value) != ERROR_OK)
 380         {
 381                 ERROR("BUG: error scheduling etm register write");
 382                 exit(-1);
 383         }
 384
 385         buf_set_u32(reg->value, 0, reg->size, value);
 386         reg->valid = 1;
 387         reg->dirty = 0;
 388
 389         return ERROR_OK;
 390 }
 391
 392 int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
 393 {
 394         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 395
 396         if (jtag_execute_queue() != ERROR_OK)
 397         {
 398                 ERROR("register write failed");
 399                 exit(-1);
 400         }
 401         return ERROR_OK;
 402 }
 403
 404 int etm_write_reg(reg_t *reg, u32 value)
 405 {
 406         etm_reg_t *etm_reg = reg->arch_info;
 407         u8 reg_addr = etm_reg->addr & 0x7f;
 408         scan_field_t fields[3];
 409
 410         DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
 411
 412         jtag_add_end_state(TAP_RTI);
 413         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 414         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 415
 416         fields[0].device = etm_reg->jtag_info->chain_pos;
 417         fields[0].num_bits = 32;
 418         fields[0].out_value = malloc(4);
 419         buf_set_u32(fields[0].out_value, 0, 32, value);
 420         fields[0].out_mask = NULL;
 421         fields[0].in_value = NULL;
 422         fields[0].in_check_value = NULL;
 423         fields[0].in_check_mask = NULL;
 424         fields[0].in_handler = NULL;
 425         fields[0].in_handler_priv = NULL;
 426
 427         fields[1].device = etm_reg->jtag_info->chain_pos;
 428         fields[1].num_bits = 7;
 429         fields[1].out_value = malloc(1);
 430         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 431         fields[1].out_mask = NULL;
 432         fields[1].in_value = NULL;
 433         fields[1].in_check_value = NULL;
 434         fields[1].in_check_mask = NULL;
 435         fields[1].in_handler = NULL;
 436         fields[1].in_handler_priv = NULL;
 437
 438         fields[2].device = etm_reg->jtag_info->chain_pos;
 439         fields[2].num_bits = 1;
 440         fields[2].out_value = malloc(1);
 441         buf_set_u32(fields[2].out_value, 0, 1, 1);
 442         fields[2].out_mask = NULL;
 443         fields[2].in_value = NULL;
 444         fields[2].in_check_value = NULL;
 445         fields[2].in_check_mask = NULL;
 446         fields[2].in_handler = NULL;
 447         fields[2].in_handler_priv = NULL;
 448
 449         jtag_add_dr_scan(3, fields, -1);
 450
 451         free(fields[0].out_value);
 452         free(fields[1].out_value);
 453         free(fields[2].out_value);
 454
 455         return ERROR_OK;
 456 }
 457
 458 int etm_store_reg(reg_t *reg)
 459 {
 460         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 461 }
 462
 463 /* ETM trace analysis functionality
 464  *
 465  */
 466 extern etm_capture_driver_t etb_capture_driver;
 467 extern etm_capture_driver_t etm_dummy_capture_driver;
 468 #if BUILD_OOCD_TRACE == 1
 469 extern etm_capture_driver_t oocd_trace_capture_driver;
 470 #endif
 471
 472 etm_capture_driver_t *etm_capture_drivers[] =
 473 {
 474         &etb_capture_driver,
 475         &etm_dummy_capture_driver,
 476 #if BUILD_OOCD_TRACE == 1
 477         &oocd_trace_capture_driver,
 478 #endif
 479         NULL
 480 };
 481
 482 char *etmv1v1_branch_reason_strings[] =
 483 {
 484         "normal PC change",
 485         "tracing enabled",
 486         "trace restarted after overflow",
 487         "exit from debug",
 488         "periodic synchronization",
 489         "reserved",
 490         "reserved",
 491         "reserved",
 492 };
 493
 494 int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 495 {
 496         int i;
 497         int section = -1;
 498         u32 size_read;
 499         u32 opcode;
 500         int retval;
 501
 502         if (!ctx->image)
 503                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 504
 505         /* search for the section the current instruction belongs to */
 506         for (i = 0; i < ctx->image->num_sections; i++)
 507         {
 508                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 509                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 510                 {
 511                         section = i;
 512                         break;
 513                 }
 514         }
 515
 516         if (section == -1)
 517         {
 518                 /* current instruction couldn't be found in the image */
 519                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 520         }
 521
 522         if (ctx->core_state == ARMV4_5_STATE_ARM)
 523         {
 524                 u8 buf[4];
 525                 if ((retval = image_read_section(ctx->image, section,
 526                         ctx->current_pc - ctx->image->sections[section].base_address,
 527                         4, buf, &size_read)) != ERROR_OK)
 528                 {
 529                         ERROR("error while reading instruction: %i", retval);
 530                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 531                 }
 532                 opcode = target_buffer_get_u32(ctx->target, buf);
 533                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 534         }
 535         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 536         {
 537                 u8 buf[2];
 538                 if ((retval = image_read_section(ctx->image, section,
 539                         ctx->current_pc - ctx->image->sections[section].base_address,
 540                         2, buf, &size_read)) != ERROR_OK)
 541                 {
 542                         ERROR("error while reading instruction: %i", retval);
 543                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 544                 }
 545                 opcode = target_buffer_get_u16(ctx->target, buf);
 546                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 547         }
 548         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 549         {
 550                 ERROR("BUG: tracing of jazelle code not supported");
 551                 exit(-1);
 552         }
 553         else
 554         {
 555                 ERROR("BUG: unknown core state encountered");
 556                 exit(-1);
 557         }
 558
 559         return ERROR_OK;
 560 }
 561
 562 int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
 563 {
 564         while (ctx->data_index < ctx->trace_depth)
 565         {
 566                 /* if the caller specified an address packet offset, skip until the
 567                  * we reach the n-th cycle marked with tracesync */
 568                 if (apo > 0)
 569                 {
 570                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 571                                 apo--;
 572
 573                         if (apo > 0)
 574                         {
 575                                 ctx->data_index++;
 576                                 ctx->data_half = 0;
 577                         }
 578                         continue;
 579                 }
 580
 581                 /* no tracedata output during a TD cycle
 582                  * or in a trigger cycle */
 583                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 584                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 585                 {
 586                         ctx->data_index++;
 587                         ctx->data_half = 0;
 588                         continue;
 589                 }
 590
 591                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 592                 {
 593                         if (ctx->data_half == 0)
 594                         {
 595                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 596                                 ctx->data_half = 1;
 597                         }
 598                         else
 599                         {
 600                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 601                                 ctx->data_half = 0;
 602                                 ctx->data_index++;
 603                         }
 604                 }
 605                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 606                 {
 607                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 608                         ctx->data_index++;
 609                 }
 610                 else
 611                 {
 612                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 613                         if (ctx->data_index > (ctx->trace_depth - 2))
 614                                 return -1;
 615
 616                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 617                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 618                         ctx->data_index += 2;
 619                 }
 620
 621                 return 0;
 622         }
 623
 624         return -1;
 625 }
 626
 627 int etmv1_branch_address(etm_context_t *ctx)
 628 {
 629         int retval;
 630         u8 packet;
 631         int shift = 0;
 632         int apo;
 633         int i;
 634
 635         /* quit analysis if less than two cycles are left in the trace
 636          * because we can't extract the APO */
 637         if (ctx->data_index > (ctx->trace_depth - 2))
 638                 return -1;
 639
 640         /* a BE could be output during an APO cycle, skip the current
 641          * and continue with the new one */
 642         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 643                 return 1;
 644         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 645                 return 2;
 646
 647         /* address packet offset encoded in the next two cycles' pipestat bits */
 648         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 649         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 650
 651         /* count number of tracesync cycles between current pipe_index and data_index
 652          * i.e. the number of tracesyncs that data_index already passed by
 653          * to subtract them from the APO */
 654         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 655         {
 656                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 657                         apo--;
 658         }
 659
 660         /* extract up to four 7-bit packets */
 661         do {
 662                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 663                         return -1;
 664                 ctx->last_branch &= ~(0x7f << shift);
 665                 ctx->last_branch |= (packet & 0x7f) << shift;
 666                 shift += 7;
 667         } while ((packet & 0x80) && (shift < 28));
 668
 669         /* one last packet holding 4 bits of the address, plus the branch reason code */
 670         if ((shift == 28) && (packet & 0x80))
 671         {
 672                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 673                         return -1;
 674                 ctx->last_branch &= 0x0fffffff;
 675                 ctx->last_branch |= (packet & 0x0f) << 28;
 676                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 677                 shift += 4;
 678         }
 679         else
 680         {
 681                 ctx->last_branch_reason = 0;
 682         }
 683
 684         if (shift == 32)
 685         {
 686                 ctx->pc_ok = 1;
 687         }
 688
 689         /* if a full address was output, we might have branched into Jazelle state */
 690         if ((shift == 32) && (packet & 0x80))
 691         {
 692                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 693         }
 694         else
 695         {
 696                 /* if we didn't branch into Jazelle state, the current processor state is
 697                  * encoded in bit 0 of the branch target address */
 698                 if (ctx->last_branch & 0x1)
 699                 {
 700                         ctx->core_state = ARMV4_5_STATE_THUMB;
 701                         ctx->last_branch &= ~0x1;
 702                 }
 703                 else
 704                 {
 705                         ctx->core_state = ARMV4_5_STATE_ARM;
 706                         ctx->last_branch &= ~0x3;
 707                 }
 708         }
 709
 710         return 0;
 711 }
 712
 713 int etmv1_data(etm_context_t *ctx, int size, u32 *data)
 714 {
 715         int j;
 716         u8 buf[4];
 717         int retval;
 718
 719         for (j = 0; j < size; j++)
 720         {
 721                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 722                         return -1;
 723         }
 724
 725         if (size == 8)
 726                 ERROR("TODO: add support for 64-bit values");
 727         else if (size == 4)
 728                 *data = target_buffer_get_u32(ctx->target, buf);
 729         else if (size == 2)
 730                 *data = target_buffer_get_u16(ctx->target, buf);
 731         else if (size == 1)
 732                 *data = buf[0];
 733
 734         return 0;
 735 }
 736
 737 int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 738 {
 739         int retval;
 740         arm_instruction_t instruction;
 741
 742         /* read the trace data if it wasn't read already */
 743         if (ctx->trace_depth == 0)
 744                 ctx->capture_driver->read_trace(ctx);
 745
 746         /* start at the beginning of the captured trace */
 747         ctx->pipe_index = 0;
 748         ctx->data_index = 0;
 749         ctx->data_half = 0;
 750
 751         /* neither the PC nor the data pointer are valid */
 752         ctx->pc_ok = 0;
 753         ctx->ptr_ok = 0;
 754
 755         while (ctx->pipe_index < ctx->trace_depth)
 756         {
 757                 u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 758                 u32 next_pc = ctx->current_pc;
 759                 u32 old_data_index = ctx->data_index;
 760                 u32 old_data_half = ctx->data_half;
 761                 u32 old_index = ctx->pipe_index;
 762                 u32 last_instruction = ctx->last_instruction;
 763                 u32 cycles = 0;
 764                 int current_pc_ok = ctx->pc_ok;
 765
 766                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 767                 {
 768                         command_print(cmd_ctx, "--- trigger ---");
 769                 }
 770
 771                 /* instructions execute in IE/D or BE/D cycles */
 772                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 773                         ctx->last_instruction = ctx->pipe_index;
 774
 775                 /* if we don't have a valid pc skip until we reach an indirect branch */
 776                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 777                 {
 778                         ctx->pipe_index++;
 779                         continue;
 780                 }
 781
 782                 /* any indirect branch could have interrupted instruction flow
 783                  * - the branch reason code could indicate a trace discontinuity
 784                  * - a branch to the exception vectors indicates an exception
 785                  */
 786                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 787                 {
 788                         /* backup current data index, to be able to consume the branch address
 789                          * before examining data address and values
 790                          */
 791                         old_data_index = ctx->data_index;
 792                         old_data_half = ctx->data_half;
 793
 794                         ctx->last_instruction = ctx->pipe_index;
 795
 796                         if ((retval = etmv1_branch_address(ctx)) != 0)
 797                         {
 798                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 799                                  * quit analysing the trace */
 800                                 if (retval < 0)
 801                                         break;
 802
 803                                 /* a positive return values means the current branch was abandoned,
 804                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 805                                  */
 806                                 WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 807                                 ctx->pipe_index += retval;
 808                                 continue;
 809                         }
 810
 811                         /* skip over APO cycles */
 812                         ctx->pipe_index += 2;
 813
 814                         switch (ctx->last_branch_reason)
 815                         {
 816                                 case 0x0:       /* normal PC change */
 817                                         next_pc = ctx->last_branch;
 818                                         break;
 819                                 case 0x1:       /* tracing enabled */
 820                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
 821                                         ctx->current_pc = ctx->last_branch;
 822                                         ctx->pipe_index++;
 823                                         continue;
 824                                         break;
 825                                 case 0x2:       /* trace restarted after FIFO overflow */
 826                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
 827                                         ctx->current_pc = ctx->last_branch;
 828                                         ctx->pipe_index++;
 829                                         continue;
 830                                         break;
 831                                 case 0x3:       /* exit from debug state */
 832                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
 833                                         ctx->current_pc = ctx->last_branch;
 834                                         ctx->pipe_index++;
 835                                         continue;
 836                                         break;
 837                                 case 0x4:       /* periodic synchronization point */
 838                                         next_pc = ctx->last_branch;
 839                                         /* if we had no valid PC prior to this synchronization point,
 840                                          * we have to move on with the next trace cycle
 841                                          */
 842                                         if (!current_pc_ok)
 843                                         {
 844                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
 845                                                 ctx->current_pc = next_pc;
 846                                                 ctx->pipe_index++;
 847                                                 continue;
 848                                         }
 849                                         break;
 850                                 default:        /* reserved */
 851                                         ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
 852                                         exit(-1);
 853                                         break;
 854                         }
 855
 856                         /* if we got here the branch was a normal PC change
 857                          * (or a periodic synchronization point, which means the same for that matter)
 858                          * if we didn't accquire a complete PC continue with the next cycle
 859                          */
 860                         if (!ctx->pc_ok)
 861                                 continue;
 862
 863                         /* indirect branch to the exception vector means an exception occured */
 864                         if (((ctx->last_branch >= 0x0) && (ctx->last_branch <= 0x20))
 865                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 866                         {
 867                                 if ((ctx->last_branch & 0xff) == 0x10)
 868                                 {
 869                                         command_print(cmd_ctx, "data abort");
 870                                 }
 871                                 else
 872                                 {
 873                                         command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
 874                                         ctx->current_pc = ctx->last_branch;
 875                                         ctx->pipe_index++;
 876                                         continue;
 877                                 }
 878                         }
 879                 }
 880
 881                 /* an instruction was executed (or not, depending on the condition flags)
 882                  * retrieve it from the image for displaying */
 883                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
 884                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
 885                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
 886                 {
 887                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
 888                         {
 889                                 /* can't continue tracing with no image available */
 890                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
 891                                 {
 892                                         return retval;
 893                                 }
 894                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
 895                                 {
 896                                         /* TODO: handle incomplete images
 897                                          * for now we just quit the analsysis*/
 898                                         return retval;
 899                                 }
 900                         }
 901
 902                         cycles = old_index - last_instruction;
 903                 }
 904
 905                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
 906                 {
 907                         u32 new_data_index = ctx->data_index;
 908                         u32 new_data_half = ctx->data_half;
 909
 910                         /* in case of a branch with data, the branch target address was consumed before
 911                          * we temporarily go back to the saved data index */
 912                         if (pipestat == STAT_BD)
 913                         {
 914                                 ctx->data_index = old_data_index;
 915                                 ctx->data_half = old_data_half;
 916                         }
 917
 918                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
 919                         {
 920                                 u8 packet;
 921                                 int shift = 0;
 922
 923                                 do {
 924                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 925                                                 return ERROR_ETM_ANALYSIS_FAILED;
 926                                         ctx->last_ptr &= ~(0x7f << shift);
 927                                         ctx->last_ptr |= (packet & 0x7f) << shift;
 928                                         shift += 7;
 929                                 } while ((packet & 0x80) && (shift < 32));
 930
 931                                 if (shift >= 32)
 932                                         ctx->ptr_ok = 1;
 933
 934                                 if (ctx->ptr_ok)
 935                                 {
 936                                         command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
 937                                 }
 938                         }
 939
 940                         if (ctx->tracemode & ETMV1_TRACE_DATA)
 941                         {
 942                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
 943                                 {
 944                                         int i;
 945                                         for (i = 0; i < 16; i++)
 946                                         {
 947                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
 948                                                 {
 949                                                         u32 data;
 950                                                         if (etmv1_data(ctx, 4, &data) != 0)
 951                                                                 return ERROR_ETM_ANALYSIS_FAILED;
 952                                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 953                                                 }
 954                                         }
 955                                 }
 956                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
 957                                 {
 958                                         u32 data;
 959                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
 960                                                 return ERROR_ETM_ANALYSIS_FAILED;
 961                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 962                                 }
 963                         }
 964
 965                         /* restore data index after consuming BD address and data */
 966                         if (pipestat == STAT_BD)
 967                         {
 968                                 ctx->data_index = new_data_index;
 969                                 ctx->data_half = new_data_half;
 970                         }
 971                 }
 972
 973                 /* adjust PC */
 974                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 975                 {
 976                         if (((instruction.type == ARM_B) ||
 977                                 (instruction.type == ARM_BL) ||
 978                                 (instruction.type == ARM_BLX)) &&
 979                                 (instruction.info.b_bl_bx_blx.target_address != -1))
 980                         {
 981                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
 982                         }
 983                         else
 984                         {
 985                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 986                         }
 987                 }
 988                 else if (pipestat == STAT_IN)
 989                 {
 990                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 991                 }
 992
 993                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
 994                 {
 995                         char cycles_text[32] = "";
 996
 997                         /* if the trace was captured with cycle accurate tracing enabled,
 998                          * output the number of cycles since the last executed instruction
 999                          */
1000                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1001                         {
1002                                 snprintf(cycles_text, 32, " (%i %s)",
1003                                         cycles,
1004                                         (cycles == 1) ? "cycle" : "cycles");
1005                         }
1006
1007                         command_print(cmd_ctx, "%s%s%s",
1008                                 instruction.text,
1009                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1010                                 cycles_text);
1011
1012                         ctx->current_pc = next_pc;
1013
1014                         /* packets for an instruction don't start on or before the preceding
1015                          * functional pipestat (i.e. other than WT or TD)
1016                          */
1017                         if (ctx->data_index <= ctx->pipe_index)
1018                         {
1019                                 ctx->data_index = ctx->pipe_index + 1;
1020                                 ctx->data_half = 0;
1021                         }
1022                 }
1023
1024                 ctx->pipe_index += 1;
1025         }
1026
1027         return ERROR_OK;
1028 }
1029
1030 int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1031 {
1032         target_t *target;
1033         armv4_5_common_t *armv4_5;
1034         arm7_9_common_t *arm7_9;
1035         etmv1_tracemode_t tracemode;
1036
1037         target = get_current_target(cmd_ctx);
1038
1039         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1040         {
1041                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1042                 return ERROR_OK;
1043         }
1044
1045         if (!arm7_9->etm_ctx)
1046         {
1047                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1048                 return ERROR_OK;
1049         }
1050
1051         tracemode = arm7_9->etm_ctx->tracemode;
1052
1053         if (argc == 4)
1054         {
1055                 if (strcmp(args[0], "none") == 0)
1056                 {
1057                         tracemode = ETMV1_TRACE_NONE;
1058                 }
1059                 else if (strcmp(args[0], "data") == 0)
1060                 {
1061                         tracemode = ETMV1_TRACE_DATA;
1062                 }
1063                 else if (strcmp(args[0], "address") == 0)
1064                 {
1065                         tracemode = ETMV1_TRACE_ADDR;
1066                 }
1067                 else if (strcmp(args[0], "all") == 0)
1068                 {
1069                         tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1070                 }
1071                 else
1072                 {
1073                         command_print(cmd_ctx, "invalid option '%s'", args[0]);
1074                         return ERROR_OK;
1075                 }
1076
1077                 switch (strtol(args[1], NULL, 0))
1078                 {
1079                         case 0:
1080                                 tracemode |= ETMV1_CONTEXTID_NONE;
1081                                 break;
1082                         case 8:
1083                                 tracemode |= ETMV1_CONTEXTID_8;
1084                                 break;
1085                         case 16:
1086                                 tracemode |= ETMV1_CONTEXTID_16;
1087                                 break;
1088                         case 32:
1089                                 tracemode |= ETMV1_CONTEXTID_32;
1090                                 break;
1091                         default:
1092                                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1093                                 return ERROR_OK;
1094                 }
1095
1096                 if (strcmp(args[2], "enable") == 0)
1097                 {
1098                         tracemode |= ETMV1_CYCLE_ACCURATE;
1099                 }
1100                 else if (strcmp(args[2], "disable") == 0)
1101                 {
1102                         tracemode |= 0;
1103                 }
1104                 else
1105                 {
1106                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1107                         return ERROR_OK;
1108                 }
1109
1110                 if (strcmp(args[3], "enable") == 0)
1111                 {
1112                         tracemode |= ETMV1_BRANCH_OUTPUT;
1113                 }
1114                 else if (strcmp(args[3], "disable") == 0)
1115                 {
1116                         tracemode |= 0;
1117                 }
1118                 else
1119                 {
1120                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1121                         return ERROR_OK;
1122                 }
1123         }
1124         else if (argc != 0)
1125         {
1126                 command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1127                 return ERROR_OK;
1128         }
1129
1130         command_print(cmd_ctx, "current tracemode configuration:");
1131
1132         switch (tracemode & ETMV1_TRACE_MASK)
1133         {
1134                 case ETMV1_TRACE_NONE:
1135                         command_print(cmd_ctx, "data tracing: none");
1136                         break;
1137                 case ETMV1_TRACE_DATA:
1138                         command_print(cmd_ctx, "data tracing: data only");
1139                         break;
1140                 case ETMV1_TRACE_ADDR:
1141                         command_print(cmd_ctx, "data tracing: address only");
1142                         break;
1143                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1144                         command_print(cmd_ctx, "data tracing: address and data");
1145                         break;
1146         }
1147
1148         switch (tracemode & ETMV1_CONTEXTID_MASK)
1149         {
1150                 case ETMV1_CONTEXTID_NONE:
1151                         command_print(cmd_ctx, "contextid tracing: none");
1152                         break;
1153                 case ETMV1_CONTEXTID_8:
1154                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1155                         break;
1156                 case ETMV1_CONTEXTID_16:
1157                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1158                         break;
1159                 case ETMV1_CONTEXTID_32:
1160                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1161                         break;
1162         }
1163
1164         if (tracemode & ETMV1_CYCLE_ACCURATE)
1165         {
1166                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1167         }
1168         else
1169         {
1170                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1171         }
1172
1173         if (tracemode & ETMV1_BRANCH_OUTPUT)
1174         {
1175                 command_print(cmd_ctx, "full branch address output enabled");
1176         }
1177         else
1178         {
1179                 command_print(cmd_ctx, "full branch address output disabled");
1180         }
1181
1182         /* only update ETM_CTRL register if tracemode changed */
1183         if (arm7_9->etm_ctx->tracemode != tracemode)
1184         {
1185                 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1186
1187                 etm_get_reg(etm_ctrl_reg);
1188
1189                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1190                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1191                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1192                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1193                 etm_store_reg(etm_ctrl_reg);
1194
1195                 arm7_9->etm_ctx->tracemode = tracemode;
1196
1197                 /* invalidate old trace data */
1198                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1199                 if (arm7_9->etm_ctx->trace_depth > 0)
1200                 {
1201                         free(arm7_9->etm_ctx->trace_data);
1202                         arm7_9->etm_ctx->trace_data = NULL;
1203                 }
1204                 arm7_9->etm_ctx->trace_depth = 0;
1205         }
1206
1207         return ERROR_OK;
1208 }
1209
1210 int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1211 {
1212         target_t *target;
1213         armv4_5_common_t *armv4_5;
1214         arm7_9_common_t *arm7_9;
1215         etm_portmode_t portmode = 0x0;
1216         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1217         int i;
1218
1219         if (argc != 5)
1220         {
1221                 ERROR("incomplete 'etm config <target> <port_width> <port_mode> <clocking> <capture_driver>' command");
1222                 exit(-1);
1223         }
1224
1225         target = get_target_by_num(strtoul(args[0], NULL, 0));
1226
1227         if (!target)
1228         {
1229                 ERROR("target number '%s' not defined", args[0]);
1230                 exit(-1);
1231         }
1232
1233         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1234         {
1235                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1236                 return ERROR_OK;
1237         }
1238
1239         switch (strtoul(args[1], NULL, 0))
1240         {
1241                 case 4:
1242                         portmode |= ETM_PORT_4BIT;
1243                         break;
1244                 case 8:
1245                         portmode |= ETM_PORT_8BIT;
1246                         break;
1247                 case 16:
1248                         portmode |= ETM_PORT_16BIT;
1249                         break;
1250                 default:
1251                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1252                         return ERROR_OK;
1253         }
1254
1255         if (strcmp("normal", args[2]) == 0)
1256         {
1257                 portmode |= ETM_PORT_NORMAL;
1258         }
1259         else if (strcmp("multiplexed", args[2]) == 0)
1260         {
1261                 portmode |= ETM_PORT_MUXED;
1262         }
1263         else if (strcmp("demultiplexed", args[2]) == 0)
1264         {
1265                 portmode |= ETM_PORT_DEMUXED;
1266         }
1267         else
1268         {
1269                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1270                 return ERROR_OK;
1271         }
1272
1273         if (strcmp("half", args[3]) == 0)
1274         {
1275                 portmode |= ETM_PORT_HALF_CLOCK;
1276         }
1277         else if (strcmp("full", args[3]) == 0)
1278         {
1279                 portmode |= ETM_PORT_FULL_CLOCK;
1280         }
1281         else
1282         {
1283                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1284                 return ERROR_OK;
1285         }
1286
1287         for (i=0; etm_capture_drivers[i]; i++)
1288         {
1289                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1290                 {
1291                         if (etm_capture_drivers[i]->register_commands(cmd_ctx) != ERROR_OK)
1292                         {
1293                                 free(etm_ctx);
1294                                 exit(-1);
1295                         }
1296
1297                         etm_ctx->capture_driver = etm_capture_drivers[i];
1298
1299                         break;
1300                 }
1301         }
1302
1303         if (!etm_capture_drivers[i])
1304         {
1305                 /* no supported capture driver found, don't register an ETM */
1306                 free(etm_ctx);
1307                 ERROR("trace capture driver '%s' not found", args[4]);
1308                 return ERROR_OK;
1309         }
1310
1311         etm_ctx->target = target;
1312         etm_ctx->trigger_percent = 50;
1313         etm_ctx->trace_data = NULL;
1314         etm_ctx->trace_depth = 0;
1315         etm_ctx->portmode = portmode;
1316         etm_ctx->tracemode = 0x0;
1317         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1318         etm_ctx->image = NULL;
1319         etm_ctx->pipe_index = 0;
1320         etm_ctx->data_index = 0;
1321         etm_ctx->current_pc = 0x0;
1322         etm_ctx->pc_ok = 0;
1323         etm_ctx->last_branch = 0x0;
1324         etm_ctx->last_branch_reason = 0x0;
1325         etm_ctx->last_ptr = 0x0;
1326         etm_ctx->ptr_ok = 0x0;
1327         etm_ctx->context_id = 0x0;
1328         etm_ctx->last_instruction = 0;
1329
1330         arm7_9->etm_ctx = etm_ctx;
1331
1332         etm_register_user_commands(cmd_ctx);
1333
1334         return ERROR_OK;
1335 }
1336
1337 int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1338 {
1339         target_t *target;
1340         armv4_5_common_t *armv4_5;
1341         arm7_9_common_t *arm7_9;
1342         reg_t *etm_config_reg;
1343         reg_t *etm_sys_config_reg;
1344
1345         int max_port_size;
1346
1347         target = get_current_target(cmd_ctx);
1348
1349         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1350         {
1351                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1352                 return ERROR_OK;
1353         }
1354
1355         if (!arm7_9->etm_ctx)
1356         {
1357                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1358                 return ERROR_OK;
1359         }
1360
1361         etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
1362         etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
1363
1364         etm_get_reg(etm_config_reg);
1365         command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
1366         command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
1367         command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
1368         command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
1369         command_print(cmd_ctx, "sequencer %spresent",
1370                         (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
1371         command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
1372         command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
1373         command_print(cmd_ctx, "FIFO full %spresent",
1374                         (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
1375         command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
1376
1377         etm_get_reg(etm_sys_config_reg);
1378
1379         switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1380         {
1381                 case 0:
1382                         max_port_size = 4;
1383                         break;
1384                 case 1:
1385                         max_port_size = 8;
1386                         break;
1387                 case 2:
1388                         max_port_size = 16;
1389                         break;
1390                 default:
1391                         ERROR("Illegal max_port_size");
1392                         exit(-1);
1393         }
1394         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1395
1396         command_print(cmd_ctx, "half-rate clocking %ssupported",
1397                         (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1398         command_print(cmd_ctx, "full-rate clocking %ssupported",
1399                         (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1400         command_print(cmd_ctx, "normal trace format %ssupported",
1401                         (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1402         command_print(cmd_ctx, "multiplex trace format %ssupported",
1403                         (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1404         command_print(cmd_ctx, "demultiplex trace format %ssupported",
1405                         (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1406         command_print(cmd_ctx, "FIFO full %ssupported",
1407                         (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1408
1409         return ERROR_OK;
1410 }
1411
1412 int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1413 {
1414         target_t *target;
1415         armv4_5_common_t *armv4_5;
1416         arm7_9_common_t *arm7_9;
1417         trace_status_t trace_status;
1418
1419         target = get_current_target(cmd_ctx);
1420
1421         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1422         {
1423                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1424                 return ERROR_OK;
1425         }
1426
1427         if (!arm7_9->etm_ctx)
1428         {
1429                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1430                 return ERROR_OK;
1431         }
1432
1433         trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1434
1435         if (trace_status == TRACE_IDLE)
1436         {
1437                 command_print(cmd_ctx, "tracing is idle");
1438         }
1439         else
1440         {
1441                 static char *completed = " completed";
1442                 static char *running = " is running";
1443                 static char *overflowed = ", trace overflowed";
1444                 static char *triggered = ", trace triggered";
1445
1446                 command_print(cmd_ctx, "trace collection%s%s%s",
1447                         (trace_status & TRACE_RUNNING) ? running : completed,
1448                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1449                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1450
1451                 if (arm7_9->etm_ctx->trace_depth > 0)
1452                 {
1453                         command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
1454                 }
1455         }
1456
1457         return ERROR_OK;
1458 }
1459
1460 int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1461 {
1462         target_t *target;
1463         armv4_5_common_t *armv4_5;
1464         arm7_9_common_t *arm7_9;
1465         etm_context_t *etm_ctx;
1466
1467         if (argc < 1)
1468         {
1469                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1470                 return ERROR_OK;
1471         }
1472
1473         target = get_current_target(cmd_ctx);
1474
1475         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1476         {
1477                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1478                 return ERROR_OK;
1479         }
1480
1481         if (!(etm_ctx = arm7_9->etm_ctx))
1482         {
1483                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1484                 return ERROR_OK;
1485         }
1486
1487         if (etm_ctx->image)
1488         {
1489                 image_close(etm_ctx->image);
1490                 free(etm_ctx->image);
1491                 command_print(cmd_ctx, "previously loaded image found and closed");
1492         }
1493
1494         etm_ctx->image = malloc(sizeof(image_t));
1495         etm_ctx->image->base_address_set = 0;
1496         etm_ctx->image->start_address_set = 0;
1497
1498         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1499         if (argc >= 2)
1500         {
1501                 etm_ctx->image->base_address_set = 1;
1502                 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1503         }
1504         else
1505         {
1506                 etm_ctx->image->base_address_set = 0;
1507         }
1508
1509         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1510         {
1511                 free(etm_ctx->image);
1512                 etm_ctx->image = NULL;
1513                 return ERROR_OK;
1514         }
1515
1516         return ERROR_OK;
1517 }
1518
1519 int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1520 {
1521         fileio_t file;
1522         target_t *target;
1523         armv4_5_common_t *armv4_5;
1524         arm7_9_common_t *arm7_9;
1525         etm_context_t *etm_ctx;
1526         int i;
1527
1528         if (argc != 1)
1529         {
1530                 command_print(cmd_ctx, "usage: etm dump <file>");
1531                 return ERROR_OK;
1532         }
1533
1534         target = get_current_target(cmd_ctx);
1535
1536         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1537         {
1538                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1539                 return ERROR_OK;
1540         }
1541
1542         if (!(etm_ctx = arm7_9->etm_ctx))
1543         {
1544                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1545                 return ERROR_OK;
1546         }
1547
1548         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1549         {
1550                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1551                 return ERROR_OK;
1552         }
1553
1554         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1555         {
1556                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1557                 command_print(cmd_ctx, "trace capture not completed");
1558                 return ERROR_OK;
1559         }
1560
1561         /* read the trace data if it wasn't read already */
1562         if (etm_ctx->trace_depth == 0)
1563                 etm_ctx->capture_driver->read_trace(etm_ctx);
1564
1565         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1566         {
1567                 return ERROR_OK;
1568         }
1569
1570         fileio_write_u32(&file, etm_ctx->capture_status);
1571         fileio_write_u32(&file, etm_ctx->portmode);
1572         fileio_write_u32(&file, etm_ctx->tracemode);
1573         fileio_write_u32(&file, etm_ctx->trace_depth);
1574
1575         for (i = 0; i < etm_ctx->trace_depth; i++)
1576         {
1577                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1578                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1579                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1580         }
1581
1582         fileio_close(&file);
1583
1584         return ERROR_OK;
1585 }
1586
1587 int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1588 {
1589         fileio_t file;
1590         target_t *target;
1591         armv4_5_common_t *armv4_5;
1592         arm7_9_common_t *arm7_9;
1593         etm_context_t *etm_ctx;
1594         int i;
1595
1596         if (argc != 1)
1597         {
1598                 command_print(cmd_ctx, "usage: etm load <file>");
1599                 return ERROR_OK;
1600         }
1601
1602         target = get_current_target(cmd_ctx);
1603
1604         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1605         {
1606                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1607                 return ERROR_OK;
1608         }
1609
1610         if (!(etm_ctx = arm7_9->etm_ctx))
1611         {
1612                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1613                 return ERROR_OK;
1614         }
1615
1616         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1617         {
1618                 command_print(cmd_ctx, "trace capture running, stop first");
1619                 return ERROR_OK;
1620         }
1621
1622         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1623         {
1624                 return ERROR_OK;
1625         }
1626
1627         if (file.size % 4)
1628         {
1629                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1630                 return ERROR_OK;
1631         }
1632
1633         if (etm_ctx->trace_depth > 0)
1634         {
1635                 free(etm_ctx->trace_data);
1636         }
1637
1638         fileio_read_u32(&file, &etm_ctx->capture_status);
1639         fileio_read_u32(&file, &etm_ctx->portmode);
1640         fileio_read_u32(&file, &etm_ctx->tracemode);
1641         fileio_read_u32(&file, &etm_ctx->trace_depth);
1642
1643         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1644
1645         for (i = 0; i < etm_ctx->trace_depth; i++)
1646         {
1647                 u32 pipestat, packet, flags;
1648                 fileio_read_u32(&file, &pipestat);
1649                 fileio_read_u32(&file, &packet);
1650                 fileio_read_u32(&file, &flags);
1651                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1652                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1653                 etm_ctx->trace_data[i].flags = flags;
1654         }
1655
1656         fileio_close(&file);
1657
1658         return ERROR_OK;
1659 }
1660
1661 int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1662 {
1663         target_t *target;
1664         armv4_5_common_t *armv4_5;
1665         arm7_9_common_t *arm7_9;
1666         etm_context_t *etm_ctx;
1667
1668         target = get_current_target(cmd_ctx);
1669
1670         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1671         {
1672                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1673                 return ERROR_OK;
1674         }
1675
1676         if (!(etm_ctx = arm7_9->etm_ctx))
1677         {
1678                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1679                 return ERROR_OK;
1680         }
1681
1682         if (argc > 0)
1683         {
1684                 u32 new_value = strtoul(args[0], NULL, 0);
1685
1686                 if ((new_value < 2) || (new_value > 100))
1687                 {
1688                         command_print(cmd_ctx, "valid settings are 2% to 100%");
1689                 }
1690                 else
1691                 {
1692                         etm_ctx->trigger_percent = new_value;
1693                 }
1694         }
1695
1696         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
1697
1698         return ERROR_OK;
1699 }
1700
1701 int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1702 {
1703         target_t *target;
1704         armv4_5_common_t *armv4_5;
1705         arm7_9_common_t *arm7_9;
1706         etm_context_t *etm_ctx;
1707         reg_t *etm_ctrl_reg;
1708
1709         target = get_current_target(cmd_ctx);
1710
1711         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1712         {
1713                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1714                 return ERROR_OK;
1715         }
1716
1717         if (!(etm_ctx = arm7_9->etm_ctx))
1718         {
1719                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1720                 return ERROR_OK;
1721         }
1722
1723         /* invalidate old tracing data */
1724         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1725         if (arm7_9->etm_ctx->trace_depth > 0)
1726         {
1727                 free(arm7_9->etm_ctx->trace_data);
1728                 arm7_9->etm_ctx->trace_data = NULL;
1729         }
1730         arm7_9->etm_ctx->trace_depth = 0;
1731
1732         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1733         etm_get_reg(etm_ctrl_reg);
1734
1735         /* Clear programming bit (10), set port selection bit (11) */
1736         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1737
1738         etm_store_reg(etm_ctrl_reg);
1739         jtag_execute_queue();
1740
1741         etm_ctx->capture_driver->start_capture(etm_ctx);
1742
1743         return ERROR_OK;
1744 }
1745
1746 int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1747 {
1748         target_t *target;
1749         armv4_5_common_t *armv4_5;
1750         arm7_9_common_t *arm7_9;
1751         etm_context_t *etm_ctx;
1752         reg_t *etm_ctrl_reg;
1753
1754         target = get_current_target(cmd_ctx);
1755
1756         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1757         {
1758                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1759                 return ERROR_OK;
1760         }
1761
1762         if (!(etm_ctx = arm7_9->etm_ctx))
1763         {
1764                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1765                 return ERROR_OK;
1766         }
1767
1768         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1769         etm_get_reg(etm_ctrl_reg);
1770
1771         /* Set programming bit (10), clear port selection bit (11) */
1772         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1773
1774         etm_store_reg(etm_ctrl_reg);
1775         jtag_execute_queue();
1776
1777         etm_ctx->capture_driver->stop_capture(etm_ctx);
1778
1779         return ERROR_OK;
1780 }
1781
1782 int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1783 {
1784         target_t *target;
1785         armv4_5_common_t *armv4_5;
1786         arm7_9_common_t *arm7_9;
1787         etm_context_t *etm_ctx;
1788         int retval;
1789
1790         target = get_current_target(cmd_ctx);
1791
1792         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1793         {
1794                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1795                 return ERROR_OK;
1796         }
1797
1798         if (!(etm_ctx = arm7_9->etm_ctx))
1799         {
1800                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1801                 return ERROR_OK;
1802         }
1803
1804         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1805         {
1806                 switch(retval)
1807                 {
1808                         case ERROR_ETM_ANALYSIS_FAILED:
1809                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1810                                 break;
1811                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1812                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1813                                 break;
1814                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
1815                                 command_print(cmd_ctx, "no image available for trace analysis");
1816                                 break;
1817                         default:
1818                                 command_print(cmd_ctx, "unknown error: %i", retval);
1819                 }
1820         }
1821
1822         return ERROR_OK;
1823 }
1824
1825 int etm_register_commands(struct command_context_s *cmd_ctx)
1826 {
1827         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1828
1829         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, NULL);
1830
1831         return ERROR_OK;
1832 }
1833
1834 int etm_register_user_commands(struct command_context_s *cmd_ctx)
1835 {
1836         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1837                 COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
1838
1839         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
1840                 COMMAND_EXEC, "display info about the current target's ETM");
1841
1842         register_command(cmd_ctx, etm_cmd, "trigger_percent <percent>", handle_etm_trigger_percent_command,
1843                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1844         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1845                 COMMAND_EXEC, "display current target's ETM status");
1846         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1847                 COMMAND_EXEC, "start ETM trace collection");
1848         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1849                 COMMAND_EXEC, "stop ETM trace collection");
1850
1851         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1852                 COMMAND_EXEC, "anaylze collected ETM trace");
1853
1854         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1855                 COMMAND_EXEC, "load image from <file> [base address]");
1856
1857         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1858                 COMMAND_EXEC, "dump captured trace data <file>");
1859         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1860                 COMMAND_EXEC, "load trace data for analysis <file>");
1861
1862         return ERROR_OK;
1863 }