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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <string.h>
  25
  26 #include "etm.h"
  27 #include "etb.h"
  28
  29 #include "armv4_5.h"
  30 #include "arm7_9_common.h"
  31 #include "arm_disassembler.h"
  32 #include "arm_simulator.h"
  33
  34 #include "log.h"
  35 #include "arm_jtag.h"
  36 #include "types.h"
  37 #include "binarybuffer.h"
  38 #include "target.h"
  39 #include "register.h"
  40 #include "jtag.h"
  41 #include "fileio.h"
  42
  43 #include <stdlib.h>
  44
  45 /* ETM register access functionality
  46  *
  47  */
  48
  49 bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
  50 {
  51         {"R", 1},
  52         {"W", 1},
  53         {"reserved", 26},
  54         {"version", 4}
  55 };
  56
  57 int etm_reg_arch_info[] =
  58 {
  59         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  60         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  61         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
  62         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
  63         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
  64         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
  65         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
  66         0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
  67         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
  68         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
  69         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
  70         0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
  71         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
  72         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  73 };
  74
  75 int etm_reg_arch_size_info[] =
  76 {
  77         32, 32, 17, 8, 3, 9, 32, 16,
  78         17, 26, 25, 8, 17, 32, 32, 17,
  79         32, 32, 32, 32, 32, 32, 32, 32,
  80         32, 32, 32, 32, 32, 32, 32, 32,
  81         7, 7, 7, 7, 7, 7, 7, 7,
  82         7, 7, 7, 7, 7, 7, 7, 7,
  83         32, 32, 32, 32, 32, 32, 32, 32,
  84         32, 32, 32, 32, 32, 32, 32, 32,
  85         32, 32, 32, 32, 32, 32, 32, 32,
  86         32, 32, 32, 32, 32, 32, 32, 32,
  87         16, 16, 16, 16, 18, 18, 18, 18,
  88         17, 17, 17, 17, 16, 16, 16, 16,
  89         17, 17, 17, 17, 17, 17, 2,
  90         17, 17, 17, 17, 32, 32, 32, 32
  91 };
  92
  93 char* etm_reg_list[] =
  94 {
  95         "ETM_CTRL",
  96         "ETM_CONFIG",
  97         "ETM_TRIG_EVENT",
  98         "ETM_MMD_CTRL",
  99         "ETM_STATUS",
 100         "ETM_SYS_CONFIG",
 101         "ETM_TRACE_RESOURCE_CTRL",
 102         "ETM_TRACE_EN_CTRL2",
 103         "ETM_TRACE_EN_EVENT",
 104         "ETM_TRACE_EN_CTRL1",
 105         "ETM_FIFOFULL_REGION",
 106         "ETM_FIFOFULL_LEVEL",
 107         "ETM_VIEWDATA_EVENT",
 108         "ETM_VIEWDATA_CTRL1",
 109         "ETM_VIEWDATA_CTRL2",
 110         "ETM_VIEWDATA_CTRL3",
 111         "ETM_ADDR_COMPARATOR_VALUE1",
 112         "ETM_ADDR_COMPARATOR_VALUE2",
 113         "ETM_ADDR_COMPARATOR_VALUE3",
 114         "ETM_ADDR_COMPARATOR_VALUE4",
 115         "ETM_ADDR_COMPARATOR_VALUE5",
 116         "ETM_ADDR_COMPARATOR_VALUE6",
 117         "ETM_ADDR_COMPARATOR_VALUE7",
 118         "ETM_ADDR_COMPARATOR_VALUE8",
 119         "ETM_ADDR_COMPARATOR_VALUE9",
 120         "ETM_ADDR_COMPARATOR_VALUE10",
 121         "ETM_ADDR_COMPARATOR_VALUE11",
 122         "ETM_ADDR_COMPARATOR_VALUE12",
 123         "ETM_ADDR_COMPARATOR_VALUE13",
 124         "ETM_ADDR_COMPARATOR_VALUE14",
 125         "ETM_ADDR_COMPARATOR_VALUE15",
 126         "ETM_ADDR_COMPARATOR_VALUE16",
 127         "ETM_ADDR_ACCESS_TYPE1",
 128         "ETM_ADDR_ACCESS_TYPE2",
 129         "ETM_ADDR_ACCESS_TYPE3",
 130         "ETM_ADDR_ACCESS_TYPE4",
 131         "ETM_ADDR_ACCESS_TYPE5",
 132         "ETM_ADDR_ACCESS_TYPE6",
 133         "ETM_ADDR_ACCESS_TYPE7",
 134         "ETM_ADDR_ACCESS_TYPE8",
 135         "ETM_ADDR_ACCESS_TYPE9",
 136         "ETM_ADDR_ACCESS_TYPE10",
 137         "ETM_ADDR_ACCESS_TYPE11",
 138         "ETM_ADDR_ACCESS_TYPE12",
 139         "ETM_ADDR_ACCESS_TYPE13",
 140         "ETM_ADDR_ACCESS_TYPE14",
 141         "ETM_ADDR_ACCESS_TYPE15",
 142         "ETM_ADDR_ACCESS_TYPE16",
 143         "ETM_DATA_COMPARATOR_VALUE1",
 144         "ETM_DATA_COMPARATOR_VALUE2",
 145         "ETM_DATA_COMPARATOR_VALUE3",
 146         "ETM_DATA_COMPARATOR_VALUE4",
 147         "ETM_DATA_COMPARATOR_VALUE5",
 148         "ETM_DATA_COMPARATOR_VALUE6",
 149         "ETM_DATA_COMPARATOR_VALUE7",
 150         "ETM_DATA_COMPARATOR_VALUE8",
 151         "ETM_DATA_COMPARATOR_VALUE9",
 152         "ETM_DATA_COMPARATOR_VALUE10",
 153         "ETM_DATA_COMPARATOR_VALUE11",
 154         "ETM_DATA_COMPARATOR_VALUE12",
 155         "ETM_DATA_COMPARATOR_VALUE13",
 156         "ETM_DATA_COMPARATOR_VALUE14",
 157         "ETM_DATA_COMPARATOR_VALUE15",
 158         "ETM_DATA_COMPARATOR_VALUE16",
 159         "ETM_DATA_COMPARATOR_MASK1",
 160         "ETM_DATA_COMPARATOR_MASK2",
 161         "ETM_DATA_COMPARATOR_MASK3",
 162         "ETM_DATA_COMPARATOR_MASK4",
 163         "ETM_DATA_COMPARATOR_MASK5",
 164         "ETM_DATA_COMPARATOR_MASK6",
 165         "ETM_DATA_COMPARATOR_MASK7",
 166         "ETM_DATA_COMPARATOR_MASK8",
 167         "ETM_DATA_COMPARATOR_MASK9",
 168         "ETM_DATA_COMPARATOR_MASK10",
 169         "ETM_DATA_COMPARATOR_MASK11",
 170         "ETM_DATA_COMPARATOR_MASK12",
 171         "ETM_DATA_COMPARATOR_MASK13",
 172         "ETM_DATA_COMPARATOR_MASK14",
 173         "ETM_DATA_COMPARATOR_MASK15",
 174         "ETM_DATA_COMPARATOR_MASK16",
 175         "ETM_COUNTER_INITAL_VALUE1",
 176         "ETM_COUNTER_INITAL_VALUE2",
 177         "ETM_COUNTER_INITAL_VALUE3",
 178         "ETM_COUNTER_INITAL_VALUE4",
 179         "ETM_COUNTER_ENABLE1",
 180         "ETM_COUNTER_ENABLE2",
 181         "ETM_COUNTER_ENABLE3",
 182         "ETM_COUNTER_ENABLE4",
 183         "ETM_COUNTER_RELOAD_VALUE1",
 184         "ETM_COUNTER_RELOAD_VALUE2",
 185         "ETM_COUNTER_RELOAD_VALUE3",
 186         "ETM_COUNTER_RELOAD_VALUE4",
 187         "ETM_COUNTER_VALUE1",
 188         "ETM_COUNTER_VALUE2",
 189         "ETM_COUNTER_VALUE3",
 190         "ETM_COUNTER_VALUE4",
 191         "ETM_SEQUENCER_CTRL1",
 192         "ETM_SEQUENCER_CTRL2",
 193         "ETM_SEQUENCER_CTRL3",
 194         "ETM_SEQUENCER_CTRL4",
 195         "ETM_SEQUENCER_CTRL5",
 196         "ETM_SEQUENCER_CTRL6",
 197         "ETM_SEQUENCER_STATE",
 198         "ETM_EXTERNAL_OUTPUT1",
 199         "ETM_EXTERNAL_OUTPUT2",
 200         "ETM_EXTERNAL_OUTPUT3",
 201         "ETM_EXTERNAL_OUTPUT4",
 202         "ETM_CONTEXTID_COMPARATOR_VALUE1",
 203         "ETM_CONTEXTID_COMPARATOR_VALUE2",
 204         "ETM_CONTEXTID_COMPARATOR_VALUE3",
 205         "ETM_CONTEXTID_COMPARATOR_MASK"
 206 };
 207
 208 int etm_reg_arch_type = -1;
 209
 210 int etm_get_reg(reg_t *reg);
 211
 212 command_t *etm_cmd = NULL;
 213
 214 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 215 {
 216         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 217         reg_t *reg_list = NULL;
 218         etm_reg_t *arch_info = NULL;
 219         int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
 220         int i;
 221
 222         /* register a register arch-type for etm registers only once */
 223         if (etm_reg_arch_type == -1)
 224                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
 225
 226         /* the actual registers are kept in two arrays */
 227         reg_list = calloc(num_regs, sizeof(reg_t));
 228         arch_info = calloc(num_regs, sizeof(etm_reg_t));
 229
 230         /* fill in values for the reg cache */
 231         reg_cache->name = "etm registers";
 232         reg_cache->next = NULL;
 233         reg_cache->reg_list = reg_list;
 234         reg_cache->num_regs = num_regs;
 235
 236         /* set up registers */
 237         for (i = 0; i < num_regs; i++)
 238         {
 239                 reg_list[i].name = etm_reg_list[i];
 240                 reg_list[i].size = 32;
 241                 reg_list[i].dirty = 0;
 242                 reg_list[i].valid = 0;
 243                 reg_list[i].bitfield_desc = NULL;
 244                 reg_list[i].num_bitfields = 0;
 245                 reg_list[i].value = calloc(1, 4);
 246                 reg_list[i].arch_info = &arch_info[i];
 247                 reg_list[i].arch_type = etm_reg_arch_type;
 248                 reg_list[i].size = etm_reg_arch_size_info[i];
 249                 arch_info[i].addr = etm_reg_arch_info[i];
 250                 arch_info[i].jtag_info = jtag_info;
 251         }
 252
 253         /* the ETM might have an ETB connected */
 254         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 255         {
 256                 etb_t *etb = etm_ctx->capture_driver_priv;
 257
 258                 if (!etb)
 259                 {
 260                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 261                         return ERROR_OK;
 262                 }
 263
 264                 reg_cache->next = etb_build_reg_cache(etb);
 265
 266                 etb->reg_cache = reg_cache->next;
 267         }
 268
 269
 270         return reg_cache;
 271 }
 272
 273 int etm_setup(target_t *target)
 274 {
 275         int retval;
 276         u32 etm_ctrl_value;
 277         armv4_5_common_t *armv4_5 = target->arch_info;
 278         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 279         etm_context_t *etm_ctx = arm7_9->etm_ctx;
 280         reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
 281         /* initialize some ETM control register settings */
 282         etm_get_reg(etm_ctrl_reg);
 283         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
 284
 285         /* clear the ETM powerdown bit (0) */
 286         etm_ctrl_value &= ~0x1;
 287
 288         /* configure port width (6:4), mode (17:16) and clocking (13) */
 289         etm_ctrl_value = (etm_ctrl_value &
 290                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 291                 | etm_ctx->portmode;
 292
 293         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 294         etm_store_reg(etm_ctrl_reg);
 295
 296         if ((retval=jtag_execute_queue())!=ERROR_OK)
 297                 return retval;
 298
 299         if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 300         {
 301                 LOG_ERROR("ETM capture driver initialization failed");
 302                 return retval;
 303         }
 304         return ERROR_OK;
 305 }
 306
 307 int etm_get_reg(reg_t *reg)
 308 {
 309         int retval;
 310         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 311         {
 312                 LOG_ERROR("BUG: error scheduling etm register read");
 313                 return retval;
 314         }
 315
 316         if ((retval = jtag_execute_queue()) != ERROR_OK)
 317         {
 318                 LOG_ERROR("register read failed");
 319                 return retval;
 320         }
 321
 322         return ERROR_OK;
 323 }
 324
 325 int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 326 {
 327         etm_reg_t *etm_reg = reg->arch_info;
 328         u8 reg_addr = etm_reg->addr & 0x7f;
 329         scan_field_t fields[3];
 330
 331         LOG_DEBUG("%i", etm_reg->addr);
 332
 333         jtag_add_end_state(TAP_IDLE);
 334         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 335         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 336
 337         fields[0].tap = etm_reg->jtag_info->tap;
 338         fields[0].num_bits = 32;
 339         fields[0].out_value = reg->value;
 340         fields[0].out_mask = NULL;
 341         fields[0].in_value = NULL;
 342         fields[0].in_check_value = NULL;
 343         fields[0].in_check_mask = NULL;
 344         fields[0].in_handler = NULL;
 345         fields[0].in_handler_priv = NULL;
 346
 347         fields[1].tap = etm_reg->jtag_info->tap;
 348         fields[1].num_bits = 7;
 349         fields[1].out_value = malloc(1);
 350         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 351         fields[1].out_mask = NULL;
 352         fields[1].in_value = NULL;
 353         fields[1].in_check_value = NULL;
 354         fields[1].in_check_mask = NULL;
 355         fields[1].in_handler = NULL;
 356         fields[1].in_handler_priv = NULL;
 357
 358         fields[2].tap = etm_reg->jtag_info->tap;
 359         fields[2].num_bits = 1;
 360         fields[2].out_value = malloc(1);
 361         buf_set_u32(fields[2].out_value, 0, 1, 0);
 362         fields[2].out_mask = NULL;
 363         fields[2].in_value = NULL;
 364         fields[2].in_check_value = NULL;
 365         fields[2].in_check_mask = NULL;
 366         fields[2].in_handler = NULL;
 367         fields[2].in_handler_priv = NULL;
 368
 369         jtag_add_dr_scan(3, fields, TAP_INVALID);
 370
 371         fields[0].in_value = reg->value;
 372         jtag_set_check_value(fields+0, check_value, check_mask, NULL);
 373
 374         jtag_add_dr_scan(3, fields, TAP_INVALID);
 375
 376         free(fields[1].out_value);
 377         free(fields[2].out_value);
 378
 379         return ERROR_OK;
 380 }
 381
 382 int etm_read_reg(reg_t *reg)
 383 {
 384         return etm_read_reg_w_check(reg, NULL, NULL);
 385 }
 386
 387 int etm_set_reg(reg_t *reg, u32 value)
 388 {
 389         int retval;
 390         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 391         {
 392                 LOG_ERROR("BUG: error scheduling etm register write");
 393                 return retval;
 394         }
 395
 396         buf_set_u32(reg->value, 0, reg->size, value);
 397         reg->valid = 1;
 398         reg->dirty = 0;
 399
 400         return ERROR_OK;
 401 }
 402
 403 int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
 404 {
 405         int retval;
 406         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 407
 408         if ((retval = jtag_execute_queue()) != ERROR_OK)
 409         {
 410                 LOG_ERROR("register write failed");
 411                 return retval;
 412         }
 413         return ERROR_OK;
 414 }
 415
 416 int etm_write_reg(reg_t *reg, u32 value)
 417 {
 418         etm_reg_t *etm_reg = reg->arch_info;
 419         u8 reg_addr = etm_reg->addr & 0x7f;
 420         scan_field_t fields[3];
 421
 422         LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
 423
 424         jtag_add_end_state(TAP_IDLE);
 425         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 426         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 427
 428         fields[0].tap = etm_reg->jtag_info->tap;
 429         fields[0].num_bits = 32;
 430         fields[0].out_value = malloc(4);
 431         buf_set_u32(fields[0].out_value, 0, 32, value);
 432         fields[0].out_mask = NULL;
 433         fields[0].in_value = NULL;
 434         fields[0].in_check_value = NULL;
 435         fields[0].in_check_mask = NULL;
 436         fields[0].in_handler = NULL;
 437         fields[0].in_handler_priv = NULL;
 438
 439         fields[1].tap = etm_reg->jtag_info->tap;
 440         fields[1].num_bits = 7;
 441         fields[1].out_value = malloc(1);
 442         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 443         fields[1].out_mask = NULL;
 444         fields[1].in_value = NULL;
 445         fields[1].in_check_value = NULL;
 446         fields[1].in_check_mask = NULL;
 447         fields[1].in_handler = NULL;
 448         fields[1].in_handler_priv = NULL;
 449
 450         fields[2].tap = etm_reg->jtag_info->tap;
 451         fields[2].num_bits = 1;
 452         fields[2].out_value = malloc(1);
 453         buf_set_u32(fields[2].out_value, 0, 1, 1);
 454         fields[2].out_mask = NULL;
 455         fields[2].in_value = NULL;
 456         fields[2].in_check_value = NULL;
 457         fields[2].in_check_mask = NULL;
 458         fields[2].in_handler = NULL;
 459         fields[2].in_handler_priv = NULL;
 460
 461         jtag_add_dr_scan(3, fields, TAP_INVALID);
 462
 463         free(fields[0].out_value);
 464         free(fields[1].out_value);
 465         free(fields[2].out_value);
 466
 467         return ERROR_OK;
 468 }
 469
 470 int etm_store_reg(reg_t *reg)
 471 {
 472         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 473 }
 474
 475 /* ETM trace analysis functionality
 476  *
 477  */
 478 extern etm_capture_driver_t etm_dummy_capture_driver;
 479 #if BUILD_OOCD_TRACE == 1
 480 extern etm_capture_driver_t oocd_trace_capture_driver;
 481 #endif
 482
 483 etm_capture_driver_t *etm_capture_drivers[] =
 484 {
 485         &etb_capture_driver,
 486         &etm_dummy_capture_driver,
 487 #if BUILD_OOCD_TRACE == 1
 488         &oocd_trace_capture_driver,
 489 #endif
 490         NULL
 491 };
 492
 493 char *etmv1v1_branch_reason_strings[] =
 494 {
 495         "normal PC change",
 496         "tracing enabled",
 497         "trace restarted after overflow",
 498         "exit from debug",
 499         "periodic synchronization",
 500         "reserved",
 501         "reserved",
 502         "reserved",
 503 };
 504
 505 int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 506 {
 507         int i;
 508         int section = -1;
 509         u32 size_read;
 510         u32 opcode;
 511         int retval;
 512
 513         if (!ctx->image)
 514                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 515
 516         /* search for the section the current instruction belongs to */
 517         for (i = 0; i < ctx->image->num_sections; i++)
 518         {
 519                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 520                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 521                 {
 522                         section = i;
 523                         break;
 524                 }
 525         }
 526
 527         if (section == -1)
 528         {
 529                 /* current instruction couldn't be found in the image */
 530                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 531         }
 532
 533         if (ctx->core_state == ARMV4_5_STATE_ARM)
 534         {
 535                 u8 buf[4];
 536                 if ((retval = image_read_section(ctx->image, section,
 537                         ctx->current_pc - ctx->image->sections[section].base_address,
 538                         4, buf, &size_read)) != ERROR_OK)
 539                 {
 540                         LOG_ERROR("error while reading instruction: %i", retval);
 541                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 542                 }
 543                 opcode = target_buffer_get_u32(ctx->target, buf);
 544                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 545         }
 546         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 547         {
 548                 u8 buf[2];
 549                 if ((retval = image_read_section(ctx->image, section,
 550                         ctx->current_pc - ctx->image->sections[section].base_address,
 551                         2, buf, &size_read)) != ERROR_OK)
 552                 {
 553                         LOG_ERROR("error while reading instruction: %i", retval);
 554                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 555                 }
 556                 opcode = target_buffer_get_u16(ctx->target, buf);
 557                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 558         }
 559         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 560         {
 561                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 562                 exit(-1);
 563         }
 564         else
 565         {
 566                 LOG_ERROR("BUG: unknown core state encountered");
 567                 exit(-1);
 568         }
 569
 570         return ERROR_OK;
 571 }
 572
 573 int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
 574 {
 575         while (ctx->data_index < ctx->trace_depth)
 576         {
 577                 /* if the caller specified an address packet offset, skip until the
 578                  * we reach the n-th cycle marked with tracesync */
 579                 if (apo > 0)
 580                 {
 581                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 582                                 apo--;
 583
 584                         if (apo > 0)
 585                         {
 586                                 ctx->data_index++;
 587                                 ctx->data_half = 0;
 588                         }
 589                         continue;
 590                 }
 591
 592                 /* no tracedata output during a TD cycle
 593                  * or in a trigger cycle */
 594                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 595                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 596                 {
 597                         ctx->data_index++;
 598                         ctx->data_half = 0;
 599                         continue;
 600                 }
 601
 602                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 603                 {
 604                         if (ctx->data_half == 0)
 605                         {
 606                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 607                                 ctx->data_half = 1;
 608                         }
 609                         else
 610                         {
 611                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 612                                 ctx->data_half = 0;
 613                                 ctx->data_index++;
 614                         }
 615                 }
 616                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 617                 {
 618                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 619                         ctx->data_index++;
 620                 }
 621                 else
 622                 {
 623                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 624                         if (ctx->data_index > (ctx->trace_depth - 2))
 625                                 return -1;
 626
 627                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 628                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 629                         ctx->data_index += 2;
 630                 }
 631
 632                 return 0;
 633         }
 634
 635         return -1;
 636 }
 637
 638 int etmv1_branch_address(etm_context_t *ctx)
 639 {
 640         int retval;
 641         u8 packet;
 642         int shift = 0;
 643         int apo;
 644         u32 i;
 645
 646         /* quit analysis if less than two cycles are left in the trace
 647          * because we can't extract the APO */
 648         if (ctx->data_index > (ctx->trace_depth - 2))
 649                 return -1;
 650
 651         /* a BE could be output during an APO cycle, skip the current
 652          * and continue with the new one */
 653         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 654                 return 1;
 655         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 656                 return 2;
 657
 658         /* address packet offset encoded in the next two cycles' pipestat bits */
 659         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 660         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 661
 662         /* count number of tracesync cycles between current pipe_index and data_index
 663          * i.e. the number of tracesyncs that data_index already passed by
 664          * to subtract them from the APO */
 665         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 666         {
 667                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 668                         apo--;
 669         }
 670
 671         /* extract up to four 7-bit packets */
 672         do {
 673                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 674                         return -1;
 675                 ctx->last_branch &= ~(0x7f << shift);
 676                 ctx->last_branch |= (packet & 0x7f) << shift;
 677                 shift += 7;
 678         } while ((packet & 0x80) && (shift < 28));
 679
 680         /* one last packet holding 4 bits of the address, plus the branch reason code */
 681         if ((shift == 28) && (packet & 0x80))
 682         {
 683                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 684                         return -1;
 685                 ctx->last_branch &= 0x0fffffff;
 686                 ctx->last_branch |= (packet & 0x0f) << 28;
 687                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 688                 shift += 4;
 689         }
 690         else
 691         {
 692                 ctx->last_branch_reason = 0;
 693         }
 694
 695         if (shift == 32)
 696         {
 697                 ctx->pc_ok = 1;
 698         }
 699
 700         /* if a full address was output, we might have branched into Jazelle state */
 701         if ((shift == 32) && (packet & 0x80))
 702         {
 703                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 704         }
 705         else
 706         {
 707                 /* if we didn't branch into Jazelle state, the current processor state is
 708                  * encoded in bit 0 of the branch target address */
 709                 if (ctx->last_branch & 0x1)
 710                 {
 711                         ctx->core_state = ARMV4_5_STATE_THUMB;
 712                         ctx->last_branch &= ~0x1;
 713                 }
 714                 else
 715                 {
 716                         ctx->core_state = ARMV4_5_STATE_ARM;
 717                         ctx->last_branch &= ~0x3;
 718                 }
 719         }
 720
 721         return 0;
 722 }
 723
 724 int etmv1_data(etm_context_t *ctx, int size, u32 *data)
 725 {
 726         int j;
 727         u8 buf[4];
 728         int retval;
 729
 730         for (j = 0; j < size; j++)
 731         {
 732                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 733                         return -1;
 734         }
 735
 736         if (size == 8)
 737         {
 738                 LOG_ERROR("TODO: add support for 64-bit values");
 739                 return -1;
 740         }
 741         else if (size == 4)
 742                 *data = target_buffer_get_u32(ctx->target, buf);
 743         else if (size == 2)
 744                 *data = target_buffer_get_u16(ctx->target, buf);
 745         else if (size == 1)
 746                 *data = buf[0];
 747         else
 748                 return -1;
 749
 750         return 0;
 751 }
 752
 753 int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 754 {
 755         int retval;
 756         arm_instruction_t instruction;
 757
 758         /* read the trace data if it wasn't read already */
 759         if (ctx->trace_depth == 0)
 760                 ctx->capture_driver->read_trace(ctx);
 761
 762         /* start at the beginning of the captured trace */
 763         ctx->pipe_index = 0;
 764         ctx->data_index = 0;
 765         ctx->data_half = 0;
 766
 767         /* neither the PC nor the data pointer are valid */
 768         ctx->pc_ok = 0;
 769         ctx->ptr_ok = 0;
 770
 771         while (ctx->pipe_index < ctx->trace_depth)
 772         {
 773                 u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 774                 u32 next_pc = ctx->current_pc;
 775                 u32 old_data_index = ctx->data_index;
 776                 u32 old_data_half = ctx->data_half;
 777                 u32 old_index = ctx->pipe_index;
 778                 u32 last_instruction = ctx->last_instruction;
 779                 u32 cycles = 0;
 780                 int current_pc_ok = ctx->pc_ok;
 781
 782                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 783                 {
 784                         command_print(cmd_ctx, "--- trigger ---");
 785                 }
 786
 787                 /* instructions execute in IE/D or BE/D cycles */
 788                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 789                         ctx->last_instruction = ctx->pipe_index;
 790
 791                 /* if we don't have a valid pc skip until we reach an indirect branch */
 792                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 793                 {
 794                         ctx->pipe_index++;
 795                         continue;
 796                 }
 797
 798                 /* any indirect branch could have interrupted instruction flow
 799                  * - the branch reason code could indicate a trace discontinuity
 800                  * - a branch to the exception vectors indicates an exception
 801                  */
 802                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 803                 {
 804                         /* backup current data index, to be able to consume the branch address
 805                          * before examining data address and values
 806                          */
 807                         old_data_index = ctx->data_index;
 808                         old_data_half = ctx->data_half;
 809
 810                         ctx->last_instruction = ctx->pipe_index;
 811
 812                         if ((retval = etmv1_branch_address(ctx)) != 0)
 813                         {
 814                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 815                                  * quit analysing the trace */
 816                                 if (retval < 0)
 817                                         break;
 818
 819                                 /* a positive return values means the current branch was abandoned,
 820                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 821                                  */
 822                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 823                                 ctx->pipe_index += retval;
 824                                 continue;
 825                         }
 826
 827                         /* skip over APO cycles */
 828                         ctx->pipe_index += 2;
 829
 830                         switch (ctx->last_branch_reason)
 831                         {
 832                                 case 0x0:       /* normal PC change */
 833                                         next_pc = ctx->last_branch;
 834                                         break;
 835                                 case 0x1:       /* tracing enabled */
 836                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
 837                                         ctx->current_pc = ctx->last_branch;
 838                                         ctx->pipe_index++;
 839                                         continue;
 840                                         break;
 841                                 case 0x2:       /* trace restarted after FIFO overflow */
 842                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
 843                                         ctx->current_pc = ctx->last_branch;
 844                                         ctx->pipe_index++;
 845                                         continue;
 846                                         break;
 847                                 case 0x3:       /* exit from debug state */
 848                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
 849                                         ctx->current_pc = ctx->last_branch;
 850                                         ctx->pipe_index++;
 851                                         continue;
 852                                         break;
 853                                 case 0x4:       /* periodic synchronization point */
 854                                         next_pc = ctx->last_branch;
 855                                         /* if we had no valid PC prior to this synchronization point,
 856                                          * we have to move on with the next trace cycle
 857                                          */
 858                                         if (!current_pc_ok)
 859                                         {
 860                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
 861                                                 ctx->current_pc = next_pc;
 862                                                 ctx->pipe_index++;
 863                                                 continue;
 864                                         }
 865                                         break;
 866                                 default:        /* reserved */
 867                                         LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
 868                                         exit(-1);
 869                                         break;
 870                         }
 871
 872                         /* if we got here the branch was a normal PC change
 873                          * (or a periodic synchronization point, which means the same for that matter)
 874                          * if we didn't accquire a complete PC continue with the next cycle
 875                          */
 876                         if (!ctx->pc_ok)
 877                                 continue;
 878
 879                         /* indirect branch to the exception vector means an exception occured */
 880                         if ((ctx->last_branch <= 0x20)
 881                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 882                         {
 883                                 if ((ctx->last_branch & 0xff) == 0x10)
 884                                 {
 885                                         command_print(cmd_ctx, "data abort");
 886                                 }
 887                                 else
 888                                 {
 889                                         command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
 890                                         ctx->current_pc = ctx->last_branch;
 891                                         ctx->pipe_index++;
 892                                         continue;
 893                                 }
 894                         }
 895                 }
 896
 897                 /* an instruction was executed (or not, depending on the condition flags)
 898                  * retrieve it from the image for displaying */
 899                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
 900                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
 901                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
 902                 {
 903                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
 904                         {
 905                                 /* can't continue tracing with no image available */
 906                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
 907                                 {
 908                                         return retval;
 909                                 }
 910                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
 911                                 {
 912                                         /* TODO: handle incomplete images
 913                                          * for now we just quit the analsysis*/
 914                                         return retval;
 915                                 }
 916                         }
 917
 918                         cycles = old_index - last_instruction;
 919                 }
 920
 921                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
 922                 {
 923                         u32 new_data_index = ctx->data_index;
 924                         u32 new_data_half = ctx->data_half;
 925
 926                         /* in case of a branch with data, the branch target address was consumed before
 927                          * we temporarily go back to the saved data index */
 928                         if (pipestat == STAT_BD)
 929                         {
 930                                 ctx->data_index = old_data_index;
 931                                 ctx->data_half = old_data_half;
 932                         }
 933
 934                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
 935                         {
 936                                 u8 packet;
 937                                 int shift = 0;
 938
 939                                 do {
 940                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 941                                                 return ERROR_ETM_ANALYSIS_FAILED;
 942                                         ctx->last_ptr &= ~(0x7f << shift);
 943                                         ctx->last_ptr |= (packet & 0x7f) << shift;
 944                                         shift += 7;
 945                                 } while ((packet & 0x80) && (shift < 32));
 946
 947                                 if (shift >= 32)
 948                                         ctx->ptr_ok = 1;
 949
 950                                 if (ctx->ptr_ok)
 951                                 {
 952                                         command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
 953                                 }
 954                         }
 955
 956                         if (ctx->tracemode & ETMV1_TRACE_DATA)
 957                         {
 958                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
 959                                 {
 960                                         int i;
 961                                         for (i = 0; i < 16; i++)
 962                                         {
 963                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
 964                                                 {
 965                                                         u32 data;
 966                                                         if (etmv1_data(ctx, 4, &data) != 0)
 967                                                                 return ERROR_ETM_ANALYSIS_FAILED;
 968                                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 969                                                 }
 970                                         }
 971                                 }
 972                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
 973                                 {
 974                                         u32 data;
 975                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
 976                                                 return ERROR_ETM_ANALYSIS_FAILED;
 977                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 978                                 }
 979                         }
 980
 981                         /* restore data index after consuming BD address and data */
 982                         if (pipestat == STAT_BD)
 983                         {
 984                                 ctx->data_index = new_data_index;
 985                                 ctx->data_half = new_data_half;
 986                         }
 987                 }
 988
 989                 /* adjust PC */
 990                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 991                 {
 992                         if (((instruction.type == ARM_B) ||
 993                                 (instruction.type == ARM_BL) ||
 994                                 (instruction.type == ARM_BLX)) &&
 995                                 (instruction.info.b_bl_bx_blx.target_address != ~0UL))
 996                         {
 997                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
 998                         }
 999                         else
1000                         {
1001                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1002                         }
1003                 }
1004                 else if (pipestat == STAT_IN)
1005                 {
1006                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1007                 }
1008
1009                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1010                 {
1011                         char cycles_text[32] = "";
1012
1013                         /* if the trace was captured with cycle accurate tracing enabled,
1014                          * output the number of cycles since the last executed instruction
1015                          */
1016                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1017                         {
1018                                 snprintf(cycles_text, 32, " (%i %s)",
1019                                         cycles,
1020                                         (cycles == 1) ? "cycle" : "cycles");
1021                         }
1022
1023                         command_print(cmd_ctx, "%s%s%s",
1024                                 instruction.text,
1025                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1026                                 cycles_text);
1027
1028                         ctx->current_pc = next_pc;
1029
1030                         /* packets for an instruction don't start on or before the preceding
1031                          * functional pipestat (i.e. other than WT or TD)
1032                          */
1033                         if (ctx->data_index <= ctx->pipe_index)
1034                         {
1035                                 ctx->data_index = ctx->pipe_index + 1;
1036                                 ctx->data_half = 0;
1037                         }
1038                 }
1039
1040                 ctx->pipe_index += 1;
1041         }
1042
1043         return ERROR_OK;
1044 }
1045
1046 int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1047 {
1048         target_t *target;
1049         armv4_5_common_t *armv4_5;
1050         arm7_9_common_t *arm7_9;
1051         etmv1_tracemode_t tracemode;
1052
1053         target = get_current_target(cmd_ctx);
1054
1055         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1056         {
1057                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1058                 return ERROR_OK;
1059         }
1060
1061         if (!arm7_9->etm_ctx)
1062         {
1063                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1064                 return ERROR_OK;
1065         }
1066
1067         tracemode = arm7_9->etm_ctx->tracemode;
1068
1069         if (argc == 4)
1070         {
1071                 if (strcmp(args[0], "none") == 0)
1072                 {
1073                         tracemode = ETMV1_TRACE_NONE;
1074                 }
1075                 else if (strcmp(args[0], "data") == 0)
1076                 {
1077                         tracemode = ETMV1_TRACE_DATA;
1078                 }
1079                 else if (strcmp(args[0], "address") == 0)
1080                 {
1081                         tracemode = ETMV1_TRACE_ADDR;
1082                 }
1083                 else if (strcmp(args[0], "all") == 0)
1084                 {
1085                         tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1086                 }
1087                 else
1088                 {
1089                         command_print(cmd_ctx, "invalid option '%s'", args[0]);
1090                         return ERROR_OK;
1091                 }
1092
1093                 switch (strtol(args[1], NULL, 0))
1094                 {
1095                         case 0:
1096                                 tracemode |= ETMV1_CONTEXTID_NONE;
1097                                 break;
1098                         case 8:
1099                                 tracemode |= ETMV1_CONTEXTID_8;
1100                                 break;
1101                         case 16:
1102                                 tracemode |= ETMV1_CONTEXTID_16;
1103                                 break;
1104                         case 32:
1105                                 tracemode |= ETMV1_CONTEXTID_32;
1106                                 break;
1107                         default:
1108                                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1109                                 return ERROR_OK;
1110                 }
1111
1112                 if (strcmp(args[2], "enable") == 0)
1113                 {
1114                         tracemode |= ETMV1_CYCLE_ACCURATE;
1115                 }
1116                 else if (strcmp(args[2], "disable") == 0)
1117                 {
1118                         tracemode |= 0;
1119                 }
1120                 else
1121                 {
1122                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1123                         return ERROR_OK;
1124                 }
1125
1126                 if (strcmp(args[3], "enable") == 0)
1127                 {
1128                         tracemode |= ETMV1_BRANCH_OUTPUT;
1129                 }
1130                 else if (strcmp(args[3], "disable") == 0)
1131                 {
1132                         tracemode |= 0;
1133                 }
1134                 else
1135                 {
1136                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1137                         return ERROR_OK;
1138                 }
1139         }
1140         else if (argc != 0)
1141         {
1142                 command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1143                 return ERROR_OK;
1144         }
1145
1146         command_print(cmd_ctx, "current tracemode configuration:");
1147
1148         switch (tracemode & ETMV1_TRACE_MASK)
1149         {
1150                 case ETMV1_TRACE_NONE:
1151                         command_print(cmd_ctx, "data tracing: none");
1152                         break;
1153                 case ETMV1_TRACE_DATA:
1154                         command_print(cmd_ctx, "data tracing: data only");
1155                         break;
1156                 case ETMV1_TRACE_ADDR:
1157                         command_print(cmd_ctx, "data tracing: address only");
1158                         break;
1159                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1160                         command_print(cmd_ctx, "data tracing: address and data");
1161                         break;
1162         }
1163
1164         switch (tracemode & ETMV1_CONTEXTID_MASK)
1165         {
1166                 case ETMV1_CONTEXTID_NONE:
1167                         command_print(cmd_ctx, "contextid tracing: none");
1168                         break;
1169                 case ETMV1_CONTEXTID_8:
1170                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1171                         break;
1172                 case ETMV1_CONTEXTID_16:
1173                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1174                         break;
1175                 case ETMV1_CONTEXTID_32:
1176                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1177                         break;
1178         }
1179
1180         if (tracemode & ETMV1_CYCLE_ACCURATE)
1181         {
1182                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1183         }
1184         else
1185         {
1186                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1187         }
1188
1189         if (tracemode & ETMV1_BRANCH_OUTPUT)
1190         {
1191                 command_print(cmd_ctx, "full branch address output enabled");
1192         }
1193         else
1194         {
1195                 command_print(cmd_ctx, "full branch address output disabled");
1196         }
1197
1198         /* only update ETM_CTRL register if tracemode changed */
1199         if (arm7_9->etm_ctx->tracemode != tracemode)
1200         {
1201                 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1202
1203                 etm_get_reg(etm_ctrl_reg);
1204
1205                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1206                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1207                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1208                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1209                 etm_store_reg(etm_ctrl_reg);
1210
1211                 arm7_9->etm_ctx->tracemode = tracemode;
1212
1213                 /* invalidate old trace data */
1214                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1215                 if (arm7_9->etm_ctx->trace_depth > 0)
1216                 {
1217                         free(arm7_9->etm_ctx->trace_data);
1218                         arm7_9->etm_ctx->trace_data = NULL;
1219                 }
1220                 arm7_9->etm_ctx->trace_depth = 0;
1221         }
1222
1223         return ERROR_OK;
1224 }
1225
1226 int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1227 {
1228         target_t *target;
1229         armv4_5_common_t *armv4_5;
1230         arm7_9_common_t *arm7_9;
1231         etm_portmode_t portmode = 0x0;
1232         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1233         int i;
1234
1235         if (argc != 5)
1236         {
1237                 return ERROR_COMMAND_SYNTAX_ERROR;
1238         }
1239
1240         target = get_target_by_num(strtoul(args[0], NULL, 0));
1241
1242         if (!target)
1243         {
1244                 LOG_ERROR("target number '%s' not defined", args[0]);
1245                 return ERROR_FAIL;
1246         }
1247
1248         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1249         {
1250                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1251                 return ERROR_FAIL;
1252         }
1253
1254         switch (strtoul(args[1], NULL, 0))
1255         {
1256                 case 4:
1257                         portmode |= ETM_PORT_4BIT;
1258                         break;
1259                 case 8:
1260                         portmode |= ETM_PORT_8BIT;
1261                         break;
1262                 case 16:
1263                         portmode |= ETM_PORT_16BIT;
1264                         break;
1265                 default:
1266                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1267                         return ERROR_FAIL;
1268         }
1269
1270         if (strcmp("normal", args[2]) == 0)
1271         {
1272                 portmode |= ETM_PORT_NORMAL;
1273         }
1274         else if (strcmp("multiplexed", args[2]) == 0)
1275         {
1276                 portmode |= ETM_PORT_MUXED;
1277         }
1278         else if (strcmp("demultiplexed", args[2]) == 0)
1279         {
1280                 portmode |= ETM_PORT_DEMUXED;
1281         }
1282         else
1283         {
1284                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1285                 return ERROR_FAIL;
1286         }
1287
1288         if (strcmp("half", args[3]) == 0)
1289         {
1290                 portmode |= ETM_PORT_HALF_CLOCK;
1291         }
1292         else if (strcmp("full", args[3]) == 0)
1293         {
1294                 portmode |= ETM_PORT_FULL_CLOCK;
1295         }
1296         else
1297         {
1298                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1299                 return ERROR_FAIL;
1300         }
1301
1302         for (i=0; etm_capture_drivers[i]; i++)
1303         {
1304                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1305                 {
1306                         int retval;
1307                         if ((retval=etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1308                         {
1309                                 free(etm_ctx);
1310                                 return retval;
1311                         }
1312
1313                         etm_ctx->capture_driver = etm_capture_drivers[i];
1314
1315                         break;
1316                 }
1317         }
1318
1319         if (!etm_capture_drivers[i])
1320         {
1321                 /* no supported capture driver found, don't register an ETM */
1322                 free(etm_ctx);
1323                 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1324                 return ERROR_FAIL;
1325         }
1326
1327         etm_ctx->target = target;
1328         etm_ctx->trigger_percent = 50;
1329         etm_ctx->trace_data = NULL;
1330         etm_ctx->trace_depth = 0;
1331         etm_ctx->portmode = portmode;
1332         etm_ctx->tracemode = 0x0;
1333         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1334         etm_ctx->image = NULL;
1335         etm_ctx->pipe_index = 0;
1336         etm_ctx->data_index = 0;
1337         etm_ctx->current_pc = 0x0;
1338         etm_ctx->pc_ok = 0;
1339         etm_ctx->last_branch = 0x0;
1340         etm_ctx->last_branch_reason = 0x0;
1341         etm_ctx->last_ptr = 0x0;
1342         etm_ctx->ptr_ok = 0x0;
1343         etm_ctx->context_id = 0x0;
1344         etm_ctx->last_instruction = 0;
1345
1346         arm7_9->etm_ctx = etm_ctx;
1347
1348         return etm_register_user_commands(cmd_ctx);
1349 }
1350
1351 int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1352 {
1353         target_t *target;
1354         armv4_5_common_t *armv4_5;
1355         arm7_9_common_t *arm7_9;
1356         reg_t *etm_config_reg;
1357         reg_t *etm_sys_config_reg;
1358
1359         int max_port_size;
1360
1361         target = get_current_target(cmd_ctx);
1362
1363         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1364         {
1365                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1366                 return ERROR_OK;
1367         }
1368
1369         if (!arm7_9->etm_ctx)
1370         {
1371                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1372                 return ERROR_OK;
1373         }
1374
1375         etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
1376         etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
1377
1378         etm_get_reg(etm_config_reg);
1379         command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
1380         command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
1381         command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
1382         command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
1383         command_print(cmd_ctx, "sequencer %spresent",
1384                         (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
1385         command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
1386         command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
1387         command_print(cmd_ctx, "FIFO full %spresent",
1388                         (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
1389         command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
1390
1391         etm_get_reg(etm_sys_config_reg);
1392
1393         switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1394         {
1395                 case 0:
1396                         max_port_size = 4;
1397                         break;
1398                 case 1:
1399                         max_port_size = 8;
1400                         break;
1401                 case 2:
1402                         max_port_size = 16;
1403                         break;
1404                 default:
1405                         LOG_ERROR("Illegal max_port_size");
1406                         exit(-1);
1407         }
1408         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1409
1410         command_print(cmd_ctx, "half-rate clocking %ssupported",
1411                         (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1412         command_print(cmd_ctx, "full-rate clocking %ssupported",
1413                         (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1414         command_print(cmd_ctx, "normal trace format %ssupported",
1415                         (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1416         command_print(cmd_ctx, "multiplex trace format %ssupported",
1417                         (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1418         command_print(cmd_ctx, "demultiplex trace format %ssupported",
1419                         (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1420         command_print(cmd_ctx, "FIFO full %ssupported",
1421                         (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1422
1423         return ERROR_OK;
1424 }
1425
1426 int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1427 {
1428         target_t *target;
1429         armv4_5_common_t *armv4_5;
1430         arm7_9_common_t *arm7_9;
1431         trace_status_t trace_status;
1432
1433         target = get_current_target(cmd_ctx);
1434
1435         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1436         {
1437                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1438                 return ERROR_OK;
1439         }
1440
1441         if (!arm7_9->etm_ctx)
1442         {
1443                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1444                 return ERROR_OK;
1445         }
1446
1447         trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1448
1449         if (trace_status == TRACE_IDLE)
1450         {
1451                 command_print(cmd_ctx, "tracing is idle");
1452         }
1453         else
1454         {
1455                 static char *completed = " completed";
1456                 static char *running = " is running";
1457                 static char *overflowed = ", trace overflowed";
1458                 static char *triggered = ", trace triggered";
1459
1460                 command_print(cmd_ctx, "trace collection%s%s%s",
1461                         (trace_status & TRACE_RUNNING) ? running : completed,
1462                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1463                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1464
1465                 if (arm7_9->etm_ctx->trace_depth > 0)
1466                 {
1467                         command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
1468                 }
1469         }
1470
1471         return ERROR_OK;
1472 }
1473
1474 int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1475 {
1476         target_t *target;
1477         armv4_5_common_t *armv4_5;
1478         arm7_9_common_t *arm7_9;
1479         etm_context_t *etm_ctx;
1480
1481         if (argc < 1)
1482         {
1483                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1484                 return ERROR_OK;
1485         }
1486
1487         target = get_current_target(cmd_ctx);
1488
1489         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1490         {
1491                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1492                 return ERROR_OK;
1493         }
1494
1495         if (!(etm_ctx = arm7_9->etm_ctx))
1496         {
1497                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1498                 return ERROR_OK;
1499         }
1500
1501         if (etm_ctx->image)
1502         {
1503                 image_close(etm_ctx->image);
1504                 free(etm_ctx->image);
1505                 command_print(cmd_ctx, "previously loaded image found and closed");
1506         }
1507
1508         etm_ctx->image = malloc(sizeof(image_t));
1509         etm_ctx->image->base_address_set = 0;
1510         etm_ctx->image->start_address_set = 0;
1511
1512         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1513         if (argc >= 2)
1514         {
1515                 etm_ctx->image->base_address_set = 1;
1516                 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1517         }
1518         else
1519         {
1520                 etm_ctx->image->base_address_set = 0;
1521         }
1522
1523         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1524         {
1525                 free(etm_ctx->image);
1526                 etm_ctx->image = NULL;
1527                 return ERROR_OK;
1528         }
1529
1530         return ERROR_OK;
1531 }
1532
1533 int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1534 {
1535         fileio_t file;
1536         target_t *target;
1537         armv4_5_common_t *armv4_5;
1538         arm7_9_common_t *arm7_9;
1539         etm_context_t *etm_ctx;
1540         u32 i;
1541
1542         if (argc != 1)
1543         {
1544                 command_print(cmd_ctx, "usage: etm dump <file>");
1545                 return ERROR_OK;
1546         }
1547
1548         target = get_current_target(cmd_ctx);
1549
1550         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1551         {
1552                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1553                 return ERROR_OK;
1554         }
1555
1556         if (!(etm_ctx = arm7_9->etm_ctx))
1557         {
1558                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1559                 return ERROR_OK;
1560         }
1561
1562         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1563         {
1564                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1565                 return ERROR_OK;
1566         }
1567
1568         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1569         {
1570                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1571                 command_print(cmd_ctx, "trace capture not completed");
1572                 return ERROR_OK;
1573         }
1574
1575         /* read the trace data if it wasn't read already */
1576         if (etm_ctx->trace_depth == 0)
1577                 etm_ctx->capture_driver->read_trace(etm_ctx);
1578
1579         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1580         {
1581                 return ERROR_OK;
1582         }
1583
1584         fileio_write_u32(&file, etm_ctx->capture_status);
1585         fileio_write_u32(&file, etm_ctx->portmode);
1586         fileio_write_u32(&file, etm_ctx->tracemode);
1587         fileio_write_u32(&file, etm_ctx->trace_depth);
1588
1589         for (i = 0; i < etm_ctx->trace_depth; i++)
1590         {
1591                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1592                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1593                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1594         }
1595
1596         fileio_close(&file);
1597
1598         return ERROR_OK;
1599 }
1600
1601 int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1602 {
1603         fileio_t file;
1604         target_t *target;
1605         armv4_5_common_t *armv4_5;
1606         arm7_9_common_t *arm7_9;
1607         etm_context_t *etm_ctx;
1608         u32 i;
1609
1610         if (argc != 1)
1611         {
1612                 command_print(cmd_ctx, "usage: etm load <file>");
1613                 return ERROR_OK;
1614         }
1615
1616         target = get_current_target(cmd_ctx);
1617
1618         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1619         {
1620                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1621                 return ERROR_OK;
1622         }
1623
1624         if (!(etm_ctx = arm7_9->etm_ctx))
1625         {
1626                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1627                 return ERROR_OK;
1628         }
1629
1630         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1631         {
1632                 command_print(cmd_ctx, "trace capture running, stop first");
1633                 return ERROR_OK;
1634         }
1635
1636         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1637         {
1638                 return ERROR_OK;
1639         }
1640
1641         if (file.size % 4)
1642         {
1643                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1644                 fileio_close(&file);
1645                 return ERROR_OK;
1646         }
1647
1648         if (etm_ctx->trace_depth > 0)
1649         {
1650                 free(etm_ctx->trace_data);
1651                 etm_ctx->trace_data = NULL;
1652         }
1653
1654         fileio_read_u32(&file, &etm_ctx->capture_status);
1655         fileio_read_u32(&file, &etm_ctx->portmode);
1656         fileio_read_u32(&file, &etm_ctx->tracemode);
1657         fileio_read_u32(&file, &etm_ctx->trace_depth);
1658
1659         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1660         if(etm_ctx->trace_data == NULL)
1661         {
1662                 command_print(cmd_ctx, "not enough memory to perform operation");
1663                 fileio_close(&file);
1664                 return ERROR_OK;
1665         }
1666
1667         for (i = 0; i < etm_ctx->trace_depth; i++)
1668         {
1669                 u32 pipestat, packet, flags;
1670                 fileio_read_u32(&file, &pipestat);
1671                 fileio_read_u32(&file, &packet);
1672                 fileio_read_u32(&file, &flags);
1673                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1674                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1675                 etm_ctx->trace_data[i].flags = flags;
1676         }
1677
1678         fileio_close(&file);
1679
1680         return ERROR_OK;
1681 }
1682
1683 int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1684 {
1685         target_t *target;
1686         armv4_5_common_t *armv4_5;
1687         arm7_9_common_t *arm7_9;
1688         etm_context_t *etm_ctx;
1689
1690         target = get_current_target(cmd_ctx);
1691
1692         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1693         {
1694                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1695                 return ERROR_OK;
1696         }
1697
1698         if (!(etm_ctx = arm7_9->etm_ctx))
1699         {
1700                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1701                 return ERROR_OK;
1702         }
1703
1704         if (argc > 0)
1705         {
1706                 u32 new_value = strtoul(args[0], NULL, 0);
1707
1708                 if ((new_value < 2) || (new_value > 100))
1709                 {
1710                         command_print(cmd_ctx, "valid settings are 2% to 100%");
1711                 }
1712                 else
1713                 {
1714                         etm_ctx->trigger_percent = new_value;
1715                 }
1716         }
1717
1718         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
1719
1720         return ERROR_OK;
1721 }
1722
1723 int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1724 {
1725         target_t *target;
1726         armv4_5_common_t *armv4_5;
1727         arm7_9_common_t *arm7_9;
1728         etm_context_t *etm_ctx;
1729         reg_t *etm_ctrl_reg;
1730
1731         target = get_current_target(cmd_ctx);
1732
1733         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1734         {
1735                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1736                 return ERROR_OK;
1737         }
1738
1739         if (!(etm_ctx = arm7_9->etm_ctx))
1740         {
1741                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1742                 return ERROR_OK;
1743         }
1744
1745         /* invalidate old tracing data */
1746         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1747         if (arm7_9->etm_ctx->trace_depth > 0)
1748         {
1749                 free(arm7_9->etm_ctx->trace_data);
1750                 arm7_9->etm_ctx->trace_data = NULL;
1751         }
1752         arm7_9->etm_ctx->trace_depth = 0;
1753
1754         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1755         etm_get_reg(etm_ctrl_reg);
1756
1757         /* Clear programming bit (10), set port selection bit (11) */
1758         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1759
1760         etm_store_reg(etm_ctrl_reg);
1761         jtag_execute_queue();
1762
1763         etm_ctx->capture_driver->start_capture(etm_ctx);
1764
1765         return ERROR_OK;
1766 }
1767
1768 int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1769 {
1770         target_t *target;
1771         armv4_5_common_t *armv4_5;
1772         arm7_9_common_t *arm7_9;
1773         etm_context_t *etm_ctx;
1774         reg_t *etm_ctrl_reg;
1775
1776         target = get_current_target(cmd_ctx);
1777
1778         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1779         {
1780                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1781                 return ERROR_OK;
1782         }
1783
1784         if (!(etm_ctx = arm7_9->etm_ctx))
1785         {
1786                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1787                 return ERROR_OK;
1788         }
1789
1790         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1791         etm_get_reg(etm_ctrl_reg);
1792
1793         /* Set programming bit (10), clear port selection bit (11) */
1794         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1795
1796         etm_store_reg(etm_ctrl_reg);
1797         jtag_execute_queue();
1798
1799         etm_ctx->capture_driver->stop_capture(etm_ctx);
1800
1801         return ERROR_OK;
1802 }
1803
1804 int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1805 {
1806         target_t *target;
1807         armv4_5_common_t *armv4_5;
1808         arm7_9_common_t *arm7_9;
1809         etm_context_t *etm_ctx;
1810         int retval;
1811
1812         target = get_current_target(cmd_ctx);
1813
1814         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1815         {
1816                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1817                 return ERROR_OK;
1818         }
1819
1820         if (!(etm_ctx = arm7_9->etm_ctx))
1821         {
1822                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1823                 return ERROR_OK;
1824         }
1825
1826         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1827         {
1828                 switch(retval)
1829                 {
1830                         case ERROR_ETM_ANALYSIS_FAILED:
1831                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1832                                 break;
1833                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1834                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1835                                 break;
1836                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
1837                                 command_print(cmd_ctx, "no image available for trace analysis");
1838                                 break;
1839                         default:
1840                                 command_print(cmd_ctx, "unknown error: %i", retval);
1841                 }
1842         }
1843
1844         return ERROR_OK;
1845 }
1846
1847 int etm_register_commands(struct command_context_s *cmd_ctx)
1848 {
1849         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1850
1851         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1852
1853         return ERROR_OK;
1854 }
1855
1856 int etm_register_user_commands(struct command_context_s *cmd_ctx)
1857 {
1858         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1859                 COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
1860
1861         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
1862                 COMMAND_EXEC, "display info about the current target's ETM");
1863
1864         register_command(cmd_ctx, etm_cmd, "trigger_percent <percent>", handle_etm_trigger_percent_command,
1865                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1866         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1867                 COMMAND_EXEC, "display current target's ETM status");
1868         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1869                 COMMAND_EXEC, "start ETM trace collection");
1870         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1871                 COMMAND_EXEC, "stop ETM trace collection");
1872
1873         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1874                 COMMAND_EXEC, "anaylze collected ETM trace");
1875
1876         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1877                 COMMAND_EXEC, "load image from <file> [base address]");
1878
1879         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1880                 COMMAND_EXEC, "dump captured trace data <file>");
1881         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1882                 COMMAND_EXEC, "load trace data for analysis <file>");
1883
1884         return ERROR_OK;
1885 }