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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <string.h>
  25
  26 #include "etm.h"
  27 #include "etb.h"
  28
  29 #include "armv4_5.h"
  30 #include "arm7_9_common.h"
  31 #include "arm_disassembler.h"
  32 #include "arm_simulator.h"
  33
  34 #include "log.h"
  35 #include "arm_jtag.h"
  36 #include "types.h"
  37 #include "binarybuffer.h"
  38 #include "target.h"
  39 #include "register.h"
  40 #include "jtag.h"
  41 #include "fileio.h"
  42
  43 #include <stdlib.h>
  44
  45 /* ETM register access functionality
  46  *
  47  */
  48
  49 bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
  50 {
  51         {"R", 1},
  52         {"W", 1},
  53         {"reserved", 26},
  54         {"version", 4}
  55 };
  56
  57 int etm_reg_arch_info[] =
  58 {
  59         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
  60         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
  61         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
  62         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
  63         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
  64         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
  65         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
  66         0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
  67         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
  68         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
  69         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
  70         0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
  71         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
  72         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  73 };
  74
  75 int etm_reg_arch_size_info[] =
  76 {
  77         32, 32, 17, 8, 3, 9, 32, 16,
  78         17, 26, 25, 8, 17, 32, 32, 17,
  79         32, 32, 32, 32, 32, 32, 32, 32,
  80         32, 32, 32, 32, 32, 32, 32, 32,
  81         7, 7, 7, 7, 7, 7, 7, 7,
  82         7, 7, 7, 7, 7, 7, 7, 7,
  83         32, 32, 32, 32, 32, 32, 32, 32,
  84         32, 32, 32, 32, 32, 32, 32, 32,
  85         32, 32, 32, 32, 32, 32, 32, 32,
  86         32, 32, 32, 32, 32, 32, 32, 32,
  87         16, 16, 16, 16, 18, 18, 18, 18,
  88         17, 17, 17, 17, 16, 16, 16, 16,
  89         17, 17, 17, 17, 17, 17, 2,
  90         17, 17, 17, 17, 32, 32, 32, 32
  91 };
  92
  93 char* etm_reg_list[] =
  94 {
  95         "ETM_CTRL",
  96         "ETM_CONFIG",
  97         "ETM_TRIG_EVENT",
  98         "ETM_MMD_CTRL",
  99         "ETM_STATUS",
 100         "ETM_SYS_CONFIG",
 101         "ETM_TRACE_RESOURCE_CTRL",
 102         "ETM_TRACE_EN_CTRL2",
 103         "ETM_TRACE_EN_EVENT",
 104         "ETM_TRACE_EN_CTRL1",
 105         "ETM_FIFOFULL_REGION",
 106         "ETM_FIFOFULL_LEVEL",
 107         "ETM_VIEWDATA_EVENT",
 108         "ETM_VIEWDATA_CTRL1",
 109         "ETM_VIEWDATA_CTRL2",
 110         "ETM_VIEWDATA_CTRL3",
 111         "ETM_ADDR_COMPARATOR_VALUE1",
 112         "ETM_ADDR_COMPARATOR_VALUE2",
 113         "ETM_ADDR_COMPARATOR_VALUE3",
 114         "ETM_ADDR_COMPARATOR_VALUE4",
 115         "ETM_ADDR_COMPARATOR_VALUE5",
 116         "ETM_ADDR_COMPARATOR_VALUE6",
 117         "ETM_ADDR_COMPARATOR_VALUE7",
 118         "ETM_ADDR_COMPARATOR_VALUE8",
 119         "ETM_ADDR_COMPARATOR_VALUE9",
 120         "ETM_ADDR_COMPARATOR_VALUE10",
 121         "ETM_ADDR_COMPARATOR_VALUE11",
 122         "ETM_ADDR_COMPARATOR_VALUE12",
 123         "ETM_ADDR_COMPARATOR_VALUE13",
 124         "ETM_ADDR_COMPARATOR_VALUE14",
 125         "ETM_ADDR_COMPARATOR_VALUE15",
 126         "ETM_ADDR_COMPARATOR_VALUE16",
 127         "ETM_ADDR_ACCESS_TYPE1",
 128         "ETM_ADDR_ACCESS_TYPE2",
 129         "ETM_ADDR_ACCESS_TYPE3",
 130         "ETM_ADDR_ACCESS_TYPE4",
 131         "ETM_ADDR_ACCESS_TYPE5",
 132         "ETM_ADDR_ACCESS_TYPE6",
 133         "ETM_ADDR_ACCESS_TYPE7",
 134         "ETM_ADDR_ACCESS_TYPE8",
 135         "ETM_ADDR_ACCESS_TYPE9",
 136         "ETM_ADDR_ACCESS_TYPE10",
 137         "ETM_ADDR_ACCESS_TYPE11",
 138         "ETM_ADDR_ACCESS_TYPE12",
 139         "ETM_ADDR_ACCESS_TYPE13",
 140         "ETM_ADDR_ACCESS_TYPE14",
 141         "ETM_ADDR_ACCESS_TYPE15",
 142         "ETM_ADDR_ACCESS_TYPE16",
 143         "ETM_DATA_COMPARATOR_VALUE1",
 144         "ETM_DATA_COMPARATOR_VALUE2",
 145         "ETM_DATA_COMPARATOR_VALUE3",
 146         "ETM_DATA_COMPARATOR_VALUE4",
 147         "ETM_DATA_COMPARATOR_VALUE5",
 148         "ETM_DATA_COMPARATOR_VALUE6",
 149         "ETM_DATA_COMPARATOR_VALUE7",
 150         "ETM_DATA_COMPARATOR_VALUE8",
 151         "ETM_DATA_COMPARATOR_VALUE9",
 152         "ETM_DATA_COMPARATOR_VALUE10",
 153         "ETM_DATA_COMPARATOR_VALUE11",
 154         "ETM_DATA_COMPARATOR_VALUE12",
 155         "ETM_DATA_COMPARATOR_VALUE13",
 156         "ETM_DATA_COMPARATOR_VALUE14",
 157         "ETM_DATA_COMPARATOR_VALUE15",
 158         "ETM_DATA_COMPARATOR_VALUE16",
 159         "ETM_DATA_COMPARATOR_MASK1",
 160         "ETM_DATA_COMPARATOR_MASK2",
 161         "ETM_DATA_COMPARATOR_MASK3",
 162         "ETM_DATA_COMPARATOR_MASK4",
 163         "ETM_DATA_COMPARATOR_MASK5",
 164         "ETM_DATA_COMPARATOR_MASK6",
 165         "ETM_DATA_COMPARATOR_MASK7",
 166         "ETM_DATA_COMPARATOR_MASK8",
 167         "ETM_DATA_COMPARATOR_MASK9",
 168         "ETM_DATA_COMPARATOR_MASK10",
 169         "ETM_DATA_COMPARATOR_MASK11",
 170         "ETM_DATA_COMPARATOR_MASK12",
 171         "ETM_DATA_COMPARATOR_MASK13",
 172         "ETM_DATA_COMPARATOR_MASK14",
 173         "ETM_DATA_COMPARATOR_MASK15",
 174         "ETM_DATA_COMPARATOR_MASK16",
 175         "ETM_COUNTER_INITAL_VALUE1",
 176         "ETM_COUNTER_INITAL_VALUE2",
 177         "ETM_COUNTER_INITAL_VALUE3",
 178         "ETM_COUNTER_INITAL_VALUE4",
 179         "ETM_COUNTER_ENABLE1",
 180         "ETM_COUNTER_ENABLE2",
 181         "ETM_COUNTER_ENABLE3",
 182         "ETM_COUNTER_ENABLE4",
 183         "ETM_COUNTER_RELOAD_VALUE1",
 184         "ETM_COUNTER_RELOAD_VALUE2",
 185         "ETM_COUNTER_RELOAD_VALUE3",
 186         "ETM_COUNTER_RELOAD_VALUE4",
 187         "ETM_COUNTER_VALUE1",
 188         "ETM_COUNTER_VALUE2",
 189         "ETM_COUNTER_VALUE3",
 190         "ETM_COUNTER_VALUE4",
 191         "ETM_SEQUENCER_CTRL1",
 192         "ETM_SEQUENCER_CTRL2",
 193         "ETM_SEQUENCER_CTRL3",
 194         "ETM_SEQUENCER_CTRL4",
 195         "ETM_SEQUENCER_CTRL5",
 196         "ETM_SEQUENCER_CTRL6",
 197         "ETM_SEQUENCER_STATE",
 198         "ETM_EXTERNAL_OUTPUT1",
 199         "ETM_EXTERNAL_OUTPUT2",
 200         "ETM_EXTERNAL_OUTPUT3",
 201         "ETM_EXTERNAL_OUTPUT4",
 202         "ETM_CONTEXTID_COMPARATOR_VALUE1",
 203         "ETM_CONTEXTID_COMPARATOR_VALUE2",
 204         "ETM_CONTEXTID_COMPARATOR_VALUE3",
 205         "ETM_CONTEXTID_COMPARATOR_MASK"
 206 };
 207
 208 int etm_reg_arch_type = -1;
 209
 210 int etm_get_reg(reg_t *reg);
 211 int etm_set_reg(reg_t *reg, u32 value);
 212 int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
 213
 214 int etm_write_reg(reg_t *reg, u32 value);
 215 int etm_read_reg(reg_t *reg);
 216
 217 command_t *etm_cmd = NULL;
 218
 219 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 220 {
 221         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 222         reg_t *reg_list = NULL;
 223         etm_reg_t *arch_info = NULL;
 224         int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
 225         int i;
 226         u32 etm_ctrl_value;
 227
 228         /* register a register arch-type for etm registers only once */
 229         if (etm_reg_arch_type == -1)
 230                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
 231
 232         /* the actual registers are kept in two arrays */
 233         reg_list = calloc(num_regs, sizeof(reg_t));
 234         arch_info = calloc(num_regs, sizeof(etm_reg_t));
 235
 236         /* fill in values for the reg cache */
 237         reg_cache->name = "etm registers";
 238         reg_cache->next = NULL;
 239         reg_cache->reg_list = reg_list;
 240         reg_cache->num_regs = num_regs;
 241
 242         /* set up registers */
 243         for (i = 0; i < num_regs; i++)
 244         {
 245                 reg_list[i].name = etm_reg_list[i];
 246                 reg_list[i].size = 32;
 247                 reg_list[i].dirty = 0;
 248                 reg_list[i].valid = 0;
 249                 reg_list[i].bitfield_desc = NULL;
 250                 reg_list[i].num_bitfields = 0;
 251                 reg_list[i].value = calloc(1, 4);
 252                 reg_list[i].arch_info = &arch_info[i];
 253                 reg_list[i].arch_type = etm_reg_arch_type;
 254                 reg_list[i].size = etm_reg_arch_size_info[i];
 255                 arch_info[i].addr = etm_reg_arch_info[i];
 256                 arch_info[i].jtag_info = jtag_info;
 257         }
 258
 259         /* initialize some ETM control register settings */
 260         etm_get_reg(&reg_list[ETM_CTRL]);
 261         etm_ctrl_value = buf_get_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size);
 262
 263         /* clear the ETM powerdown bit (0) */
 264         etm_ctrl_value &= ~0x1;
 265
 266         /* configure port width (6:4), mode (17:16) and clocking (13) */
 267         etm_ctrl_value = (etm_ctrl_value &
 268                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
 269                 | etm_ctx->portmode;
 270
 271         buf_set_u32(reg_list[ETM_CTRL].value, 0, reg_list[ETM_CTRL].size, etm_ctrl_value);
 272         etm_store_reg(&reg_list[ETM_CTRL]);
 273
 274         /* the ETM might have an ETB connected */
 275         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 276         {
 277                 etb_t *etb = etm_ctx->capture_driver_priv;
 278
 279                 if (!etb)
 280                 {
 281                         ERROR("etb selected as etm capture driver, but no ETB configured");
 282                         return ERROR_OK;
 283                 }
 284
 285                 reg_cache->next = etb_build_reg_cache(etb);
 286
 287                 etb->reg_cache = reg_cache->next;
 288
 289                 if (etm_ctx->capture_driver->init(etm_ctx) != ERROR_OK)
 290                 {
 291                         ERROR("ETM capture driver initialization failed");
 292                         exit(-1);
 293                 }
 294         }
 295
 296         return reg_cache;
 297 }
 298
 299 int etm_get_reg(reg_t *reg)
 300 {
 301         if (etm_read_reg(reg) != ERROR_OK)
 302         {
 303                 ERROR("BUG: error scheduling etm register read");
 304                 exit(-1);
 305         }
 306
 307         if (jtag_execute_queue() != ERROR_OK)
 308         {
 309                 ERROR("register read failed");
 310         }
 311
 312         return ERROR_OK;
 313 }
 314
 315 int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 316 {
 317         etm_reg_t *etm_reg = reg->arch_info;
 318         u8 reg_addr = etm_reg->addr & 0x7f;
 319         scan_field_t fields[3];
 320
 321         DEBUG("%i", etm_reg->addr);
 322
 323         jtag_add_end_state(TAP_RTI);
 324         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 325         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 326
 327         fields[0].device = etm_reg->jtag_info->chain_pos;
 328         fields[0].num_bits = 32;
 329         fields[0].out_value = reg->value;
 330         fields[0].out_mask = NULL;
 331         fields[0].in_value = NULL;
 332         fields[0].in_check_value = NULL;
 333         fields[0].in_check_mask = NULL;
 334         fields[0].in_handler = NULL;
 335         fields[0].in_handler_priv = NULL;
 336
 337         fields[1].device = etm_reg->jtag_info->chain_pos;
 338         fields[1].num_bits = 7;
 339         fields[1].out_value = malloc(1);
 340         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 341         fields[1].out_mask = NULL;
 342         fields[1].in_value = NULL;
 343         fields[1].in_check_value = NULL;
 344         fields[1].in_check_mask = NULL;
 345         fields[1].in_handler = NULL;
 346         fields[1].in_handler_priv = NULL;
 347
 348         fields[2].device = etm_reg->jtag_info->chain_pos;
 349         fields[2].num_bits = 1;
 350         fields[2].out_value = malloc(1);
 351         buf_set_u32(fields[2].out_value, 0, 1, 0);
 352         fields[2].out_mask = NULL;
 353         fields[2].in_value = NULL;
 354         fields[2].in_check_value = NULL;
 355         fields[2].in_check_mask = NULL;
 356         fields[2].in_handler = NULL;
 357         fields[2].in_handler_priv = NULL;
 358
 359         jtag_add_dr_scan(3, fields, -1, NULL);
 360
 361         fields[0].in_value = reg->value;
 362         fields[0].in_check_value = check_value;
 363         fields[0].in_check_mask = check_mask;
 364
 365         jtag_add_dr_scan(3, fields, -1, NULL);
 366
 367         free(fields[1].out_value);
 368         free(fields[2].out_value);
 369
 370         return ERROR_OK;
 371 }
 372
 373 int etm_read_reg(reg_t *reg)
 374 {
 375         return etm_read_reg_w_check(reg, NULL, NULL);
 376 }
 377
 378 int etm_set_reg(reg_t *reg, u32 value)
 379 {
 380         if (etm_write_reg(reg, value) != ERROR_OK)
 381         {
 382                 ERROR("BUG: error scheduling etm register write");
 383                 exit(-1);
 384         }
 385
 386         buf_set_u32(reg->value, 0, reg->size, value);
 387         reg->valid = 1;
 388         reg->dirty = 0;
 389
 390         return ERROR_OK;
 391 }
 392
 393 int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
 394 {
 395         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 396
 397         if (jtag_execute_queue() != ERROR_OK)
 398         {
 399                 ERROR("register write failed");
 400                 exit(-1);
 401         }
 402         return ERROR_OK;
 403 }
 404
 405 int etm_write_reg(reg_t *reg, u32 value)
 406 {
 407         etm_reg_t *etm_reg = reg->arch_info;
 408         u8 reg_addr = etm_reg->addr & 0x7f;
 409         scan_field_t fields[3];
 410
 411         DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
 412
 413         jtag_add_end_state(TAP_RTI);
 414         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 415         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 416
 417         fields[0].device = etm_reg->jtag_info->chain_pos;
 418         fields[0].num_bits = 32;
 419         fields[0].out_value = malloc(4);
 420         buf_set_u32(fields[0].out_value, 0, 32, value);
 421         fields[0].out_mask = NULL;
 422         fields[0].in_value = NULL;
 423         fields[0].in_check_value = NULL;
 424         fields[0].in_check_mask = NULL;
 425         fields[0].in_handler = NULL;
 426         fields[0].in_handler_priv = NULL;
 427
 428         fields[1].device = etm_reg->jtag_info->chain_pos;
 429         fields[1].num_bits = 7;
 430         fields[1].out_value = malloc(1);
 431         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 432         fields[1].out_mask = NULL;
 433         fields[1].in_value = NULL;
 434         fields[1].in_check_value = NULL;
 435         fields[1].in_check_mask = NULL;
 436         fields[1].in_handler = NULL;
 437         fields[1].in_handler_priv = NULL;
 438
 439         fields[2].device = etm_reg->jtag_info->chain_pos;
 440         fields[2].num_bits = 1;
 441         fields[2].out_value = malloc(1);
 442         buf_set_u32(fields[2].out_value, 0, 1, 1);
 443         fields[2].out_mask = NULL;
 444         fields[2].in_value = NULL;
 445         fields[2].in_check_value = NULL;
 446         fields[2].in_check_mask = NULL;
 447         fields[2].in_handler = NULL;
 448         fields[2].in_handler_priv = NULL;
 449
 450         jtag_add_dr_scan(3, fields, -1, NULL);
 451
 452         free(fields[0].out_value);
 453         free(fields[1].out_value);
 454         free(fields[2].out_value);
 455
 456         return ERROR_OK;
 457 }
 458
 459 int etm_store_reg(reg_t *reg)
 460 {
 461         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 462 }
 463
 464 /* ETM trace analysis functionality
 465  *
 466  */
 467 extern etm_capture_driver_t etb_capture_driver;
 468 extern etm_capture_driver_t etm_dummy_capture_driver;
 469
 470 etm_capture_driver_t *etm_capture_drivers[] =
 471 {
 472         &etb_capture_driver,
 473         &etm_dummy_capture_driver,
 474         NULL
 475 };
 476
 477 char *etmv1v1_branch_reason_strings[] =
 478 {
 479         "normal PC change",
 480         "tracing enabled",
 481         "trace restarted after overflow",
 482         "exit from debug",
 483         "periodic synchronization",
 484         "reserved",
 485         "reserved",
 486         "reserved",
 487 };
 488
 489 int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 490 {
 491         int i;
 492         int section = -1;
 493         u32 size_read;
 494         u32 opcode;
 495         int retval;
 496
 497         if (!ctx->image)
 498                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 499
 500         /* search for the section the current instruction belongs to */
 501         for (i = 0; i < ctx->image->num_sections; i++)
 502         {
 503                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 504                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 505                 {
 506                         section = i;
 507                         break;
 508                 }
 509         }
 510
 511         if (section == -1)
 512         {
 513                 /* current instruction couldn't be found in the image */
 514                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 515         }
 516
 517         if (ctx->core_state == ARMV4_5_STATE_ARM)
 518         {
 519                 u8 buf[4];
 520                 if ((retval = image_read_section(ctx->image, section,
 521                         ctx->current_pc - ctx->image->sections[section].base_address,
 522                         4, buf, &size_read)) != ERROR_OK)
 523                 {
 524                         ERROR("error while reading instruction: %i", retval);
 525                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 526                 }
 527                 opcode = target_buffer_get_u32(ctx->target, buf);
 528                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 529         }
 530         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 531         {
 532                 u8 buf[2];
 533                 if ((retval = image_read_section(ctx->image, section,
 534                         ctx->current_pc - ctx->image->sections[section].base_address,
 535                         2, buf, &size_read)) != ERROR_OK)
 536                 {
 537                         ERROR("error while reading instruction: %i", retval);
 538                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 539                 }
 540                 opcode = target_buffer_get_u16(ctx->target, buf);
 541                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 542         }
 543         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 544         {
 545                 ERROR("BUG: tracing of jazelle code not supported");
 546                 exit(-1);
 547         }
 548         else
 549         {
 550                 ERROR("BUG: unknown core state encountered");
 551                 exit(-1);
 552         }
 553
 554         return ERROR_OK;
 555 }
 556
 557 int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo)
 558 {
 559         while (ctx->data_index < ctx->trace_depth)
 560         {
 561                 /* if the caller specified an address packet offset, skip until the
 562                  * we reach the n-th cycle marked with tracesync */
 563                 if (apo > 0)
 564                 {
 565                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 566                                 apo--;
 567
 568                         if (apo > 0)
 569                         {
 570                                 ctx->data_index++;
 571                                 ctx->data_half = 0;
 572                         }
 573                         continue;
 574                 }
 575
 576                 /* no tracedata output during a TD cycle
 577                  * or in a trigger cycle */
 578                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 579                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 580                 {
 581                         ctx->data_index++;
 582                         ctx->data_half = 0;
 583                         continue;
 584                 }
 585
 586                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 587                 {
 588                         if (ctx->data_half == 0)
 589                         {
 590                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 591                                 ctx->data_half = 1;
 592                         }
 593                         else
 594                         {
 595                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 596                                 ctx->data_half = 0;
 597                                 ctx->data_index++;
 598                         }
 599                 }
 600                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 601                 {
 602                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 603                         ctx->data_index++;
 604                 }
 605                 else
 606                 {
 607                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 608                         if (ctx->data_index > (ctx->trace_depth - 2))
 609                                 return -1;
 610
 611                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 612                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 613                         ctx->data_index += 2;
 614                 }
 615
 616                 return 0;
 617         }
 618
 619         return -1;
 620 }
 621
 622 int etmv1_branch_address(etm_context_t *ctx)
 623 {
 624         int retval;
 625         u8 packet;
 626         int shift = 0;
 627         int apo;
 628         int i;
 629
 630         /* quit analysis if less than two cycles are left in the trace
 631          * because we can't extract the APO */
 632         if (ctx->data_index > (ctx->trace_depth - 2))
 633                 return -1;
 634
 635         /* a BE could be output during an APO cycle, skip the current
 636          * and continue with the new one */
 637         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 638                 return 1;
 639         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 640                 return 2;
 641
 642         /* address packet offset encoded in the next two cycles' pipestat bits */
 643         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 644         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 645
 646         /* count number of tracesync cycles between current pipe_index and data_index
 647          * i.e. the number of tracesyncs that data_index already passed by
 648          * to subtract them from the APO */
 649         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 650         {
 651                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 652                         apo--;
 653         }
 654
 655         /* extract up to four 7-bit packets */
 656         do {
 657                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 658                         return -1;
 659                 ctx->last_branch &= ~(0x7f << shift);
 660                 ctx->last_branch |= (packet & 0x7f) << shift;
 661                 shift += 7;
 662         } while ((packet & 0x80) && (shift < 28));
 663
 664         /* one last packet holding 4 bits of the address, plus the branch reason code */
 665         if ((shift == 28) && (packet & 0x80))
 666         {
 667                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 668                         return -1;
 669                 ctx->last_branch &= 0x0fffffff;
 670                 ctx->last_branch |= (packet & 0x0f) << 28;
 671                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 672                 shift += 4;
 673         }
 674         else
 675         {
 676                 ctx->last_branch_reason = 0;
 677         }
 678
 679         if (shift == 32)
 680         {
 681                 ctx->pc_ok = 1;
 682         }
 683
 684         /* if a full address was output, we might have branched into Jazelle state */
 685         if ((shift == 32) && (packet & 0x80))
 686         {
 687                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 688         }
 689         else
 690         {
 691                 /* if we didn't branch into Jazelle state, the current processor state is
 692                  * encoded in bit 0 of the branch target address */
 693                 if (ctx->last_branch & 0x1)
 694                 {
 695                         ctx->core_state = ARMV4_5_STATE_THUMB;
 696                         ctx->last_branch &= ~0x1;
 697                 }
 698                 else
 699                 {
 700                         ctx->core_state = ARMV4_5_STATE_ARM;
 701                         ctx->last_branch &= ~0x3;
 702                 }
 703         }
 704
 705         return 0;
 706 }
 707
 708 int etmv1_data(etm_context_t *ctx, int size, u32 *data)
 709 {
 710         int j;
 711         u8 buf[4];
 712         int retval;
 713
 714         for (j = 0; j < size; j++)
 715         {
 716                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 717                         return -1;
 718         }
 719
 720         if (size == 8)
 721                 ERROR("TODO: add support for 64-bit values");
 722         else if (size == 4)
 723                 *data = target_buffer_get_u32(ctx->target, buf);
 724         else if (size == 2)
 725                 *data = target_buffer_get_u16(ctx->target, buf);
 726         else if (size == 1)
 727                 *data = buf[0];
 728
 729         return 0;
 730 }
 731
 732 int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
 733 {
 734         int retval;
 735         arm_instruction_t instruction;
 736
 737         /* read the trace data if it wasn't read already */
 738         if (ctx->trace_depth == 0)
 739                 ctx->capture_driver->read_trace(ctx);
 740
 741         /* start at the beginning of the captured trace */
 742         ctx->pipe_index = 0;
 743         ctx->data_index = 0;
 744         ctx->data_half = 0;
 745
 746         /* neither the PC nor the data pointer are valid */
 747         ctx->pc_ok = 0;
 748         ctx->ptr_ok = 0;
 749
 750         while (ctx->pipe_index < ctx->trace_depth)
 751         {
 752                 u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 753                 u32 next_pc = ctx->current_pc;
 754                 u32 old_data_index = ctx->data_index;
 755                 u32 old_data_half = ctx->data_half;
 756
 757                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 758                 {
 759                         command_print(cmd_ctx, "--- trigger ---");
 760                 }
 761
 762                 /* if we don't have a valid pc skip until we reach an indirect branch */
 763                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 764                 {
 765                         ctx->pipe_index++;
 766                         continue;
 767                 }
 768
 769                 /* any indirect branch could have interrupted instruction flow
 770                  * - the branch reason code could indicate a trace discontinuity
 771                  * - a branch to the exception vectors indicates an exception
 772                  */
 773                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 774                 {
 775                         /* backup current data index, to be able to consume the branch address
 776                          * before examining data address and values
 777                          */
 778                         old_data_index = ctx->data_index;
 779                         old_data_half = ctx->data_half;
 780
 781                         if ((retval = etmv1_branch_address(ctx)) != 0)
 782                         {
 783                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 784                                  * quit analysing the trace */
 785                                 if (retval < 0)
 786                                         break;
 787
 788                                 /* a positive return values means the current branch was abandoned,
 789                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 790                                  */
 791                                 WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 792                                 ctx->pipe_index += retval;
 793                                 continue;
 794                         }
 795
 796                         /* skip over APO cycles */
 797                         ctx->pipe_index += 2;
 798
 799                         switch (ctx->last_branch_reason)
 800                         {
 801                                 case 0x0:       /* normal PC change */
 802                                         next_pc = ctx->last_branch;
 803                                         break;
 804                                 case 0x1:       /* tracing enabled */
 805                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
 806                                         ctx->current_pc = ctx->last_branch;
 807                                         ctx->pipe_index++;
 808                                         continue;
 809                                         break;
 810                                 case 0x2:       /* trace restarted after FIFO overflow */
 811                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
 812                                         ctx->current_pc = ctx->last_branch;
 813                                         ctx->pipe_index++;
 814                                         continue;
 815                                         break;
 816                                 case 0x3:       /* exit from debug state */
 817                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
 818                                         ctx->current_pc = ctx->last_branch;
 819                                         ctx->pipe_index++;
 820                                         continue;
 821                                         break;
 822                                 case 0x4:       /* periodic synchronization point */
 823                                         next_pc = ctx->last_branch;
 824                                         break;
 825                                 default:        /* reserved */
 826                                         ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
 827                                         exit(-1);
 828                                         break;
 829                         }
 830
 831                         /* if we got here the branch was a normal PC change
 832                          * (or a periodic synchronization point, which means the same for that matter)
 833                          * if we didn't accquire a complete PC continue with the next cycle
 834                          */
 835                         if (!ctx->pc_ok)
 836                                 continue;
 837
 838                         /* indirect branch to the exception vector means an exception occured */
 839                         if (((ctx->last_branch >= 0x0) && (ctx->last_branch <= 0x20))
 840                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
 841                         {
 842                                 if ((ctx->last_branch & 0xff) == 0x10)
 843                                 {
 844                                         command_print(cmd_ctx, "data abort");
 845                                 }
 846                                 else
 847                                 {
 848                                         command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
 849                                         ctx->current_pc = ctx->last_branch;
 850                                         ctx->pipe_index++;
 851                                         continue;
 852                                 }
 853                         }
 854                 }
 855
 856                 /* an instruction was executed (or not, depending on the condition flags)
 857                  * retrieve it from the image for displaying */
 858                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
 859                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
 860                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
 861                 {
 862                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
 863                         {
 864                                 /* can't continue tracing with no image available */
 865                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
 866                                 {
 867                                         return retval;
 868                                 }
 869                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
 870                                 {
 871                                         /* TODO: handle incomplete images */
 872                                 }
 873                         }
 874                 }
 875
 876                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
 877                 {
 878                         u32 new_data_index = ctx->data_index;
 879                         u32 new_data_half = ctx->data_half;
 880
 881                         /* in case of a branch with data, the branch target address was consumed before
 882                          * we temporarily go back to the saved data index */
 883                         if (pipestat == STAT_BD)
 884                         {
 885                                 ctx->data_index = old_data_index;
 886                                 ctx->data_half = old_data_half;
 887                         }
 888
 889                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
 890                         {
 891                                 u8 packet;
 892                                 int shift = 0;
 893
 894                                 do {
 895                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 896                                                 return -1;
 897                                         ctx->last_ptr &= ~(0x7f << shift);
 898                                         ctx->last_ptr |= (packet & 0x7f) << shift;
 899                                         shift += 7;
 900                                 } while ((packet & 0x80) && (shift < 32));
 901
 902                                 if (shift >= 32)
 903                                         ctx->ptr_ok = 1;
 904
 905                                 if (ctx->ptr_ok)
 906                                 {
 907                                         command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
 908                                 }
 909                         }
 910
 911                         if (ctx->tracemode & ETMV1_TRACE_DATA)
 912                         {
 913                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
 914                                 {
 915                                         int i;
 916                                         for (i = 0; i < 16; i++)
 917                                         {
 918                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
 919                                                 {
 920                                                         u32 data;
 921                                                         if (etmv1_data(ctx, 4, &data) != 0)
 922                                                                 return -1;
 923                                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 924                                                 }
 925                                         }
 926                                 }
 927                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
 928                                 {
 929                                         u32 data;
 930                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
 931                                                 return -1;
 932                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
 933                                 }
 934                         }
 935
 936                         /* restore data index after consuming BD address and data */
 937                         if (pipestat == STAT_BD)
 938                         {
 939                                 ctx->data_index = new_data_index;
 940                                 ctx->data_half = new_data_half;
 941                         }
 942                 }
 943
 944                 /* adjust PC */
 945                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 946                 {
 947                         if (((instruction.type == ARM_B) ||
 948                                 (instruction.type == ARM_BL) ||
 949                                 (instruction.type == ARM_BLX)) &&
 950                                 (instruction.info.b_bl_bx_blx.target_address != -1))
 951                         {
 952                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
 953                         }
 954                         else
 955                         {
 956                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 957                         }
 958                 }
 959                 else if (pipestat == STAT_IN)
 960                 {
 961                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
 962                 }
 963
 964                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
 965                 {
 966                         command_print(cmd_ctx, "%s%s",
 967                                 instruction.text, (pipestat == STAT_IN) ? " (not executed)" : "");
 968
 969                         ctx->current_pc = next_pc;
 970
 971                         /* packets for an instruction don't start on or before the preceding
 972                          * functional pipestat (i.e. other than WT or TD)
 973                          */
 974                         if (ctx->data_index <= ctx->pipe_index)
 975                         {
 976                                 ctx->data_index = ctx->pipe_index + 1;
 977                                 ctx->data_half = 0;
 978                         }
 979                 }
 980
 981                 ctx->pipe_index += 1;
 982         }
 983
 984         return ERROR_OK;
 985 }
 986
 987 int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 988 {
 989         target_t *target;
 990         armv4_5_common_t *armv4_5;
 991         arm7_9_common_t *arm7_9;
 992         etmv1_tracemode_t tracemode;
 993
 994         target = get_current_target(cmd_ctx);
 995
 996         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 997         {
 998                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 999                 return ERROR_OK;
1000         }
1001
1002         if (!arm7_9->etm_ctx)
1003         {
1004                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1005                 return ERROR_OK;
1006         }
1007
1008         tracemode = arm7_9->etm_ctx->tracemode;
1009
1010         if (argc == 4)
1011         {
1012                 if (strcmp(args[0], "none") == 0)
1013                 {
1014                         tracemode = ETMV1_TRACE_NONE;
1015                 }
1016                 else if (strcmp(args[0], "data") == 0)
1017                 {
1018                         tracemode = ETMV1_TRACE_DATA;
1019                 }
1020                 else if (strcmp(args[0], "address") == 0)
1021                 {
1022                         tracemode = ETMV1_TRACE_ADDR;
1023                 }
1024                 else if (strcmp(args[0], "all") == 0)
1025                 {
1026                         tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1027                 }
1028                 else
1029                 {
1030                         command_print(cmd_ctx, "invalid option '%s'", args[0]);
1031                         return ERROR_OK;
1032                 }
1033
1034                 switch (strtol(args[1], NULL, 0))
1035                 {
1036                         case 0:
1037                                 tracemode |= ETMV1_CONTEXTID_NONE;
1038                                 break;
1039                         case 8:
1040                                 tracemode |= ETMV1_CONTEXTID_8;
1041                                 break;
1042                         case 16:
1043                                 tracemode |= ETMV1_CONTEXTID_16;
1044                                 break;
1045                         case 32:
1046                                 tracemode |= ETMV1_CONTEXTID_32;
1047                                 break;
1048                         default:
1049                                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1050                                 return ERROR_OK;
1051                 }
1052
1053                 if (strcmp(args[2], "enable") == 0)
1054                 {
1055                         tracemode |= ETMV1_CYCLE_ACCURATE;
1056                 }
1057                 else if (strcmp(args[2], "disable") == 0)
1058                 {
1059                         tracemode |= 0;
1060                 }
1061                 else
1062                 {
1063                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1064                         return ERROR_OK;
1065                 }
1066
1067                 if (strcmp(args[3], "enable") == 0)
1068                 {
1069                         tracemode |= ETMV1_BRANCH_OUTPUT;
1070                 }
1071                 else if (strcmp(args[3], "disable") == 0)
1072                 {
1073                         tracemode |= 0;
1074                 }
1075                 else
1076                 {
1077                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1078                         return ERROR_OK;
1079                 }
1080         }
1081         else if (argc != 0)
1082         {
1083                 command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1084                 return ERROR_OK;
1085         }
1086
1087         command_print(cmd_ctx, "current tracemode configuration:");
1088
1089         switch (tracemode & ETMV1_TRACE_MASK)
1090         {
1091                 case ETMV1_TRACE_NONE:
1092                         command_print(cmd_ctx, "data tracing: none");
1093                         break;
1094                 case ETMV1_TRACE_DATA:
1095                         command_print(cmd_ctx, "data tracing: data only");
1096                         break;
1097                 case ETMV1_TRACE_ADDR:
1098                         command_print(cmd_ctx, "data tracing: address only");
1099                         break;
1100                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1101                         command_print(cmd_ctx, "data tracing: address and data");
1102                         break;
1103         }
1104
1105         switch (tracemode & ETMV1_CONTEXTID_MASK)
1106         {
1107                 case ETMV1_CONTEXTID_NONE:
1108                         command_print(cmd_ctx, "contextid tracing: none");
1109                         break;
1110                 case ETMV1_CONTEXTID_8:
1111                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1112                         break;
1113                 case ETMV1_CONTEXTID_16:
1114                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1115                         break;
1116                 case ETMV1_CONTEXTID_32:
1117                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1118                         break;
1119         }
1120
1121         if (tracemode & ETMV1_CYCLE_ACCURATE)
1122         {
1123                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1124         }
1125         else
1126         {
1127                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1128         }
1129
1130         if (tracemode & ETMV1_BRANCH_OUTPUT)
1131         {
1132                 command_print(cmd_ctx, "full branch address output enabled");
1133         }
1134         else
1135         {
1136                 command_print(cmd_ctx, "full branch address output disabled");
1137         }
1138
1139         /* only update ETM_CTRL register if tracemode changed */
1140         if (arm7_9->etm_ctx->tracemode != tracemode)
1141         {
1142                 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1143
1144                 etm_get_reg(etm_ctrl_reg);
1145
1146                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1147                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1148                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1149                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1150                 etm_store_reg(etm_ctrl_reg);
1151
1152                 arm7_9->etm_ctx->tracemode = tracemode;
1153
1154                 /* invalidate old trace data */
1155                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1156                 if (arm7_9->etm_ctx->trace_depth > 0)
1157                 {
1158                         free(arm7_9->etm_ctx->trace_data);
1159                 }
1160                 arm7_9->etm_ctx->trace_depth = 0;
1161         }
1162
1163         return ERROR_OK;
1164 }
1165
1166 int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1167 {
1168         target_t *target;
1169         armv4_5_common_t *armv4_5;
1170         arm7_9_common_t *arm7_9;
1171         etm_portmode_t portmode = 0x0;
1172         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1173         int i;
1174
1175         if (argc != 5)
1176         {
1177                 ERROR("incomplete 'etm config <target> <port_width> <port_mode> <clocking> <capture_driver>' command");
1178                 exit(-1);
1179         }
1180
1181         target = get_target_by_num(strtoul(args[0], NULL, 0));
1182
1183         if (!target)
1184         {
1185                 ERROR("target number '%s' not defined", args[0]);
1186                 exit(-1);
1187         }
1188
1189         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1190         {
1191                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1192                 return ERROR_OK;
1193         }
1194
1195         switch (strtoul(args[1], NULL, 0))
1196         {
1197                 case 4:
1198                         portmode |= ETM_PORT_4BIT;
1199                         break;
1200                 case 8:
1201                         portmode |= ETM_PORT_8BIT;
1202                         break;
1203                 case 16:
1204                         portmode |= ETM_PORT_16BIT;
1205                         break;
1206                 default:
1207                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1208                         return ERROR_OK;
1209         }
1210
1211         if (strcmp("normal", args[2]) == 0)
1212         {
1213                 portmode |= ETM_PORT_NORMAL;
1214         }
1215         else if (strcmp("multiplexed", args[2]) == 0)
1216         {
1217                 portmode |= ETM_PORT_MUXED;
1218         }
1219         else if (strcmp("demultiplexed", args[2]) == 0)
1220         {
1221                 portmode |= ETM_PORT_DEMUXED;
1222         }
1223         else
1224         {
1225                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1226                 return ERROR_OK;
1227         }
1228
1229         if (strcmp("half", args[3]) == 0)
1230         {
1231                 portmode |= ETM_PORT_HALF_CLOCK;
1232         }
1233         else if (strcmp("full", args[3]) == 0)
1234         {
1235                 portmode |= ETM_PORT_FULL_CLOCK;
1236         }
1237         else
1238         {
1239                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1240                 return ERROR_OK;
1241         }
1242
1243         for (i=0; etm_capture_drivers[i]; i++)
1244         {
1245                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1246                 {
1247                         if (etm_capture_drivers[i]->register_commands(cmd_ctx) != ERROR_OK)
1248                         {
1249                                 free(etm_ctx);
1250                                 exit(-1);
1251                         }
1252
1253                         etm_ctx->capture_driver = etm_capture_drivers[i];
1254
1255                         break;
1256                 }
1257         }
1258
1259         if (!etm_capture_drivers[i])
1260         {
1261                 /* no supported capture driver found, don't register an ETM */
1262                 free(etm_ctx);
1263                 ERROR("trace capture driver '%s' not found", args[4]);
1264                 return ERROR_OK;
1265         }
1266
1267         etm_ctx->target = target;
1268         etm_ctx->trace_data = NULL;
1269         etm_ctx->trace_depth = 0;
1270         etm_ctx->portmode = portmode;
1271         etm_ctx->tracemode = 0x0;
1272         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1273         etm_ctx->image = NULL;
1274         etm_ctx->pipe_index = 0;
1275         etm_ctx->data_index = 0;
1276         etm_ctx->current_pc = 0x0;
1277         etm_ctx->pc_ok = 0;
1278         etm_ctx->last_branch = 0x0;
1279         etm_ctx->last_branch_reason = 0x0;
1280         etm_ctx->last_ptr = 0x0;
1281         etm_ctx->ptr_ok = 0x0;
1282         etm_ctx->context_id = 0x0;
1283
1284         arm7_9->etm_ctx = etm_ctx;
1285
1286         etm_register_user_commands(cmd_ctx);
1287
1288         return ERROR_OK;
1289 }
1290
1291 int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1292 {
1293         target_t *target;
1294         armv4_5_common_t *armv4_5;
1295         arm7_9_common_t *arm7_9;
1296         trace_status_t trace_status;
1297
1298         target = get_current_target(cmd_ctx);
1299
1300         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1301         {
1302                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1303                 return ERROR_OK;
1304         }
1305
1306         if (!arm7_9->etm_ctx)
1307         {
1308                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1309                 return ERROR_OK;
1310         }
1311
1312         trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1313
1314         if (trace_status == TRACE_IDLE)
1315         {
1316                 command_print(cmd_ctx, "tracing is idle");
1317         }
1318         else
1319         {
1320                 static char *completed = " completed";
1321                 static char *running = " is running";
1322                 static char *overflowed = ", trace overflowed";
1323                 static char *triggered = ", trace triggered";
1324
1325                 command_print(cmd_ctx, "trace collection%s%s%s",
1326                         (trace_status & TRACE_RUNNING) ? running : completed,
1327                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1328                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1329
1330                 if (arm7_9->etm_ctx->trace_depth > 0)
1331                 {
1332                         command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
1333                 }
1334         }
1335
1336         return ERROR_OK;
1337 }
1338
1339 int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1340 {
1341         target_t *target;
1342         armv4_5_common_t *armv4_5;
1343         arm7_9_common_t *arm7_9;
1344         etm_context_t *etm_ctx;
1345
1346         if (argc < 1)
1347         {
1348                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1349                 return ERROR_OK;
1350         }
1351
1352         target = get_current_target(cmd_ctx);
1353
1354         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1355         {
1356                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1357                 return ERROR_OK;
1358         }
1359
1360         if (!(etm_ctx = arm7_9->etm_ctx))
1361         {
1362                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1363                 return ERROR_OK;
1364         }
1365
1366         if (etm_ctx->image)
1367         {
1368                 image_close(etm_ctx->image);
1369                 free(etm_ctx->image);
1370                 command_print(cmd_ctx, "previously loaded image found and closed");
1371         }
1372
1373         etm_ctx->image = malloc(sizeof(image_t));
1374         etm_ctx->image->base_address_set = 0;
1375         etm_ctx->image->start_address_set = 0;
1376
1377         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1378         if (argc >= 2)
1379         {
1380                 etm_ctx->image->base_address_set = 1;
1381                 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1382         }
1383         else
1384         {
1385                 etm_ctx->image->base_address_set = 0;
1386         }
1387
1388         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1389         {
1390                 command_print(cmd_ctx, "image opening error: %s", etm_ctx->image->error_str);
1391                 free(etm_ctx->image);
1392                 etm_ctx->image = NULL;
1393                 return ERROR_OK;
1394         }
1395
1396         return ERROR_OK;
1397 }
1398
1399 int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1400 {
1401         fileio_t file;
1402         target_t *target;
1403         armv4_5_common_t *armv4_5;
1404         arm7_9_common_t *arm7_9;
1405         etm_context_t *etm_ctx;
1406         int i;
1407
1408         if (argc != 1)
1409         {
1410                 command_print(cmd_ctx, "usage: etm dump <file>");
1411                 return ERROR_OK;
1412         }
1413
1414         target = get_current_target(cmd_ctx);
1415
1416         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1417         {
1418                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1419                 return ERROR_OK;
1420         }
1421
1422         if (!(etm_ctx = arm7_9->etm_ctx))
1423         {
1424                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1425                 return ERROR_OK;
1426         }
1427
1428         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1429         {
1430                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1431                 return ERROR_OK;
1432         }
1433
1434         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1435         {
1436                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1437                 command_print(cmd_ctx, "trace capture not completed");
1438                 return ERROR_OK;
1439         }
1440
1441         /* read the trace data if it wasn't read already */
1442         if (etm_ctx->trace_depth == 0)
1443                 etm_ctx->capture_driver->read_trace(etm_ctx);
1444
1445         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1446         {
1447                 command_print(cmd_ctx, "file open error: %s", file.error_str);
1448                 return ERROR_OK;
1449         }
1450
1451         fileio_write_u32(&file, etm_ctx->capture_status);
1452         fileio_write_u32(&file, etm_ctx->portmode);
1453         fileio_write_u32(&file, etm_ctx->tracemode);
1454         fileio_write_u32(&file, etm_ctx->trace_depth);
1455
1456         for (i = 0; i < etm_ctx->trace_depth; i++)
1457         {
1458                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1459                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1460                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1461         }
1462
1463         fileio_close(&file);
1464
1465         return ERROR_OK;
1466 }
1467
1468 int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1469 {
1470         fileio_t file;
1471         target_t *target;
1472         armv4_5_common_t *armv4_5;
1473         arm7_9_common_t *arm7_9;
1474         etm_context_t *etm_ctx;
1475         int i;
1476
1477         if (argc != 1)
1478         {
1479                 command_print(cmd_ctx, "usage: etm load <file>");
1480                 return ERROR_OK;
1481         }
1482
1483         target = get_current_target(cmd_ctx);
1484
1485         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1486         {
1487                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1488                 return ERROR_OK;
1489         }
1490
1491         if (!(etm_ctx = arm7_9->etm_ctx))
1492         {
1493                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1494                 return ERROR_OK;
1495         }
1496
1497         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1498         {
1499                 command_print(cmd_ctx, "trace capture running, stop first");
1500                 return ERROR_OK;
1501         }
1502
1503         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1504         {
1505                 command_print(cmd_ctx, "file open error: %s", file.error_str);
1506                 return ERROR_OK;
1507         }
1508
1509         if (file.size % 4)
1510         {
1511                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1512                 return ERROR_OK;
1513         }
1514
1515         if (etm_ctx->trace_depth > 0)
1516         {
1517                 free(etm_ctx->trace_data);
1518         }
1519
1520         fileio_read_u32(&file, &etm_ctx->capture_status);
1521         fileio_read_u32(&file, &etm_ctx->portmode);
1522         fileio_read_u32(&file, &etm_ctx->tracemode);
1523         fileio_read_u32(&file, &etm_ctx->trace_depth);
1524
1525         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1526
1527         for (i = 0; i < etm_ctx->trace_depth; i++)
1528         {
1529                 u32 pipestat, packet, flags;
1530                 fileio_read_u32(&file, &pipestat);
1531                 fileio_read_u32(&file, &packet);
1532                 fileio_read_u32(&file, &flags);
1533                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1534                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1535                 etm_ctx->trace_data[i].flags = flags;
1536         }
1537
1538         fileio_close(&file);
1539
1540         return ERROR_OK;
1541 }
1542
1543 int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1544 {
1545         target_t *target;
1546         armv4_5_common_t *armv4_5;
1547         arm7_9_common_t *arm7_9;
1548         etm_context_t *etm_ctx;
1549         reg_t *etm_ctrl_reg;
1550
1551         target = get_current_target(cmd_ctx);
1552
1553         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1554         {
1555                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1556                 return ERROR_OK;
1557         }
1558
1559         if (!(etm_ctx = arm7_9->etm_ctx))
1560         {
1561                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1562                 return ERROR_OK;
1563         }
1564
1565         /* invalidate old tracing data */
1566         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1567         if (arm7_9->etm_ctx->trace_depth > 0)
1568         {
1569                 free(arm7_9->etm_ctx->trace_data);
1570         }
1571         arm7_9->etm_ctx->trace_depth = 0;
1572
1573         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1574         etm_get_reg(etm_ctrl_reg);
1575
1576         /* Clear programming bit (10), set port selection bit (11) */
1577         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1578
1579         etm_store_reg(etm_ctrl_reg);
1580         jtag_execute_queue();
1581
1582         etm_ctx->capture_driver->start_capture(etm_ctx);
1583
1584         return ERROR_OK;
1585 }
1586
1587 int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1588 {
1589         target_t *target;
1590         armv4_5_common_t *armv4_5;
1591         arm7_9_common_t *arm7_9;
1592         etm_context_t *etm_ctx;
1593         reg_t *etm_ctrl_reg;
1594
1595         target = get_current_target(cmd_ctx);
1596
1597         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1598         {
1599                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1600                 return ERROR_OK;
1601         }
1602
1603         if (!(etm_ctx = arm7_9->etm_ctx))
1604         {
1605                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1606                 return ERROR_OK;
1607         }
1608
1609         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1610         etm_get_reg(etm_ctrl_reg);
1611
1612         /* Set programming bit (10), clear port selection bit (11) */
1613         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1614
1615         etm_store_reg(etm_ctrl_reg);
1616         jtag_execute_queue();
1617
1618         etm_ctx->capture_driver->stop_capture(etm_ctx);
1619
1620         return ERROR_OK;
1621 }
1622
1623 int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1624 {
1625         target_t *target;
1626         armv4_5_common_t *armv4_5;
1627         arm7_9_common_t *arm7_9;
1628         etm_context_t *etm_ctx;
1629
1630         target = get_current_target(cmd_ctx);
1631
1632         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1633         {
1634                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1635                 return ERROR_OK;
1636         }
1637
1638         if (!(etm_ctx = arm7_9->etm_ctx))
1639         {
1640                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1641                 return ERROR_OK;
1642         }
1643
1644         etmv1_analyze_trace(etm_ctx, cmd_ctx);
1645
1646         return ERROR_OK;
1647 }
1648
1649 int etm_register_commands(struct command_context_s *cmd_ctx)
1650 {
1651         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1652
1653         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, NULL);
1654
1655         return ERROR_OK;
1656 }
1657
1658 int etm_register_user_commands(struct command_context_s *cmd_ctx)
1659 {
1660         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1661                 COMMAND_EXEC, "configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output");
1662
1663         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1664                 COMMAND_EXEC, "display current target's ETM status");
1665         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1666                 COMMAND_EXEC, "start ETM trace collection");
1667         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1668                 COMMAND_EXEC, "stop ETM trace collection");
1669
1670         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1671                 COMMAND_EXEC, "anaylze collected ETM trace");
1672
1673         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1674                 COMMAND_EXEC, "load image from <file> [base address]");
1675
1676         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1677                 COMMAND_EXEC, "dump captured trace data <file>");
1678         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1679                 COMMAND_EXEC, "load trace data for analysis <file>");
1680
1681         return ERROR_OK;
1682 }