projects / fw / openocd / blob
? search:


fec0a69a09d9e1aa2054ccf4d2f11c431207579e
[fw/openocd] / src / target / etm.c
1 /***************************************************************************
2  *   Copyright (C) 2005 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "etm.h"
25 #include "etb.h"
26 #include "image.h"
27 #include "arm7_9_common.h"
28 #include "arm_disassembler.h"
29
30
31 /* ETM register access functionality
32  *
33  */
34
35 #if 0
36 static bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
37 {
38         {"R", 1},
39         {"W", 1},
40         {"reserved", 26},
41         {"version", 4}
42 };
43 #endif
44
45 static int etm_reg_arch_info[] =
46 {
47         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
48         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
49         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
50         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
51         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
52         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
53         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
54         0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
55         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
56         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
57         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
58         0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
59         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
60         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
61 };
62
63 static int etm_reg_arch_size_info[] =
64 {
65         32, 32, 17, 8, 3, 9, 32, 16,
66         17, 26, 25, 8, 17, 32, 32, 17,
67         32, 32, 32, 32, 32, 32, 32, 32,
68         32, 32, 32, 32, 32, 32, 32, 32,
69         7, 7, 7, 7, 7, 7, 7, 7,
70         7, 7, 7, 7, 7, 7, 7, 7,
71         32, 32, 32, 32, 32, 32, 32, 32,
72         32, 32, 32, 32, 32, 32, 32, 32,
73         32, 32, 32, 32, 32, 32, 32, 32,
74         32, 32, 32, 32, 32, 32, 32, 32,
75         16, 16, 16, 16, 18, 18, 18, 18,
76         17, 17, 17, 17, 16, 16, 16, 16,
77         17, 17, 17, 17, 17, 17, 2,
78         17, 17, 17, 17, 32, 32, 32, 32
79 };
80
81 static char* etm_reg_list[] =
82 {
83         "ETM_CTRL",
84         "ETM_CONFIG",
85         "ETM_TRIG_EVENT",
86         "ETM_MMD_CTRL",
87         "ETM_STATUS",
88         "ETM_SYS_CONFIG",
89         "ETM_TRACE_RESOURCE_CTRL",
90         "ETM_TRACE_EN_CTRL2",
91         "ETM_TRACE_EN_EVENT",
92         "ETM_TRACE_EN_CTRL1",
93         "ETM_FIFOFULL_REGION",
94         "ETM_FIFOFULL_LEVEL",
95         "ETM_VIEWDATA_EVENT",
96         "ETM_VIEWDATA_CTRL1",
97         "ETM_VIEWDATA_CTRL2",
98         "ETM_VIEWDATA_CTRL3",
99         "ETM_ADDR_COMPARATOR_VALUE1",
100         "ETM_ADDR_COMPARATOR_VALUE2",
101         "ETM_ADDR_COMPARATOR_VALUE3",
102         "ETM_ADDR_COMPARATOR_VALUE4",
103         "ETM_ADDR_COMPARATOR_VALUE5",
104         "ETM_ADDR_COMPARATOR_VALUE6",
105         "ETM_ADDR_COMPARATOR_VALUE7",
106         "ETM_ADDR_COMPARATOR_VALUE8",
107         "ETM_ADDR_COMPARATOR_VALUE9",
108         "ETM_ADDR_COMPARATOR_VALUE10",
109         "ETM_ADDR_COMPARATOR_VALUE11",
110         "ETM_ADDR_COMPARATOR_VALUE12",
111         "ETM_ADDR_COMPARATOR_VALUE13",
112         "ETM_ADDR_COMPARATOR_VALUE14",
113         "ETM_ADDR_COMPARATOR_VALUE15",
114         "ETM_ADDR_COMPARATOR_VALUE16",
115         "ETM_ADDR_ACCESS_TYPE1",
116         "ETM_ADDR_ACCESS_TYPE2",
117         "ETM_ADDR_ACCESS_TYPE3",
118         "ETM_ADDR_ACCESS_TYPE4",
119         "ETM_ADDR_ACCESS_TYPE5",
120         "ETM_ADDR_ACCESS_TYPE6",
121         "ETM_ADDR_ACCESS_TYPE7",
122         "ETM_ADDR_ACCESS_TYPE8",
123         "ETM_ADDR_ACCESS_TYPE9",
124         "ETM_ADDR_ACCESS_TYPE10",
125         "ETM_ADDR_ACCESS_TYPE11",
126         "ETM_ADDR_ACCESS_TYPE12",
127         "ETM_ADDR_ACCESS_TYPE13",
128         "ETM_ADDR_ACCESS_TYPE14",
129         "ETM_ADDR_ACCESS_TYPE15",
130         "ETM_ADDR_ACCESS_TYPE16",
131         "ETM_DATA_COMPARATOR_VALUE1",
132         "ETM_DATA_COMPARATOR_VALUE2",
133         "ETM_DATA_COMPARATOR_VALUE3",
134         "ETM_DATA_COMPARATOR_VALUE4",
135         "ETM_DATA_COMPARATOR_VALUE5",
136         "ETM_DATA_COMPARATOR_VALUE6",
137         "ETM_DATA_COMPARATOR_VALUE7",
138         "ETM_DATA_COMPARATOR_VALUE8",
139         "ETM_DATA_COMPARATOR_VALUE9",
140         "ETM_DATA_COMPARATOR_VALUE10",
141         "ETM_DATA_COMPARATOR_VALUE11",
142         "ETM_DATA_COMPARATOR_VALUE12",
143         "ETM_DATA_COMPARATOR_VALUE13",
144         "ETM_DATA_COMPARATOR_VALUE14",
145         "ETM_DATA_COMPARATOR_VALUE15",
146         "ETM_DATA_COMPARATOR_VALUE16",
147         "ETM_DATA_COMPARATOR_MASK1",
148         "ETM_DATA_COMPARATOR_MASK2",
149         "ETM_DATA_COMPARATOR_MASK3",
150         "ETM_DATA_COMPARATOR_MASK4",
151         "ETM_DATA_COMPARATOR_MASK5",
152         "ETM_DATA_COMPARATOR_MASK6",
153         "ETM_DATA_COMPARATOR_MASK7",
154         "ETM_DATA_COMPARATOR_MASK8",
155         "ETM_DATA_COMPARATOR_MASK9",
156         "ETM_DATA_COMPARATOR_MASK10",
157         "ETM_DATA_COMPARATOR_MASK11",
158         "ETM_DATA_COMPARATOR_MASK12",
159         "ETM_DATA_COMPARATOR_MASK13",
160         "ETM_DATA_COMPARATOR_MASK14",
161         "ETM_DATA_COMPARATOR_MASK15",
162         "ETM_DATA_COMPARATOR_MASK16",
163         "ETM_COUNTER_INITAL_VALUE1",
164         "ETM_COUNTER_INITAL_VALUE2",
165         "ETM_COUNTER_INITAL_VALUE3",
166         "ETM_COUNTER_INITAL_VALUE4",
167         "ETM_COUNTER_ENABLE1",
168         "ETM_COUNTER_ENABLE2",
169         "ETM_COUNTER_ENABLE3",
170         "ETM_COUNTER_ENABLE4",
171         "ETM_COUNTER_RELOAD_VALUE1",
172         "ETM_COUNTER_RELOAD_VALUE2",
173         "ETM_COUNTER_RELOAD_VALUE3",
174         "ETM_COUNTER_RELOAD_VALUE4",
175         "ETM_COUNTER_VALUE1",
176         "ETM_COUNTER_VALUE2",
177         "ETM_COUNTER_VALUE3",
178         "ETM_COUNTER_VALUE4",
179         "ETM_SEQUENCER_CTRL1",
180         "ETM_SEQUENCER_CTRL2",
181         "ETM_SEQUENCER_CTRL3",
182         "ETM_SEQUENCER_CTRL4",
183         "ETM_SEQUENCER_CTRL5",
184         "ETM_SEQUENCER_CTRL6",
185         "ETM_SEQUENCER_STATE",
186         "ETM_EXTERNAL_OUTPUT1",
187         "ETM_EXTERNAL_OUTPUT2",
188         "ETM_EXTERNAL_OUTPUT3",
189         "ETM_EXTERNAL_OUTPUT4",
190         "ETM_CONTEXTID_COMPARATOR_VALUE1",
191         "ETM_CONTEXTID_COMPARATOR_VALUE2",
192         "ETM_CONTEXTID_COMPARATOR_VALUE3",
193         "ETM_CONTEXTID_COMPARATOR_MASK"
194 };
195
196 static int etm_reg_arch_type = -1;
197
198 static int etm_get_reg(reg_t *reg);
199
200 static command_t *etm_cmd = NULL;
201
202 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
203 {
204         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
205         reg_t *reg_list = NULL;
206         etm_reg_t *arch_info = NULL;
207         int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
208         int i;
209
210         /* register a register arch-type for etm registers only once */
211         if (etm_reg_arch_type == -1)
212                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
213
214         /* the actual registers are kept in two arrays */
215         reg_list = calloc(num_regs, sizeof(reg_t));
216         arch_info = calloc(num_regs, sizeof(etm_reg_t));
217
218         /* fill in values for the reg cache */
219         reg_cache->name = "etm registers";
220         reg_cache->next = NULL;
221         reg_cache->reg_list = reg_list;
222         reg_cache->num_regs = num_regs;
223
224         /* set up registers */
225         for (i = 0; i < num_regs; i++)
226         {
227                 reg_list[i].name = etm_reg_list[i];
228                 reg_list[i].size = 32;
229                 reg_list[i].dirty = 0;
230                 reg_list[i].valid = 0;
231                 reg_list[i].bitfield_desc = NULL;
232                 reg_list[i].num_bitfields = 0;
233                 reg_list[i].value = calloc(1, 4);
234                 reg_list[i].arch_info = &arch_info[i];
235                 reg_list[i].arch_type = etm_reg_arch_type;
236                 reg_list[i].size = etm_reg_arch_size_info[i];
237                 arch_info[i].addr = etm_reg_arch_info[i];
238                 arch_info[i].jtag_info = jtag_info;
239         }
240
241         /* the ETM might have an ETB connected */
242         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
243         {
244                 etb_t *etb = etm_ctx->capture_driver_priv;
245
246                 if (!etb)
247                 {
248                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
249                         return ERROR_OK;
250                 }
251
252                 reg_cache->next = etb_build_reg_cache(etb);
253
254                 etb->reg_cache = reg_cache->next;
255         }
256
257
258         return reg_cache;
259 }
260
261 int etm_setup(target_t *target)
262 {
263         int retval;
264         u32 etm_ctrl_value;
265         armv4_5_common_t *armv4_5 = target->arch_info;
266         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
267         etm_context_t *etm_ctx = arm7_9->etm_ctx;
268         reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
269
270         /* initialize some ETM control register settings */
271         etm_get_reg(etm_ctrl_reg);
272         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
273
274         /* clear the ETM powerdown bit (0) */
275         etm_ctrl_value &= ~0x1;
276
277         /* configure port width (6:4), mode (17:16) and clocking (13) */
278         etm_ctrl_value = (etm_ctrl_value &
279                 ~ETM_PORT_WIDTH_MASK & ~ETM_PORT_MODE_MASK & ~ETM_PORT_CLOCK_MASK)
280                 | etm_ctx->portmode;
281
282         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
283         etm_store_reg(etm_ctrl_reg);
284
285         if ((retval=jtag_execute_queue())!=ERROR_OK)
286                 return retval;
287
288         if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
289         {
290                 LOG_ERROR("ETM capture driver initialization failed");
291                 return retval;
292         }
293         return ERROR_OK;
294 }
295
296 int etm_get_reg(reg_t *reg)
297 {
298         int retval;
299
300         if ((retval = etm_read_reg(reg)) != ERROR_OK)
301         {
302                 LOG_ERROR("BUG: error scheduling etm register read");
303                 return retval;
304         }
305
306         if ((retval = jtag_execute_queue()) != ERROR_OK)
307         {
308                 LOG_ERROR("register read failed");
309                 return retval;
310         }
311
312         return ERROR_OK;
313 }
314
315 int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask)
316 {
317         etm_reg_t *etm_reg = reg->arch_info;
318         uint8_t reg_addr = etm_reg->addr & 0x7f;
319         scan_field_t fields[3];
320
321         LOG_DEBUG("%i", etm_reg->addr);
322
323         jtag_set_end_state(TAP_IDLE);
324         arm_jtag_scann(etm_reg->jtag_info, 0x6);
325         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
326
327         fields[0].tap = etm_reg->jtag_info->tap;
328         fields[0].num_bits = 32;
329         fields[0].out_value = reg->value;
330         fields[0].in_value = NULL;
331         fields[0].check_value = NULL;
332         fields[0].check_mask = NULL;
333
334         fields[1].tap = etm_reg->jtag_info->tap;
335         fields[1].num_bits = 7;
336         fields[1].out_value = malloc(1);
337         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
338         fields[1].in_value = NULL;
339         fields[1].check_value = NULL;
340         fields[1].check_mask = NULL;
341
342         fields[2].tap = etm_reg->jtag_info->tap;
343         fields[2].num_bits = 1;
344         fields[2].out_value = malloc(1);
345         buf_set_u32(fields[2].out_value, 0, 1, 0);
346         fields[2].in_value = NULL;
347         fields[2].check_value = NULL;
348         fields[2].check_mask = NULL;
349
350         jtag_add_dr_scan(3, fields, jtag_get_end_state());
351
352         fields[0].in_value = reg->value;
353         fields[0].check_value = check_value;
354         fields[0].check_mask = check_mask;
355
356         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
357
358         free(fields[1].out_value);
359         free(fields[2].out_value);
360
361         return ERROR_OK;
362 }
363
364 int etm_read_reg(reg_t *reg)
365 {
366         return etm_read_reg_w_check(reg, NULL, NULL);
367 }
368
369 int etm_set_reg(reg_t *reg, u32 value)
370 {
371         int retval;
372
373         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
374         {
375                 LOG_ERROR("BUG: error scheduling etm register write");
376                 return retval;
377         }
378
379         buf_set_u32(reg->value, 0, reg->size, value);
380         reg->valid = 1;
381         reg->dirty = 0;
382
383         return ERROR_OK;
384 }
385
386 int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
387 {
388         int retval;
389
390         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
391
392         if ((retval = jtag_execute_queue()) != ERROR_OK)
393         {
394                 LOG_ERROR("register write failed");
395                 return retval;
396         }
397         return ERROR_OK;
398 }
399
400 int etm_write_reg(reg_t *reg, u32 value)
401 {
402         etm_reg_t *etm_reg = reg->arch_info;
403         uint8_t reg_addr = etm_reg->addr & 0x7f;
404         scan_field_t fields[3];
405
406         LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
407
408         jtag_set_end_state(TAP_IDLE);
409         arm_jtag_scann(etm_reg->jtag_info, 0x6);
410         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
411
412         fields[0].tap = etm_reg->jtag_info->tap;
413         fields[0].num_bits = 32;
414         uint8_t tmp1[4];
415         fields[0].out_value = tmp1;
416         buf_set_u32(fields[0].out_value, 0, 32, value);
417         fields[0].in_value = NULL;
418
419         fields[1].tap = etm_reg->jtag_info->tap;
420         fields[1].num_bits = 7;
421         uint8_t tmp2;
422         fields[1].out_value = &tmp2;
423         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
424         fields[1].in_value = NULL;
425
426         fields[2].tap = etm_reg->jtag_info->tap;
427         fields[2].num_bits = 1;
428         uint8_t tmp3;
429         fields[2].out_value = &tmp3;
430         buf_set_u32(fields[2].out_value, 0, 1, 1);
431         fields[2].in_value = NULL;
432
433         jtag_add_dr_scan(3, fields, jtag_get_end_state());
434
435         return ERROR_OK;
436 }
437
438 int etm_store_reg(reg_t *reg)
439 {
440         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
441 }
442
443 /* ETM trace analysis functionality
444  *
445  */
446 extern etm_capture_driver_t etm_dummy_capture_driver;
447 #if BUILD_OOCD_TRACE == 1
448 extern etm_capture_driver_t oocd_trace_capture_driver;
449 #endif
450
451 static etm_capture_driver_t *etm_capture_drivers[] =
452 {
453         &etb_capture_driver,
454         &etm_dummy_capture_driver,
455 #if BUILD_OOCD_TRACE == 1
456         &oocd_trace_capture_driver,
457 #endif
458         NULL
459 };
460
461 char *etmv1v1_branch_reason_strings[] =
462 {
463         "normal PC change",
464         "tracing enabled",
465         "trace restarted after overflow",
466         "exit from debug",
467         "periodic synchronization",
468         "reserved",
469         "reserved",
470         "reserved",
471 };
472
473 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
474 {
475         int i;
476         int section = -1;
477         u32 size_read;
478         u32 opcode;
479         int retval;
480
481         if (!ctx->image)
482                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
483
484         /* search for the section the current instruction belongs to */
485         for (i = 0; i < ctx->image->num_sections; i++)
486         {
487                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
488                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
489                 {
490                         section = i;
491                         break;
492                 }
493         }
494
495         if (section == -1)
496         {
497                 /* current instruction couldn't be found in the image */
498                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
499         }
500
501         if (ctx->core_state == ARMV4_5_STATE_ARM)
502         {
503                 uint8_t buf[4];
504                 if ((retval = image_read_section(ctx->image, section,
505                         ctx->current_pc - ctx->image->sections[section].base_address,
506                         4, buf, &size_read)) != ERROR_OK)
507                 {
508                         LOG_ERROR("error while reading instruction: %i", retval);
509                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
510                 }
511                 opcode = target_buffer_get_u32(ctx->target, buf);
512                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
513         }
514         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
515         {
516                 uint8_t buf[2];
517                 if ((retval = image_read_section(ctx->image, section,
518                         ctx->current_pc - ctx->image->sections[section].base_address,
519                         2, buf, &size_read)) != ERROR_OK)
520                 {
521                         LOG_ERROR("error while reading instruction: %i", retval);
522                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
523                 }
524                 opcode = target_buffer_get_u16(ctx->target, buf);
525                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
526         }
527         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
528         {
529                 LOG_ERROR("BUG: tracing of jazelle code not supported");
530                 exit(-1);
531         }
532         else
533         {
534                 LOG_ERROR("BUG: unknown core state encountered");
535                 exit(-1);
536         }
537
538         return ERROR_OK;
539 }
540
541 static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo)
542 {
543         while (ctx->data_index < ctx->trace_depth)
544         {
545                 /* if the caller specified an address packet offset, skip until the
546                  * we reach the n-th cycle marked with tracesync */
547                 if (apo > 0)
548                 {
549                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
550                                 apo--;
551
552                         if (apo > 0)
553                         {
554                                 ctx->data_index++;
555                                 ctx->data_half = 0;
556                         }
557                         continue;
558                 }
559
560                 /* no tracedata output during a TD cycle
561                  * or in a trigger cycle */
562                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
563                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
564                 {
565                         ctx->data_index++;
566                         ctx->data_half = 0;
567                         continue;
568                 }
569
570                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
571                 {
572                         if (ctx->data_half == 0)
573                         {
574                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
575                                 ctx->data_half = 1;
576                         }
577                         else
578                         {
579                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
580                                 ctx->data_half = 0;
581                                 ctx->data_index++;
582                         }
583                 }
584                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
585                 {
586                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
587                         ctx->data_index++;
588                 }
589                 else
590                 {
591                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
592                         if (ctx->data_index > (ctx->trace_depth - 2))
593                                 return -1;
594
595                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
596                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
597                         ctx->data_index += 2;
598                 }
599
600                 return 0;
601         }
602
603         return -1;
604 }
605
606 static int etmv1_branch_address(etm_context_t *ctx)
607 {
608         int retval;
609         uint8_t packet;
610         int shift = 0;
611         int apo;
612         u32 i;
613
614         /* quit analysis if less than two cycles are left in the trace
615          * because we can't extract the APO */
616         if (ctx->data_index > (ctx->trace_depth - 2))
617                 return -1;
618
619         /* a BE could be output during an APO cycle, skip the current
620          * and continue with the new one */
621         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
622                 return 1;
623         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
624                 return 2;
625
626         /* address packet offset encoded in the next two cycles' pipestat bits */
627         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
628         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
629
630         /* count number of tracesync cycles between current pipe_index and data_index
631          * i.e. the number of tracesyncs that data_index already passed by
632          * to subtract them from the APO */
633         for (i = ctx->pipe_index; i < ctx->data_index; i++)
634         {
635                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
636                         apo--;
637         }
638
639         /* extract up to four 7-bit packets */
640         do {
641                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
642                         return -1;
643                 ctx->last_branch &= ~(0x7f << shift);
644                 ctx->last_branch |= (packet & 0x7f) << shift;
645                 shift += 7;
646         } while ((packet & 0x80) && (shift < 28));
647
648         /* one last packet holding 4 bits of the address, plus the branch reason code */
649         if ((shift == 28) && (packet & 0x80))
650         {
651                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
652                         return -1;
653                 ctx->last_branch &= 0x0fffffff;
654                 ctx->last_branch |= (packet & 0x0f) << 28;
655                 ctx->last_branch_reason = (packet & 0x70) >> 4;
656                 shift += 4;
657         }
658         else
659         {
660                 ctx->last_branch_reason = 0;
661         }
662
663         if (shift == 32)
664         {
665                 ctx->pc_ok = 1;
666         }
667
668         /* if a full address was output, we might have branched into Jazelle state */
669         if ((shift == 32) && (packet & 0x80))
670         {
671                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
672         }
673         else
674         {
675                 /* if we didn't branch into Jazelle state, the current processor state is
676                  * encoded in bit 0 of the branch target address */
677                 if (ctx->last_branch & 0x1)
678                 {
679                         ctx->core_state = ARMV4_5_STATE_THUMB;
680                         ctx->last_branch &= ~0x1;
681                 }
682                 else
683                 {
684                         ctx->core_state = ARMV4_5_STATE_ARM;
685                         ctx->last_branch &= ~0x3;
686                 }
687         }
688
689         return 0;
690 }
691
692 static int etmv1_data(etm_context_t *ctx, int size, u32 *data)
693 {
694         int j;
695         uint8_t buf[4];
696         int retval;
697
698         for (j = 0; j < size; j++)
699         {
700                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
701                         return -1;
702         }
703
704         if (size == 8)
705         {
706                 LOG_ERROR("TODO: add support for 64-bit values");
707                 return -1;
708         }
709         else if (size == 4)
710                 *data = target_buffer_get_u32(ctx->target, buf);
711         else if (size == 2)
712                 *data = target_buffer_get_u16(ctx->target, buf);
713         else if (size == 1)
714                 *data = buf[0];
715         else
716                 return -1;
717
718         return 0;
719 }
720
721 static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
722 {
723         int retval;
724         arm_instruction_t instruction;
725
726         /* read the trace data if it wasn't read already */
727         if (ctx->trace_depth == 0)
728                 ctx->capture_driver->read_trace(ctx);
729
730         /* start at the beginning of the captured trace */
731         ctx->pipe_index = 0;
732         ctx->data_index = 0;
733         ctx->data_half = 0;
734
735         /* neither the PC nor the data pointer are valid */
736         ctx->pc_ok = 0;
737         ctx->ptr_ok = 0;
738
739         while (ctx->pipe_index < ctx->trace_depth)
740         {
741                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
742                 u32 next_pc = ctx->current_pc;
743                 u32 old_data_index = ctx->data_index;
744                 u32 old_data_half = ctx->data_half;
745                 u32 old_index = ctx->pipe_index;
746                 u32 last_instruction = ctx->last_instruction;
747                 u32 cycles = 0;
748                 int current_pc_ok = ctx->pc_ok;
749
750                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
751                 {
752                         command_print(cmd_ctx, "--- trigger ---");
753                 }
754
755                 /* instructions execute in IE/D or BE/D cycles */
756                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
757                         ctx->last_instruction = ctx->pipe_index;
758
759                 /* if we don't have a valid pc skip until we reach an indirect branch */
760                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
761                 {
762                         ctx->pipe_index++;
763                         continue;
764                 }
765
766                 /* any indirect branch could have interrupted instruction flow
767                  * - the branch reason code could indicate a trace discontinuity
768                  * - a branch to the exception vectors indicates an exception
769                  */
770                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
771                 {
772                         /* backup current data index, to be able to consume the branch address
773                          * before examining data address and values
774                          */
775                         old_data_index = ctx->data_index;
776                         old_data_half = ctx->data_half;
777
778                         ctx->last_instruction = ctx->pipe_index;
779
780                         if ((retval = etmv1_branch_address(ctx)) != 0)
781                         {
782                                 /* negative return value from etmv1_branch_address means we ran out of packets,
783                                  * quit analysing the trace */
784                                 if (retval < 0)
785                                         break;
786
787                                 /* a positive return values means the current branch was abandoned,
788                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
789                                  */
790                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
791                                 ctx->pipe_index += retval;
792                                 continue;
793                         }
794
795                         /* skip over APO cycles */
796                         ctx->pipe_index += 2;
797
798                         switch (ctx->last_branch_reason)
799                         {
800                                 case 0x0:       /* normal PC change */
801                                         next_pc = ctx->last_branch;
802                                         break;
803                                 case 0x1:       /* tracing enabled */
804                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
805                                         ctx->current_pc = ctx->last_branch;
806                                         ctx->pipe_index++;
807                                         continue;
808                                         break;
809                                 case 0x2:       /* trace restarted after FIFO overflow */
810                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
811                                         ctx->current_pc = ctx->last_branch;
812                                         ctx->pipe_index++;
813                                         continue;
814                                         break;
815                                 case 0x3:       /* exit from debug state */
816                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
817                                         ctx->current_pc = ctx->last_branch;
818                                         ctx->pipe_index++;
819                                         continue;
820                                         break;
821                                 case 0x4:       /* periodic synchronization point */
822                                         next_pc = ctx->last_branch;
823                                         /* if we had no valid PC prior to this synchronization point,
824                                          * we have to move on with the next trace cycle
825                                          */
826                                         if (!current_pc_ok)
827                                         {
828                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
829                                                 ctx->current_pc = next_pc;
830                                                 ctx->pipe_index++;
831                                                 continue;
832                                         }
833                                         break;
834                                 default:        /* reserved */
835                                         LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
836                                         exit(-1);
837                                         break;
838                         }
839
840                         /* if we got here the branch was a normal PC change
841                          * (or a periodic synchronization point, which means the same for that matter)
842                          * if we didn't accquire a complete PC continue with the next cycle
843                          */
844                         if (!ctx->pc_ok)
845                                 continue;
846
847                         /* indirect branch to the exception vector means an exception occured */
848                         if ((ctx->last_branch <= 0x20)
849                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
850                         {
851                                 if ((ctx->last_branch & 0xff) == 0x10)
852                                 {
853                                         command_print(cmd_ctx, "data abort");
854                                 }
855                                 else
856                                 {
857                                         command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
858                                         ctx->current_pc = ctx->last_branch;
859                                         ctx->pipe_index++;
860                                         continue;
861                                 }
862                         }
863                 }
864
865                 /* an instruction was executed (or not, depending on the condition flags)
866                  * retrieve it from the image for displaying */
867                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
868                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
869                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
870                 {
871                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
872                         {
873                                 /* can't continue tracing with no image available */
874                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
875                                 {
876                                         return retval;
877                                 }
878                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
879                                 {
880                                         /* TODO: handle incomplete images
881                                          * for now we just quit the analsysis*/
882                                         return retval;
883                                 }
884                         }
885
886                         cycles = old_index - last_instruction;
887                 }
888
889                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
890                 {
891                         u32 new_data_index = ctx->data_index;
892                         u32 new_data_half = ctx->data_half;
893
894                         /* in case of a branch with data, the branch target address was consumed before
895                          * we temporarily go back to the saved data index */
896                         if (pipestat == STAT_BD)
897                         {
898                                 ctx->data_index = old_data_index;
899                                 ctx->data_half = old_data_half;
900                         }
901
902                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
903                         {
904                                 uint8_t packet;
905                                 int shift = 0;
906
907                                 do {
908                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
909                                                 return ERROR_ETM_ANALYSIS_FAILED;
910                                         ctx->last_ptr &= ~(0x7f << shift);
911                                         ctx->last_ptr |= (packet & 0x7f) << shift;
912                                         shift += 7;
913                                 } while ((packet & 0x80) && (shift < 32));
914
915                                 if (shift >= 32)
916                                         ctx->ptr_ok = 1;
917
918                                 if (ctx->ptr_ok)
919                                 {
920                                         command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
921                                 }
922                         }
923
924                         if (ctx->tracemode & ETMV1_TRACE_DATA)
925                         {
926                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
927                                 {
928                                         int i;
929                                         for (i = 0; i < 16; i++)
930                                         {
931                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
932                                                 {
933                                                         u32 data;
934                                                         if (etmv1_data(ctx, 4, &data) != 0)
935                                                                 return ERROR_ETM_ANALYSIS_FAILED;
936                                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
937                                                 }
938                                         }
939                                 }
940                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
941                                 {
942                                         u32 data;
943                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
944                                                 return ERROR_ETM_ANALYSIS_FAILED;
945                                         command_print(cmd_ctx, "data: 0x%8.8x", data);
946                                 }
947                         }
948
949                         /* restore data index after consuming BD address and data */
950                         if (pipestat == STAT_BD)
951                         {
952                                 ctx->data_index = new_data_index;
953                                 ctx->data_half = new_data_half;
954                         }
955                 }
956
957                 /* adjust PC */
958                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
959                 {
960                         if (((instruction.type == ARM_B) ||
961                              (instruction.type == ARM_BL) ||
962                              (instruction.type == ARM_BLX)) &&
963                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
964                         {
965                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
966                         }
967                         else
968                         {
969                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
970                         }
971                 }
972                 else if (pipestat == STAT_IN)
973                 {
974                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
975                 }
976
977                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
978                 {
979                         char cycles_text[32] = "";
980
981                         /* if the trace was captured with cycle accurate tracing enabled,
982                          * output the number of cycles since the last executed instruction
983                          */
984                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
985                         {
986                                 snprintf(cycles_text, 32, " (%i %s)",
987                                         cycles,
988                                         (cycles == 1) ? "cycle" : "cycles");
989                         }
990
991                         command_print(cmd_ctx, "%s%s%s",
992                                 instruction.text,
993                                 (pipestat == STAT_IN) ? " (not executed)" : "",
994                                 cycles_text);
995
996                         ctx->current_pc = next_pc;
997
998                         /* packets for an instruction don't start on or before the preceding
999                          * functional pipestat (i.e. other than WT or TD)
1000                          */
1001                         if (ctx->data_index <= ctx->pipe_index)
1002                         {
1003                                 ctx->data_index = ctx->pipe_index + 1;
1004                                 ctx->data_half = 0;
1005                         }
1006                 }
1007
1008                 ctx->pipe_index += 1;
1009         }
1010
1011         return ERROR_OK;
1012 }
1013
1014 static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1015 {
1016         target_t *target;
1017         armv4_5_common_t *armv4_5;
1018         arm7_9_common_t *arm7_9;
1019         etmv1_tracemode_t tracemode;
1020
1021         target = get_current_target(cmd_ctx);
1022
1023         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1024         {
1025                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1026                 return ERROR_OK;
1027         }
1028
1029         if (!arm7_9->etm_ctx)
1030         {
1031                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1032                 return ERROR_OK;
1033         }
1034
1035         tracemode = arm7_9->etm_ctx->tracemode;
1036
1037         if (argc == 4)
1038         {
1039                 if (strcmp(args[0], "none") == 0)
1040                 {
1041                         tracemode = ETMV1_TRACE_NONE;
1042                 }
1043                 else if (strcmp(args[0], "data") == 0)
1044                 {
1045                         tracemode = ETMV1_TRACE_DATA;
1046                 }
1047                 else if (strcmp(args[0], "address") == 0)
1048                 {
1049                         tracemode = ETMV1_TRACE_ADDR;
1050                 }
1051                 else if (strcmp(args[0], "all") == 0)
1052                 {
1053                         tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1054                 }
1055                 else
1056                 {
1057                         command_print(cmd_ctx, "invalid option '%s'", args[0]);
1058                         return ERROR_OK;
1059                 }
1060
1061                 switch (strtol(args[1], NULL, 0))
1062                 {
1063                         case 0:
1064                                 tracemode |= ETMV1_CONTEXTID_NONE;
1065                                 break;
1066                         case 8:
1067                                 tracemode |= ETMV1_CONTEXTID_8;
1068                                 break;
1069                         case 16:
1070                                 tracemode |= ETMV1_CONTEXTID_16;
1071                                 break;
1072                         case 32:
1073                                 tracemode |= ETMV1_CONTEXTID_32;
1074                                 break;
1075                         default:
1076                                 command_print(cmd_ctx, "invalid option '%s'", args[1]);
1077                                 return ERROR_OK;
1078                 }
1079
1080                 if (strcmp(args[2], "enable") == 0)
1081                 {
1082                         tracemode |= ETMV1_CYCLE_ACCURATE;
1083                 }
1084                 else if (strcmp(args[2], "disable") == 0)
1085                 {
1086                         tracemode |= 0;
1087                 }
1088                 else
1089                 {
1090                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1091                         return ERROR_OK;
1092                 }
1093
1094                 if (strcmp(args[3], "enable") == 0)
1095                 {
1096                         tracemode |= ETMV1_BRANCH_OUTPUT;
1097                 }
1098                 else if (strcmp(args[3], "disable") == 0)
1099                 {
1100                         tracemode |= 0;
1101                 }
1102                 else
1103                 {
1104                         command_print(cmd_ctx, "invalid option '%s'", args[2]);
1105                         return ERROR_OK;
1106                 }
1107         }
1108         else if (argc != 0)
1109         {
1110                 command_print(cmd_ctx, "usage: configure trace mode <none|data|address|all> <context id bits> <cycle accurate> <branch output>");
1111                 return ERROR_OK;
1112         }
1113
1114         command_print(cmd_ctx, "current tracemode configuration:");
1115
1116         switch (tracemode & ETMV1_TRACE_MASK)
1117         {
1118                 case ETMV1_TRACE_NONE:
1119                         command_print(cmd_ctx, "data tracing: none");
1120                         break;
1121                 case ETMV1_TRACE_DATA:
1122                         command_print(cmd_ctx, "data tracing: data only");
1123                         break;
1124                 case ETMV1_TRACE_ADDR:
1125                         command_print(cmd_ctx, "data tracing: address only");
1126                         break;
1127                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1128                         command_print(cmd_ctx, "data tracing: address and data");
1129                         break;
1130         }
1131
1132         switch (tracemode & ETMV1_CONTEXTID_MASK)
1133         {
1134                 case ETMV1_CONTEXTID_NONE:
1135                         command_print(cmd_ctx, "contextid tracing: none");
1136                         break;
1137                 case ETMV1_CONTEXTID_8:
1138                         command_print(cmd_ctx, "contextid tracing: 8 bit");
1139                         break;
1140                 case ETMV1_CONTEXTID_16:
1141                         command_print(cmd_ctx, "contextid tracing: 16 bit");
1142                         break;
1143                 case ETMV1_CONTEXTID_32:
1144                         command_print(cmd_ctx, "contextid tracing: 32 bit");
1145                         break;
1146         }
1147
1148         if (tracemode & ETMV1_CYCLE_ACCURATE)
1149         {
1150                 command_print(cmd_ctx, "cycle-accurate tracing enabled");
1151         }
1152         else
1153         {
1154                 command_print(cmd_ctx, "cycle-accurate tracing disabled");
1155         }
1156
1157         if (tracemode & ETMV1_BRANCH_OUTPUT)
1158         {
1159                 command_print(cmd_ctx, "full branch address output enabled");
1160         }
1161         else
1162         {
1163                 command_print(cmd_ctx, "full branch address output disabled");
1164         }
1165
1166         /* only update ETM_CTRL register if tracemode changed */
1167         if (arm7_9->etm_ctx->tracemode != tracemode)
1168         {
1169                 reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1170
1171                 etm_get_reg(etm_ctrl_reg);
1172
1173                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1174                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1175                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1176                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1177                 etm_store_reg(etm_ctrl_reg);
1178
1179                 arm7_9->etm_ctx->tracemode = tracemode;
1180
1181                 /* invalidate old trace data */
1182                 arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1183                 if (arm7_9->etm_ctx->trace_depth > 0)
1184                 {
1185                         free(arm7_9->etm_ctx->trace_data);
1186                         arm7_9->etm_ctx->trace_data = NULL;
1187                 }
1188                 arm7_9->etm_ctx->trace_depth = 0;
1189         }
1190
1191         return ERROR_OK;
1192 }
1193
1194 static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1195 {
1196         target_t *target;
1197         armv4_5_common_t *armv4_5;
1198         arm7_9_common_t *arm7_9;
1199         etm_portmode_t portmode = 0x0;
1200         etm_context_t *etm_ctx = malloc(sizeof(etm_context_t));
1201         int i;
1202
1203         if (argc != 5)
1204         {
1205                 return ERROR_COMMAND_SYNTAX_ERROR;
1206         }
1207
1208         target = get_target(args[0]);
1209         if (!target)
1210         {
1211                 LOG_ERROR("target '%s' not defined", args[0]);
1212                 return ERROR_FAIL;
1213         }
1214
1215         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1216         {
1217                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1218                 return ERROR_FAIL;
1219         }
1220
1221         switch (strtoul(args[1], NULL, 0))
1222         {
1223                 case 4:
1224                         portmode |= ETM_PORT_4BIT;
1225                         break;
1226                 case 8:
1227                         portmode |= ETM_PORT_8BIT;
1228                         break;
1229                 case 16:
1230                         portmode |= ETM_PORT_16BIT;
1231                         break;
1232                 default:
1233                         command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
1234                         return ERROR_FAIL;
1235         }
1236
1237         if (strcmp("normal", args[2]) == 0)
1238         {
1239                 portmode |= ETM_PORT_NORMAL;
1240         }
1241         else if (strcmp("multiplexed", args[2]) == 0)
1242         {
1243                 portmode |= ETM_PORT_MUXED;
1244         }
1245         else if (strcmp("demultiplexed", args[2]) == 0)
1246         {
1247                 portmode |= ETM_PORT_DEMUXED;
1248         }
1249         else
1250         {
1251                 command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
1252                 return ERROR_FAIL;
1253         }
1254
1255         if (strcmp("half", args[3]) == 0)
1256         {
1257                 portmode |= ETM_PORT_HALF_CLOCK;
1258         }
1259         else if (strcmp("full", args[3]) == 0)
1260         {
1261                 portmode |= ETM_PORT_FULL_CLOCK;
1262         }
1263         else
1264         {
1265                 command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
1266                 return ERROR_FAIL;
1267         }
1268
1269         for (i=0; etm_capture_drivers[i]; i++)
1270         {
1271                 if (strcmp(args[4], etm_capture_drivers[i]->name) == 0)
1272                 {
1273                         int retval;
1274                         if ((retval=etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK)
1275                         {
1276                                 free(etm_ctx);
1277                                 return retval;
1278                         }
1279
1280                         etm_ctx->capture_driver = etm_capture_drivers[i];
1281
1282                         break;
1283                 }
1284         }
1285
1286         if (!etm_capture_drivers[i])
1287         {
1288                 /* no supported capture driver found, don't register an ETM */
1289                 free(etm_ctx);
1290                 LOG_ERROR("trace capture driver '%s' not found", args[4]);
1291                 return ERROR_FAIL;
1292         }
1293
1294         etm_ctx->target = target;
1295         etm_ctx->trigger_percent = 50;
1296         etm_ctx->trace_data = NULL;
1297         etm_ctx->trace_depth = 0;
1298         etm_ctx->portmode = portmode;
1299         etm_ctx->tracemode = 0x0;
1300         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1301         etm_ctx->image = NULL;
1302         etm_ctx->pipe_index = 0;
1303         etm_ctx->data_index = 0;
1304         etm_ctx->current_pc = 0x0;
1305         etm_ctx->pc_ok = 0;
1306         etm_ctx->last_branch = 0x0;
1307         etm_ctx->last_branch_reason = 0x0;
1308         etm_ctx->last_ptr = 0x0;
1309         etm_ctx->ptr_ok = 0x0;
1310         etm_ctx->context_id = 0x0;
1311         etm_ctx->last_instruction = 0;
1312
1313         arm7_9->etm_ctx = etm_ctx;
1314
1315         return etm_register_user_commands(cmd_ctx);
1316 }
1317
1318 int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1319 {
1320         target_t *target;
1321         armv4_5_common_t *armv4_5;
1322         arm7_9_common_t *arm7_9;
1323         reg_t *etm_config_reg;
1324         reg_t *etm_sys_config_reg;
1325
1326         int max_port_size;
1327
1328         target = get_current_target(cmd_ctx);
1329
1330         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1331         {
1332                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1333                 return ERROR_OK;
1334         }
1335
1336         if (!arm7_9->etm_ctx)
1337         {
1338                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1339                 return ERROR_OK;
1340         }
1341
1342         etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
1343         etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
1344
1345         etm_get_reg(etm_config_reg);
1346         command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
1347         command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
1348         command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
1349         command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
1350         command_print(cmd_ctx, "sequencer %spresent",
1351                         (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
1352         command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
1353         command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
1354         command_print(cmd_ctx, "FIFO full %spresent",
1355                         (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
1356         command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
1357
1358         etm_get_reg(etm_sys_config_reg);
1359
1360         switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))
1361         {
1362                 case 0:
1363                         max_port_size = 4;
1364                         break;
1365                 case 1:
1366                         max_port_size = 8;
1367                         break;
1368                 case 2:
1369                         max_port_size = 16;
1370                         break;
1371                 default:
1372                         LOG_ERROR("Illegal max_port_size");
1373                         exit(-1);
1374         }
1375         command_print(cmd_ctx, "max. port size: %i", max_port_size);
1376
1377         command_print(cmd_ctx, "half-rate clocking %ssupported",
1378                         (buf_get_u32(etm_sys_config_reg->value, 3, 1) == 1) ? "" : "not ");
1379         command_print(cmd_ctx, "full-rate clocking %ssupported",
1380                         (buf_get_u32(etm_sys_config_reg->value, 4, 1) == 1) ? "" : "not ");
1381         command_print(cmd_ctx, "normal trace format %ssupported",
1382                         (buf_get_u32(etm_sys_config_reg->value, 5, 1) == 1) ? "" : "not ");
1383         command_print(cmd_ctx, "multiplex trace format %ssupported",
1384                         (buf_get_u32(etm_sys_config_reg->value, 6, 1) == 1) ? "" : "not ");
1385         command_print(cmd_ctx, "demultiplex trace format %ssupported",
1386                         (buf_get_u32(etm_sys_config_reg->value, 7, 1) == 1) ? "" : "not ");
1387         command_print(cmd_ctx, "FIFO full %ssupported",
1388                         (buf_get_u32(etm_sys_config_reg->value, 8, 1) == 1) ? "" : "not ");
1389
1390         return ERROR_OK;
1391 }
1392
1393 static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1394 {
1395         target_t *target;
1396         armv4_5_common_t *armv4_5;
1397         arm7_9_common_t *arm7_9;
1398         trace_status_t trace_status;
1399
1400         target = get_current_target(cmd_ctx);
1401
1402         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1403         {
1404                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1405                 return ERROR_OK;
1406         }
1407
1408         if (!arm7_9->etm_ctx)
1409         {
1410                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1411                 return ERROR_OK;
1412         }
1413
1414         trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
1415
1416         if (trace_status == TRACE_IDLE)
1417         {
1418                 command_print(cmd_ctx, "tracing is idle");
1419         }
1420         else
1421         {
1422                 static char *completed = " completed";
1423                 static char *running = " is running";
1424                 static char *overflowed = ", trace overflowed";
1425                 static char *triggered = ", trace triggered";
1426
1427                 command_print(cmd_ctx, "trace collection%s%s%s",
1428                         (trace_status & TRACE_RUNNING) ? running : completed,
1429                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1430                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1431
1432                 if (arm7_9->etm_ctx->trace_depth > 0)
1433                 {
1434                         command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
1435                 }
1436         }
1437
1438         return ERROR_OK;
1439 }
1440
1441 static int handle_etm_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1442 {
1443         target_t *target;
1444         armv4_5_common_t *armv4_5;
1445         arm7_9_common_t *arm7_9;
1446         etm_context_t *etm_ctx;
1447
1448         if (argc < 1)
1449         {
1450                 command_print(cmd_ctx, "usage: etm image <file> [base address] [type]");
1451                 return ERROR_OK;
1452         }
1453
1454         target = get_current_target(cmd_ctx);
1455
1456         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1457         {
1458                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1459                 return ERROR_OK;
1460         }
1461
1462         if (!(etm_ctx = arm7_9->etm_ctx))
1463         {
1464                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1465                 return ERROR_OK;
1466         }
1467
1468         if (etm_ctx->image)
1469         {
1470                 image_close(etm_ctx->image);
1471                 free(etm_ctx->image);
1472                 command_print(cmd_ctx, "previously loaded image found and closed");
1473         }
1474
1475         etm_ctx->image = malloc(sizeof(image_t));
1476         etm_ctx->image->base_address_set = 0;
1477         etm_ctx->image->start_address_set = 0;
1478
1479         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1480         if (argc >= 2)
1481         {
1482                 etm_ctx->image->base_address_set = 1;
1483                 etm_ctx->image->base_address = strtoul(args[1], NULL, 0);
1484         }
1485         else
1486         {
1487                 etm_ctx->image->base_address_set = 0;
1488         }
1489
1490         if (image_open(etm_ctx->image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
1491         {
1492                 free(etm_ctx->image);
1493                 etm_ctx->image = NULL;
1494                 return ERROR_OK;
1495         }
1496
1497         return ERROR_OK;
1498 }
1499
1500 static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1501 {
1502         fileio_t file;
1503         target_t *target;
1504         armv4_5_common_t *armv4_5;
1505         arm7_9_common_t *arm7_9;
1506         etm_context_t *etm_ctx;
1507         u32 i;
1508
1509         if (argc != 1)
1510         {
1511                 command_print(cmd_ctx, "usage: etm dump <file>");
1512                 return ERROR_OK;
1513         }
1514
1515         target = get_current_target(cmd_ctx);
1516
1517         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1518         {
1519                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1520                 return ERROR_OK;
1521         }
1522
1523         if (!(etm_ctx = arm7_9->etm_ctx))
1524         {
1525                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1526                 return ERROR_OK;
1527         }
1528
1529         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1530         {
1531                 command_print(cmd_ctx, "trace capture wasn't enabled, no trace data captured");
1532                 return ERROR_OK;
1533         }
1534
1535         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1536         {
1537                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1538                 command_print(cmd_ctx, "trace capture not completed");
1539                 return ERROR_OK;
1540         }
1541
1542         /* read the trace data if it wasn't read already */
1543         if (etm_ctx->trace_depth == 0)
1544                 etm_ctx->capture_driver->read_trace(etm_ctx);
1545
1546         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1547         {
1548                 return ERROR_OK;
1549         }
1550
1551         fileio_write_u32(&file, etm_ctx->capture_status);
1552         fileio_write_u32(&file, etm_ctx->portmode);
1553         fileio_write_u32(&file, etm_ctx->tracemode);
1554         fileio_write_u32(&file, etm_ctx->trace_depth);
1555
1556         for (i = 0; i < etm_ctx->trace_depth; i++)
1557         {
1558                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1559                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1560                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1561         }
1562
1563         fileio_close(&file);
1564
1565         return ERROR_OK;
1566 }
1567
1568 static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1569 {
1570         fileio_t file;
1571         target_t *target;
1572         armv4_5_common_t *armv4_5;
1573         arm7_9_common_t *arm7_9;
1574         etm_context_t *etm_ctx;
1575         u32 i;
1576
1577         if (argc != 1)
1578         {
1579                 command_print(cmd_ctx, "usage: etm load <file>");
1580                 return ERROR_OK;
1581         }
1582
1583         target = get_current_target(cmd_ctx);
1584
1585         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1586         {
1587                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1588                 return ERROR_OK;
1589         }
1590
1591         if (!(etm_ctx = arm7_9->etm_ctx))
1592         {
1593                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1594                 return ERROR_OK;
1595         }
1596
1597         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1598         {
1599                 command_print(cmd_ctx, "trace capture running, stop first");
1600                 return ERROR_OK;
1601         }
1602
1603         if (fileio_open(&file, args[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1604         {
1605                 return ERROR_OK;
1606         }
1607
1608         if (file.size % 4)
1609         {
1610                 command_print(cmd_ctx, "size isn't a multiple of 4, no valid trace data");
1611                 fileio_close(&file);
1612                 return ERROR_OK;
1613         }
1614
1615         if (etm_ctx->trace_depth > 0)
1616         {
1617                 free(etm_ctx->trace_data);
1618                 etm_ctx->trace_data = NULL;
1619         }
1620
1621         fileio_read_u32(&file, &etm_ctx->capture_status);
1622         fileio_read_u32(&file, &etm_ctx->portmode);
1623         fileio_read_u32(&file, &etm_ctx->tracemode);
1624         fileio_read_u32(&file, &etm_ctx->trace_depth);
1625
1626         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
1627         if (etm_ctx->trace_data == NULL)
1628         {
1629                 command_print(cmd_ctx, "not enough memory to perform operation");
1630                 fileio_close(&file);
1631                 return ERROR_OK;
1632         }
1633
1634         for (i = 0; i < etm_ctx->trace_depth; i++)
1635         {
1636                 u32 pipestat, packet, flags;
1637                 fileio_read_u32(&file, &pipestat);
1638                 fileio_read_u32(&file, &packet);
1639                 fileio_read_u32(&file, &flags);
1640                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1641                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1642                 etm_ctx->trace_data[i].flags = flags;
1643         }
1644
1645         fileio_close(&file);
1646
1647         return ERROR_OK;
1648 }
1649
1650 static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1651 {
1652         target_t *target;
1653         armv4_5_common_t *armv4_5;
1654         arm7_9_common_t *arm7_9;
1655         etm_context_t *etm_ctx;
1656
1657         target = get_current_target(cmd_ctx);
1658
1659         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1660         {
1661                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1662                 return ERROR_OK;
1663         }
1664
1665         if (!(etm_ctx = arm7_9->etm_ctx))
1666         {
1667                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1668                 return ERROR_OK;
1669         }
1670
1671         if (argc > 0)
1672         {
1673                 u32 new_value = strtoul(args[0], NULL, 0);
1674
1675                 if ((new_value < 2) || (new_value > 100))
1676                 {
1677                         command_print(cmd_ctx, "valid settings are 2%% to 100%%");
1678                 }
1679                 else
1680                 {
1681                         etm_ctx->trigger_percent = new_value;
1682                 }
1683         }
1684
1685         command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
1686
1687         return ERROR_OK;
1688 }
1689
1690 static int handle_etm_start_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1691 {
1692         target_t *target;
1693         armv4_5_common_t *armv4_5;
1694         arm7_9_common_t *arm7_9;
1695         etm_context_t *etm_ctx;
1696         reg_t *etm_ctrl_reg;
1697
1698         target = get_current_target(cmd_ctx);
1699
1700         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1701         {
1702                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1703                 return ERROR_OK;
1704         }
1705
1706         if (!(etm_ctx = arm7_9->etm_ctx))
1707         {
1708                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1709                 return ERROR_OK;
1710         }
1711
1712         /* invalidate old tracing data */
1713         arm7_9->etm_ctx->capture_status = TRACE_IDLE;
1714         if (arm7_9->etm_ctx->trace_depth > 0)
1715         {
1716                 free(arm7_9->etm_ctx->trace_data);
1717                 arm7_9->etm_ctx->trace_data = NULL;
1718         }
1719         arm7_9->etm_ctx->trace_depth = 0;
1720
1721         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1722         etm_get_reg(etm_ctrl_reg);
1723
1724         /* Clear programming bit (10), set port selection bit (11) */
1725         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1726
1727         etm_store_reg(etm_ctrl_reg);
1728         jtag_execute_queue();
1729
1730         etm_ctx->capture_driver->start_capture(etm_ctx);
1731
1732         return ERROR_OK;
1733 }
1734
1735 static int handle_etm_stop_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1736 {
1737         target_t *target;
1738         armv4_5_common_t *armv4_5;
1739         arm7_9_common_t *arm7_9;
1740         etm_context_t *etm_ctx;
1741         reg_t *etm_ctrl_reg;
1742
1743         target = get_current_target(cmd_ctx);
1744
1745         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1746         {
1747                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1748                 return ERROR_OK;
1749         }
1750
1751         if (!(etm_ctx = arm7_9->etm_ctx))
1752         {
1753                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1754                 return ERROR_OK;
1755         }
1756
1757         etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
1758         etm_get_reg(etm_ctrl_reg);
1759
1760         /* Set programming bit (10), clear port selection bit (11) */
1761         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1762
1763         etm_store_reg(etm_ctrl_reg);
1764         jtag_execute_queue();
1765
1766         etm_ctx->capture_driver->stop_capture(etm_ctx);
1767
1768         return ERROR_OK;
1769 }
1770
1771 static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1772 {
1773         target_t *target;
1774         armv4_5_common_t *armv4_5;
1775         arm7_9_common_t *arm7_9;
1776         etm_context_t *etm_ctx;
1777         int retval;
1778
1779         target = get_current_target(cmd_ctx);
1780
1781         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
1782         {
1783                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
1784                 return ERROR_OK;
1785         }
1786
1787         if (!(etm_ctx = arm7_9->etm_ctx))
1788         {
1789                 command_print(cmd_ctx, "current target doesn't have an ETM configured");
1790                 return ERROR_OK;
1791         }
1792
1793         if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK)
1794         {
1795                 switch (retval)
1796                 {
1797                         case ERROR_ETM_ANALYSIS_FAILED:
1798                                 command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data");
1799                                 break;
1800                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1801                                 command_print(cmd_ctx, "no instruction for current address available, analysis aborted");
1802                                 break;
1803                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
1804                                 command_print(cmd_ctx, "no image available for trace analysis");
1805                                 break;
1806                         default:
1807                                 command_print(cmd_ctx, "unknown error: %i", retval);
1808                 }
1809         }
1810
1811         return ERROR_OK;
1812 }
1813
1814 int etm_register_commands(struct command_context_s *cmd_ctx)
1815 {
1816         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
1817
1818         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
1819                 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
1820
1821         return ERROR_OK;
1822 }
1823
1824 int etm_register_user_commands(struct command_context_s *cmd_ctx)
1825 {
1826         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
1827                 COMMAND_EXEC, "configure trace mode <none|data|address|all> "
1828                         "<context_id_bits> <cycle_accurate> <branch_output>");
1829
1830         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
1831                 COMMAND_EXEC, "display info about the current target's ETM");
1832
1833         register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
1834                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
1835         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
1836                 COMMAND_EXEC, "display current target's ETM status");
1837         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
1838                 COMMAND_EXEC, "start ETM trace collection");
1839         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
1840                 COMMAND_EXEC, "stop ETM trace collection");
1841
1842         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
1843                 COMMAND_EXEC, "anaylze collected ETM trace");
1844
1845         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
1846                 COMMAND_EXEC, "load image from <file> [base address]");
1847
1848         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
1849                 COMMAND_EXEC, "dump captured trace data <file>");
1850         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
1851                 COMMAND_EXEC, "load trace data for analysis <file>");
1852
1853         return ERROR_OK;
1854 }
openocd with support for Altus Metrum targets