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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm.h"
  25 #include "etm.h"
  26 #include "etb.h"
  27 #include "image.h"
  28 #include "arm_disassembler.h"
  29 #include "register.h"
  30 #include "etm_dummy.h"
  31
  32 #if BUILD_OOCD_TRACE == 1
  33 #include "oocd_trace.h"
  34 #endif
  35
  36
  37 /*
  38  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  39  *
  40  * ETM modules collect instruction and/or data trace information, compress
  41  * it, and transfer it to a debugging host through either a (buffered) trace
  42  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  43  *
  44  * There are several generations of these modules.  Original versions have
  45  * JTAG access through a dedicated scan chain.  Recent versions have added
  46  * access via coprocessor instructions, memory addressing, and the ARM Debug
  47  * Interface v5 (ADIv5); and phased out direct JTAG access.
  48  *
  49  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  50  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  51  * implying non-JTAG connectivity options.
  52  *
  53  * Relevant documentation includes:
  54  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  55  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  56  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  57  */
  58
  59 enum {
  60         RO,                             /* read/only */
  61         WO,                             /* write/only */
  62         RW,                             /* read/write */
  63 };
  64
  65 struct etm_reg_info {
  66         uint8_t         addr;
  67         uint8_t         size;           /* low-N of 32 bits */
  68         uint8_t         mode;           /* RO, WO, RW */
  69         uint8_t         bcd_vers;       /* 1.0, 2.0, etc */
  70         char            *name;
  71 };
  72
  73 /*
  74  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  75  * (Or on some processors, through coprocessor operations.)
  76  * Newer versions of ETM make some W/O registers R/W, and
  77  * provide definitions for some previously-unused bits.
  78  */
  79
  80 /* core registers used to version/configure the ETM */
  81 static const struct etm_reg_info etm_core[] = {
  82         /* NOTE: we "know" the order here ... */
  83         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  84         { ETM_ID, 32, RO, 0x20, "ETM_id", },
  85 };
  86
  87 /* basic registers that are always there given the right ETM version */
  88 static const struct etm_reg_info etm_basic[] = {
  89         /* ETM Trace Registers */
  90         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  91         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  92         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
  93         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
  94         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
  95
  96         /* TraceEnable configuration */
  97         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  98         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  99         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
 100         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
 101
 102         /* ViewData configuration (data trace) */
 103         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
 104         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
 105         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
 106         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
 107
 108         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 109
 110         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
 111         { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
 112         { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
 113         { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
 114         { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
 115 };
 116
 117 static const struct etm_reg_info etm_fifofull[] = {
 118         /* FIFOFULL configuration */
 119         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
 120         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
 121 };
 122
 123 static const struct etm_reg_info etm_addr_comp[] = {
 124         /* Address comparator register pairs */
 125 #define ADDR_COMPARATOR(i) \
 126                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
 127                                 "ETM_addr_" #i "_comparator_value", }, \
 128                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
 129                                 "ETM_addr_" #i "_access_type", }
 130         ADDR_COMPARATOR(1),
 131         ADDR_COMPARATOR(2),
 132         ADDR_COMPARATOR(3),
 133         ADDR_COMPARATOR(4),
 134         ADDR_COMPARATOR(5),
 135         ADDR_COMPARATOR(6),
 136         ADDR_COMPARATOR(7),
 137         ADDR_COMPARATOR(8),
 138
 139         ADDR_COMPARATOR(9),
 140         ADDR_COMPARATOR(10),
 141         ADDR_COMPARATOR(11),
 142         ADDR_COMPARATOR(12),
 143         ADDR_COMPARATOR(13),
 144         ADDR_COMPARATOR(14),
 145         ADDR_COMPARATOR(15),
 146         ADDR_COMPARATOR(16),
 147 #undef ADDR_COMPARATOR
 148 };
 149
 150 static const struct etm_reg_info etm_data_comp[] = {
 151         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 152 #define DATA_COMPARATOR(i) \
 153                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
 154                                 "ETM_data_" #i "_comparator_value", }, \
 155                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
 156                                 "ETM_data_" #i "_comparator_mask", }
 157         DATA_COMPARATOR(1),
 158         DATA_COMPARATOR(2),
 159         DATA_COMPARATOR(3),
 160         DATA_COMPARATOR(4),
 161         DATA_COMPARATOR(5),
 162         DATA_COMPARATOR(6),
 163         DATA_COMPARATOR(7),
 164         DATA_COMPARATOR(8),
 165 #undef DATA_COMPARATOR
 166 };
 167
 168 static const struct etm_reg_info etm_counters[] = {
 169 #define ETM_COUNTER(i) \
 170                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
 171                                 "ETM_counter_" #i "_reload_value", }, \
 172                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
 173                                 "ETM_counter_" #i "_enable", }, \
 174                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
 175                                 "ETM_counter_" #i "_reload_event", }, \
 176                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
 177                                 "ETM_counter_" #i "_value", }
 178         ETM_COUNTER(1),
 179         ETM_COUNTER(2),
 180         ETM_COUNTER(3),
 181         ETM_COUNTER(4),
 182 #undef ETM_COUNTER
 183 };
 184
 185 static const struct etm_reg_info etm_sequencer[] = {
 186 #define ETM_SEQ(i) \
 187                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 188                                 "ETM_sequencer_event" #i, }
 189         ETM_SEQ(0),                             /* 1->2 */
 190         ETM_SEQ(1),                             /* 2->1 */
 191         ETM_SEQ(2),                             /* 2->3 */
 192         ETM_SEQ(3),                             /* 3->1 */
 193         ETM_SEQ(4),                             /* 3->2 */
 194         ETM_SEQ(5),                             /* 1->3 */
 195 #undef ETM_SEQ
 196         /* 0x66 reserved */
 197         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
 198 };
 199
 200 static const struct etm_reg_info etm_outputs[] = {
 201 #define ETM_OUTPUT(i) \
 202                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
 203                                 "ETM_external_output" #i, }
 204
 205         ETM_OUTPUT(1),
 206         ETM_OUTPUT(2),
 207         ETM_OUTPUT(3),
 208         ETM_OUTPUT(4),
 209 #undef ETM_OUTPUT
 210 };
 211
 212 #if 0
 213         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 214
 215         /* Context ID Comparators */
 216         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
 217         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
 218         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
 219         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
 220 #endif
 221
 222 static int etm_get_reg(struct reg *reg);
 223 static int etm_read_reg_w_check(struct reg *reg,
 224                 uint8_t* check_value, uint8_t* check_mask);
 225 static int etm_register_user_commands(struct command_context *cmd_ctx);
 226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
 227 static int etm_write_reg(struct reg *reg, uint32_t value);
 228
 229 static const struct reg_arch_type etm_scan6_type = {
 230         .get = etm_get_reg,
 231         .set = etm_set_reg_w_exec,
 232 };
 233
 234 /* Look up register by ID ... most ETM instances only
 235  * support a subset of the possible registers.
 236  */
 237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
 238 {
 239         struct reg_cache *cache = etm_ctx->reg_cache;
 240         unsigned i;
 241
 242         for (i = 0; i < cache->num_regs; i++) {
 243                 struct etm_reg *reg = cache->reg_list[i].arch_info;
 244
 245                 if (reg->reg_info->addr == id)
 246                         return &cache->reg_list[i];
 247         }
 248
 249         /* caller asking for nonexistent register is a bug! */
 250         /* REVISIT say which of the N targets was involved */
 251         LOG_ERROR("ETM: register 0x%02x not available", id);
 252         return NULL;
 253 }
 254
 255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
 256                 struct reg_cache *cache, struct etm_reg *ereg,
 257                 const struct etm_reg_info *r, unsigned nreg)
 258 {
 259         struct reg *reg = cache->reg_list;
 260
 261         reg += cache->num_regs;
 262         ereg += cache->num_regs;
 263
 264         /* add up to "nreg" registers from "r", if supported by this
 265          * version of the ETM, to the specified cache.
 266          */
 267         for (; nreg--; r++) {
 268
 269                 /* this ETM may be too old to have some registers */
 270                 if (r->bcd_vers > bcd_vers)
 271                         continue;
 272
 273                 reg->name = r->name;
 274                 reg->size = r->size;
 275                 reg->value = &ereg->value;
 276                 reg->arch_info = ereg;
 277                 reg->type = &etm_scan6_type;
 278                 reg++;
 279                 cache->num_regs++;
 280
 281                 ereg->reg_info = r;
 282                 ereg->jtag_info = jtag_info;
 283                 ereg++;
 284         }
 285 }
 286
 287 struct reg_cache *etm_build_reg_cache(struct target *target,
 288                 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
 289 {
 290         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 291         struct reg *reg_list = NULL;
 292         struct etm_reg *arch_info = NULL;
 293         unsigned bcd_vers, config;
 294
 295         /* the actual registers are kept in two arrays */
 296         reg_list = calloc(128, sizeof(struct reg));
 297         arch_info = calloc(128, sizeof(struct etm_reg));
 298
 299         /* fill in values for the reg cache */
 300         reg_cache->name = "etm registers";
 301         reg_cache->next = NULL;
 302         reg_cache->reg_list = reg_list;
 303         reg_cache->num_regs = 0;
 304
 305         /* add ETM_CONFIG, then parse its values to see
 306          * which other registers exist in this ETM
 307          */
 308         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 309                         etm_core, 1);
 310
 311         etm_get_reg(reg_list);
 312         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 313         config = etm_ctx->config;
 314
 315         /* figure ETM version then add base registers */
 316         if (config & (1 << 31)) {
 317                 bcd_vers = 0x20;
 318                 LOG_WARNING("ETMv2+ support is incomplete");
 319
 320                 /* REVISIT more registers may exist; they may now be
 321                  * readable; more register bits have defined meanings;
 322                  * don't presume trace start/stop support is present;
 323                  * and include any context ID comparator registers.
 324                  */
 325                 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
 326                                 etm_core + 1, 1);
 327                 etm_get_reg(reg_list + 1);
 328                 etm_ctx->id = buf_get_u32(
 329                                 (void *)&arch_info[1].value, 0, 32);
 330                 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
 331                 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
 332
 333         } else {
 334                 switch (config >> 28) {
 335                 case 7:
 336                 case 5:
 337                 case 3:
 338                         bcd_vers = 0x13;
 339                         break;
 340                 case 4:
 341                 case 2:
 342                         bcd_vers = 0x12;
 343                         break;
 344                 case 1:
 345                         bcd_vers = 0x11;
 346                         break;
 347                 case 0:
 348                         bcd_vers = 0x10;
 349                         break;
 350                 default:
 351                         LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 352                         goto fail;
 353                 }
 354         }
 355         etm_ctx->bcd_vers = bcd_vers;
 356         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 357
 358         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 359                         etm_basic, ARRAY_SIZE(etm_basic));
 360
 361         /* address and data comparators; counters; outputs */
 362         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 363                         etm_addr_comp, 4 * (0x0f & (config >> 0)));
 364         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 365                         etm_data_comp, 2 * (0x0f & (config >> 4)));
 366         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 367                         etm_counters, 4 * (0x07 & (config >> 13)));
 368         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 369                         etm_outputs, (0x07 & (config >> 20)));
 370
 371         /* FIFOFULL presence is optional
 372          * REVISIT for ETMv1.2 and later, don't bother adding this
 373          * unless ETM_SYS_CONFIG says it's also *supported* ...
 374          */
 375         if (config & (1 << 23))
 376                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 377                                 etm_fifofull, ARRAY_SIZE(etm_fifofull));
 378
 379         /* sequencer is optional (for state-dependant triggering) */
 380         if (config & (1 << 16))
 381                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 382                                 etm_sequencer, ARRAY_SIZE(etm_sequencer));
 383
 384         /* REVISIT could realloc and likely save half the memory
 385          * in the two chunks we allocated...
 386          */
 387
 388         /* the ETM might have an ETB connected */
 389         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 390         {
 391                 struct etb *etb = etm_ctx->capture_driver_priv;
 392
 393                 if (!etb)
 394                 {
 395                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 396                         goto fail;
 397                 }
 398
 399                 reg_cache->next = etb_build_reg_cache(etb);
 400
 401                 etb->reg_cache = reg_cache->next;
 402         }
 403
 404         etm_ctx->reg_cache = reg_cache;
 405         return reg_cache;
 406
 407 fail:
 408         free(reg_cache);
 409         free(reg_list);
 410         free(arch_info);
 411         return NULL;
 412 }
 413
 414 static int etm_read_reg(struct reg *reg)
 415 {
 416         return etm_read_reg_w_check(reg, NULL, NULL);
 417 }
 418
 419 static int etm_store_reg(struct reg *reg)
 420 {
 421         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 422 }
 423
 424 int etm_setup(struct target *target)
 425 {
 426         int retval;
 427         uint32_t etm_ctrl_value;
 428         struct arm *arm = target_to_arm(target);
 429         struct etm_context *etm_ctx = arm->etm;
 430         struct reg *etm_ctrl_reg;
 431
 432         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 433         if (!etm_ctrl_reg)
 434                 return ERROR_OK;
 435
 436         /* initialize some ETM control register settings */
 437         etm_get_reg(etm_ctrl_reg);
 438         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
 439
 440         /* clear the ETM powerdown bit (0) */
 441         etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
 442
 443         /* configure port width (21,6:4), mode (13,17:16) and
 444          * for older modules clocking (13)
 445          */
 446         etm_ctrl_value = (etm_ctrl_value
 447                         & ~ETM_PORT_WIDTH_MASK
 448                         & ~ETM_PORT_MODE_MASK
 449                         & ~ETM_CTRL_DBGRQ
 450                         & ~ETM_PORT_CLOCK_MASK)
 451                 | etm_ctx->control;
 452
 453         buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
 454         etm_store_reg(etm_ctrl_reg);
 455
 456         etm_ctx->control = etm_ctrl_value;
 457
 458         if ((retval = jtag_execute_queue()) != ERROR_OK)
 459                 return retval;
 460
 461         /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
 462          * verify that those width and mode settings are OK ...
 463          */
 464
 465         if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 466         {
 467                 LOG_ERROR("ETM capture driver initialization failed");
 468                 return retval;
 469         }
 470         return ERROR_OK;
 471 }
 472
 473 static int etm_get_reg(struct reg *reg)
 474 {
 475         int retval;
 476
 477         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 478         {
 479                 LOG_ERROR("BUG: error scheduling etm register read");
 480                 return retval;
 481         }
 482
 483         if ((retval = jtag_execute_queue()) != ERROR_OK)
 484         {
 485                 LOG_ERROR("register read failed");
 486                 return retval;
 487         }
 488
 489         return ERROR_OK;
 490 }
 491
 492 static int etm_read_reg_w_check(struct reg *reg,
 493                 uint8_t* check_value, uint8_t* check_mask)
 494 {
 495         struct etm_reg *etm_reg = reg->arch_info;
 496         const struct etm_reg_info *r = etm_reg->reg_info;
 497         uint8_t reg_addr = r->addr & 0x7f;
 498         struct scan_field fields[3];
 499
 500         if (etm_reg->reg_info->mode == WO) {
 501                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 502                 return ERROR_INVALID_ARGUMENTS;
 503         }
 504
 505         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 506
 507         jtag_set_end_state(TAP_IDLE);
 508         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 509         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 510
 511         fields[0].tap = etm_reg->jtag_info->tap;
 512         fields[0].num_bits = 32;
 513         fields[0].out_value = reg->value;
 514         fields[0].in_value = NULL;
 515         fields[0].check_value = NULL;
 516         fields[0].check_mask = NULL;
 517
 518         fields[1].tap = etm_reg->jtag_info->tap;
 519         fields[1].num_bits = 7;
 520         fields[1].out_value = malloc(1);
 521         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 522         fields[1].in_value = NULL;
 523         fields[1].check_value = NULL;
 524         fields[1].check_mask = NULL;
 525
 526         fields[2].tap = etm_reg->jtag_info->tap;
 527         fields[2].num_bits = 1;
 528         fields[2].out_value = malloc(1);
 529         buf_set_u32(fields[2].out_value, 0, 1, 0);
 530         fields[2].in_value = NULL;
 531         fields[2].check_value = NULL;
 532         fields[2].check_mask = NULL;
 533
 534         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 535
 536         fields[0].in_value = reg->value;
 537         fields[0].check_value = check_value;
 538         fields[0].check_mask = check_mask;
 539
 540         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 541
 542         free(fields[1].out_value);
 543         free(fields[2].out_value);
 544
 545         return ERROR_OK;
 546 }
 547
 548 static int etm_set_reg(struct reg *reg, uint32_t value)
 549 {
 550         int retval;
 551
 552         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 553         {
 554                 LOG_ERROR("BUG: error scheduling etm register write");
 555                 return retval;
 556         }
 557
 558         buf_set_u32(reg->value, 0, reg->size, value);
 559         reg->valid = 1;
 560         reg->dirty = 0;
 561
 562         return ERROR_OK;
 563 }
 564
 565 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 566 {
 567         int retval;
 568
 569         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 570
 571         if ((retval = jtag_execute_queue()) != ERROR_OK)
 572         {
 573                 LOG_ERROR("register write failed");
 574                 return retval;
 575         }
 576         return ERROR_OK;
 577 }
 578
 579 static int etm_write_reg(struct reg *reg, uint32_t value)
 580 {
 581         struct etm_reg *etm_reg = reg->arch_info;
 582         const struct etm_reg_info *r = etm_reg->reg_info;
 583         uint8_t reg_addr = r->addr & 0x7f;
 584         struct scan_field fields[3];
 585
 586         if (etm_reg->reg_info->mode == RO) {
 587                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 588                 return ERROR_INVALID_ARGUMENTS;
 589         }
 590
 591         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 592
 593         jtag_set_end_state(TAP_IDLE);
 594         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 595         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 596
 597         fields[0].tap = etm_reg->jtag_info->tap;
 598         fields[0].num_bits = 32;
 599         uint8_t tmp1[4];
 600         fields[0].out_value = tmp1;
 601         buf_set_u32(fields[0].out_value, 0, 32, value);
 602         fields[0].in_value = NULL;
 603
 604         fields[1].tap = etm_reg->jtag_info->tap;
 605         fields[1].num_bits = 7;
 606         uint8_t tmp2;
 607         fields[1].out_value = &tmp2;
 608         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 609         fields[1].in_value = NULL;
 610
 611         fields[2].tap = etm_reg->jtag_info->tap;
 612         fields[2].num_bits = 1;
 613         uint8_t tmp3;
 614         fields[2].out_value = &tmp3;
 615         buf_set_u32(fields[2].out_value, 0, 1, 1);
 616         fields[2].in_value = NULL;
 617
 618         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 619
 620         return ERROR_OK;
 621 }
 622
 623
 624 /* ETM trace analysis functionality */
 625
 626 static struct etm_capture_driver *etm_capture_drivers[] =
 627 {
 628         &etb_capture_driver,
 629         &etm_dummy_capture_driver,
 630 #if BUILD_OOCD_TRACE == 1
 631         &oocd_trace_capture_driver,
 632 #endif
 633         NULL
 634 };
 635
 636 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
 637 {
 638         int i;
 639         int section = -1;
 640         size_t size_read;
 641         uint32_t opcode;
 642         int retval;
 643
 644         if (!ctx->image)
 645                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 646
 647         /* search for the section the current instruction belongs to */
 648         for (i = 0; i < ctx->image->num_sections; i++)
 649         {
 650                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 651                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 652                 {
 653                         section = i;
 654                         break;
 655                 }
 656         }
 657
 658         if (section == -1)
 659         {
 660                 /* current instruction couldn't be found in the image */
 661                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 662         }
 663
 664         if (ctx->core_state == ARM_STATE_ARM)
 665         {
 666                 uint8_t buf[4];
 667                 if ((retval = image_read_section(ctx->image, section,
 668                         ctx->current_pc - ctx->image->sections[section].base_address,
 669                         4, buf, &size_read)) != ERROR_OK)
 670                 {
 671                         LOG_ERROR("error while reading instruction: %i", retval);
 672                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 673                 }
 674                 opcode = target_buffer_get_u32(ctx->target, buf);
 675                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 676         }
 677         else if (ctx->core_state == ARM_STATE_THUMB)
 678         {
 679                 uint8_t buf[2];
 680                 if ((retval = image_read_section(ctx->image, section,
 681                         ctx->current_pc - ctx->image->sections[section].base_address,
 682                         2, buf, &size_read)) != ERROR_OK)
 683                 {
 684                         LOG_ERROR("error while reading instruction: %i", retval);
 685                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 686                 }
 687                 opcode = target_buffer_get_u16(ctx->target, buf);
 688                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 689         }
 690         else if (ctx->core_state == ARM_STATE_JAZELLE)
 691         {
 692                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 693                 return ERROR_FAIL;
 694         }
 695         else
 696         {
 697                 LOG_ERROR("BUG: unknown core state encountered");
 698                 return ERROR_FAIL;
 699         }
 700
 701         return ERROR_OK;
 702 }
 703
 704 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
 705 {
 706         while (ctx->data_index < ctx->trace_depth)
 707         {
 708                 /* if the caller specified an address packet offset, skip until the
 709                  * we reach the n-th cycle marked with tracesync */
 710                 if (apo > 0)
 711                 {
 712                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 713                                 apo--;
 714
 715                         if (apo > 0)
 716                         {
 717                                 ctx->data_index++;
 718                                 ctx->data_half = 0;
 719                         }
 720                         continue;
 721                 }
 722
 723                 /* no tracedata output during a TD cycle
 724                  * or in a trigger cycle */
 725                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 726                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 727                 {
 728                         ctx->data_index++;
 729                         ctx->data_half = 0;
 730                         continue;
 731                 }
 732
 733                 /* FIXME there are more port widths than these... */
 734                 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 735                 {
 736                         if (ctx->data_half == 0)
 737                         {
 738                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 739                                 ctx->data_half = 1;
 740                         }
 741                         else
 742                         {
 743                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 744                                 ctx->data_half = 0;
 745                                 ctx->data_index++;
 746                         }
 747                 }
 748                 else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 749                 {
 750                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 751                         ctx->data_index++;
 752                 }
 753                 else
 754                 {
 755                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 756                         if (ctx->data_index > (ctx->trace_depth - 2))
 757                                 return -1;
 758
 759                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 760                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 761                         ctx->data_index += 2;
 762                 }
 763
 764                 return 0;
 765         }
 766
 767         return -1;
 768 }
 769
 770 static int etmv1_branch_address(struct etm_context *ctx)
 771 {
 772         int retval;
 773         uint8_t packet;
 774         int shift = 0;
 775         int apo;
 776         uint32_t i;
 777
 778         /* quit analysis if less than two cycles are left in the trace
 779          * because we can't extract the APO */
 780         if (ctx->data_index > (ctx->trace_depth - 2))
 781                 return -1;
 782
 783         /* a BE could be output during an APO cycle, skip the current
 784          * and continue with the new one */
 785         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 786                 return 1;
 787         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 788                 return 2;
 789
 790         /* address packet offset encoded in the next two cycles' pipestat bits */
 791         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 792         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 793
 794         /* count number of tracesync cycles between current pipe_index and data_index
 795          * i.e. the number of tracesyncs that data_index already passed by
 796          * to subtract them from the APO */
 797         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 798         {
 799                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 800                         apo--;
 801         }
 802
 803         /* extract up to four 7-bit packets */
 804         do {
 805                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 806                         return -1;
 807                 ctx->last_branch &= ~(0x7f << shift);
 808                 ctx->last_branch |= (packet & 0x7f) << shift;
 809                 shift += 7;
 810         } while ((packet & 0x80) && (shift < 28));
 811
 812         /* one last packet holding 4 bits of the address, plus the branch reason code */
 813         if ((shift == 28) && (packet & 0x80))
 814         {
 815                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 816                         return -1;
 817                 ctx->last_branch &= 0x0fffffff;
 818                 ctx->last_branch |= (packet & 0x0f) << 28;
 819                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 820                 shift += 4;
 821         }
 822         else
 823         {
 824                 ctx->last_branch_reason = 0;
 825         }
 826
 827         if (shift == 32)
 828         {
 829                 ctx->pc_ok = 1;
 830         }
 831
 832         /* if a full address was output, we might have branched into Jazelle state */
 833         if ((shift == 32) && (packet & 0x80))
 834         {
 835                 ctx->core_state = ARM_STATE_JAZELLE;
 836         }
 837         else
 838         {
 839                 /* if we didn't branch into Jazelle state, the current processor state is
 840                  * encoded in bit 0 of the branch target address */
 841                 if (ctx->last_branch & 0x1)
 842                 {
 843                         ctx->core_state = ARM_STATE_THUMB;
 844                         ctx->last_branch &= ~0x1;
 845                 }
 846                 else
 847                 {
 848                         ctx->core_state = ARM_STATE_ARM;
 849                         ctx->last_branch &= ~0x3;
 850                 }
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
 857 {
 858         int j;
 859         uint8_t buf[4];
 860         int retval;
 861
 862         for (j = 0; j < size; j++)
 863         {
 864                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 865                         return -1;
 866         }
 867
 868         if (size == 8)
 869         {
 870                 LOG_ERROR("TODO: add support for 64-bit values");
 871                 return -1;
 872         }
 873         else if (size == 4)
 874                 *data = target_buffer_get_u32(ctx->target, buf);
 875         else if (size == 2)
 876                 *data = target_buffer_get_u16(ctx->target, buf);
 877         else if (size == 1)
 878                 *data = buf[0];
 879         else
 880                 return -1;
 881
 882         return 0;
 883 }
 884
 885 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
 886 {
 887         int retval;
 888         struct arm_instruction instruction;
 889
 890         /* read the trace data if it wasn't read already */
 891         if (ctx->trace_depth == 0)
 892                 ctx->capture_driver->read_trace(ctx);
 893
 894         /* start at the beginning of the captured trace */
 895         ctx->pipe_index = 0;
 896         ctx->data_index = 0;
 897         ctx->data_half = 0;
 898
 899         /* neither the PC nor the data pointer are valid */
 900         ctx->pc_ok = 0;
 901         ctx->ptr_ok = 0;
 902
 903         while (ctx->pipe_index < ctx->trace_depth)
 904         {
 905                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 906                 uint32_t next_pc = ctx->current_pc;
 907                 uint32_t old_data_index = ctx->data_index;
 908                 uint32_t old_data_half = ctx->data_half;
 909                 uint32_t old_index = ctx->pipe_index;
 910                 uint32_t last_instruction = ctx->last_instruction;
 911                 uint32_t cycles = 0;
 912                 int current_pc_ok = ctx->pc_ok;
 913
 914                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 915                 {
 916                         command_print(cmd_ctx, "--- trigger ---");
 917                 }
 918
 919                 /* instructions execute in IE/D or BE/D cycles */
 920                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 921                         ctx->last_instruction = ctx->pipe_index;
 922
 923                 /* if we don't have a valid pc skip until we reach an indirect branch */
 924                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 925                 {
 926                         ctx->pipe_index++;
 927                         continue;
 928                 }
 929
 930                 /* any indirect branch could have interrupted instruction flow
 931                  * - the branch reason code could indicate a trace discontinuity
 932                  * - a branch to the exception vectors indicates an exception
 933                  */
 934                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 935                 {
 936                         /* backup current data index, to be able to consume the branch address
 937                          * before examining data address and values
 938                          */
 939                         old_data_index = ctx->data_index;
 940                         old_data_half = ctx->data_half;
 941
 942                         ctx->last_instruction = ctx->pipe_index;
 943
 944                         if ((retval = etmv1_branch_address(ctx)) != 0)
 945                         {
 946                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 947                                  * quit analysing the trace */
 948                                 if (retval < 0)
 949                                         break;
 950
 951                                 /* a positive return values means the current branch was abandoned,
 952                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 953                                  */
 954                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 955                                 ctx->pipe_index += retval;
 956                                 continue;
 957                         }
 958
 959                         /* skip over APO cycles */
 960                         ctx->pipe_index += 2;
 961
 962                         switch (ctx->last_branch_reason)
 963                         {
 964                                 case 0x0:       /* normal PC change */
 965                                         next_pc = ctx->last_branch;
 966                                         break;
 967                                 case 0x1:       /* tracing enabled */
 968                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 969                                         ctx->current_pc = ctx->last_branch;
 970                                         ctx->pipe_index++;
 971                                         continue;
 972                                         break;
 973                                 case 0x2:       /* trace restarted after FIFO overflow */
 974                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 975                                         ctx->current_pc = ctx->last_branch;
 976                                         ctx->pipe_index++;
 977                                         continue;
 978                                         break;
 979                                 case 0x3:       /* exit from debug state */
 980                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 981                                         ctx->current_pc = ctx->last_branch;
 982                                         ctx->pipe_index++;
 983                                         continue;
 984                                         break;
 985                                 case 0x4:       /* periodic synchronization point */
 986                                         next_pc = ctx->last_branch;
 987                                         /* if we had no valid PC prior to this synchronization point,
 988                                          * we have to move on with the next trace cycle
 989                                          */
 990                                         if (!current_pc_ok)
 991                                         {
 992                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 993                                                 ctx->current_pc = next_pc;
 994                                                 ctx->pipe_index++;
 995                                                 continue;
 996                                         }
 997                                         break;
 998                                 default:        /* reserved */
 999                                         LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
1000                                         return ERROR_FAIL;
1001                         }
1002
1003                         /* if we got here the branch was a normal PC change
1004                          * (or a periodic synchronization point, which means the same for that matter)
1005                          * if we didn't accquire a complete PC continue with the next cycle
1006                          */
1007                         if (!ctx->pc_ok)
1008                                 continue;
1009
1010                         /* indirect branch to the exception vector means an exception occured */
1011                         if ((ctx->last_branch <= 0x20)
1012                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1013                         {
1014                                 if ((ctx->last_branch & 0xff) == 0x10)
1015                                 {
1016                                         command_print(cmd_ctx, "data abort");
1017                                 }
1018                                 else
1019                                 {
1020                                         command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1021                                         ctx->current_pc = ctx->last_branch;
1022                                         ctx->pipe_index++;
1023                                         continue;
1024                                 }
1025                         }
1026                 }
1027
1028                 /* an instruction was executed (or not, depending on the condition flags)
1029                  * retrieve it from the image for displaying */
1030                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1031                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1032                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1033                 {
1034                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1035                         {
1036                                 /* can't continue tracing with no image available */
1037                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1038                                 {
1039                                         return retval;
1040                                 }
1041                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1042                                 {
1043                                         /* TODO: handle incomplete images
1044                                          * for now we just quit the analsysis*/
1045                                         return retval;
1046                                 }
1047                         }
1048
1049                         cycles = old_index - last_instruction;
1050                 }
1051
1052                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1053                 {
1054                         uint32_t new_data_index = ctx->data_index;
1055                         uint32_t new_data_half = ctx->data_half;
1056
1057                         /* in case of a branch with data, the branch target address was consumed before
1058                          * we temporarily go back to the saved data index */
1059                         if (pipestat == STAT_BD)
1060                         {
1061                                 ctx->data_index = old_data_index;
1062                                 ctx->data_half = old_data_half;
1063                         }
1064
1065                         if (ctx->control & ETM_CTRL_TRACE_ADDR)
1066                         {
1067                                 uint8_t packet;
1068                                 int shift = 0;
1069
1070                                 do {
1071                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1072                                                 return ERROR_ETM_ANALYSIS_FAILED;
1073                                         ctx->last_ptr &= ~(0x7f << shift);
1074                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1075                                         shift += 7;
1076                                 } while ((packet & 0x80) && (shift < 32));
1077
1078                                 if (shift >= 32)
1079                                         ctx->ptr_ok = 1;
1080
1081                                 if (ctx->ptr_ok)
1082                                 {
1083                                         command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1084                                 }
1085                         }
1086
1087                         if (ctx->control & ETM_CTRL_TRACE_DATA)
1088                         {
1089                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1090                                 {
1091                                         int i;
1092                                         for (i = 0; i < 16; i++)
1093                                         {
1094                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
1095                                                 {
1096                                                         uint32_t data;
1097                                                         if (etmv1_data(ctx, 4, &data) != 0)
1098                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1099                                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1100                                                 }
1101                                         }
1102                                 }
1103                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1104                                 {
1105                                         uint32_t data;
1106                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1107                                                 return ERROR_ETM_ANALYSIS_FAILED;
1108                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1109                                 }
1110                         }
1111
1112                         /* restore data index after consuming BD address and data */
1113                         if (pipestat == STAT_BD)
1114                         {
1115                                 ctx->data_index = new_data_index;
1116                                 ctx->data_half = new_data_half;
1117                         }
1118                 }
1119
1120                 /* adjust PC */
1121                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1122                 {
1123                         if (((instruction.type == ARM_B) ||
1124                              (instruction.type == ARM_BL) ||
1125                              (instruction.type == ARM_BLX)) &&
1126                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1127                         {
1128                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1129                         }
1130                         else
1131                         {
1132                                 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1133                         }
1134                 }
1135                 else if (pipestat == STAT_IN)
1136                 {
1137                         next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1138                 }
1139
1140                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1141                 {
1142                         char cycles_text[32] = "";
1143
1144                         /* if the trace was captured with cycle accurate tracing enabled,
1145                          * output the number of cycles since the last executed instruction
1146                          */
1147                         if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
1148                         {
1149                                 snprintf(cycles_text, 32, " (%i %s)",
1150                                          (int)cycles,
1151                                         (cycles == 1) ? "cycle" : "cycles");
1152                         }
1153
1154                         command_print(cmd_ctx, "%s%s%s",
1155                                 instruction.text,
1156                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1157                                 cycles_text);
1158
1159                         ctx->current_pc = next_pc;
1160
1161                         /* packets for an instruction don't start on or before the preceding
1162                          * functional pipestat (i.e. other than WT or TD)
1163                          */
1164                         if (ctx->data_index <= ctx->pipe_index)
1165                         {
1166                                 ctx->data_index = ctx->pipe_index + 1;
1167                                 ctx->data_half = 0;
1168                         }
1169                 }
1170
1171                 ctx->pipe_index += 1;
1172         }
1173
1174         return ERROR_OK;
1175 }
1176
1177 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1178                 uint32_t *mode)
1179 {
1180         uint32_t tracemode;
1181
1182         /* what parts of data access are traced? */
1183         if (strcmp(CMD_ARGV[0], "none") == 0)
1184                 tracemode = 0;
1185         else if (strcmp(CMD_ARGV[0], "data") == 0)
1186                 tracemode = ETM_CTRL_TRACE_DATA;
1187         else if (strcmp(CMD_ARGV[0], "address") == 0)
1188                 tracemode = ETM_CTRL_TRACE_ADDR;
1189         else if (strcmp(CMD_ARGV[0], "all") == 0)
1190                 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1191         else
1192         {
1193                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1194                 return ERROR_INVALID_ARGUMENTS;
1195         }
1196
1197         uint8_t context_id;
1198         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1199         switch (context_id)
1200         {
1201         case 0:
1202                 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1203                 break;
1204         case 8:
1205                 tracemode |= ETM_CTRL_CONTEXTID_8;
1206                 break;
1207         case 16:
1208                 tracemode |= ETM_CTRL_CONTEXTID_16;
1209                 break;
1210         case 32:
1211                 tracemode |= ETM_CTRL_CONTEXTID_32;
1212                 break;
1213         default:
1214                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1215                 return ERROR_INVALID_ARGUMENTS;
1216         }
1217
1218         bool etmv1_cycle_accurate;
1219         COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1220         if (etmv1_cycle_accurate)
1221                 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1222
1223         bool etmv1_branch_output;
1224         COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1225         if (etmv1_branch_output)
1226                 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1227
1228         /* IGNORED:
1229          *  - CPRT tracing (coprocessor register transfers)
1230          *  - debug request (causes debug entry on trigger)
1231          *  - stall on FIFOFULL (preventing tracedata lossage)
1232          */
1233         *mode = tracemode;
1234
1235         return ERROR_OK;
1236 }
1237
1238 COMMAND_HANDLER(handle_etm_tracemode_command)
1239 {
1240         struct target *target = get_current_target(CMD_CTX);
1241         struct arm *arm = target_to_arm(target);
1242         struct etm_context *etm;
1243
1244         if (!is_arm(arm)) {
1245                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1246                 return ERROR_FAIL;
1247         }
1248
1249         etm = arm->etm;
1250         if (!etm) {
1251                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1252                 return ERROR_FAIL;
1253         }
1254
1255         uint32_t tracemode = etm->control;
1256
1257         switch (CMD_ARGC)
1258         {
1259         case 0:
1260                 break;
1261         case 4:
1262                 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode);
1263                 break;
1264         default:
1265                 command_print(CMD_CTX, "usage: configure trace mode "
1266                                 "<none | data | address | all> "
1267                                 "<context id bits> <cycle accurate> <branch output>");
1268                 return ERROR_FAIL;
1269         }
1270
1271         /**
1272          * todo: fail if parameters were invalid for this hardware,
1273          * or couldn't be written; display actual hardware state...
1274          */
1275
1276         command_print(CMD_CTX, "current tracemode configuration:");
1277
1278         switch (tracemode & ETM_CTRL_TRACE_MASK)
1279         {
1280                 default:
1281                         command_print(CMD_CTX, "data tracing: none");
1282                         break;
1283                 case ETM_CTRL_TRACE_DATA:
1284                         command_print(CMD_CTX, "data tracing: data only");
1285                         break;
1286                 case ETM_CTRL_TRACE_ADDR:
1287                         command_print(CMD_CTX, "data tracing: address only");
1288                         break;
1289                 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1290                         command_print(CMD_CTX, "data tracing: address and data");
1291                         break;
1292         }
1293
1294         switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
1295         {
1296                 case ETM_CTRL_CONTEXTID_NONE:
1297                         command_print(CMD_CTX, "contextid tracing: none");
1298                         break;
1299                 case ETM_CTRL_CONTEXTID_8:
1300                         command_print(CMD_CTX, "contextid tracing: 8 bit");
1301                         break;
1302                 case ETM_CTRL_CONTEXTID_16:
1303                         command_print(CMD_CTX, "contextid tracing: 16 bit");
1304                         break;
1305                 case ETM_CTRL_CONTEXTID_32:
1306                         command_print(CMD_CTX, "contextid tracing: 32 bit");
1307                         break;
1308         }
1309
1310         if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1311         {
1312                 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1313         }
1314         else
1315         {
1316                 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1317         }
1318
1319         if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1320         {
1321                 command_print(CMD_CTX, "full branch address output enabled");
1322         }
1323         else
1324         {
1325                 command_print(CMD_CTX, "full branch address output disabled");
1326         }
1327
1328 #define TRACEMODE_MASK ( \
1329           ETM_CTRL_CONTEXTID_MASK \
1330         | ETM_CTRL_BRANCH_OUTPUT \
1331         | ETM_CTRL_CYCLE_ACCURATE \
1332         | ETM_CTRL_TRACE_MASK \
1333         )
1334
1335         /* only update ETM_CTRL register if tracemode changed */
1336         if ((etm->control & TRACEMODE_MASK) != tracemode)
1337         {
1338                 struct reg *etm_ctrl_reg;
1339
1340                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1341                 if (!etm_ctrl_reg)
1342                         return ERROR_FAIL;
1343
1344                 etm->control &= ~TRACEMODE_MASK;
1345                 etm->control |= tracemode & TRACEMODE_MASK;
1346
1347                 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1348                 etm_store_reg(etm_ctrl_reg);
1349
1350                 /* invalidate old trace data */
1351                 etm->capture_status = TRACE_IDLE;
1352                 if (etm->trace_depth > 0)
1353                 {
1354                         free(etm->trace_data);
1355                         etm->trace_data = NULL;
1356                 }
1357                 etm->trace_depth = 0;
1358         }
1359
1360 #undef TRACEMODE_MASK
1361
1362         return ERROR_OK;
1363 }
1364
1365 COMMAND_HANDLER(handle_etm_config_command)
1366 {
1367         struct target *target;
1368         struct arm *arm;
1369         uint32_t portmode = 0x0;
1370         struct etm_context *etm_ctx;
1371         int i;
1372
1373         if (CMD_ARGC != 5)
1374                 return ERROR_COMMAND_SYNTAX_ERROR;
1375
1376         target = get_target(CMD_ARGV[0]);
1377         if (!target)
1378         {
1379                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1380                 return ERROR_FAIL;
1381         }
1382
1383         arm = target_to_arm(target);
1384         if (!is_arm(arm)) {
1385                 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1386                                 target_name(target),
1387                                 target_type_name(target));
1388                 return ERROR_FAIL;
1389         }
1390
1391         /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1392          * version we'll be using!! -- so we can't know how to validate
1393          * params yet.  "etm config" should likely be *AFTER* hookup...
1394          *
1395          *  - Many more widths might be supported ... and we can easily
1396          *    check whether our setting "took".
1397          *
1398          *  - The "clock" and "mode" bits are interpreted differently.
1399          *    See ARM IHI 0014O table 2-17 for the old behavior, and
1400          *    table 2-18 for the new.  With ETB it's best to specify
1401          *    "normal full" ...
1402          */
1403         uint8_t port_width;
1404         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1405         switch (port_width)
1406         {
1407                 /* before ETMv3.0 */
1408                 case 4:
1409                         portmode |= ETM_PORT_4BIT;
1410                         break;
1411                 case 8:
1412                         portmode |= ETM_PORT_8BIT;
1413                         break;
1414                 case 16:
1415                         portmode |= ETM_PORT_16BIT;
1416                         break;
1417                 /* ETMv3.0 and later*/
1418                 case 24:
1419                         portmode |= ETM_PORT_24BIT;
1420                         break;
1421                 case 32:
1422                         portmode |= ETM_PORT_32BIT;
1423                         break;
1424                 case 48:
1425                         portmode |= ETM_PORT_48BIT;
1426                         break;
1427                 case 64:
1428                         portmode |= ETM_PORT_64BIT;
1429                         break;
1430                 case 1:
1431                         portmode |= ETM_PORT_1BIT;
1432                         break;
1433                 case 2:
1434                         portmode |= ETM_PORT_2BIT;
1435                         break;
1436                 default:
1437                         command_print(CMD_CTX,
1438                                 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1439                         return ERROR_FAIL;
1440         }
1441
1442         if (strcmp("normal", CMD_ARGV[2]) == 0)
1443         {
1444                 portmode |= ETM_PORT_NORMAL;
1445         }
1446         else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1447         {
1448                 portmode |= ETM_PORT_MUXED;
1449         }
1450         else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1451         {
1452                 portmode |= ETM_PORT_DEMUXED;
1453         }
1454         else
1455         {
1456                 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1457                 return ERROR_FAIL;
1458         }
1459
1460         if (strcmp("half", CMD_ARGV[3]) == 0)
1461         {
1462                 portmode |= ETM_PORT_HALF_CLOCK;
1463         }
1464         else if (strcmp("full", CMD_ARGV[3]) == 0)
1465         {
1466                 portmode |= ETM_PORT_FULL_CLOCK;
1467         }
1468         else
1469         {
1470                 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1471                 return ERROR_FAIL;
1472         }
1473
1474         etm_ctx = calloc(1, sizeof(struct etm_context));
1475         if (!etm_ctx) {
1476                 LOG_DEBUG("out of memory");
1477                 return ERROR_FAIL;
1478         }
1479
1480         for (i = 0; etm_capture_drivers[i]; i++)
1481         {
1482                 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1483                 {
1484                         int retval = register_commands(CMD_CTX, NULL,
1485                                         etm_capture_drivers[i]->commands);
1486                         if (ERROR_OK != retval)
1487                         {
1488                                 free(etm_ctx);
1489                                 return retval;
1490                         }
1491
1492                         etm_ctx->capture_driver = etm_capture_drivers[i];
1493
1494                         break;
1495                 }
1496         }
1497
1498         if (!etm_capture_drivers[i])
1499         {
1500                 /* no supported capture driver found, don't register an ETM */
1501                 free(etm_ctx);
1502                 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1503                 return ERROR_FAIL;
1504         }
1505
1506         etm_ctx->target = target;
1507         etm_ctx->trace_data = NULL;
1508         etm_ctx->control = portmode;
1509         etm_ctx->core_state = ARM_STATE_ARM;
1510
1511         arm->etm = etm_ctx;
1512
1513         return etm_register_user_commands(CMD_CTX);
1514 }
1515
1516 COMMAND_HANDLER(handle_etm_info_command)
1517 {
1518         struct target *target;
1519         struct arm *arm;
1520         struct etm_context *etm;
1521         struct reg *etm_sys_config_reg;
1522         int max_port_size;
1523         uint32_t config;
1524
1525         target = get_current_target(CMD_CTX);
1526         arm = target_to_arm(target);
1527         if (!is_arm(arm))
1528         {
1529                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1530                 return ERROR_FAIL;
1531         }
1532
1533         etm = arm->etm;
1534         if (!etm)
1535         {
1536                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1537                 return ERROR_FAIL;
1538         }
1539
1540         command_print(CMD_CTX, "ETM v%d.%d",
1541                         etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1542         command_print(CMD_CTX, "pairs of address comparators: %i",
1543                         (int) (etm->config >> 0) & 0x0f);
1544         command_print(CMD_CTX, "data comparators: %i",
1545                         (int) (etm->config >> 4) & 0x0f);
1546         command_print(CMD_CTX, "memory map decoders: %i",
1547                         (int) (etm->config >> 8) & 0x1f);
1548         command_print(CMD_CTX, "number of counters: %i",
1549                         (int) (etm->config >> 13) & 0x07);
1550         command_print(CMD_CTX, "sequencer %spresent",
1551                         (int) (etm->config & (1 << 16)) ? "" : "not ");
1552         command_print(CMD_CTX, "number of ext. inputs: %i",
1553                         (int) (etm->config >> 17) & 0x07);
1554         command_print(CMD_CTX, "number of ext. outputs: %i",
1555                         (int) (etm->config >> 20) & 0x07);
1556         command_print(CMD_CTX, "FIFO full %spresent",
1557                         (int) (etm->config & (1 << 23)) ? "" : "not ");
1558         if (etm->bcd_vers < 0x20)
1559                 command_print(CMD_CTX, "protocol version: %i",
1560                                 (int) (etm->config >> 28) & 0x07);
1561         else {
1562                 command_print(CMD_CTX,
1563                                 "coprocessor and memory access %ssupported",
1564                                 (etm->config & (1 << 26)) ? "" : "not ");
1565                 command_print(CMD_CTX, "trace start/stop %spresent",
1566                                 (etm->config & (1 << 26)) ? "" : "not ");
1567                 command_print(CMD_CTX, "number of context comparators: %i",
1568                                 (int) (etm->config >> 24) & 0x03);
1569         }
1570
1571         /* SYS_CONFIG isn't present before ETMv1.2 */
1572         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1573         if (!etm_sys_config_reg)
1574                 return ERROR_OK;
1575
1576         etm_get_reg(etm_sys_config_reg);
1577         config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1578
1579         LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1580
1581         max_port_size = config & 0x7;
1582         if (etm->bcd_vers >= 0x30)
1583                 max_port_size |= (config >> 6) & 0x08;
1584         switch (max_port_size)
1585         {
1586                 /* before ETMv3.0 */
1587                 case 0:
1588                         max_port_size = 4;
1589                         break;
1590                 case 1:
1591                         max_port_size = 8;
1592                         break;
1593                 case 2:
1594                         max_port_size = 16;
1595                         break;
1596                 /* ETMv3.0 and later*/
1597                 case 3:
1598                         max_port_size = 24;
1599                         break;
1600                 case 4:
1601                         max_port_size = 32;
1602                         break;
1603                 case 5:
1604                         max_port_size = 48;
1605                         break;
1606                 case 6:
1607                         max_port_size = 64;
1608                         break;
1609                 case 8:
1610                         max_port_size = 1;
1611                         break;
1612                 case 9:
1613                         max_port_size = 2;
1614                         break;
1615                 default:
1616                         LOG_ERROR("Illegal max_port_size");
1617                         return ERROR_FAIL;
1618         }
1619         command_print(CMD_CTX, "max. port size: %i", max_port_size);
1620
1621         if (etm->bcd_vers < 0x30) {
1622                 command_print(CMD_CTX, "half-rate clocking %ssupported",
1623                                 (config & (1 << 3)) ? "" : "not ");
1624                 command_print(CMD_CTX, "full-rate clocking %ssupported",
1625                                 (config & (1 << 4)) ? "" : "not ");
1626                 command_print(CMD_CTX, "normal trace format %ssupported",
1627                                 (config & (1 << 5)) ? "" : "not ");
1628                 command_print(CMD_CTX, "multiplex trace format %ssupported",
1629                                 (config & (1 << 6)) ? "" : "not ");
1630                 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1631                                 (config & (1 << 7)) ? "" : "not ");
1632         } else {
1633                 /* REVISIT show which size and format are selected ... */
1634                 command_print(CMD_CTX, "current port size %ssupported",
1635                                 (config & (1 << 10)) ? "" : "not ");
1636                 command_print(CMD_CTX, "current trace format %ssupported",
1637                                 (config & (1 << 11)) ? "" : "not ");
1638         }
1639         if (etm->bcd_vers >= 0x21)
1640                 command_print(CMD_CTX, "fetch comparisons %ssupported",
1641                                 (config & (1 << 17)) ? "not " : "");
1642         command_print(CMD_CTX, "FIFO full %ssupported",
1643                         (config & (1 << 8)) ? "" : "not ");
1644
1645         return ERROR_OK;
1646 }
1647
1648 COMMAND_HANDLER(handle_etm_status_command)
1649 {
1650         struct target *target;
1651         struct arm *arm;
1652         struct etm_context *etm;
1653         trace_status_t trace_status;
1654
1655         target = get_current_target(CMD_CTX);
1656         arm = target_to_arm(target);
1657         if (!is_arm(arm))
1658         {
1659                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1660                 return ERROR_FAIL;
1661         }
1662
1663         etm = arm->etm;
1664         if (!etm)
1665         {
1666                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1667                 return ERROR_FAIL;
1668         }
1669
1670         /* ETM status */
1671         if (etm->bcd_vers >= 0x11) {
1672                 struct reg *reg;
1673
1674                 reg = etm_reg_lookup(etm, ETM_STATUS);
1675                 if (!reg)
1676                         return ERROR_FAIL;
1677                 if (etm_get_reg(reg) == ERROR_OK) {
1678                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1679
1680                         command_print(CMD_CTX, "etm: %s%s%s%s",
1681                                 /* bit(1) == progbit */
1682                                 (etm->bcd_vers >= 0x12)
1683                                         ? ((s & (1 << 1))
1684                                                 ? "disabled" : "enabled")
1685                                         : "?",
1686                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1687                                         ? " triggered" : "",
1688                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1689                                         ? " start/stop" : "",
1690                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1691                                         ? " untraced-overflow" : "");
1692                 } /* else ignore and try showing trace port status */
1693         }
1694
1695         /* Trace Port Driver status */
1696         trace_status = etm->capture_driver->status(etm);
1697         if (trace_status == TRACE_IDLE)
1698         {
1699                 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1700         }
1701         else
1702         {
1703                 static char *completed = " completed";
1704                 static char *running = " is running";
1705                 static char *overflowed = ", overflowed";
1706                 static char *triggered = ", triggered";
1707
1708                 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1709                         etm->capture_driver->name,
1710                         (trace_status & TRACE_RUNNING) ? running : completed,
1711                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1712                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1713
1714                 if (etm->trace_depth > 0)
1715                 {
1716                         command_print(CMD_CTX, "%i frames of trace data read",
1717                                         (int)(etm->trace_depth));
1718                 }
1719         }
1720
1721         return ERROR_OK;
1722 }
1723
1724 COMMAND_HANDLER(handle_etm_image_command)
1725 {
1726         struct target *target;
1727         struct arm *arm;
1728         struct etm_context *etm_ctx;
1729
1730         if (CMD_ARGC < 1)
1731         {
1732                 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1733                 return ERROR_FAIL;
1734         }
1735
1736         target = get_current_target(CMD_CTX);
1737         arm = target_to_arm(target);
1738         if (!is_arm(arm))
1739         {
1740                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1741                 return ERROR_FAIL;
1742         }
1743
1744         etm_ctx = arm->etm;
1745         if (!etm_ctx)
1746         {
1747                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1748                 return ERROR_FAIL;
1749         }
1750
1751         if (etm_ctx->image)
1752         {
1753                 image_close(etm_ctx->image);
1754                 free(etm_ctx->image);
1755                 command_print(CMD_CTX, "previously loaded image found and closed");
1756         }
1757
1758         etm_ctx->image = malloc(sizeof(struct image));
1759         etm_ctx->image->base_address_set = 0;
1760         etm_ctx->image->start_address_set = 0;
1761
1762         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1763         if (CMD_ARGC >= 2)
1764         {
1765                 etm_ctx->image->base_address_set = 1;
1766                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], etm_ctx->image->base_address);
1767         }
1768         else
1769         {
1770                 etm_ctx->image->base_address_set = 0;
1771         }
1772
1773         if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1774         {
1775                 free(etm_ctx->image);
1776                 etm_ctx->image = NULL;
1777                 return ERROR_FAIL;
1778         }
1779
1780         return ERROR_OK;
1781 }
1782
1783 COMMAND_HANDLER(handle_etm_dump_command)
1784 {
1785         struct fileio file;
1786         struct target *target;
1787         struct arm *arm;
1788         struct etm_context *etm_ctx;
1789         uint32_t i;
1790
1791         if (CMD_ARGC != 1)
1792         {
1793                 command_print(CMD_CTX, "usage: etm dump <file>");
1794                 return ERROR_FAIL;
1795         }
1796
1797         target = get_current_target(CMD_CTX);
1798         arm = target_to_arm(target);
1799         if (!is_arm(arm))
1800         {
1801                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1802                 return ERROR_FAIL;
1803         }
1804
1805         etm_ctx = arm->etm;
1806         if (!etm_ctx)
1807         {
1808                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1809                 return ERROR_FAIL;
1810         }
1811
1812         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1813         {
1814                 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1815                 return ERROR_OK;
1816         }
1817
1818         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1819         {
1820                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1821                 command_print(CMD_CTX, "trace capture not completed");
1822                 return ERROR_FAIL;
1823         }
1824
1825         /* read the trace data if it wasn't read already */
1826         if (etm_ctx->trace_depth == 0)
1827                 etm_ctx->capture_driver->read_trace(etm_ctx);
1828
1829         if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1830         {
1831                 return ERROR_FAIL;
1832         }
1833
1834         fileio_write_u32(&file, etm_ctx->capture_status);
1835         fileio_write_u32(&file, etm_ctx->control);
1836         fileio_write_u32(&file, etm_ctx->trace_depth);
1837
1838         for (i = 0; i < etm_ctx->trace_depth; i++)
1839         {
1840                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1841                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1842                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1843         }
1844
1845         fileio_close(&file);
1846
1847         return ERROR_OK;
1848 }
1849
1850 COMMAND_HANDLER(handle_etm_load_command)
1851 {
1852         struct fileio file;
1853         struct target *target;
1854         struct arm *arm;
1855         struct etm_context *etm_ctx;
1856         uint32_t i;
1857
1858         if (CMD_ARGC != 1)
1859         {
1860                 command_print(CMD_CTX, "usage: etm load <file>");
1861                 return ERROR_FAIL;
1862         }
1863
1864         target = get_current_target(CMD_CTX);
1865         arm = target_to_arm(target);
1866         if (!is_arm(arm))
1867         {
1868                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1869                 return ERROR_FAIL;
1870         }
1871
1872         etm_ctx = arm->etm;
1873         if (!etm_ctx)
1874         {
1875                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1876                 return ERROR_FAIL;
1877         }
1878
1879         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1880         {
1881                 command_print(CMD_CTX, "trace capture running, stop first");
1882                 return ERROR_FAIL;
1883         }
1884
1885         if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1886         {
1887                 return ERROR_FAIL;
1888         }
1889
1890         if (file.size % 4)
1891         {
1892                 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1893                 fileio_close(&file);
1894                 return ERROR_FAIL;
1895         }
1896
1897         if (etm_ctx->trace_depth > 0)
1898         {
1899                 free(etm_ctx->trace_data);
1900                 etm_ctx->trace_data = NULL;
1901         }
1902
1903         {
1904           uint32_t tmp;
1905           fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1906           fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1907           fileio_read_u32(&file, &etm_ctx->trace_depth);
1908         }
1909         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1910         if (etm_ctx->trace_data == NULL)
1911         {
1912                 command_print(CMD_CTX, "not enough memory to perform operation");
1913                 fileio_close(&file);
1914                 return ERROR_FAIL;
1915         }
1916
1917         for (i = 0; i < etm_ctx->trace_depth; i++)
1918         {
1919                 uint32_t pipestat, packet, flags;
1920                 fileio_read_u32(&file, &pipestat);
1921                 fileio_read_u32(&file, &packet);
1922                 fileio_read_u32(&file, &flags);
1923                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1924                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1925                 etm_ctx->trace_data[i].flags = flags;
1926         }
1927
1928         fileio_close(&file);
1929
1930         return ERROR_OK;
1931 }
1932
1933 COMMAND_HANDLER(handle_etm_start_command)
1934 {
1935         struct target *target;
1936         struct arm *arm;
1937         struct etm_context *etm_ctx;
1938         struct reg *etm_ctrl_reg;
1939
1940         target = get_current_target(CMD_CTX);
1941         arm = target_to_arm(target);
1942         if (!is_arm(arm))
1943         {
1944                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1945                 return ERROR_FAIL;
1946         }
1947
1948         etm_ctx = arm->etm;
1949         if (!etm_ctx)
1950         {
1951                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1952                 return ERROR_FAIL;
1953         }
1954
1955         /* invalidate old tracing data */
1956         etm_ctx->capture_status = TRACE_IDLE;
1957         if (etm_ctx->trace_depth > 0)
1958         {
1959                 free(etm_ctx->trace_data);
1960                 etm_ctx->trace_data = NULL;
1961         }
1962         etm_ctx->trace_depth = 0;
1963
1964         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1965         if (!etm_ctrl_reg)
1966                 return ERROR_FAIL;
1967
1968         etm_get_reg(etm_ctrl_reg);
1969
1970         /* Clear programming bit (10), set port selection bit (11) */
1971         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1972
1973         etm_store_reg(etm_ctrl_reg);
1974         jtag_execute_queue();
1975
1976         etm_ctx->capture_driver->start_capture(etm_ctx);
1977
1978         return ERROR_OK;
1979 }
1980
1981 COMMAND_HANDLER(handle_etm_stop_command)
1982 {
1983         struct target *target;
1984         struct arm *arm;
1985         struct etm_context *etm_ctx;
1986         struct reg *etm_ctrl_reg;
1987
1988         target = get_current_target(CMD_CTX);
1989         arm = target_to_arm(target);
1990         if (!is_arm(arm))
1991         {
1992                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1993                 return ERROR_FAIL;
1994         }
1995
1996         etm_ctx = arm->etm;
1997         if (!etm_ctx)
1998         {
1999                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2000                 return ERROR_FAIL;
2001         }
2002
2003         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2004         if (!etm_ctrl_reg)
2005                 return ERROR_FAIL;
2006
2007         etm_get_reg(etm_ctrl_reg);
2008
2009         /* Set programming bit (10), clear port selection bit (11) */
2010         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2011
2012         etm_store_reg(etm_ctrl_reg);
2013         jtag_execute_queue();
2014
2015         etm_ctx->capture_driver->stop_capture(etm_ctx);
2016
2017         return ERROR_OK;
2018 }
2019
2020 COMMAND_HANDLER(handle_etm_trigger_debug_command)
2021 {
2022         struct target *target;
2023         struct arm *arm;
2024         struct etm_context *etm;
2025
2026         target = get_current_target(CMD_CTX);
2027         arm = target_to_arm(target);
2028         if (!is_arm(arm))
2029         {
2030                 command_print(CMD_CTX, "ETM: %s isn't an ARM",
2031                                 target_name(target));
2032                 return ERROR_FAIL;
2033         }
2034
2035         etm = arm->etm;
2036         if (!etm)
2037         {
2038                 command_print(CMD_CTX, "ETM: no ETM configured for %s",
2039                                 target_name(target));
2040                 return ERROR_FAIL;
2041         }
2042
2043         if (CMD_ARGC == 1) {
2044                 struct reg *etm_ctrl_reg;
2045                 bool dbgrq;
2046
2047                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
2048                 if (!etm_ctrl_reg)
2049                         return ERROR_FAIL;
2050
2051                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
2052                 if (dbgrq)
2053                         etm->control |= ETM_CTRL_DBGRQ;
2054                 else
2055                         etm->control &= ~ETM_CTRL_DBGRQ;
2056
2057                 /* etm->control will be written to hardware
2058                  * the next time an "etm start" is issued.
2059                  */
2060                 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
2061         }
2062
2063         command_print(CMD_CTX, "ETM: %s debug halt",
2064                         (etm->control & ETM_CTRL_DBGRQ)
2065                                 ? "triggers"
2066                                 : "does not trigger");
2067         return ERROR_OK;
2068 }
2069
2070 COMMAND_HANDLER(handle_etm_analyze_command)
2071 {
2072         struct target *target;
2073         struct arm *arm;
2074         struct etm_context *etm_ctx;
2075         int retval;
2076
2077         target = get_current_target(CMD_CTX);
2078         arm = target_to_arm(target);
2079         if (!is_arm(arm))
2080         {
2081                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2082                 return ERROR_FAIL;
2083         }
2084
2085         etm_ctx = arm->etm;
2086         if (!etm_ctx)
2087         {
2088                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2089                 return ERROR_FAIL;
2090         }
2091
2092         if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2093         {
2094                 switch (retval)
2095                 {
2096                         case ERROR_ETM_ANALYSIS_FAILED:
2097                                 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2098                                 break;
2099                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2100                                 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2101                                 break;
2102                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
2103                                 command_print(CMD_CTX, "no image available for trace analysis");
2104                                 break;
2105                         default:
2106                                 command_print(CMD_CTX, "unknown error: %i", retval);
2107                 }
2108         }
2109
2110         return retval;
2111 }
2112
2113 static const struct command_registration etm_config_command_handlers[] = {
2114         {
2115                 .name = "config",
2116                 .handler = &handle_etm_config_command,
2117                 .mode = COMMAND_CONFIG,
2118                 .usage = "<target> <port_width> <port_mode> "
2119                         "<clocking> <capture_driver>",
2120         },
2121         COMMAND_REGISTRATION_DONE
2122 };
2123 const struct command_registration etm_command_handlers[] = {
2124         {
2125                 .name = "etm",
2126                 .mode = COMMAND_ANY,
2127                 .help = "Emebdded Trace Macrocell command group",
2128                 .chain = etm_config_command_handlers,
2129         },
2130         COMMAND_REGISTRATION_DONE
2131 };
2132
2133 static const struct command_registration etm_exec_command_handlers[] = {
2134         {
2135                 .name = "tracemode", handle_etm_tracemode_command,
2136                 .mode = COMMAND_EXEC,
2137                 .help = "configure/display trace mode",
2138                 .usage = "<none | data | address | all> "
2139                         "<context_id_bits> <cycle_accurate> <branch_output>",
2140         },
2141         {
2142                 .name = "info",
2143                 .handler = &handle_etm_info_command,
2144                 .mode = COMMAND_EXEC,
2145                 .help = "display info about the current target's ETM",
2146         },
2147         {
2148                 .name = "status",
2149                 .handler = &handle_etm_status_command,
2150                 .mode = COMMAND_EXEC,
2151                 .help = "display current target's ETM status",
2152         },
2153         {
2154                 .name = "start",
2155                 .handler = &handle_etm_start_command,
2156                 .mode = COMMAND_EXEC,
2157                 .help = "start ETM trace collection",
2158         },
2159         {
2160                 .name = "stop",
2161                 .handler = &handle_etm_stop_command,
2162                 .mode = COMMAND_EXEC,
2163                 .help = "stop ETM trace collection",
2164         },
2165         {
2166                 .name = "trigger_debug",
2167                 .handler = handle_etm_trigger_debug_command,
2168                 .mode = COMMAND_EXEC,
2169                 .help = "enable/disable debug entry on trigger",
2170                 .usage = "(enable | disable)",
2171         },
2172         {
2173                 .name = "analyze",
2174                 .handler = handle_etm_analyze_command,
2175                 .mode = COMMAND_EXEC,
2176                 .help = "analyze collected ETM trace",
2177         },
2178         {
2179                 .name = "image",
2180                 .handler = &handle_etm_image_command,
2181                 .mode = COMMAND_EXEC,
2182                 .help = "load image from <file> [base address]",
2183         },
2184         {
2185                 .name = "dump",
2186                 .handler = &handle_etm_dump_command,
2187                 .mode = COMMAND_EXEC,
2188                 .help = "dump captured trace data <file>",
2189         },
2190         {
2191                 .name = "load",
2192                 .handler = &handle_etm_load_command,
2193                 .mode = COMMAND_EXEC,
2194                 .help = "load trace data for analysis <file>",
2195         },
2196         COMMAND_REGISTRATION_DONE
2197 };
2198
2199 static int etm_register_user_commands(struct command_context *cmd_ctx)
2200 {
2201         struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2202         return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2203 }