93dbd29488fb5b38169ba35a5e26dd1f128723b0
[fw/openocd] / src / target / etm.c
1 /***************************************************************************
2  *   Copyright (C) 2005 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
17  ***************************************************************************/
18 #ifdef HAVE_CONFIG_H
19 #include "config.h"
20 #endif
21
22 #include "arm.h"
23 #include "etm.h"
24 #include "etb.h"
25 #include "image.h"
26 #include "arm_disassembler.h"
27 #include "register.h"
28 #include "etm_dummy.h"
29
30 #if BUILD_OOCD_TRACE == 1
31 #include "oocd_trace.h"
32 #endif
33
34
35 /*
36  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
37  *
38  * ETM modules collect instruction and/or data trace information, compress
39  * it, and transfer it to a debugging host through either a (buffered) trace
40  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
41  *
42  * There are several generations of these modules.  Original versions have
43  * JTAG access through a dedicated scan chain.  Recent versions have added
44  * access via coprocessor instructions, memory addressing, and the ARM Debug
45  * Interface v5 (ADIv5); and phased out direct JTAG access.
46  *
47  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
48  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
49  * implying non-JTAG connectivity options.
50  *
51  * Relevant documentation includes:
52  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
53  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
54  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
55  */
56
57 enum {
58         RO,                             /* read/only */
59         WO,                             /* write/only */
60         RW,                             /* read/write */
61 };
62
63 struct etm_reg_info {
64         uint8_t addr;
65         uint8_t size;                   /* low-N of 32 bits */
66         uint8_t mode;                   /* RO, WO, RW */
67         uint8_t bcd_vers;               /* 1.0, 2.0, etc */
68         const char *name;
69 };
70
71 /*
72  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
73  * (Or on some processors, through coprocessor operations.)
74  * Newer versions of ETM make some W/O registers R/W, and
75  * provide definitions for some previously-unused bits.
76  */
77
78 /* core registers used to version/configure the ETM */
79 static const struct etm_reg_info etm_core[] = {
80         /* NOTE: we "know" the order here ... */
81         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
82         { ETM_ID, 32, RO, 0x20, "ETM_id", },
83 };
84
85 /* basic registers that are always there given the right ETM version */
86 static const struct etm_reg_info etm_basic[] = {
87         /* ETM Trace Registers */
88         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
89         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
90         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
91         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
92         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
93
94         /* TraceEnable configuration */
95         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
96         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
97         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
98         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
99
100         /* ViewData configuration (data trace) */
101         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
102         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
103         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
104         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
105
106         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
107
108         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
109         { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
110         { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
111         { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
112         { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
113 };
114
115 static const struct etm_reg_info etm_fifofull[] = {
116         /* FIFOFULL configuration */
117         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
118         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
119 };
120
121 static const struct etm_reg_info etm_addr_comp[] = {
122         /* Address comparator register pairs */
123 #define ADDR_COMPARATOR(i) \
124                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
125                                 "ETM_addr_" #i "_comparator_value", }, \
126                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
127                                 "ETM_addr_" #i "_access_type", }
128         ADDR_COMPARATOR(1),
129         ADDR_COMPARATOR(2),
130         ADDR_COMPARATOR(3),
131         ADDR_COMPARATOR(4),
132         ADDR_COMPARATOR(5),
133         ADDR_COMPARATOR(6),
134         ADDR_COMPARATOR(7),
135         ADDR_COMPARATOR(8),
136
137         ADDR_COMPARATOR(9),
138         ADDR_COMPARATOR(10),
139         ADDR_COMPARATOR(11),
140         ADDR_COMPARATOR(12),
141         ADDR_COMPARATOR(13),
142         ADDR_COMPARATOR(14),
143         ADDR_COMPARATOR(15),
144         ADDR_COMPARATOR(16),
145         { 0, 0, 0, 0, NULL }
146 #undef ADDR_COMPARATOR
147 };
148
149 static const struct etm_reg_info etm_data_comp[] = {
150         /* Data Value Comparators (NOTE: odd addresses are reserved) */
151 #define DATA_COMPARATOR(i) \
152                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
153                                 "ETM_data_" #i "_comparator_value", }, \
154                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
155                                 "ETM_data_" #i "_comparator_mask", }
156         DATA_COMPARATOR(1),
157         DATA_COMPARATOR(2),
158         DATA_COMPARATOR(3),
159         DATA_COMPARATOR(4),
160         DATA_COMPARATOR(5),
161         DATA_COMPARATOR(6),
162         DATA_COMPARATOR(7),
163         DATA_COMPARATOR(8),
164         { 0, 0, 0, 0, NULL }
165 #undef DATA_COMPARATOR
166 };
167
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171                                 "ETM_counter_" #i "_reload_value", }, \
172                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173                                 "ETM_counter_" #i "_enable", }, \
174                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175                                 "ETM_counter_" #i "_reload_event", }, \
176                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177                                 "ETM_counter_" #i "_value", }
178         ETM_COUNTER(1),
179         ETM_COUNTER(2),
180         ETM_COUNTER(3),
181         ETM_COUNTER(4),
182         { 0, 0, 0, 0, NULL }
183 #undef ETM_COUNTER
184 };
185
186 static const struct etm_reg_info etm_sequencer[] = {
187 #define ETM_SEQ(i) \
188                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
189                                 "ETM_sequencer_event" #i, }
190         ETM_SEQ(0),                             /* 1->2 */
191         ETM_SEQ(1),                             /* 2->1 */
192         ETM_SEQ(2),                             /* 2->3 */
193         ETM_SEQ(3),                             /* 3->1 */
194         ETM_SEQ(4),                             /* 3->2 */
195         ETM_SEQ(5),                             /* 1->3 */
196 #undef ETM_SEQ
197         /* 0x66 reserved */
198         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
199 };
200
201 static const struct etm_reg_info etm_outputs[] = {
202 #define ETM_OUTPUT(i) \
203                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
204                                 "ETM_external_output" #i, }
205
206         ETM_OUTPUT(1),
207         ETM_OUTPUT(2),
208         ETM_OUTPUT(3),
209         ETM_OUTPUT(4),
210         { 0, 0, 0, 0, NULL }
211 #undef ETM_OUTPUT
212 };
213
214 #if 0
215         /* registers from 0x6c..0x7f were added after ETMv1.3 */
216
217         /* Context ID Comparators */
218         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
219         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
220         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
221         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
222 #endif
223
224 static int etm_get_reg(struct reg *reg);
225 static int etm_read_reg_w_check(struct reg *reg,
226         uint8_t *check_value, uint8_t *check_mask);
227 static int etm_register_user_commands(struct command_context *cmd_ctx);
228 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
229 static int etm_write_reg(struct reg *reg, uint32_t value);
230
231 static const struct reg_arch_type etm_scan6_type = {
232         .get = etm_get_reg,
233         .set = etm_set_reg_w_exec,
234 };
235
236 /* Look up register by ID ... most ETM instances only
237  * support a subset of the possible registers.
238  */
239 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
240 {
241         struct reg_cache *cache = etm_ctx->reg_cache;
242         unsigned i;
243
244         for (i = 0; i < cache->num_regs; i++) {
245                 struct etm_reg *reg = cache->reg_list[i].arch_info;
246
247                 if (reg->reg_info->addr == id)
248                         return &cache->reg_list[i];
249         }
250
251         /* caller asking for nonexistent register is a bug!
252          * REVISIT say which of the N targets was involved */
253         LOG_ERROR("ETM: register 0x%02x not available", id);
254         return NULL;
255 }
256
257 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
258         struct reg_cache *cache, struct etm_reg *ereg,
259         const struct etm_reg_info *r, unsigned nreg)
260 {
261         struct reg *reg = cache->reg_list;
262
263         reg += cache->num_regs;
264         ereg += cache->num_regs;
265
266         /* add up to "nreg" registers from "r", if supported by this
267          * version of the ETM, to the specified cache.
268          */
269         for (; nreg--; r++) {
270                 /* No more registers to add */
271                 if (!r->size) {
272                         LOG_ERROR("etm_reg_add is requested to add non-existing registers, ETM config might be bogus");
273                         return;
274                 }
275
276                 /* this ETM may be too old to have some registers */
277                 if (r->bcd_vers > bcd_vers)
278                         continue;
279
280                 reg->name = r->name;
281                 reg->size = r->size;
282                 reg->value = &ereg->value;
283                 reg->arch_info = ereg;
284                 reg->type = &etm_scan6_type;
285                 reg++;
286                 cache->num_regs++;
287
288                 ereg->reg_info = r;
289                 ereg->jtag_info = jtag_info;
290                 ereg++;
291         }
292 }
293
294 struct reg_cache *etm_build_reg_cache(struct target *target,
295         struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
296 {
297         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
298         struct reg *reg_list = NULL;
299         struct etm_reg *arch_info = NULL;
300         unsigned bcd_vers, config;
301
302         /* the actual registers are kept in two arrays */
303         reg_list = calloc(128, sizeof(struct reg));
304         arch_info = calloc(128, sizeof(struct etm_reg));
305
306         if (reg_cache == NULL || reg_list == NULL || arch_info == NULL) {
307                 LOG_ERROR("No memory");
308                 goto fail;
309         }
310
311         /* fill in values for the reg cache */
312         reg_cache->name = "etm registers";
313         reg_cache->next = NULL;
314         reg_cache->reg_list = reg_list;
315         reg_cache->num_regs = 0;
316
317         /* add ETM_CONFIG, then parse its values to see
318          * which other registers exist in this ETM
319          */
320         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
321                 etm_core, 1);
322
323         etm_get_reg(reg_list);
324         etm_ctx->config = buf_get_u32(arch_info->value, 0, 32);
325         config = etm_ctx->config;
326
327         /* figure ETM version then add base registers */
328         if (config & (1 << 31)) {
329                 LOG_WARNING("ETMv2+ support is incomplete");
330
331                 /* REVISIT more registers may exist; they may now be
332                  * readable; more register bits have defined meanings;
333                  * don't presume trace start/stop support is present;
334                  * and include any context ID comparator registers.
335                  */
336                 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
337                         etm_core + 1, 1);
338                 etm_get_reg(reg_list + 1);
339                 etm_ctx->id = buf_get_u32(
340                                 arch_info[1].value, 0, 32);
341                 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
342                 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
343
344         } else {
345                 switch (config >> 28) {
346                         case 7:
347                         case 5:
348                         case 3:
349                                 bcd_vers = 0x13;
350                                 break;
351                         case 4:
352                         case 2:
353                                 bcd_vers = 0x12;
354                                 break;
355                         case 1:
356                                 bcd_vers = 0x11;
357                                 break;
358                         case 0:
359                                 bcd_vers = 0x10;
360                                 break;
361                         default:
362                                 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
363                                 goto fail;
364                 }
365         }
366         etm_ctx->bcd_vers = bcd_vers;
367         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
368
369         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
370                 etm_basic, ARRAY_SIZE(etm_basic));
371
372         /* address and data comparators; counters; outputs */
373         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
374                 etm_addr_comp, 4 * (0x0f & (config >> 0)));
375         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
376                 etm_data_comp, 2 * (0x0f & (config >> 4)));
377         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
378                 etm_counters, 4 * (0x07 & (config >> 13)));
379         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
380                 etm_outputs, (0x07 & (config >> 20)));
381
382         /* FIFOFULL presence is optional
383          * REVISIT for ETMv1.2 and later, don't bother adding this
384          * unless ETM_SYS_CONFIG says it's also *supported* ...
385          */
386         if (config & (1 << 23))
387                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
388                         etm_fifofull, ARRAY_SIZE(etm_fifofull));
389
390         /* sequencer is optional (for state-dependant triggering) */
391         if (config & (1 << 16))
392                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
393                         etm_sequencer, ARRAY_SIZE(etm_sequencer));
394
395         /* REVISIT could realloc and likely save half the memory
396          * in the two chunks we allocated...
397          */
398
399         /* the ETM might have an ETB connected */
400         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0) {
401                 struct etb *etb = etm_ctx->capture_driver_priv;
402
403                 if (!etb) {
404                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
405                         goto fail;
406                 }
407
408                 reg_cache->next = etb_build_reg_cache(etb);
409
410                 etb->reg_cache = reg_cache->next;
411         }
412
413         etm_ctx->reg_cache = reg_cache;
414         return reg_cache;
415
416 fail:
417         free(reg_cache);
418         free(reg_list);
419         free(arch_info);
420         return NULL;
421 }
422
423 static int etm_read_reg(struct reg *reg)
424 {
425         return etm_read_reg_w_check(reg, NULL, NULL);
426 }
427
428 static int etm_store_reg(struct reg *reg)
429 {
430         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
431 }
432
433 int etm_setup(struct target *target)
434 {
435         int retval;
436         uint32_t etm_ctrl_value;
437         struct arm *arm = target_to_arm(target);
438         struct etm_context *etm_ctx = arm->etm;
439         struct reg *etm_ctrl_reg;
440
441         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
442         if (!etm_ctrl_reg)
443                 return ERROR_OK;
444
445         /* initialize some ETM control register settings */
446         etm_get_reg(etm_ctrl_reg);
447         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
448
449         /* clear the ETM powerdown bit (0) */
450         etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
451
452         /* configure port width (21,6:4), mode (13,17:16) and
453          * for older modules clocking (13)
454          */
455         etm_ctrl_value = (etm_ctrl_value
456                 & ~ETM_PORT_WIDTH_MASK
457                 & ~ETM_PORT_MODE_MASK
458                 & ~ETM_CTRL_DBGRQ
459                 & ~ETM_PORT_CLOCK_MASK)
460                 | etm_ctx->control;
461
462         buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
463         etm_store_reg(etm_ctrl_reg);
464
465         etm_ctx->control = etm_ctrl_value;
466
467         retval = jtag_execute_queue();
468         if (retval != ERROR_OK)
469                 return retval;
470
471         /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
472          * verify that those width and mode settings are OK ...
473          */
474
475         retval = etm_ctx->capture_driver->init(etm_ctx);
476         if (retval != ERROR_OK) {
477                 LOG_ERROR("ETM capture driver initialization failed");
478                 return retval;
479         }
480         return ERROR_OK;
481 }
482
483 static int etm_get_reg(struct reg *reg)
484 {
485         int retval;
486
487         retval = etm_read_reg(reg);
488         if (retval != ERROR_OK) {
489                 LOG_ERROR("BUG: error scheduling etm register read");
490                 return retval;
491         }
492
493         retval = jtag_execute_queue();
494         if (retval != ERROR_OK) {
495                 LOG_ERROR("register read failed");
496                 return retval;
497         }
498
499         return ERROR_OK;
500 }
501
502 static int etm_read_reg_w_check(struct reg *reg,
503         uint8_t *check_value, uint8_t *check_mask)
504 {
505         struct etm_reg *etm_reg = reg->arch_info;
506         assert(etm_reg);
507         const struct etm_reg_info *r = etm_reg->reg_info;
508         uint8_t reg_addr = r->addr & 0x7f;
509         struct scan_field fields[3];
510         int retval;
511
512         if (etm_reg->reg_info->mode == WO) {
513                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
514                 return ERROR_COMMAND_SYNTAX_ERROR;
515         }
516
517         LOG_DEBUG("%s (%u)", r->name, reg_addr);
518
519         retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
520         if (retval != ERROR_OK)
521                 return retval;
522         retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
523                         etm_reg->jtag_info->intest_instr,
524                         NULL,
525                         TAP_IDLE);
526         if (retval != ERROR_OK)
527                 return retval;
528
529         fields[0].num_bits = 32;
530         fields[0].out_value = reg->value;
531         fields[0].in_value = NULL;
532         fields[0].check_value = NULL;
533         fields[0].check_mask = NULL;
534
535         fields[1].num_bits = 7;
536         uint8_t temp1 = 0;
537         fields[1].out_value = &temp1;
538         buf_set_u32(&temp1, 0, 7, reg_addr);
539         fields[1].in_value = NULL;
540         fields[1].check_value = NULL;
541         fields[1].check_mask = NULL;
542
543         fields[2].num_bits = 1;
544         uint8_t temp2 = 0;
545         fields[2].out_value = &temp2;
546         buf_set_u32(&temp2, 0, 1, 0);
547         fields[2].in_value = NULL;
548         fields[2].check_value = NULL;
549         fields[2].check_mask = NULL;
550
551         jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
552
553         fields[0].in_value = reg->value;
554         fields[0].check_value = check_value;
555         fields[0].check_mask = check_mask;
556
557         jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
558
559         return ERROR_OK;
560 }
561
562 static int etm_set_reg(struct reg *reg, uint32_t value)
563 {
564         int retval = etm_write_reg(reg, value);
565         if (retval != ERROR_OK) {
566                 LOG_ERROR("BUG: error scheduling etm register write");
567                 return retval;
568         }
569
570         buf_set_u32(reg->value, 0, reg->size, value);
571         reg->valid = 1;
572         reg->dirty = 0;
573
574         return ERROR_OK;
575 }
576
577 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
578 {
579         int retval;
580
581         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
582
583         retval = jtag_execute_queue();
584         if (retval != ERROR_OK) {
585                 LOG_ERROR("register write failed");
586                 return retval;
587         }
588         return ERROR_OK;
589 }
590
591 static int etm_write_reg(struct reg *reg, uint32_t value)
592 {
593         struct etm_reg *etm_reg = reg->arch_info;
594         const struct etm_reg_info *r = etm_reg->reg_info;
595         uint8_t reg_addr = r->addr & 0x7f;
596         struct scan_field fields[3];
597         int retval;
598
599         if (etm_reg->reg_info->mode == RO) {
600                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
601                 return ERROR_COMMAND_SYNTAX_ERROR;
602         }
603
604         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
605
606         retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
607         if (retval != ERROR_OK)
608                 return retval;
609         retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
610                         etm_reg->jtag_info->intest_instr,
611                         NULL,
612                         TAP_IDLE);
613         if (retval != ERROR_OK)
614                 return retval;
615
616         fields[0].num_bits = 32;
617         uint8_t tmp1[4];
618         fields[0].out_value = tmp1;
619         buf_set_u32(tmp1, 0, 32, value);
620         fields[0].in_value = NULL;
621
622         fields[1].num_bits = 7;
623         uint8_t tmp2 = 0;
624         fields[1].out_value = &tmp2;
625         buf_set_u32(&tmp2, 0, 7, reg_addr);
626         fields[1].in_value = NULL;
627
628         fields[2].num_bits = 1;
629         uint8_t tmp3 = 0;
630         fields[2].out_value = &tmp3;
631         buf_set_u32(&tmp3, 0, 1, 1);
632         fields[2].in_value = NULL;
633
634         jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
635
636         return ERROR_OK;
637 }
638
639
640 /* ETM trace analysis functionality */
641
642 static struct etm_capture_driver *etm_capture_drivers[] = {
643         &etb_capture_driver,
644         &etm_dummy_capture_driver,
645 #if BUILD_OOCD_TRACE == 1
646         &oocd_trace_capture_driver,
647 #endif
648         NULL
649 };
650
651 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
652 {
653         int section = -1;
654         size_t size_read;
655         uint32_t opcode;
656         int retval;
657
658         if (!ctx->image)
659                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
660
661         /* search for the section the current instruction belongs to */
662         for (unsigned int i = 0; i < ctx->image->num_sections; i++) {
663                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
664                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size >
665                         ctx->current_pc)) {
666                         section = i;
667                         break;
668                 }
669         }
670
671         if (section == -1) {
672                 /* current instruction couldn't be found in the image */
673                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
674         }
675
676         if (ctx->core_state == ARM_STATE_ARM) {
677                 uint8_t buf[4];
678                 retval = image_read_section(ctx->image, section,
679                                 ctx->current_pc -
680                                 ctx->image->sections[section].base_address,
681                                 4, buf, &size_read);
682                 if (retval != ERROR_OK) {
683                         LOG_ERROR("error while reading instruction");
684                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
685                 }
686                 opcode = target_buffer_get_u32(ctx->target, buf);
687                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
688         } else if (ctx->core_state == ARM_STATE_THUMB) {
689                 uint8_t buf[2];
690                 retval = image_read_section(ctx->image, section,
691                                 ctx->current_pc -
692                                 ctx->image->sections[section].base_address,
693                                 2, buf, &size_read);
694                 if (retval != ERROR_OK) {
695                         LOG_ERROR("error while reading instruction");
696                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
697                 }
698                 opcode = target_buffer_get_u16(ctx->target, buf);
699                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
700         } else if (ctx->core_state == ARM_STATE_JAZELLE) {
701                 LOG_ERROR("BUG: tracing of jazelle code not supported");
702                 return ERROR_FAIL;
703         } else {
704                 LOG_ERROR("BUG: unknown core state encountered");
705                 return ERROR_FAIL;
706         }
707
708         return ERROR_OK;
709 }
710
711 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
712 {
713         while (ctx->data_index < ctx->trace_depth) {
714                 /* if the caller specified an address packet offset, skip until the
715                  * we reach the n-th cycle marked with tracesync */
716                 if (apo > 0) {
717                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
718                                 apo--;
719
720                         if (apo > 0) {
721                                 ctx->data_index++;
722                                 ctx->data_half = 0;
723                         }
724                         continue;
725                 }
726
727                 /* no tracedata output during a TD cycle
728                  * or in a trigger cycle */
729                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
730                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE)) {
731                         ctx->data_index++;
732                         ctx->data_half = 0;
733                         continue;
734                 }
735
736                 /* FIXME there are more port widths than these... */
737                 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT) {
738                         if (ctx->data_half == 0) {
739                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
740                                 ctx->data_half = 1;
741                         } else {
742                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
743                                 ctx->data_half = 0;
744                                 ctx->data_index++;
745                         }
746                 } else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) {
747                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
748                         ctx->data_index++;
749                 } else {
750                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
751                         if (ctx->data_index > (ctx->trace_depth - 2))
752                                 return -1;
753
754                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
755                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
756                         ctx->data_index += 2;
757                 }
758
759                 return 0;
760         }
761
762         return -1;
763 }
764
765 static int etmv1_branch_address(struct etm_context *ctx)
766 {
767         int retval;
768         uint8_t packet;
769         int shift = 0;
770         int apo;
771         uint32_t i;
772
773         /* quit analysis if less than two cycles are left in the trace
774          * because we can't extract the APO */
775         if (ctx->data_index > (ctx->trace_depth - 2))
776                 return -1;
777
778         /* a BE could be output during an APO cycle, skip the current
779          * and continue with the new one */
780         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
781                 return 1;
782         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
783                 return 2;
784
785         /* address packet offset encoded in the next two cycles' pipestat bits */
786         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
787         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
788
789         /* count number of tracesync cycles between current pipe_index and data_index
790          * i.e. the number of tracesyncs that data_index already passed by
791          * to subtract them from the APO */
792         for (i = ctx->pipe_index; i < ctx->data_index; i++) {
793                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
794                         apo--;
795         }
796
797         /* extract up to four 7-bit packets */
798         do {
799                 retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0);
800                 if (retval != 0)
801                         return -1;
802                 ctx->last_branch &= ~(0x7f << shift);
803                 ctx->last_branch |= (packet & 0x7f) << shift;
804                 shift += 7;
805         } while ((packet & 0x80) && (shift < 28));
806
807         /* one last packet holding 4 bits of the address, plus the branch reason code */
808         if ((shift == 28) && (packet & 0x80)) {
809                 retval = etmv1_next_packet(ctx, &packet, 0);
810                 if (retval != 0)
811                         return -1;
812                 ctx->last_branch &= 0x0fffffff;
813                 ctx->last_branch |= (packet & 0x0f) << 28;
814                 ctx->last_branch_reason = (packet & 0x70) >> 4;
815                 shift += 4;
816         } else
817                 ctx->last_branch_reason = 0;
818
819         if (shift == 32)
820                 ctx->pc_ok = 1;
821
822         /* if a full address was output, we might have branched into Jazelle state */
823         if ((shift == 32) && (packet & 0x80))
824                 ctx->core_state = ARM_STATE_JAZELLE;
825         else {
826                 /* if we didn't branch into Jazelle state, the current processor state is
827                  * encoded in bit 0 of the branch target address */
828                 if (ctx->last_branch & 0x1) {
829                         ctx->core_state = ARM_STATE_THUMB;
830                         ctx->last_branch &= ~0x1;
831                 } else {
832                         ctx->core_state = ARM_STATE_ARM;
833                         ctx->last_branch &= ~0x3;
834                 }
835         }
836
837         return 0;
838 }
839
840 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
841 {
842         int j;
843         uint8_t buf[4];
844         int retval;
845
846         for (j = 0; j < size; j++) {
847                 retval = etmv1_next_packet(ctx, &buf[j], 0);
848                 if (retval != 0)
849                         return -1;
850         }
851
852         if (size == 8) {
853                 LOG_ERROR("TODO: add support for 64-bit values");
854                 return -1;
855         } else if (size == 4)
856                 *data = target_buffer_get_u32(ctx->target, buf);
857         else if (size == 2)
858                 *data = target_buffer_get_u16(ctx->target, buf);
859         else if (size == 1)
860                 *data = buf[0];
861         else
862                 return -1;
863
864         return 0;
865 }
866
867 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocation *cmd)
868 {
869         int retval;
870         struct arm_instruction instruction;
871
872         /* read the trace data if it wasn't read already */
873         if (ctx->trace_depth == 0)
874                 ctx->capture_driver->read_trace(ctx);
875
876         if (ctx->trace_depth == 0) {
877                 command_print(cmd, "Trace is empty.");
878                 return ERROR_OK;
879         }
880
881         /* start at the beginning of the captured trace */
882         ctx->pipe_index = 0;
883         ctx->data_index = 0;
884         ctx->data_half = 0;
885
886         /* neither the PC nor the data pointer are valid */
887         ctx->pc_ok = 0;
888         ctx->ptr_ok = 0;
889
890         while (ctx->pipe_index < ctx->trace_depth) {
891                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
892                 uint32_t next_pc = ctx->current_pc;
893                 uint32_t old_data_index = ctx->data_index;
894                 uint32_t old_data_half = ctx->data_half;
895                 uint32_t old_index = ctx->pipe_index;
896                 uint32_t last_instruction = ctx->last_instruction;
897                 uint32_t cycles = 0;
898                 int current_pc_ok = ctx->pc_ok;
899
900                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
901                         command_print(cmd, "--- trigger ---");
902
903                 /* instructions execute in IE/D or BE/D cycles */
904                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
905                         ctx->last_instruction = ctx->pipe_index;
906
907                 /* if we don't have a valid pc skip until we reach an indirect branch */
908                 if ((!ctx->pc_ok) && (pipestat != STAT_BE)) {
909                         ctx->pipe_index++;
910                         continue;
911                 }
912
913                 /* any indirect branch could have interrupted instruction flow
914                  * - the branch reason code could indicate a trace discontinuity
915                  * - a branch to the exception vectors indicates an exception
916                  */
917                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD)) {
918                         /* backup current data index, to be able to consume the branch address
919                          * before examining data address and values
920                          */
921                         old_data_index = ctx->data_index;
922                         old_data_half = ctx->data_half;
923
924                         ctx->last_instruction = ctx->pipe_index;
925
926                         retval = etmv1_branch_address(ctx);
927                         if (retval != 0) {
928                                 /* negative return value from etmv1_branch_address means we ran out of packets,
929                                  * quit analysing the trace */
930                                 if (retval < 0)
931                                         break;
932
933                                 /* a positive return values means the current branch was abandoned,
934                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
935                                  */
936                                 LOG_WARNING(
937                                         "abandoned branch encountered, correctness of analysis uncertain");
938                                 ctx->pipe_index += retval;
939                                 continue;
940                         }
941
942                         /* skip over APO cycles */
943                         ctx->pipe_index += 2;
944
945                         switch (ctx->last_branch_reason) {
946                                 case 0x0:       /* normal PC change */
947                                         next_pc = ctx->last_branch;
948                                         break;
949                                 case 0x1:       /* tracing enabled */
950                                         command_print(cmd,
951                                                 "--- tracing enabled at 0x%8.8" PRIx32 " ---",
952                                                 ctx->last_branch);
953                                         ctx->current_pc = ctx->last_branch;
954                                         ctx->pipe_index++;
955                                         continue;
956                                         break;
957                                 case 0x2:       /* trace restarted after FIFO overflow */
958                                         command_print(cmd,
959                                                 "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---",
960                                                 ctx->last_branch);
961                                         ctx->current_pc = ctx->last_branch;
962                                         ctx->pipe_index++;
963                                         continue;
964                                         break;
965                                 case 0x3:       /* exit from debug state */
966                                         command_print(cmd,
967                                                 "--- exit from debug state at 0x%8.8" PRIx32 " ---",
968                                                 ctx->last_branch);
969                                         ctx->current_pc = ctx->last_branch;
970                                         ctx->pipe_index++;
971                                         continue;
972                                         break;
973                                 case 0x4:       /* periodic synchronization point */
974                                         next_pc = ctx->last_branch;
975                                         /* if we had no valid PC prior to this synchronization point,
976                                          * we have to move on with the next trace cycle
977                                          */
978                                         if (!current_pc_ok) {
979                                                 command_print(cmd,
980                                                         "--- periodic synchronization point at 0x%8.8" PRIx32 " ---",
981                                                         next_pc);
982                                                 ctx->current_pc = next_pc;
983                                                 ctx->pipe_index++;
984                                                 continue;
985                                         }
986                                         break;
987                                 default:        /* reserved */
988                                         LOG_ERROR(
989                                                 "BUG: branch reason code 0x%" PRIx32 " is reserved",
990                                                 ctx->last_branch_reason);
991                                         return ERROR_FAIL;
992                         }
993
994                         /* if we got here the branch was a normal PC change
995                          * (or a periodic synchronization point, which means the same for that matter)
996                          * if we didn't acquire a complete PC continue with the next cycle
997                          */
998                         if (!ctx->pc_ok)
999                                 continue;
1000
1001                         /* indirect branch to the exception vector means an exception occurred */
1002                         if ((ctx->last_branch <= 0x20)
1003                                 || ((ctx->last_branch >= 0xffff0000) &&
1004                                 (ctx->last_branch <= 0xffff0020))) {
1005                                 if ((ctx->last_branch & 0xff) == 0x10)
1006                                         command_print(cmd, "data abort");
1007                                 else {
1008                                         command_print(cmd,
1009                                                 "exception vector 0x%2.2" PRIx32 "",
1010                                                 ctx->last_branch);
1011                                         ctx->current_pc = ctx->last_branch;
1012                                         ctx->pipe_index++;
1013                                         continue;
1014                                 }
1015                         }
1016                 }
1017
1018                 /* an instruction was executed (or not, depending on the condition flags)
1019                  * retrieve it from the image for displaying */
1020                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1021                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1022                         ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4)))) {
1023                         retval = etm_read_instruction(ctx, &instruction);
1024                         if (retval != ERROR_OK) {
1025                                 /* can't continue tracing with no image available */
1026                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1027                                         return retval;
1028                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE) {
1029                                         /* TODO: handle incomplete images
1030                                          * for now we just quit the analysis*/
1031                                         return retval;
1032                                 }
1033                         }
1034
1035                         cycles = old_index - last_instruction;
1036                 }
1037
1038                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD)) {
1039                         uint32_t new_data_index = ctx->data_index;
1040                         uint32_t new_data_half = ctx->data_half;
1041
1042                         /* in case of a branch with data, the branch target address was consumed before
1043                          * we temporarily go back to the saved data index */
1044                         if (pipestat == STAT_BD) {
1045                                 ctx->data_index = old_data_index;
1046                                 ctx->data_half = old_data_half;
1047                         }
1048
1049                         if (ctx->control & ETM_CTRL_TRACE_ADDR) {
1050                                 uint8_t packet;
1051                                 int shift = 0;
1052
1053                                 do {
1054                                         retval = etmv1_next_packet(ctx, &packet, 0);
1055                                         if (retval != 0)
1056                                                 return ERROR_ETM_ANALYSIS_FAILED;
1057                                         ctx->last_ptr &= ~(0x7f << shift);
1058                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1059                                         shift += 7;
1060                                 } while ((packet & 0x80) && (shift < 32));
1061
1062                                 if (shift >= 32)
1063                                         ctx->ptr_ok = 1;
1064
1065                                 if (ctx->ptr_ok)
1066                                         command_print(cmd,
1067                                                 "address: 0x%8.8" PRIx32 "",
1068                                                 ctx->last_ptr);
1069                         }
1070
1071                         if (ctx->control & ETM_CTRL_TRACE_DATA) {
1072                                 if ((instruction.type == ARM_LDM) ||
1073                                         (instruction.type == ARM_STM)) {
1074                                         int i;
1075                                         for (i = 0; i < 16; i++) {
1076                                                 if (instruction.info.load_store_multiple.register_list
1077                                                         & (1 << i)) {
1078                                                         uint32_t data;
1079                                                         if (etmv1_data(ctx, 4, &data) != 0)
1080                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1081                                                         command_print(cmd,
1082                                                                 "data: 0x%8.8" PRIx32 "",
1083                                                                 data);
1084                                                 }
1085                                         }
1086                                 } else if ((instruction.type >= ARM_LDR) &&
1087                                         (instruction.type <= ARM_STRH)) {
1088                                         uint32_t data;
1089                                         if (etmv1_data(ctx, arm_access_size(&instruction),
1090                                                 &data) != 0)
1091                                                 return ERROR_ETM_ANALYSIS_FAILED;
1092                                         command_print(cmd, "data: 0x%8.8" PRIx32 "", data);
1093                                 }
1094                         }
1095
1096                         /* restore data index after consuming BD address and data */
1097                         if (pipestat == STAT_BD) {
1098                                 ctx->data_index = new_data_index;
1099                                 ctx->data_half = new_data_half;
1100                         }
1101                 }
1102
1103                 /* adjust PC */
1104                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID)) {
1105                         if (((instruction.type == ARM_B) ||
1106                                 (instruction.type == ARM_BL) ||
1107                                 (instruction.type == ARM_BLX)) &&
1108                                 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1109                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1110                         else
1111                                 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1112                 } else if (pipestat == STAT_IN)
1113                         next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1114
1115                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT)) {
1116                         char cycles_text[32] = "";
1117
1118                         /* if the trace was captured with cycle accurate tracing enabled,
1119                          * output the number of cycles since the last executed instruction
1120                          */
1121                         if (ctx->control & ETM_CTRL_CYCLE_ACCURATE) {
1122                                 snprintf(cycles_text, 32, " (%i %s)",
1123                                         (int)cycles,
1124                                         (cycles == 1) ? "cycle" : "cycles");
1125                         }
1126
1127                         command_print(cmd, "%s%s%s",
1128                                 instruction.text,
1129                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1130                                 cycles_text);
1131
1132                         ctx->current_pc = next_pc;
1133
1134                         /* packets for an instruction don't start on or before the preceding
1135                          * functional pipestat (i.e. other than WT or TD)
1136                          */
1137                         if (ctx->data_index <= ctx->pipe_index) {
1138                                 ctx->data_index = ctx->pipe_index + 1;
1139                                 ctx->data_half = 0;
1140                         }
1141                 }
1142
1143                 ctx->pipe_index += 1;
1144         }
1145
1146         return ERROR_OK;
1147 }
1148
1149 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1150         uint32_t *mode)
1151 {
1152         uint32_t tracemode;
1153
1154         /* what parts of data access are traced? */
1155         if (strcmp(CMD_ARGV[0], "none") == 0)
1156                 tracemode = 0;
1157         else if (strcmp(CMD_ARGV[0], "data") == 0)
1158                 tracemode = ETM_CTRL_TRACE_DATA;
1159         else if (strcmp(CMD_ARGV[0], "address") == 0)
1160                 tracemode = ETM_CTRL_TRACE_ADDR;
1161         else if (strcmp(CMD_ARGV[0], "all") == 0)
1162                 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1163         else {
1164                 command_print(CMD, "invalid option '%s'", CMD_ARGV[0]);
1165                 return ERROR_COMMAND_SYNTAX_ERROR;
1166         }
1167
1168         uint8_t context_id;
1169         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1170         switch (context_id) {
1171                 case 0:
1172                         tracemode |= ETM_CTRL_CONTEXTID_NONE;
1173                         break;
1174                 case 8:
1175                         tracemode |= ETM_CTRL_CONTEXTID_8;
1176                         break;
1177                 case 16:
1178                         tracemode |= ETM_CTRL_CONTEXTID_16;
1179                         break;
1180                 case 32:
1181                         tracemode |= ETM_CTRL_CONTEXTID_32;
1182                         break;
1183                 default:
1184                         command_print(CMD, "invalid option '%s'", CMD_ARGV[1]);
1185                         return ERROR_COMMAND_SYNTAX_ERROR;
1186         }
1187
1188         bool etmv1_cycle_accurate;
1189         COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1190         if (etmv1_cycle_accurate)
1191                 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1192
1193         bool etmv1_branch_output;
1194         COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1195         if (etmv1_branch_output)
1196                 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1197
1198         /* IGNORED:
1199          *  - CPRT tracing (coprocessor register transfers)
1200          *  - debug request (causes debug entry on trigger)
1201          *  - stall on FIFOFULL (preventing tracedata loss)
1202          */
1203         *mode = tracemode;
1204
1205         return ERROR_OK;
1206 }
1207
1208 COMMAND_HANDLER(handle_etm_tracemode_command)
1209 {
1210         struct target *target = get_current_target(CMD_CTX);
1211         struct arm *arm = target_to_arm(target);
1212         struct etm_context *etm;
1213
1214         if (!is_arm(arm)) {
1215                 command_print(CMD, "ETM: current target isn't an ARM");
1216                 return ERROR_FAIL;
1217         }
1218
1219         etm = arm->etm;
1220         if (!etm) {
1221                 command_print(CMD, "current target doesn't have an ETM configured");
1222                 return ERROR_FAIL;
1223         }
1224
1225         uint32_t tracemode = etm->control;
1226
1227         switch (CMD_ARGC) {
1228                 case 0:
1229                         break;
1230                 case 4:
1231                         CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1232                                 &tracemode);
1233                         break;
1234                 default:
1235                         return ERROR_COMMAND_SYNTAX_ERROR;
1236         }
1237
1238         /**
1239          * todo: fail if parameters were invalid for this hardware,
1240          * or couldn't be written; display actual hardware state...
1241          */
1242
1243         command_print(CMD, "current tracemode configuration:");
1244
1245         switch (tracemode & ETM_CTRL_TRACE_MASK) {
1246                 default:
1247                         command_print(CMD, "data tracing: none");
1248                         break;
1249                 case ETM_CTRL_TRACE_DATA:
1250                         command_print(CMD, "data tracing: data only");
1251                         break;
1252                 case ETM_CTRL_TRACE_ADDR:
1253                         command_print(CMD, "data tracing: address only");
1254                         break;
1255                 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1256                         command_print(CMD, "data tracing: address and data");
1257                         break;
1258         }
1259
1260         switch (tracemode & ETM_CTRL_CONTEXTID_MASK) {
1261                 case ETM_CTRL_CONTEXTID_NONE:
1262                         command_print(CMD, "contextid tracing: none");
1263                         break;
1264                 case ETM_CTRL_CONTEXTID_8:
1265                         command_print(CMD, "contextid tracing: 8 bit");
1266                         break;
1267                 case ETM_CTRL_CONTEXTID_16:
1268                         command_print(CMD, "contextid tracing: 16 bit");
1269                         break;
1270                 case ETM_CTRL_CONTEXTID_32:
1271                         command_print(CMD, "contextid tracing: 32 bit");
1272                         break;
1273         }
1274
1275         if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1276                 command_print(CMD, "cycle-accurate tracing enabled");
1277         else
1278                 command_print(CMD, "cycle-accurate tracing disabled");
1279
1280         if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1281                 command_print(CMD, "full branch address output enabled");
1282         else
1283                 command_print(CMD, "full branch address output disabled");
1284
1285 #define TRACEMODE_MASK ( \
1286                 ETM_CTRL_CONTEXTID_MASK \
1287                 | ETM_CTRL_BRANCH_OUTPUT \
1288                 | ETM_CTRL_CYCLE_ACCURATE \
1289                 | ETM_CTRL_TRACE_MASK \
1290                 )
1291
1292         /* only update ETM_CTRL register if tracemode changed */
1293         if ((etm->control & TRACEMODE_MASK) != tracemode) {
1294                 struct reg *etm_ctrl_reg;
1295
1296                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1297                 if (!etm_ctrl_reg)
1298                         return ERROR_FAIL;
1299
1300                 etm->control &= ~TRACEMODE_MASK;
1301                 etm->control |= tracemode & TRACEMODE_MASK;
1302
1303                 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1304                 etm_store_reg(etm_ctrl_reg);
1305
1306                 /* invalidate old trace data */
1307                 etm->capture_status = TRACE_IDLE;
1308                 if (etm->trace_depth > 0) {
1309                         free(etm->trace_data);
1310                         etm->trace_data = NULL;
1311                 }
1312                 etm->trace_depth = 0;
1313         }
1314
1315 #undef TRACEMODE_MASK
1316
1317         return ERROR_OK;
1318 }
1319
1320 COMMAND_HANDLER(handle_etm_config_command)
1321 {
1322         struct target *target;
1323         struct arm *arm;
1324         uint32_t portmode = 0x0;
1325         struct etm_context *etm_ctx;
1326         int i;
1327
1328         if (CMD_ARGC != 5)
1329                 return ERROR_COMMAND_SYNTAX_ERROR;
1330
1331         target = get_target(CMD_ARGV[0]);
1332         if (!target) {
1333                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1334                 return ERROR_FAIL;
1335         }
1336
1337         arm = target_to_arm(target);
1338         if (!is_arm(arm)) {
1339                 command_print(CMD, "target '%s' is '%s'; not an ARM",
1340                         target_name(target),
1341                         target_type_name(target));
1342                 return ERROR_FAIL;
1343         }
1344
1345         /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1346          * version we'll be using!! -- so we can't know how to validate
1347          * params yet.  "etm config" should likely be *AFTER* hookup...
1348          *
1349          *  - Many more widths might be supported ... and we can easily
1350          *    check whether our setting "took".
1351          *
1352          *  - The "clock" and "mode" bits are interpreted differently.
1353          *    See ARM IHI 0014O table 2-17 for the old behaviour, and
1354          *    table 2-18 for the new.  With ETB it's best to specify
1355          *    "normal full" ...
1356          */
1357         uint8_t port_width;
1358         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1359         switch (port_width) {
1360                 /* before ETMv3.0 */
1361                 case 4:
1362                         portmode |= ETM_PORT_4BIT;
1363                         break;
1364                 case 8:
1365                         portmode |= ETM_PORT_8BIT;
1366                         break;
1367                 case 16:
1368                         portmode |= ETM_PORT_16BIT;
1369                         break;
1370                 /* ETMv3.0 and later*/
1371                 case 24:
1372                         portmode |= ETM_PORT_24BIT;
1373                         break;
1374                 case 32:
1375                         portmode |= ETM_PORT_32BIT;
1376                         break;
1377                 case 48:
1378                         portmode |= ETM_PORT_48BIT;
1379                         break;
1380                 case 64:
1381                         portmode |= ETM_PORT_64BIT;
1382                         break;
1383                 case 1:
1384                         portmode |= ETM_PORT_1BIT;
1385                         break;
1386                 case 2:
1387                         portmode |= ETM_PORT_2BIT;
1388                         break;
1389                 default:
1390                         command_print(CMD,
1391                                 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1392                         return ERROR_FAIL;
1393         }
1394
1395         if (strcmp("normal", CMD_ARGV[2]) == 0)
1396                 portmode |= ETM_PORT_NORMAL;
1397         else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1398                 portmode |= ETM_PORT_MUXED;
1399         else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1400                 portmode |= ETM_PORT_DEMUXED;
1401         else {
1402                 command_print(CMD,
1403                         "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'",
1404                         CMD_ARGV[2]);
1405                 return ERROR_FAIL;
1406         }
1407
1408         if (strcmp("half", CMD_ARGV[3]) == 0)
1409                 portmode |= ETM_PORT_HALF_CLOCK;
1410         else if (strcmp("full", CMD_ARGV[3]) == 0)
1411                 portmode |= ETM_PORT_FULL_CLOCK;
1412         else {
1413                 command_print(CMD,
1414                         "unsupported ETM port clocking '%s', must be 'full' or 'half'",
1415                         CMD_ARGV[3]);
1416                 return ERROR_FAIL;
1417         }
1418
1419         etm_ctx = calloc(1, sizeof(struct etm_context));
1420         if (!etm_ctx) {
1421                 LOG_DEBUG("out of memory");
1422                 return ERROR_FAIL;
1423         }
1424
1425         for (i = 0; etm_capture_drivers[i]; i++) {
1426                 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0) {
1427                         int retval = register_commands(CMD_CTX, NULL,
1428                                         etm_capture_drivers[i]->commands);
1429                         if (ERROR_OK != retval) {
1430                                 free(etm_ctx);
1431                                 return retval;
1432                         }
1433
1434                         etm_ctx->capture_driver = etm_capture_drivers[i];
1435
1436                         break;
1437                 }
1438         }
1439
1440         if (!etm_capture_drivers[i]) {
1441                 /* no supported capture driver found, don't register an ETM */
1442                 free(etm_ctx);
1443                 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1444                 return ERROR_FAIL;
1445         }
1446
1447         etm_ctx->target = target;
1448         etm_ctx->trace_data = NULL;
1449         etm_ctx->control = portmode;
1450         etm_ctx->core_state = ARM_STATE_ARM;
1451
1452         arm->etm = etm_ctx;
1453
1454         return etm_register_user_commands(CMD_CTX);
1455 }
1456
1457 COMMAND_HANDLER(handle_etm_info_command)
1458 {
1459         struct target *target;
1460         struct arm *arm;
1461         struct etm_context *etm;
1462         struct reg *etm_sys_config_reg;
1463         int max_port_size;
1464         uint32_t config;
1465
1466         target = get_current_target(CMD_CTX);
1467         arm = target_to_arm(target);
1468         if (!is_arm(arm)) {
1469                 command_print(CMD, "ETM: current target isn't an ARM");
1470                 return ERROR_FAIL;
1471         }
1472
1473         etm = arm->etm;
1474         if (!etm) {
1475                 command_print(CMD, "current target doesn't have an ETM configured");
1476                 return ERROR_FAIL;
1477         }
1478
1479         command_print(CMD, "ETM v%d.%d",
1480                 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1481         command_print(CMD, "pairs of address comparators: %i",
1482                 (int) (etm->config >> 0) & 0x0f);
1483         command_print(CMD, "data comparators: %i",
1484                 (int) (etm->config >> 4) & 0x0f);
1485         command_print(CMD, "memory map decoders: %i",
1486                 (int) (etm->config >> 8) & 0x1f);
1487         command_print(CMD, "number of counters: %i",
1488                 (int) (etm->config >> 13) & 0x07);
1489         command_print(CMD, "sequencer %spresent",
1490                 (int) (etm->config & (1 << 16)) ? "" : "not ");
1491         command_print(CMD, "number of ext. inputs: %i",
1492                 (int) (etm->config >> 17) & 0x07);
1493         command_print(CMD, "number of ext. outputs: %i",
1494                 (int) (etm->config >> 20) & 0x07);
1495         command_print(CMD, "FIFO full %spresent",
1496                 (int) (etm->config & (1 << 23)) ? "" : "not ");
1497         if (etm->bcd_vers < 0x20)
1498                 command_print(CMD, "protocol version: %i",
1499                         (int) (etm->config >> 28) & 0x07);
1500         else {
1501                 command_print(CMD,
1502                         "coprocessor and memory access %ssupported",
1503                         (etm->config & (1 << 26)) ? "" : "not ");
1504                 command_print(CMD, "trace start/stop %spresent",
1505                         (etm->config & (1 << 26)) ? "" : "not ");
1506                 command_print(CMD, "number of context comparators: %i",
1507                         (int) (etm->config >> 24) & 0x03);
1508         }
1509
1510         /* SYS_CONFIG isn't present before ETMv1.2 */
1511         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1512         if (!etm_sys_config_reg)
1513                 return ERROR_OK;
1514
1515         etm_get_reg(etm_sys_config_reg);
1516         config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1517
1518         LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1519
1520         max_port_size = config & 0x7;
1521         if (etm->bcd_vers >= 0x30)
1522                 max_port_size |= (config >> 6) & 0x08;
1523         switch (max_port_size) {
1524                 /* before ETMv3.0 */
1525                 case 0:
1526                         max_port_size = 4;
1527                         break;
1528                 case 1:
1529                         max_port_size = 8;
1530                         break;
1531                 case 2:
1532                         max_port_size = 16;
1533                         break;
1534                 /* ETMv3.0 and later*/
1535                 case 3:
1536                         max_port_size = 24;
1537                         break;
1538                 case 4:
1539                         max_port_size = 32;
1540                         break;
1541                 case 5:
1542                         max_port_size = 48;
1543                         break;
1544                 case 6:
1545                         max_port_size = 64;
1546                         break;
1547                 case 8:
1548                         max_port_size = 1;
1549                         break;
1550                 case 9:
1551                         max_port_size = 2;
1552                         break;
1553                 default:
1554                         LOG_ERROR("Illegal max_port_size");
1555                         return ERROR_FAIL;
1556         }
1557         command_print(CMD, "max. port size: %i", max_port_size);
1558
1559         if (etm->bcd_vers < 0x30) {
1560                 command_print(CMD, "half-rate clocking %ssupported",
1561                         (config & (1 << 3)) ? "" : "not ");
1562                 command_print(CMD, "full-rate clocking %ssupported",
1563                         (config & (1 << 4)) ? "" : "not ");
1564                 command_print(CMD, "normal trace format %ssupported",
1565                         (config & (1 << 5)) ? "" : "not ");
1566                 command_print(CMD, "multiplex trace format %ssupported",
1567                         (config & (1 << 6)) ? "" : "not ");
1568                 command_print(CMD, "demultiplex trace format %ssupported",
1569                         (config & (1 << 7)) ? "" : "not ");
1570         } else {
1571                 /* REVISIT show which size and format are selected ... */
1572                 command_print(CMD, "current port size %ssupported",
1573                         (config & (1 << 10)) ? "" : "not ");
1574                 command_print(CMD, "current trace format %ssupported",
1575                         (config & (1 << 11)) ? "" : "not ");
1576         }
1577         if (etm->bcd_vers >= 0x21)
1578                 command_print(CMD, "fetch comparisons %ssupported",
1579                         (config & (1 << 17)) ? "not " : "");
1580         command_print(CMD, "FIFO full %ssupported",
1581                 (config & (1 << 8)) ? "" : "not ");
1582
1583         return ERROR_OK;
1584 }
1585
1586 COMMAND_HANDLER(handle_etm_status_command)
1587 {
1588         struct target *target;
1589         struct arm *arm;
1590         struct etm_context *etm;
1591         trace_status_t trace_status;
1592
1593         target = get_current_target(CMD_CTX);
1594         arm = target_to_arm(target);
1595         if (!is_arm(arm)) {
1596                 command_print(CMD, "ETM: current target isn't an ARM");
1597                 return ERROR_FAIL;
1598         }
1599
1600         etm = arm->etm;
1601         if (!etm) {
1602                 command_print(CMD, "current target doesn't have an ETM configured");
1603                 return ERROR_FAIL;
1604         }
1605
1606         /* ETM status */
1607         if (etm->bcd_vers >= 0x11) {
1608                 struct reg *reg;
1609
1610                 reg = etm_reg_lookup(etm, ETM_STATUS);
1611                 if (!reg)
1612                         return ERROR_FAIL;
1613                 if (etm_get_reg(reg) == ERROR_OK) {
1614                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1615
1616                         command_print(CMD, "etm: %s%s%s%s",
1617                                 /* bit(1) == progbit */
1618                                 (etm->bcd_vers >= 0x12)
1619                                 ? ((s & (1 << 1))
1620                                 ? "disabled" : "enabled")
1621                                 : "?",
1622                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1623                                 ? " triggered" : "",
1624                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1625                                 ? " start/stop" : "",
1626                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1627                                 ? " untraced-overflow" : "");
1628                 }       /* else ignore and try showing trace port status */
1629         }
1630
1631         /* Trace Port Driver status */
1632         trace_status = etm->capture_driver->status(etm);
1633         if (trace_status == TRACE_IDLE)
1634                 command_print(CMD, "%s: idle", etm->capture_driver->name);
1635         else {
1636                 static char *completed = " completed";
1637                 static char *running = " is running";
1638                 static char *overflowed = ", overflowed";
1639                 static char *triggered = ", triggered";
1640
1641                 command_print(CMD, "%s: trace collection%s%s%s",
1642                         etm->capture_driver->name,
1643                         (trace_status & TRACE_RUNNING) ? running : completed,
1644                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1645                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1646
1647                 if (etm->trace_depth > 0) {
1648                         command_print(CMD, "%i frames of trace data read",
1649                                 (int)(etm->trace_depth));
1650                 }
1651         }
1652
1653         return ERROR_OK;
1654 }
1655
1656 COMMAND_HANDLER(handle_etm_image_command)
1657 {
1658         struct target *target;
1659         struct arm *arm;
1660         struct etm_context *etm_ctx;
1661
1662         if (CMD_ARGC < 1)
1663                 return ERROR_COMMAND_SYNTAX_ERROR;
1664
1665         target = get_current_target(CMD_CTX);
1666         arm = target_to_arm(target);
1667         if (!is_arm(arm)) {
1668                 command_print(CMD, "ETM: current target isn't an ARM");
1669                 return ERROR_FAIL;
1670         }
1671
1672         etm_ctx = arm->etm;
1673         if (!etm_ctx) {
1674                 command_print(CMD, "current target doesn't have an ETM configured");
1675                 return ERROR_FAIL;
1676         }
1677
1678         if (etm_ctx->image) {
1679                 image_close(etm_ctx->image);
1680                 free(etm_ctx->image);
1681                 command_print(CMD, "previously loaded image found and closed");
1682         }
1683
1684         etm_ctx->image = malloc(sizeof(struct image));
1685         etm_ctx->image->base_address_set = false;
1686         etm_ctx->image->start_address_set = false;
1687
1688         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1689         if (CMD_ARGC >= 2) {
1690                 etm_ctx->image->base_address_set = true;
1691                 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1692         } else
1693                 etm_ctx->image->base_address_set = false;
1694
1695         if (image_open(etm_ctx->image, CMD_ARGV[0],
1696                 (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {
1697                 free(etm_ctx->image);
1698                 etm_ctx->image = NULL;
1699                 return ERROR_FAIL;
1700         }
1701
1702         return ERROR_OK;
1703 }
1704
1705 COMMAND_HANDLER(handle_etm_dump_command)
1706 {
1707         struct fileio *file;
1708         struct target *target;
1709         struct arm *arm;
1710         struct etm_context *etm_ctx;
1711         uint32_t i;
1712
1713         if (CMD_ARGC != 1)
1714                 return ERROR_COMMAND_SYNTAX_ERROR;
1715
1716         target = get_current_target(CMD_CTX);
1717         arm = target_to_arm(target);
1718         if (!is_arm(arm)) {
1719                 command_print(CMD, "ETM: current target isn't an ARM");
1720                 return ERROR_FAIL;
1721         }
1722
1723         etm_ctx = arm->etm;
1724         if (!etm_ctx) {
1725                 command_print(CMD, "current target doesn't have an ETM configured");
1726                 return ERROR_FAIL;
1727         }
1728
1729         if (etm_ctx->capture_driver->status == TRACE_IDLE) {
1730                 command_print(CMD, "trace capture wasn't enabled, no trace data captured");
1731                 return ERROR_OK;
1732         }
1733
1734         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1735                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1736                 command_print(CMD, "trace capture not completed");
1737                 return ERROR_FAIL;
1738         }
1739
1740         /* read the trace data if it wasn't read already */
1741         if (etm_ctx->trace_depth == 0)
1742                 etm_ctx->capture_driver->read_trace(etm_ctx);
1743
1744         if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1745                 return ERROR_FAIL;
1746
1747         fileio_write_u32(file, etm_ctx->capture_status);
1748         fileio_write_u32(file, etm_ctx->control);
1749         fileio_write_u32(file, etm_ctx->trace_depth);
1750
1751         for (i = 0; i < etm_ctx->trace_depth; i++) {
1752                 fileio_write_u32(file, etm_ctx->trace_data[i].pipestat);
1753                 fileio_write_u32(file, etm_ctx->trace_data[i].packet);
1754                 fileio_write_u32(file, etm_ctx->trace_data[i].flags);
1755         }
1756
1757         fileio_close(file);
1758
1759         return ERROR_OK;
1760 }
1761
1762 COMMAND_HANDLER(handle_etm_load_command)
1763 {
1764         struct fileio *file;
1765         struct target *target;
1766         struct arm *arm;
1767         struct etm_context *etm_ctx;
1768         uint32_t i;
1769
1770         if (CMD_ARGC != 1)
1771                 return ERROR_COMMAND_SYNTAX_ERROR;
1772
1773         target = get_current_target(CMD_CTX);
1774         arm = target_to_arm(target);
1775         if (!is_arm(arm)) {
1776                 command_print(CMD, "ETM: current target isn't an ARM");
1777                 return ERROR_FAIL;
1778         }
1779
1780         etm_ctx = arm->etm;
1781         if (!etm_ctx) {
1782                 command_print(CMD, "current target doesn't have an ETM configured");
1783                 return ERROR_FAIL;
1784         }
1785
1786         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1787                 command_print(CMD, "trace capture running, stop first");
1788                 return ERROR_FAIL;
1789         }
1790
1791         if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1792                 return ERROR_FAIL;
1793
1794         size_t filesize;
1795         int retval = fileio_size(file, &filesize);
1796         if (retval != ERROR_OK) {
1797                 fileio_close(file);
1798                 return retval;
1799         }
1800
1801         if (filesize % 4) {
1802                 command_print(CMD, "size isn't a multiple of 4, no valid trace data");
1803                 fileio_close(file);
1804                 return ERROR_FAIL;
1805         }
1806
1807         if (etm_ctx->trace_depth > 0) {
1808                 free(etm_ctx->trace_data);
1809                 etm_ctx->trace_data = NULL;
1810         }
1811
1812         {
1813                 uint32_t tmp;
1814                 fileio_read_u32(file, &tmp); etm_ctx->capture_status = tmp;
1815                 fileio_read_u32(file, &tmp); etm_ctx->control = tmp;
1816                 fileio_read_u32(file, &etm_ctx->trace_depth);
1817         }
1818         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1819         if (etm_ctx->trace_data == NULL) {
1820                 command_print(CMD, "not enough memory to perform operation");
1821                 fileio_close(file);
1822                 return ERROR_FAIL;
1823         }
1824
1825         for (i = 0; i < etm_ctx->trace_depth; i++) {
1826                 uint32_t pipestat, packet, flags;
1827                 fileio_read_u32(file, &pipestat);
1828                 fileio_read_u32(file, &packet);
1829                 fileio_read_u32(file, &flags);
1830                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1831                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1832                 etm_ctx->trace_data[i].flags = flags;
1833         }
1834
1835         fileio_close(file);
1836
1837         return ERROR_OK;
1838 }
1839
1840 COMMAND_HANDLER(handle_etm_start_command)
1841 {
1842         struct target *target;
1843         struct arm *arm;
1844         struct etm_context *etm_ctx;
1845         struct reg *etm_ctrl_reg;
1846
1847         target = get_current_target(CMD_CTX);
1848         arm = target_to_arm(target);
1849         if (!is_arm(arm)) {
1850                 command_print(CMD, "ETM: current target isn't an ARM");
1851                 return ERROR_FAIL;
1852         }
1853
1854         etm_ctx = arm->etm;
1855         if (!etm_ctx) {
1856                 command_print(CMD, "current target doesn't have an ETM configured");
1857                 return ERROR_FAIL;
1858         }
1859
1860         /* invalidate old tracing data */
1861         etm_ctx->capture_status = TRACE_IDLE;
1862         if (etm_ctx->trace_depth > 0) {
1863                 free(etm_ctx->trace_data);
1864                 etm_ctx->trace_data = NULL;
1865         }
1866         etm_ctx->trace_depth = 0;
1867
1868         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1869         if (!etm_ctrl_reg)
1870                 return ERROR_FAIL;
1871
1872         etm_get_reg(etm_ctrl_reg);
1873
1874         /* Clear programming bit (10), set port selection bit (11) */
1875         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1876
1877         etm_store_reg(etm_ctrl_reg);
1878         jtag_execute_queue();
1879
1880         etm_ctx->capture_driver->start_capture(etm_ctx);
1881
1882         return ERROR_OK;
1883 }
1884
1885 COMMAND_HANDLER(handle_etm_stop_command)
1886 {
1887         struct target *target;
1888         struct arm *arm;
1889         struct etm_context *etm_ctx;
1890         struct reg *etm_ctrl_reg;
1891
1892         target = get_current_target(CMD_CTX);
1893         arm = target_to_arm(target);
1894         if (!is_arm(arm)) {
1895                 command_print(CMD, "ETM: current target isn't an ARM");
1896                 return ERROR_FAIL;
1897         }
1898
1899         etm_ctx = arm->etm;
1900         if (!etm_ctx) {
1901                 command_print(CMD, "current target doesn't have an ETM configured");
1902                 return ERROR_FAIL;
1903         }
1904
1905         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1906         if (!etm_ctrl_reg)
1907                 return ERROR_FAIL;
1908
1909         etm_get_reg(etm_ctrl_reg);
1910
1911         /* Set programming bit (10), clear port selection bit (11) */
1912         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1913
1914         etm_store_reg(etm_ctrl_reg);
1915         jtag_execute_queue();
1916
1917         etm_ctx->capture_driver->stop_capture(etm_ctx);
1918
1919         return ERROR_OK;
1920 }
1921
1922 COMMAND_HANDLER(handle_etm_trigger_debug_command)
1923 {
1924         struct target *target;
1925         struct arm *arm;
1926         struct etm_context *etm;
1927
1928         target = get_current_target(CMD_CTX);
1929         arm = target_to_arm(target);
1930         if (!is_arm(arm)) {
1931                 command_print(CMD, "ETM: %s isn't an ARM",
1932                         target_name(target));
1933                 return ERROR_FAIL;
1934         }
1935
1936         etm = arm->etm;
1937         if (!etm) {
1938                 command_print(CMD, "ETM: no ETM configured for %s",
1939                         target_name(target));
1940                 return ERROR_FAIL;
1941         }
1942
1943         if (CMD_ARGC == 1) {
1944                 struct reg *etm_ctrl_reg;
1945                 bool dbgrq;
1946
1947                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1948                 if (!etm_ctrl_reg)
1949                         return ERROR_FAIL;
1950
1951                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
1952                 if (dbgrq)
1953                         etm->control |= ETM_CTRL_DBGRQ;
1954                 else
1955                         etm->control &= ~ETM_CTRL_DBGRQ;
1956
1957                 /* etm->control will be written to hardware
1958                  * the next time an "etm start" is issued.
1959                  */
1960                 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1961         }
1962
1963         command_print(CMD, "ETM: %s debug halt",
1964                 (etm->control & ETM_CTRL_DBGRQ)
1965                 ? "triggers"
1966                 : "does not trigger");
1967         return ERROR_OK;
1968 }
1969
1970 COMMAND_HANDLER(handle_etm_analyze_command)
1971 {
1972         struct target *target;
1973         struct arm *arm;
1974         struct etm_context *etm_ctx;
1975         int retval;
1976
1977         target = get_current_target(CMD_CTX);
1978         arm = target_to_arm(target);
1979         if (!is_arm(arm)) {
1980                 command_print(CMD, "ETM: current target isn't an ARM");
1981                 return ERROR_FAIL;
1982         }
1983
1984         etm_ctx = arm->etm;
1985         if (!etm_ctx) {
1986                 command_print(CMD, "current target doesn't have an ETM configured");
1987                 return ERROR_FAIL;
1988         }
1989
1990         retval = etmv1_analyze_trace(etm_ctx, CMD);
1991         if (retval != ERROR_OK) {
1992                 /* FIX! error should be reported inside etmv1_analyze_trace() */
1993                 switch (retval) {
1994                         case ERROR_ETM_ANALYSIS_FAILED:
1995                                 command_print(CMD,
1996                                         "further analysis failed (corrupted trace data or just end of data");
1997                                 break;
1998                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1999                                 command_print(CMD,
2000                                         "no instruction for current address available, analysis aborted");
2001                                 break;
2002                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
2003                                 command_print(CMD, "no image available for trace analysis");
2004                                 break;
2005                         default:
2006                                 command_print(CMD, "unknown error");
2007                 }
2008         }
2009
2010         return retval;
2011 }
2012
2013 static const struct command_registration etm_config_command_handlers[] = {
2014         {
2015                 /* NOTE:  with ADIv5, ETMs are accessed by DAP operations,
2016                  * possibly over SWD, not JTAG scanchain 6 of 'target'.
2017                  *
2018                  * Also, these parameters don't match ETM v3+ modules...
2019                  */
2020                 .name = "config",
2021                 .handler = handle_etm_config_command,
2022                 .mode = COMMAND_CONFIG,
2023                 .help = "Set up ETM output port.",
2024                 .usage = "target port_width port_mode clocking capture_driver",
2025         },
2026         COMMAND_REGISTRATION_DONE
2027 };
2028 const struct command_registration etm_command_handlers[] = {
2029         {
2030                 .name = "etm",
2031                 .mode = COMMAND_ANY,
2032                 .help = "Embedded Trace Macrocell command group",
2033                 .usage = "",
2034                 .chain = etm_config_command_handlers,
2035         },
2036         COMMAND_REGISTRATION_DONE
2037 };
2038
2039 static const struct command_registration etm_exec_command_handlers[] = {
2040         {
2041                 .name = "tracemode",
2042                 .handler = handle_etm_tracemode_command,
2043                 .mode = COMMAND_EXEC,
2044                 .help = "configure/display trace mode",
2045                 .usage = "('none'|'data'|'address'|'all') "
2046                         "context_id_bits "
2047                         "['enable'|'disable'] "
2048                         "['enable'|'disable']",
2049         },
2050         {
2051                 .name = "info",
2052                 .handler = handle_etm_info_command,
2053                 .mode = COMMAND_EXEC,
2054                 .usage = "",
2055                 .help = "display info about the current target's ETM",
2056         },
2057         {
2058                 .name = "status",
2059                 .handler = handle_etm_status_command,
2060                 .mode = COMMAND_EXEC,
2061                 .usage = "",
2062                 .help = "display current target's ETM status",
2063         },
2064         {
2065                 .name = "start",
2066                 .handler = handle_etm_start_command,
2067                 .mode = COMMAND_EXEC,
2068                 .usage = "",
2069                 .help = "start ETM trace collection",
2070         },
2071         {
2072                 .name = "stop",
2073                 .handler = handle_etm_stop_command,
2074                 .mode = COMMAND_EXEC,
2075                 .usage = "",
2076                 .help = "stop ETM trace collection",
2077         },
2078         {
2079                 .name = "trigger_debug",
2080                 .handler = handle_etm_trigger_debug_command,
2081                 .mode = COMMAND_EXEC,
2082                 .help = "enable/disable debug entry on trigger",
2083                 .usage = "['enable'|'disable']",
2084         },
2085         {
2086                 .name = "analyze",
2087                 .handler = handle_etm_analyze_command,
2088                 .mode = COMMAND_EXEC,
2089                 .usage = "",
2090                 .help = "analyze collected ETM trace",
2091         },
2092         {
2093                 .name = "image",
2094                 .handler = handle_etm_image_command,
2095                 .mode = COMMAND_EXEC,
2096                 .help = "load image from file with optional offset",
2097                 .usage = "<file> [base address] [type]",
2098         },
2099         {
2100                 .name = "dump",
2101                 .handler = handle_etm_dump_command,
2102                 .mode = COMMAND_EXEC,
2103                 .help = "dump captured trace data to file",
2104                 .usage = "filename",
2105         },
2106         {
2107                 .name = "load",
2108                 .handler = handle_etm_load_command,
2109                 .mode = COMMAND_EXEC,
2110                 .usage = "",
2111                 .help = "load trace data for analysis <file>",
2112         },
2113         COMMAND_REGISTRATION_DONE
2114 };
2115
2116 static int etm_register_user_commands(struct command_context *cmd_ctx)
2117 {
2118         struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2119         return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2120 }