1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
26 #include "arm_disassembler.h"
28 #include "etm_dummy.h"
30 #if BUILD_OOCD_TRACE == 1
31 #include "oocd_trace.h"
36 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
38 * ETM modules collect instruction and/or data trace information, compress
39 * it, and transfer it to a debugging host through either a (buffered) trace
40 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
42 * There are several generations of these modules. Original versions have
43 * JTAG access through a dedicated scan chain. Recent versions have added
44 * access via coprocessor instructions, memory addressing, and the ARM Debug
45 * Interface v5 (ADIv5); and phased out direct JTAG access.
47 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
48 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
49 * implying non-JTAG connectivity options.
51 * Relevant documentation includes:
52 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
53 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
54 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
65 uint8_t size; /* low-N of 32 bits */
66 uint8_t mode; /* RO, WO, RW */
67 uint8_t bcd_vers; /* 1.0, 2.0, etc */
72 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
73 * (Or on some processors, through coprocessor operations.)
74 * Newer versions of ETM make some W/O registers R/W, and
75 * provide definitions for some previously-unused bits.
78 /* core registers used to version/configure the ETM */
79 static const struct etm_reg_info etm_core[] = {
80 /* NOTE: we "know" the order here ... */
81 { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
82 { ETM_ID, 32, RO, 0x20, "ETM_id", },
85 /* basic registers that are always there given the right ETM version */
86 static const struct etm_reg_info etm_basic[] = {
87 /* ETM Trace Registers */
88 { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
89 { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
90 { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
91 { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
92 { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
94 /* TraceEnable configuration */
95 { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
96 { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
97 { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
98 { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
100 /* ViewData configuration (data trace) */
101 { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
102 { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
103 { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
104 { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
106 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
108 { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
109 { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
110 { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
111 { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
112 { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
115 static const struct etm_reg_info etm_fifofull[] = {
116 /* FIFOFULL configuration */
117 { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
118 { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
121 static const struct etm_reg_info etm_addr_comp[] = {
122 /* Address comparator register pairs */
123 #define ADDR_COMPARATOR(i) \
124 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
125 "ETM_addr_" #i "_comparator_value", }, \
126 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
127 "ETM_addr_" #i "_access_type", }
146 #undef ADDR_COMPARATOR
149 static const struct etm_reg_info etm_data_comp[] = {
150 /* Data Value Comparators (NOTE: odd addresses are reserved) */
151 #define DATA_COMPARATOR(i) \
152 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
153 "ETM_data_" #i "_comparator_value", }, \
154 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
155 "ETM_data_" #i "_comparator_mask", }
165 #undef DATA_COMPARATOR
168 static const struct etm_reg_info etm_counters[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
186 static const struct etm_reg_info etm_sequencer[] = {
188 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
189 "ETM_sequencer_event" #i, }
190 ETM_SEQ(0), /* 1->2 */
191 ETM_SEQ(1), /* 2->1 */
192 ETM_SEQ(2), /* 2->3 */
193 ETM_SEQ(3), /* 3->1 */
194 ETM_SEQ(4), /* 3->2 */
195 ETM_SEQ(5), /* 1->3 */
198 { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
201 static const struct etm_reg_info etm_outputs[] = {
202 #define ETM_OUTPUT(i) \
203 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
204 "ETM_external_output" #i, }
215 /* registers from 0x6c..0x7f were added after ETMv1.3 */
217 /* Context ID Comparators */
218 { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
219 { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
220 { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
221 { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
224 static int etm_get_reg(struct reg *reg);
225 static int etm_read_reg_w_check(struct reg *reg,
226 uint8_t *check_value, uint8_t *check_mask);
227 static int etm_register_user_commands(struct command_context *cmd_ctx);
228 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
229 static int etm_write_reg(struct reg *reg, uint32_t value);
231 static const struct reg_arch_type etm_scan6_type = {
233 .set = etm_set_reg_w_exec,
236 /* Look up register by ID ... most ETM instances only
237 * support a subset of the possible registers.
239 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
241 struct reg_cache *cache = etm_ctx->reg_cache;
244 for (i = 0; i < cache->num_regs; i++) {
245 struct etm_reg *reg = cache->reg_list[i].arch_info;
247 if (reg->reg_info->addr == id)
248 return &cache->reg_list[i];
251 /* caller asking for nonexistent register is a bug!
252 * REVISIT say which of the N targets was involved */
253 LOG_ERROR("ETM: register 0x%02x not available", id);
257 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
258 struct reg_cache *cache, struct etm_reg *ereg,
259 const struct etm_reg_info *r, unsigned nreg)
261 struct reg *reg = cache->reg_list;
263 reg += cache->num_regs;
264 ereg += cache->num_regs;
266 /* add up to "nreg" registers from "r", if supported by this
267 * version of the ETM, to the specified cache.
269 for (; nreg--; r++) {
270 /* No more registers to add */
272 LOG_ERROR("etm_reg_add is requested to add non-existing registers, ETM config might be bogus");
276 /* this ETM may be too old to have some registers */
277 if (r->bcd_vers > bcd_vers)
282 reg->value = &ereg->value;
283 reg->arch_info = ereg;
284 reg->type = &etm_scan6_type;
289 ereg->jtag_info = jtag_info;
294 struct reg_cache *etm_build_reg_cache(struct target *target,
295 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
297 struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
298 struct reg *reg_list = NULL;
299 struct etm_reg *arch_info = NULL;
300 unsigned bcd_vers, config;
302 /* the actual registers are kept in two arrays */
303 reg_list = calloc(128, sizeof(struct reg));
304 arch_info = calloc(128, sizeof(struct etm_reg));
306 if (reg_cache == NULL || reg_list == NULL || arch_info == NULL) {
307 LOG_ERROR("No memory");
311 /* fill in values for the reg cache */
312 reg_cache->name = "etm registers";
313 reg_cache->next = NULL;
314 reg_cache->reg_list = reg_list;
315 reg_cache->num_regs = 0;
317 /* add ETM_CONFIG, then parse its values to see
318 * which other registers exist in this ETM
320 etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
323 etm_get_reg(reg_list);
324 etm_ctx->config = buf_get_u32(arch_info->value, 0, 32);
325 config = etm_ctx->config;
327 /* figure ETM version then add base registers */
328 if (config & (1 << 31)) {
329 LOG_WARNING("ETMv2+ support is incomplete");
331 /* REVISIT more registers may exist; they may now be
332 * readable; more register bits have defined meanings;
333 * don't presume trace start/stop support is present;
334 * and include any context ID comparator registers.
336 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
338 etm_get_reg(reg_list + 1);
339 etm_ctx->id = buf_get_u32(
340 arch_info[1].value, 0, 32);
341 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
342 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
345 switch (config >> 28) {
362 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
366 etm_ctx->bcd_vers = bcd_vers;
367 LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
369 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
370 etm_basic, ARRAY_SIZE(etm_basic));
372 /* address and data comparators; counters; outputs */
373 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
374 etm_addr_comp, 4 * (0x0f & (config >> 0)));
375 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
376 etm_data_comp, 2 * (0x0f & (config >> 4)));
377 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
378 etm_counters, 4 * (0x07 & (config >> 13)));
379 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
380 etm_outputs, (0x07 & (config >> 20)));
382 /* FIFOFULL presence is optional
383 * REVISIT for ETMv1.2 and later, don't bother adding this
384 * unless ETM_SYS_CONFIG says it's also *supported* ...
386 if (config & (1 << 23))
387 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
388 etm_fifofull, ARRAY_SIZE(etm_fifofull));
390 /* sequencer is optional (for state-dependant triggering) */
391 if (config & (1 << 16))
392 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
393 etm_sequencer, ARRAY_SIZE(etm_sequencer));
395 /* REVISIT could realloc and likely save half the memory
396 * in the two chunks we allocated...
399 /* the ETM might have an ETB connected */
400 if (strcmp(etm_ctx->capture_driver->name, "etb") == 0) {
401 struct etb *etb = etm_ctx->capture_driver_priv;
404 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
408 reg_cache->next = etb_build_reg_cache(etb);
410 etb->reg_cache = reg_cache->next;
413 etm_ctx->reg_cache = reg_cache;
423 static int etm_read_reg(struct reg *reg)
425 return etm_read_reg_w_check(reg, NULL, NULL);
428 static int etm_store_reg(struct reg *reg)
430 return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
433 int etm_setup(struct target *target)
436 uint32_t etm_ctrl_value;
437 struct arm *arm = target_to_arm(target);
438 struct etm_context *etm_ctx = arm->etm;
439 struct reg *etm_ctrl_reg;
441 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
445 /* initialize some ETM control register settings */
446 etm_get_reg(etm_ctrl_reg);
447 etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
449 /* clear the ETM powerdown bit (0) */
450 etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
452 /* configure port width (21,6:4), mode (13,17:16) and
453 * for older modules clocking (13)
455 etm_ctrl_value = (etm_ctrl_value
456 & ~ETM_PORT_WIDTH_MASK
457 & ~ETM_PORT_MODE_MASK
459 & ~ETM_PORT_CLOCK_MASK)
462 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
463 etm_store_reg(etm_ctrl_reg);
465 etm_ctx->control = etm_ctrl_value;
467 retval = jtag_execute_queue();
468 if (retval != ERROR_OK)
471 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
472 * verify that those width and mode settings are OK ...
475 retval = etm_ctx->capture_driver->init(etm_ctx);
476 if (retval != ERROR_OK) {
477 LOG_ERROR("ETM capture driver initialization failed");
483 static int etm_get_reg(struct reg *reg)
487 retval = etm_read_reg(reg);
488 if (retval != ERROR_OK) {
489 LOG_ERROR("BUG: error scheduling etm register read");
493 retval = jtag_execute_queue();
494 if (retval != ERROR_OK) {
495 LOG_ERROR("register read failed");
502 static int etm_read_reg_w_check(struct reg *reg,
503 uint8_t *check_value, uint8_t *check_mask)
505 struct etm_reg *etm_reg = reg->arch_info;
507 const struct etm_reg_info *r = etm_reg->reg_info;
508 uint8_t reg_addr = r->addr & 0x7f;
509 struct scan_field fields[3];
512 if (etm_reg->reg_info->mode == WO) {
513 LOG_ERROR("BUG: can't read write-only register %s", r->name);
514 return ERROR_COMMAND_SYNTAX_ERROR;
517 LOG_DEBUG("%s (%u)", r->name, reg_addr);
519 retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
520 if (retval != ERROR_OK)
522 retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
523 etm_reg->jtag_info->intest_instr,
526 if (retval != ERROR_OK)
529 fields[0].num_bits = 32;
530 fields[0].out_value = reg->value;
531 fields[0].in_value = NULL;
532 fields[0].check_value = NULL;
533 fields[0].check_mask = NULL;
535 fields[1].num_bits = 7;
537 fields[1].out_value = &temp1;
538 buf_set_u32(&temp1, 0, 7, reg_addr);
539 fields[1].in_value = NULL;
540 fields[1].check_value = NULL;
541 fields[1].check_mask = NULL;
543 fields[2].num_bits = 1;
545 fields[2].out_value = &temp2;
546 buf_set_u32(&temp2, 0, 1, 0);
547 fields[2].in_value = NULL;
548 fields[2].check_value = NULL;
549 fields[2].check_mask = NULL;
551 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
553 fields[0].in_value = reg->value;
554 fields[0].check_value = check_value;
555 fields[0].check_mask = check_mask;
557 jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
562 static int etm_set_reg(struct reg *reg, uint32_t value)
564 int retval = etm_write_reg(reg, value);
565 if (retval != ERROR_OK) {
566 LOG_ERROR("BUG: error scheduling etm register write");
570 buf_set_u32(reg->value, 0, reg->size, value);
577 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
581 etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
583 retval = jtag_execute_queue();
584 if (retval != ERROR_OK) {
585 LOG_ERROR("register write failed");
591 static int etm_write_reg(struct reg *reg, uint32_t value)
593 struct etm_reg *etm_reg = reg->arch_info;
594 const struct etm_reg_info *r = etm_reg->reg_info;
595 uint8_t reg_addr = r->addr & 0x7f;
596 struct scan_field fields[3];
599 if (etm_reg->reg_info->mode == RO) {
600 LOG_ERROR("BUG: can't write read--only register %s", r->name);
601 return ERROR_COMMAND_SYNTAX_ERROR;
604 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
606 retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
607 if (retval != ERROR_OK)
609 retval = arm_jtag_set_instr(etm_reg->jtag_info->tap,
610 etm_reg->jtag_info->intest_instr,
613 if (retval != ERROR_OK)
616 fields[0].num_bits = 32;
618 fields[0].out_value = tmp1;
619 buf_set_u32(tmp1, 0, 32, value);
620 fields[0].in_value = NULL;
622 fields[1].num_bits = 7;
624 fields[1].out_value = &tmp2;
625 buf_set_u32(&tmp2, 0, 7, reg_addr);
626 fields[1].in_value = NULL;
628 fields[2].num_bits = 1;
630 fields[2].out_value = &tmp3;
631 buf_set_u32(&tmp3, 0, 1, 1);
632 fields[2].in_value = NULL;
634 jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
640 /* ETM trace analysis functionality */
642 static struct etm_capture_driver *etm_capture_drivers[] = {
644 &etm_dummy_capture_driver,
645 #if BUILD_OOCD_TRACE == 1
646 &oocd_trace_capture_driver,
651 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
659 return ERROR_TRACE_IMAGE_UNAVAILABLE;
661 /* search for the section the current instruction belongs to */
662 for (unsigned int i = 0; i < ctx->image->num_sections; i++) {
663 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
664 (ctx->image->sections[i].base_address + ctx->image->sections[i].size >
672 /* current instruction couldn't be found in the image */
673 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
676 if (ctx->core_state == ARM_STATE_ARM) {
678 retval = image_read_section(ctx->image, section,
680 ctx->image->sections[section].base_address,
682 if (retval != ERROR_OK) {
683 LOG_ERROR("error while reading instruction");
684 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
686 opcode = target_buffer_get_u32(ctx->target, buf);
687 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
688 } else if (ctx->core_state == ARM_STATE_THUMB) {
690 retval = image_read_section(ctx->image, section,
692 ctx->image->sections[section].base_address,
694 if (retval != ERROR_OK) {
695 LOG_ERROR("error while reading instruction");
696 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
698 opcode = target_buffer_get_u16(ctx->target, buf);
699 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
700 } else if (ctx->core_state == ARM_STATE_JAZELLE) {
701 LOG_ERROR("BUG: tracing of jazelle code not supported");
704 LOG_ERROR("BUG: unknown core state encountered");
711 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
713 while (ctx->data_index < ctx->trace_depth) {
714 /* if the caller specified an address packet offset, skip until the
715 * we reach the n-th cycle marked with tracesync */
717 if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
727 /* no tracedata output during a TD cycle
728 * or in a trigger cycle */
729 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
730 || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE)) {
736 /* FIXME there are more port widths than these... */
737 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT) {
738 if (ctx->data_half == 0) {
739 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
742 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
746 } else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) {
747 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
750 /* on a 4-bit port, a packet will be output during two consecutive cycles */
751 if (ctx->data_index > (ctx->trace_depth - 2))
754 *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
755 *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
756 ctx->data_index += 2;
765 static int etmv1_branch_address(struct etm_context *ctx)
773 /* quit analysis if less than two cycles are left in the trace
774 * because we can't extract the APO */
775 if (ctx->data_index > (ctx->trace_depth - 2))
778 /* a BE could be output during an APO cycle, skip the current
779 * and continue with the new one */
780 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
782 if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
785 /* address packet offset encoded in the next two cycles' pipestat bits */
786 apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
787 apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
789 /* count number of tracesync cycles between current pipe_index and data_index
790 * i.e. the number of tracesyncs that data_index already passed by
791 * to subtract them from the APO */
792 for (i = ctx->pipe_index; i < ctx->data_index; i++) {
793 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
797 /* extract up to four 7-bit packets */
799 retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0);
802 ctx->last_branch &= ~(0x7f << shift);
803 ctx->last_branch |= (packet & 0x7f) << shift;
805 } while ((packet & 0x80) && (shift < 28));
807 /* one last packet holding 4 bits of the address, plus the branch reason code */
808 if ((shift == 28) && (packet & 0x80)) {
809 retval = etmv1_next_packet(ctx, &packet, 0);
812 ctx->last_branch &= 0x0fffffff;
813 ctx->last_branch |= (packet & 0x0f) << 28;
814 ctx->last_branch_reason = (packet & 0x70) >> 4;
817 ctx->last_branch_reason = 0;
822 /* if a full address was output, we might have branched into Jazelle state */
823 if ((shift == 32) && (packet & 0x80))
824 ctx->core_state = ARM_STATE_JAZELLE;
826 /* if we didn't branch into Jazelle state, the current processor state is
827 * encoded in bit 0 of the branch target address */
828 if (ctx->last_branch & 0x1) {
829 ctx->core_state = ARM_STATE_THUMB;
830 ctx->last_branch &= ~0x1;
832 ctx->core_state = ARM_STATE_ARM;
833 ctx->last_branch &= ~0x3;
840 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
846 for (j = 0; j < size; j++) {
847 retval = etmv1_next_packet(ctx, &buf[j], 0);
853 LOG_ERROR("TODO: add support for 64-bit values");
855 } else if (size == 4)
856 *data = target_buffer_get_u32(ctx->target, buf);
858 *data = target_buffer_get_u16(ctx->target, buf);
867 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocation *cmd)
870 struct arm_instruction instruction;
872 /* read the trace data if it wasn't read already */
873 if (ctx->trace_depth == 0)
874 ctx->capture_driver->read_trace(ctx);
876 if (ctx->trace_depth == 0) {
877 command_print(cmd, "Trace is empty.");
881 /* start at the beginning of the captured trace */
886 /* neither the PC nor the data pointer are valid */
890 while (ctx->pipe_index < ctx->trace_depth) {
891 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
892 uint32_t next_pc = ctx->current_pc;
893 uint32_t old_data_index = ctx->data_index;
894 uint32_t old_data_half = ctx->data_half;
895 uint32_t old_index = ctx->pipe_index;
896 uint32_t last_instruction = ctx->last_instruction;
898 int current_pc_ok = ctx->pc_ok;
900 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
901 command_print(cmd, "--- trigger ---");
903 /* instructions execute in IE/D or BE/D cycles */
904 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
905 ctx->last_instruction = ctx->pipe_index;
907 /* if we don't have a valid pc skip until we reach an indirect branch */
908 if ((!ctx->pc_ok) && (pipestat != STAT_BE)) {
913 /* any indirect branch could have interrupted instruction flow
914 * - the branch reason code could indicate a trace discontinuity
915 * - a branch to the exception vectors indicates an exception
917 if ((pipestat == STAT_BE) || (pipestat == STAT_BD)) {
918 /* backup current data index, to be able to consume the branch address
919 * before examining data address and values
921 old_data_index = ctx->data_index;
922 old_data_half = ctx->data_half;
924 ctx->last_instruction = ctx->pipe_index;
926 retval = etmv1_branch_address(ctx);
928 /* negative return value from etmv1_branch_address means we ran out of packets,
929 * quit analysing the trace */
933 /* a positive return values means the current branch was abandoned,
934 * and a new branch was encountered in cycle ctx->pipe_index + retval;
937 "abandoned branch encountered, correctness of analysis uncertain");
938 ctx->pipe_index += retval;
942 /* skip over APO cycles */
943 ctx->pipe_index += 2;
945 switch (ctx->last_branch_reason) {
946 case 0x0: /* normal PC change */
947 next_pc = ctx->last_branch;
949 case 0x1: /* tracing enabled */
951 "--- tracing enabled at 0x%8.8" PRIx32 " ---",
953 ctx->current_pc = ctx->last_branch;
957 case 0x2: /* trace restarted after FIFO overflow */
959 "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---",
961 ctx->current_pc = ctx->last_branch;
965 case 0x3: /* exit from debug state */
967 "--- exit from debug state at 0x%8.8" PRIx32 " ---",
969 ctx->current_pc = ctx->last_branch;
973 case 0x4: /* periodic synchronization point */
974 next_pc = ctx->last_branch;
975 /* if we had no valid PC prior to this synchronization point,
976 * we have to move on with the next trace cycle
978 if (!current_pc_ok) {
980 "--- periodic synchronization point at 0x%8.8" PRIx32 " ---",
982 ctx->current_pc = next_pc;
987 default: /* reserved */
989 "BUG: branch reason code 0x%" PRIx32 " is reserved",
990 ctx->last_branch_reason);
994 /* if we got here the branch was a normal PC change
995 * (or a periodic synchronization point, which means the same for that matter)
996 * if we didn't acquire a complete PC continue with the next cycle
1001 /* indirect branch to the exception vector means an exception occurred */
1002 if ((ctx->last_branch <= 0x20)
1003 || ((ctx->last_branch >= 0xffff0000) &&
1004 (ctx->last_branch <= 0xffff0020))) {
1005 if ((ctx->last_branch & 0xff) == 0x10)
1006 command_print(cmd, "data abort");
1009 "exception vector 0x%2.2" PRIx32 "",
1011 ctx->current_pc = ctx->last_branch;
1018 /* an instruction was executed (or not, depending on the condition flags)
1019 * retrieve it from the image for displaying */
1020 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1021 !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1022 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4)))) {
1023 retval = etm_read_instruction(ctx, &instruction);
1024 if (retval != ERROR_OK) {
1025 /* can't continue tracing with no image available */
1026 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1028 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE) {
1029 /* TODO: handle incomplete images
1030 * for now we just quit the analysis*/
1035 cycles = old_index - last_instruction;
1038 if ((pipestat == STAT_ID) || (pipestat == STAT_BD)) {
1039 uint32_t new_data_index = ctx->data_index;
1040 uint32_t new_data_half = ctx->data_half;
1042 /* in case of a branch with data, the branch target address was consumed before
1043 * we temporarily go back to the saved data index */
1044 if (pipestat == STAT_BD) {
1045 ctx->data_index = old_data_index;
1046 ctx->data_half = old_data_half;
1049 if (ctx->control & ETM_CTRL_TRACE_ADDR) {
1054 retval = etmv1_next_packet(ctx, &packet, 0);
1056 return ERROR_ETM_ANALYSIS_FAILED;
1057 ctx->last_ptr &= ~(0x7f << shift);
1058 ctx->last_ptr |= (packet & 0x7f) << shift;
1060 } while ((packet & 0x80) && (shift < 32));
1067 "address: 0x%8.8" PRIx32 "",
1071 if (ctx->control & ETM_CTRL_TRACE_DATA) {
1072 if ((instruction.type == ARM_LDM) ||
1073 (instruction.type == ARM_STM)) {
1075 for (i = 0; i < 16; i++) {
1076 if (instruction.info.load_store_multiple.register_list
1079 if (etmv1_data(ctx, 4, &data) != 0)
1080 return ERROR_ETM_ANALYSIS_FAILED;
1082 "data: 0x%8.8" PRIx32 "",
1086 } else if ((instruction.type >= ARM_LDR) &&
1087 (instruction.type <= ARM_STRH)) {
1089 if (etmv1_data(ctx, arm_access_size(&instruction),
1091 return ERROR_ETM_ANALYSIS_FAILED;
1092 command_print(cmd, "data: 0x%8.8" PRIx32 "", data);
1096 /* restore data index after consuming BD address and data */
1097 if (pipestat == STAT_BD) {
1098 ctx->data_index = new_data_index;
1099 ctx->data_half = new_data_half;
1104 if ((pipestat == STAT_IE) || (pipestat == STAT_ID)) {
1105 if (((instruction.type == ARM_B) ||
1106 (instruction.type == ARM_BL) ||
1107 (instruction.type == ARM_BLX)) &&
1108 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1109 next_pc = instruction.info.b_bl_bx_blx.target_address;
1111 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1112 } else if (pipestat == STAT_IN)
1113 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1115 if ((pipestat != STAT_TD) && (pipestat != STAT_WT)) {
1116 char cycles_text[32] = "";
1118 /* if the trace was captured with cycle accurate tracing enabled,
1119 * output the number of cycles since the last executed instruction
1121 if (ctx->control & ETM_CTRL_CYCLE_ACCURATE) {
1122 snprintf(cycles_text, 32, " (%i %s)",
1124 (cycles == 1) ? "cycle" : "cycles");
1127 command_print(cmd, "%s%s%s",
1129 (pipestat == STAT_IN) ? " (not executed)" : "",
1132 ctx->current_pc = next_pc;
1134 /* packets for an instruction don't start on or before the preceding
1135 * functional pipestat (i.e. other than WT or TD)
1137 if (ctx->data_index <= ctx->pipe_index) {
1138 ctx->data_index = ctx->pipe_index + 1;
1143 ctx->pipe_index += 1;
1149 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1154 /* what parts of data access are traced? */
1155 if (strcmp(CMD_ARGV[0], "none") == 0)
1157 else if (strcmp(CMD_ARGV[0], "data") == 0)
1158 tracemode = ETM_CTRL_TRACE_DATA;
1159 else if (strcmp(CMD_ARGV[0], "address") == 0)
1160 tracemode = ETM_CTRL_TRACE_ADDR;
1161 else if (strcmp(CMD_ARGV[0], "all") == 0)
1162 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1164 command_print(CMD, "invalid option '%s'", CMD_ARGV[0]);
1165 return ERROR_COMMAND_SYNTAX_ERROR;
1169 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1170 switch (context_id) {
1172 tracemode |= ETM_CTRL_CONTEXTID_NONE;
1175 tracemode |= ETM_CTRL_CONTEXTID_8;
1178 tracemode |= ETM_CTRL_CONTEXTID_16;
1181 tracemode |= ETM_CTRL_CONTEXTID_32;
1184 command_print(CMD, "invalid option '%s'", CMD_ARGV[1]);
1185 return ERROR_COMMAND_SYNTAX_ERROR;
1188 bool etmv1_cycle_accurate;
1189 COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1190 if (etmv1_cycle_accurate)
1191 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1193 bool etmv1_branch_output;
1194 COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1195 if (etmv1_branch_output)
1196 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1199 * - CPRT tracing (coprocessor register transfers)
1200 * - debug request (causes debug entry on trigger)
1201 * - stall on FIFOFULL (preventing tracedata loss)
1208 COMMAND_HANDLER(handle_etm_tracemode_command)
1210 struct target *target = get_current_target(CMD_CTX);
1211 struct arm *arm = target_to_arm(target);
1212 struct etm_context *etm;
1215 command_print(CMD, "ETM: current target isn't an ARM");
1221 command_print(CMD, "current target doesn't have an ETM configured");
1225 uint32_t tracemode = etm->control;
1231 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1235 return ERROR_COMMAND_SYNTAX_ERROR;
1239 * todo: fail if parameters were invalid for this hardware,
1240 * or couldn't be written; display actual hardware state...
1243 command_print(CMD, "current tracemode configuration:");
1245 switch (tracemode & ETM_CTRL_TRACE_MASK) {
1247 command_print(CMD, "data tracing: none");
1249 case ETM_CTRL_TRACE_DATA:
1250 command_print(CMD, "data tracing: data only");
1252 case ETM_CTRL_TRACE_ADDR:
1253 command_print(CMD, "data tracing: address only");
1255 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1256 command_print(CMD, "data tracing: address and data");
1260 switch (tracemode & ETM_CTRL_CONTEXTID_MASK) {
1261 case ETM_CTRL_CONTEXTID_NONE:
1262 command_print(CMD, "contextid tracing: none");
1264 case ETM_CTRL_CONTEXTID_8:
1265 command_print(CMD, "contextid tracing: 8 bit");
1267 case ETM_CTRL_CONTEXTID_16:
1268 command_print(CMD, "contextid tracing: 16 bit");
1270 case ETM_CTRL_CONTEXTID_32:
1271 command_print(CMD, "contextid tracing: 32 bit");
1275 if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1276 command_print(CMD, "cycle-accurate tracing enabled");
1278 command_print(CMD, "cycle-accurate tracing disabled");
1280 if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1281 command_print(CMD, "full branch address output enabled");
1283 command_print(CMD, "full branch address output disabled");
1285 #define TRACEMODE_MASK ( \
1286 ETM_CTRL_CONTEXTID_MASK \
1287 | ETM_CTRL_BRANCH_OUTPUT \
1288 | ETM_CTRL_CYCLE_ACCURATE \
1289 | ETM_CTRL_TRACE_MASK \
1292 /* only update ETM_CTRL register if tracemode changed */
1293 if ((etm->control & TRACEMODE_MASK) != tracemode) {
1294 struct reg *etm_ctrl_reg;
1296 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1300 etm->control &= ~TRACEMODE_MASK;
1301 etm->control |= tracemode & TRACEMODE_MASK;
1303 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1304 etm_store_reg(etm_ctrl_reg);
1306 /* invalidate old trace data */
1307 etm->capture_status = TRACE_IDLE;
1308 if (etm->trace_depth > 0) {
1309 free(etm->trace_data);
1310 etm->trace_data = NULL;
1312 etm->trace_depth = 0;
1315 #undef TRACEMODE_MASK
1320 COMMAND_HANDLER(handle_etm_config_command)
1322 struct target *target;
1324 uint32_t portmode = 0x0;
1325 struct etm_context *etm_ctx;
1329 return ERROR_COMMAND_SYNTAX_ERROR;
1331 target = get_target(CMD_ARGV[0]);
1333 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1337 arm = target_to_arm(target);
1339 command_print(CMD, "target '%s' is '%s'; not an ARM",
1340 target_name(target),
1341 target_type_name(target));
1345 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1346 * version we'll be using!! -- so we can't know how to validate
1347 * params yet. "etm config" should likely be *AFTER* hookup...
1349 * - Many more widths might be supported ... and we can easily
1350 * check whether our setting "took".
1352 * - The "clock" and "mode" bits are interpreted differently.
1353 * See ARM IHI 0014O table 2-17 for the old behaviour, and
1354 * table 2-18 for the new. With ETB it's best to specify
1358 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1359 switch (port_width) {
1360 /* before ETMv3.0 */
1362 portmode |= ETM_PORT_4BIT;
1365 portmode |= ETM_PORT_8BIT;
1368 portmode |= ETM_PORT_16BIT;
1370 /* ETMv3.0 and later*/
1372 portmode |= ETM_PORT_24BIT;
1375 portmode |= ETM_PORT_32BIT;
1378 portmode |= ETM_PORT_48BIT;
1381 portmode |= ETM_PORT_64BIT;
1384 portmode |= ETM_PORT_1BIT;
1387 portmode |= ETM_PORT_2BIT;
1391 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1395 if (strcmp("normal", CMD_ARGV[2]) == 0)
1396 portmode |= ETM_PORT_NORMAL;
1397 else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1398 portmode |= ETM_PORT_MUXED;
1399 else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1400 portmode |= ETM_PORT_DEMUXED;
1403 "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'",
1408 if (strcmp("half", CMD_ARGV[3]) == 0)
1409 portmode |= ETM_PORT_HALF_CLOCK;
1410 else if (strcmp("full", CMD_ARGV[3]) == 0)
1411 portmode |= ETM_PORT_FULL_CLOCK;
1414 "unsupported ETM port clocking '%s', must be 'full' or 'half'",
1419 etm_ctx = calloc(1, sizeof(struct etm_context));
1421 LOG_DEBUG("out of memory");
1425 for (i = 0; etm_capture_drivers[i]; i++) {
1426 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0) {
1427 int retval = register_commands(CMD_CTX, NULL,
1428 etm_capture_drivers[i]->commands);
1429 if (ERROR_OK != retval) {
1434 etm_ctx->capture_driver = etm_capture_drivers[i];
1440 if (!etm_capture_drivers[i]) {
1441 /* no supported capture driver found, don't register an ETM */
1443 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1447 etm_ctx->target = target;
1448 etm_ctx->trace_data = NULL;
1449 etm_ctx->control = portmode;
1450 etm_ctx->core_state = ARM_STATE_ARM;
1454 return etm_register_user_commands(CMD_CTX);
1457 COMMAND_HANDLER(handle_etm_info_command)
1459 struct target *target;
1461 struct etm_context *etm;
1462 struct reg *etm_sys_config_reg;
1466 target = get_current_target(CMD_CTX);
1467 arm = target_to_arm(target);
1469 command_print(CMD, "ETM: current target isn't an ARM");
1475 command_print(CMD, "current target doesn't have an ETM configured");
1479 command_print(CMD, "ETM v%d.%d",
1480 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1481 command_print(CMD, "pairs of address comparators: %i",
1482 (int) (etm->config >> 0) & 0x0f);
1483 command_print(CMD, "data comparators: %i",
1484 (int) (etm->config >> 4) & 0x0f);
1485 command_print(CMD, "memory map decoders: %i",
1486 (int) (etm->config >> 8) & 0x1f);
1487 command_print(CMD, "number of counters: %i",
1488 (int) (etm->config >> 13) & 0x07);
1489 command_print(CMD, "sequencer %spresent",
1490 (int) (etm->config & (1 << 16)) ? "" : "not ");
1491 command_print(CMD, "number of ext. inputs: %i",
1492 (int) (etm->config >> 17) & 0x07);
1493 command_print(CMD, "number of ext. outputs: %i",
1494 (int) (etm->config >> 20) & 0x07);
1495 command_print(CMD, "FIFO full %spresent",
1496 (int) (etm->config & (1 << 23)) ? "" : "not ");
1497 if (etm->bcd_vers < 0x20)
1498 command_print(CMD, "protocol version: %i",
1499 (int) (etm->config >> 28) & 0x07);
1502 "coprocessor and memory access %ssupported",
1503 (etm->config & (1 << 26)) ? "" : "not ");
1504 command_print(CMD, "trace start/stop %spresent",
1505 (etm->config & (1 << 26)) ? "" : "not ");
1506 command_print(CMD, "number of context comparators: %i",
1507 (int) (etm->config >> 24) & 0x03);
1510 /* SYS_CONFIG isn't present before ETMv1.2 */
1511 etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1512 if (!etm_sys_config_reg)
1515 etm_get_reg(etm_sys_config_reg);
1516 config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1518 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1520 max_port_size = config & 0x7;
1521 if (etm->bcd_vers >= 0x30)
1522 max_port_size |= (config >> 6) & 0x08;
1523 switch (max_port_size) {
1524 /* before ETMv3.0 */
1534 /* ETMv3.0 and later*/
1554 LOG_ERROR("Illegal max_port_size");
1557 command_print(CMD, "max. port size: %i", max_port_size);
1559 if (etm->bcd_vers < 0x30) {
1560 command_print(CMD, "half-rate clocking %ssupported",
1561 (config & (1 << 3)) ? "" : "not ");
1562 command_print(CMD, "full-rate clocking %ssupported",
1563 (config & (1 << 4)) ? "" : "not ");
1564 command_print(CMD, "normal trace format %ssupported",
1565 (config & (1 << 5)) ? "" : "not ");
1566 command_print(CMD, "multiplex trace format %ssupported",
1567 (config & (1 << 6)) ? "" : "not ");
1568 command_print(CMD, "demultiplex trace format %ssupported",
1569 (config & (1 << 7)) ? "" : "not ");
1571 /* REVISIT show which size and format are selected ... */
1572 command_print(CMD, "current port size %ssupported",
1573 (config & (1 << 10)) ? "" : "not ");
1574 command_print(CMD, "current trace format %ssupported",
1575 (config & (1 << 11)) ? "" : "not ");
1577 if (etm->bcd_vers >= 0x21)
1578 command_print(CMD, "fetch comparisons %ssupported",
1579 (config & (1 << 17)) ? "not " : "");
1580 command_print(CMD, "FIFO full %ssupported",
1581 (config & (1 << 8)) ? "" : "not ");
1586 COMMAND_HANDLER(handle_etm_status_command)
1588 struct target *target;
1590 struct etm_context *etm;
1591 trace_status_t trace_status;
1593 target = get_current_target(CMD_CTX);
1594 arm = target_to_arm(target);
1596 command_print(CMD, "ETM: current target isn't an ARM");
1602 command_print(CMD, "current target doesn't have an ETM configured");
1607 if (etm->bcd_vers >= 0x11) {
1610 reg = etm_reg_lookup(etm, ETM_STATUS);
1613 if (etm_get_reg(reg) == ERROR_OK) {
1614 unsigned s = buf_get_u32(reg->value, 0, reg->size);
1616 command_print(CMD, "etm: %s%s%s%s",
1617 /* bit(1) == progbit */
1618 (etm->bcd_vers >= 0x12)
1620 ? "disabled" : "enabled")
1622 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1623 ? " triggered" : "",
1624 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1625 ? " start/stop" : "",
1626 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1627 ? " untraced-overflow" : "");
1628 } /* else ignore and try showing trace port status */
1631 /* Trace Port Driver status */
1632 trace_status = etm->capture_driver->status(etm);
1633 if (trace_status == TRACE_IDLE)
1634 command_print(CMD, "%s: idle", etm->capture_driver->name);
1636 static char *completed = " completed";
1637 static char *running = " is running";
1638 static char *overflowed = ", overflowed";
1639 static char *triggered = ", triggered";
1641 command_print(CMD, "%s: trace collection%s%s%s",
1642 etm->capture_driver->name,
1643 (trace_status & TRACE_RUNNING) ? running : completed,
1644 (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1645 (trace_status & TRACE_TRIGGERED) ? triggered : "");
1647 if (etm->trace_depth > 0) {
1648 command_print(CMD, "%i frames of trace data read",
1649 (int)(etm->trace_depth));
1656 COMMAND_HANDLER(handle_etm_image_command)
1658 struct target *target;
1660 struct etm_context *etm_ctx;
1663 return ERROR_COMMAND_SYNTAX_ERROR;
1665 target = get_current_target(CMD_CTX);
1666 arm = target_to_arm(target);
1668 command_print(CMD, "ETM: current target isn't an ARM");
1674 command_print(CMD, "current target doesn't have an ETM configured");
1678 if (etm_ctx->image) {
1679 image_close(etm_ctx->image);
1680 free(etm_ctx->image);
1681 command_print(CMD, "previously loaded image found and closed");
1684 etm_ctx->image = malloc(sizeof(struct image));
1685 etm_ctx->image->base_address_set = false;
1686 etm_ctx->image->start_address_set = false;
1688 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1689 if (CMD_ARGC >= 2) {
1690 etm_ctx->image->base_address_set = true;
1691 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1693 etm_ctx->image->base_address_set = false;
1695 if (image_open(etm_ctx->image, CMD_ARGV[0],
1696 (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {
1697 free(etm_ctx->image);
1698 etm_ctx->image = NULL;
1705 COMMAND_HANDLER(handle_etm_dump_command)
1707 struct fileio *file;
1708 struct target *target;
1710 struct etm_context *etm_ctx;
1714 return ERROR_COMMAND_SYNTAX_ERROR;
1716 target = get_current_target(CMD_CTX);
1717 arm = target_to_arm(target);
1719 command_print(CMD, "ETM: current target isn't an ARM");
1725 command_print(CMD, "current target doesn't have an ETM configured");
1729 if (etm_ctx->capture_driver->status == TRACE_IDLE) {
1730 command_print(CMD, "trace capture wasn't enabled, no trace data captured");
1734 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1735 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1736 command_print(CMD, "trace capture not completed");
1740 /* read the trace data if it wasn't read already */
1741 if (etm_ctx->trace_depth == 0)
1742 etm_ctx->capture_driver->read_trace(etm_ctx);
1744 if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1747 fileio_write_u32(file, etm_ctx->capture_status);
1748 fileio_write_u32(file, etm_ctx->control);
1749 fileio_write_u32(file, etm_ctx->trace_depth);
1751 for (i = 0; i < etm_ctx->trace_depth; i++) {
1752 fileio_write_u32(file, etm_ctx->trace_data[i].pipestat);
1753 fileio_write_u32(file, etm_ctx->trace_data[i].packet);
1754 fileio_write_u32(file, etm_ctx->trace_data[i].flags);
1762 COMMAND_HANDLER(handle_etm_load_command)
1764 struct fileio *file;
1765 struct target *target;
1767 struct etm_context *etm_ctx;
1771 return ERROR_COMMAND_SYNTAX_ERROR;
1773 target = get_current_target(CMD_CTX);
1774 arm = target_to_arm(target);
1776 command_print(CMD, "ETM: current target isn't an ARM");
1782 command_print(CMD, "current target doesn't have an ETM configured");
1786 if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1787 command_print(CMD, "trace capture running, stop first");
1791 if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1795 int retval = fileio_size(file, &filesize);
1796 if (retval != ERROR_OK) {
1802 command_print(CMD, "size isn't a multiple of 4, no valid trace data");
1807 if (etm_ctx->trace_depth > 0) {
1808 free(etm_ctx->trace_data);
1809 etm_ctx->trace_data = NULL;
1814 fileio_read_u32(file, &tmp); etm_ctx->capture_status = tmp;
1815 fileio_read_u32(file, &tmp); etm_ctx->control = tmp;
1816 fileio_read_u32(file, &etm_ctx->trace_depth);
1818 etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1819 if (etm_ctx->trace_data == NULL) {
1820 command_print(CMD, "not enough memory to perform operation");
1825 for (i = 0; i < etm_ctx->trace_depth; i++) {
1826 uint32_t pipestat, packet, flags;
1827 fileio_read_u32(file, &pipestat);
1828 fileio_read_u32(file, &packet);
1829 fileio_read_u32(file, &flags);
1830 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1831 etm_ctx->trace_data[i].packet = packet & 0xffff;
1832 etm_ctx->trace_data[i].flags = flags;
1840 COMMAND_HANDLER(handle_etm_start_command)
1842 struct target *target;
1844 struct etm_context *etm_ctx;
1845 struct reg *etm_ctrl_reg;
1847 target = get_current_target(CMD_CTX);
1848 arm = target_to_arm(target);
1850 command_print(CMD, "ETM: current target isn't an ARM");
1856 command_print(CMD, "current target doesn't have an ETM configured");
1860 /* invalidate old tracing data */
1861 etm_ctx->capture_status = TRACE_IDLE;
1862 if (etm_ctx->trace_depth > 0) {
1863 free(etm_ctx->trace_data);
1864 etm_ctx->trace_data = NULL;
1866 etm_ctx->trace_depth = 0;
1868 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1872 etm_get_reg(etm_ctrl_reg);
1874 /* Clear programming bit (10), set port selection bit (11) */
1875 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1877 etm_store_reg(etm_ctrl_reg);
1878 jtag_execute_queue();
1880 etm_ctx->capture_driver->start_capture(etm_ctx);
1885 COMMAND_HANDLER(handle_etm_stop_command)
1887 struct target *target;
1889 struct etm_context *etm_ctx;
1890 struct reg *etm_ctrl_reg;
1892 target = get_current_target(CMD_CTX);
1893 arm = target_to_arm(target);
1895 command_print(CMD, "ETM: current target isn't an ARM");
1901 command_print(CMD, "current target doesn't have an ETM configured");
1905 etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1909 etm_get_reg(etm_ctrl_reg);
1911 /* Set programming bit (10), clear port selection bit (11) */
1912 buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1914 etm_store_reg(etm_ctrl_reg);
1915 jtag_execute_queue();
1917 etm_ctx->capture_driver->stop_capture(etm_ctx);
1922 COMMAND_HANDLER(handle_etm_trigger_debug_command)
1924 struct target *target;
1926 struct etm_context *etm;
1928 target = get_current_target(CMD_CTX);
1929 arm = target_to_arm(target);
1931 command_print(CMD, "ETM: %s isn't an ARM",
1932 target_name(target));
1938 command_print(CMD, "ETM: no ETM configured for %s",
1939 target_name(target));
1943 if (CMD_ARGC == 1) {
1944 struct reg *etm_ctrl_reg;
1947 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1951 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
1953 etm->control |= ETM_CTRL_DBGRQ;
1955 etm->control &= ~ETM_CTRL_DBGRQ;
1957 /* etm->control will be written to hardware
1958 * the next time an "etm start" is issued.
1960 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1963 command_print(CMD, "ETM: %s debug halt",
1964 (etm->control & ETM_CTRL_DBGRQ)
1966 : "does not trigger");
1970 COMMAND_HANDLER(handle_etm_analyze_command)
1972 struct target *target;
1974 struct etm_context *etm_ctx;
1977 target = get_current_target(CMD_CTX);
1978 arm = target_to_arm(target);
1980 command_print(CMD, "ETM: current target isn't an ARM");
1986 command_print(CMD, "current target doesn't have an ETM configured");
1990 retval = etmv1_analyze_trace(etm_ctx, CMD);
1991 if (retval != ERROR_OK) {
1992 /* FIX! error should be reported inside etmv1_analyze_trace() */
1994 case ERROR_ETM_ANALYSIS_FAILED:
1996 "further analysis failed (corrupted trace data or just end of data");
1998 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2000 "no instruction for current address available, analysis aborted");
2002 case ERROR_TRACE_IMAGE_UNAVAILABLE:
2003 command_print(CMD, "no image available for trace analysis");
2006 command_print(CMD, "unknown error");
2013 static const struct command_registration etm_config_command_handlers[] = {
2015 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2016 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2018 * Also, these parameters don't match ETM v3+ modules...
2021 .handler = handle_etm_config_command,
2022 .mode = COMMAND_CONFIG,
2023 .help = "Set up ETM output port.",
2024 .usage = "target port_width port_mode clocking capture_driver",
2026 COMMAND_REGISTRATION_DONE
2028 const struct command_registration etm_command_handlers[] = {
2031 .mode = COMMAND_ANY,
2032 .help = "Embedded Trace Macrocell command group",
2034 .chain = etm_config_command_handlers,
2036 COMMAND_REGISTRATION_DONE
2039 static const struct command_registration etm_exec_command_handlers[] = {
2041 .name = "tracemode",
2042 .handler = handle_etm_tracemode_command,
2043 .mode = COMMAND_EXEC,
2044 .help = "configure/display trace mode",
2045 .usage = "('none'|'data'|'address'|'all') "
2047 "['enable'|'disable'] "
2048 "['enable'|'disable']",
2052 .handler = handle_etm_info_command,
2053 .mode = COMMAND_EXEC,
2055 .help = "display info about the current target's ETM",
2059 .handler = handle_etm_status_command,
2060 .mode = COMMAND_EXEC,
2062 .help = "display current target's ETM status",
2066 .handler = handle_etm_start_command,
2067 .mode = COMMAND_EXEC,
2069 .help = "start ETM trace collection",
2073 .handler = handle_etm_stop_command,
2074 .mode = COMMAND_EXEC,
2076 .help = "stop ETM trace collection",
2079 .name = "trigger_debug",
2080 .handler = handle_etm_trigger_debug_command,
2081 .mode = COMMAND_EXEC,
2082 .help = "enable/disable debug entry on trigger",
2083 .usage = "['enable'|'disable']",
2087 .handler = handle_etm_analyze_command,
2088 .mode = COMMAND_EXEC,
2090 .help = "analyze collected ETM trace",
2094 .handler = handle_etm_image_command,
2095 .mode = COMMAND_EXEC,
2096 .help = "load image from file with optional offset",
2097 .usage = "<file> [base address] [type]",
2101 .handler = handle_etm_dump_command,
2102 .mode = COMMAND_EXEC,
2103 .help = "dump captured trace data to file",
2104 .usage = "filename",
2108 .handler = handle_etm_load_command,
2109 .mode = COMMAND_EXEC,
2111 .help = "load trace data for analysis <file>",
2113 COMMAND_REGISTRATION_DONE
2116 static int etm_register_user_commands(struct command_context *cmd_ctx)
2118 struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2119 return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);