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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm.h"
  25 #include "etm.h"
  26 #include "etb.h"
  27 #include "image.h"
  28 #include "arm_disassembler.h"
  29 #include "register.h"
  30 #include "etm_dummy.h"
  31
  32 #if BUILD_OOCD_TRACE == 1
  33 #include "oocd_trace.h"
  34 #endif
  35
  36
  37 /*
  38  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  39  *
  40  * ETM modules collect instruction and/or data trace information, compress
  41  * it, and transfer it to a debugging host through either a (buffered) trace
  42  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  43  *
  44  * There are several generations of these modules.  Original versions have
  45  * JTAG access through a dedicated scan chain.  Recent versions have added
  46  * access via coprocessor instructions, memory addressing, and the ARM Debug
  47  * Interface v5 (ADIv5); and phased out direct JTAG access.
  48  *
  49  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  50  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  51  * implying non-JTAG connectivity options.
  52  *
  53  * Relevant documentation includes:
  54  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  55  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  56  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  57  */
  58
  59 enum {
  60         RO,                             /* read/only */
  61         WO,                             /* write/only */
  62         RW,                             /* read/write */
  63 };
  64
  65 struct etm_reg_info {
  66         uint8_t addr;
  67         uint8_t size;                   /* low-N of 32 bits */
  68         uint8_t mode;                   /* RO, WO, RW */
  69         uint8_t bcd_vers;               /* 1.0, 2.0, etc */
  70         char *name;
  71 };
  72
  73 /*
  74  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  75  * (Or on some processors, through coprocessor operations.)
  76  * Newer versions of ETM make some W/O registers R/W, and
  77  * provide definitions for some previously-unused bits.
  78  */
  79
  80 /* core registers used to version/configure the ETM */
  81 static const struct etm_reg_info etm_core[] = {
  82         /* NOTE: we "know" the order here ... */
  83         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  84         { ETM_ID, 32, RO, 0x20, "ETM_id", },
  85 };
  86
  87 /* basic registers that are always there given the right ETM version */
  88 static const struct etm_reg_info etm_basic[] = {
  89         /* ETM Trace Registers */
  90         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  91         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  92         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
  93         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
  94         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
  95
  96         /* TraceEnable configuration */
  97         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  98         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  99         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
 100         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
 101
 102         /* ViewData configuration (data trace) */
 103         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
 104         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
 105         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
 106         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
 107
 108         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 109
 110         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
 111         { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
 112         { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
 113         { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
 114         { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
 115 };
 116
 117 static const struct etm_reg_info etm_fifofull[] = {
 118         /* FIFOFULL configuration */
 119         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
 120         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
 121 };
 122
 123 static const struct etm_reg_info etm_addr_comp[] = {
 124         /* Address comparator register pairs */
 125 #define ADDR_COMPARATOR(i) \
 126                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
 127                                 "ETM_addr_" #i "_comparator_value", }, \
 128                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
 129                                 "ETM_addr_" #i "_access_type", }
 130         ADDR_COMPARATOR(1),
 131         ADDR_COMPARATOR(2),
 132         ADDR_COMPARATOR(3),
 133         ADDR_COMPARATOR(4),
 134         ADDR_COMPARATOR(5),
 135         ADDR_COMPARATOR(6),
 136         ADDR_COMPARATOR(7),
 137         ADDR_COMPARATOR(8),
 138
 139         ADDR_COMPARATOR(9),
 140         ADDR_COMPARATOR(10),
 141         ADDR_COMPARATOR(11),
 142         ADDR_COMPARATOR(12),
 143         ADDR_COMPARATOR(13),
 144         ADDR_COMPARATOR(14),
 145         ADDR_COMPARATOR(15),
 146         ADDR_COMPARATOR(16),
 147 #undef ADDR_COMPARATOR
 148 };
 149
 150 static const struct etm_reg_info etm_data_comp[] = {
 151         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 152 #define DATA_COMPARATOR(i) \
 153                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
 154                                 "ETM_data_" #i "_comparator_value", }, \
 155                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
 156                                 "ETM_data_" #i "_comparator_mask", }
 157         DATA_COMPARATOR(1),
 158         DATA_COMPARATOR(2),
 159         DATA_COMPARATOR(3),
 160         DATA_COMPARATOR(4),
 161         DATA_COMPARATOR(5),
 162         DATA_COMPARATOR(6),
 163         DATA_COMPARATOR(7),
 164         DATA_COMPARATOR(8),
 165 #undef DATA_COMPARATOR
 166 };
 167
 168 static const struct etm_reg_info etm_counters[] = {
 169 #define ETM_COUNTER(i) \
 170                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
 171                                 "ETM_counter_" #i "_reload_value", }, \
 172                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
 173                                 "ETM_counter_" #i "_enable", }, \
 174                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
 175                                 "ETM_counter_" #i "_reload_event", }, \
 176                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
 177                                 "ETM_counter_" #i "_value", }
 178         ETM_COUNTER(1),
 179         ETM_COUNTER(2),
 180         ETM_COUNTER(3),
 181         ETM_COUNTER(4),
 182 #undef ETM_COUNTER
 183 };
 184
 185 static const struct etm_reg_info etm_sequencer[] = {
 186 #define ETM_SEQ(i) \
 187                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 188                                 "ETM_sequencer_event" #i, }
 189         ETM_SEQ(0),                             /* 1->2 */
 190         ETM_SEQ(1),                             /* 2->1 */
 191         ETM_SEQ(2),                             /* 2->3 */
 192         ETM_SEQ(3),                             /* 3->1 */
 193         ETM_SEQ(4),                             /* 3->2 */
 194         ETM_SEQ(5),                             /* 1->3 */
 195 #undef ETM_SEQ
 196         /* 0x66 reserved */
 197         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
 198 };
 199
 200 static const struct etm_reg_info etm_outputs[] = {
 201 #define ETM_OUTPUT(i) \
 202                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
 203                                 "ETM_external_output" #i, }
 204
 205         ETM_OUTPUT(1),
 206         ETM_OUTPUT(2),
 207         ETM_OUTPUT(3),
 208         ETM_OUTPUT(4),
 209 #undef ETM_OUTPUT
 210 };
 211
 212 #if 0
 213         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 214
 215         /* Context ID Comparators */
 216         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
 217         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
 218         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
 219         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
 220 #endif
 221
 222 static int etm_get_reg(struct reg *reg);
 223 static int etm_read_reg_w_check(struct reg *reg,
 224         uint8_t *check_value, uint8_t *check_mask);
 225 static int etm_register_user_commands(struct command_context *cmd_ctx);
 226 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
 227 static int etm_write_reg(struct reg *reg, uint32_t value);
 228
 229 static const struct reg_arch_type etm_scan6_type = {
 230         .get = etm_get_reg,
 231         .set = etm_set_reg_w_exec,
 232 };
 233
 234 /* Look up register by ID ... most ETM instances only
 235  * support a subset of the possible registers.
 236  */
 237 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
 238 {
 239         struct reg_cache *cache = etm_ctx->reg_cache;
 240         unsigned i;
 241
 242         for (i = 0; i < cache->num_regs; i++) {
 243                 struct etm_reg *reg = cache->reg_list[i].arch_info;
 244
 245                 if (reg->reg_info->addr == id)
 246                         return &cache->reg_list[i];
 247         }
 248
 249         /* caller asking for nonexistent register is a bug!
 250          * REVISIT say which of the N targets was involved */
 251         LOG_ERROR("ETM: register 0x%02x not available", id);
 252         return NULL;
 253 }
 254
 255 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
 256         struct reg_cache *cache, struct etm_reg *ereg,
 257         const struct etm_reg_info *r, unsigned nreg)
 258 {
 259         struct reg *reg = cache->reg_list;
 260
 261         reg += cache->num_regs;
 262         ereg += cache->num_regs;
 263
 264         /* add up to "nreg" registers from "r", if supported by this
 265          * version of the ETM, to the specified cache.
 266          */
 267         for (; nreg--; r++) {
 268
 269                 /* this ETM may be too old to have some registers */
 270                 if (r->bcd_vers > bcd_vers)
 271                         continue;
 272
 273                 reg->name = r->name;
 274                 reg->size = r->size;
 275                 reg->value = &ereg->value;
 276                 reg->arch_info = ereg;
 277                 reg->type = &etm_scan6_type;
 278                 reg++;
 279                 cache->num_regs++;
 280
 281                 ereg->reg_info = r;
 282                 ereg->jtag_info = jtag_info;
 283                 ereg++;
 284         }
 285 }
 286
 287 struct reg_cache *etm_build_reg_cache(struct target *target,
 288         struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
 289 {
 290         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 291         struct reg *reg_list = NULL;
 292         struct etm_reg *arch_info = NULL;
 293         unsigned bcd_vers, config;
 294
 295         /* the actual registers are kept in two arrays */
 296         reg_list = calloc(128, sizeof(struct reg));
 297         arch_info = calloc(128, sizeof(struct etm_reg));
 298
 299         /* fill in values for the reg cache */
 300         reg_cache->name = "etm registers";
 301         reg_cache->next = NULL;
 302         reg_cache->reg_list = reg_list;
 303         reg_cache->num_regs = 0;
 304
 305         /* add ETM_CONFIG, then parse its values to see
 306          * which other registers exist in this ETM
 307          */
 308         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 309                 etm_core, 1);
 310
 311         etm_get_reg(reg_list);
 312         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 313         config = etm_ctx->config;
 314
 315         /* figure ETM version then add base registers */
 316         if (config & (1 << 31)) {
 317                 LOG_WARNING("ETMv2+ support is incomplete");
 318
 319                 /* REVISIT more registers may exist; they may now be
 320                  * readable; more register bits have defined meanings;
 321                  * don't presume trace start/stop support is present;
 322                  * and include any context ID comparator registers.
 323                  */
 324                 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
 325                         etm_core + 1, 1);
 326                 etm_get_reg(reg_list + 1);
 327                 etm_ctx->id = buf_get_u32(
 328                                 (void *)&arch_info[1].value, 0, 32);
 329                 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
 330                 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
 331
 332         } else {
 333                 switch (config >> 28) {
 334                         case 7:
 335                         case 5:
 336                         case 3:
 337                                 bcd_vers = 0x13;
 338                                 break;
 339                         case 4:
 340                         case 2:
 341                                 bcd_vers = 0x12;
 342                                 break;
 343                         case 1:
 344                                 bcd_vers = 0x11;
 345                                 break;
 346                         case 0:
 347                                 bcd_vers = 0x10;
 348                                 break;
 349                         default:
 350                                 LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 351                                 goto fail;
 352                 }
 353         }
 354         etm_ctx->bcd_vers = bcd_vers;
 355         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 356
 357         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 358                 etm_basic, ARRAY_SIZE(etm_basic));
 359
 360         /* address and data comparators; counters; outputs */
 361         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 362                 etm_addr_comp, 4 * (0x0f & (config >> 0)));
 363         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 364                 etm_data_comp, 2 * (0x0f & (config >> 4)));
 365         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 366                 etm_counters, 4 * (0x07 & (config >> 13)));
 367         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 368                 etm_outputs, (0x07 & (config >> 20)));
 369
 370         /* FIFOFULL presence is optional
 371          * REVISIT for ETMv1.2 and later, don't bother adding this
 372          * unless ETM_SYS_CONFIG says it's also *supported* ...
 373          */
 374         if (config & (1 << 23))
 375                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 376                         etm_fifofull, ARRAY_SIZE(etm_fifofull));
 377
 378         /* sequencer is optional (for state-dependant triggering) */
 379         if (config & (1 << 16))
 380                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 381                         etm_sequencer, ARRAY_SIZE(etm_sequencer));
 382
 383         /* REVISIT could realloc and likely save half the memory
 384          * in the two chunks we allocated...
 385          */
 386
 387         /* the ETM might have an ETB connected */
 388         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0) {
 389                 struct etb *etb = etm_ctx->capture_driver_priv;
 390
 391                 if (!etb) {
 392                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 393                         goto fail;
 394                 }
 395
 396                 reg_cache->next = etb_build_reg_cache(etb);
 397
 398                 etb->reg_cache = reg_cache->next;
 399         }
 400
 401         etm_ctx->reg_cache = reg_cache;
 402         return reg_cache;
 403
 404 fail:
 405         free(reg_cache);
 406         free(reg_list);
 407         free(arch_info);
 408         return NULL;
 409 }
 410
 411 static int etm_read_reg(struct reg *reg)
 412 {
 413         return etm_read_reg_w_check(reg, NULL, NULL);
 414 }
 415
 416 static int etm_store_reg(struct reg *reg)
 417 {
 418         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 419 }
 420
 421 int etm_setup(struct target *target)
 422 {
 423         int retval;
 424         uint32_t etm_ctrl_value;
 425         struct arm *arm = target_to_arm(target);
 426         struct etm_context *etm_ctx = arm->etm;
 427         struct reg *etm_ctrl_reg;
 428
 429         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 430         if (!etm_ctrl_reg)
 431                 return ERROR_OK;
 432
 433         /* initialize some ETM control register settings */
 434         etm_get_reg(etm_ctrl_reg);
 435         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
 436
 437         /* clear the ETM powerdown bit (0) */
 438         etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
 439
 440         /* configure port width (21,6:4), mode (13,17:16) and
 441          * for older modules clocking (13)
 442          */
 443         etm_ctrl_value = (etm_ctrl_value
 444                 & ~ETM_PORT_WIDTH_MASK
 445                 & ~ETM_PORT_MODE_MASK
 446                 & ~ETM_CTRL_DBGRQ
 447                 & ~ETM_PORT_CLOCK_MASK)
 448                 | etm_ctx->control;
 449
 450         buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
 451         etm_store_reg(etm_ctrl_reg);
 452
 453         etm_ctx->control = etm_ctrl_value;
 454
 455         retval = jtag_execute_queue();
 456         if (retval != ERROR_OK)
 457                 return retval;
 458
 459         /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
 460          * verify that those width and mode settings are OK ...
 461          */
 462
 463         retval = etm_ctx->capture_driver->init(etm_ctx);
 464         if (retval != ERROR_OK) {
 465                 LOG_ERROR("ETM capture driver initialization failed");
 466                 return retval;
 467         }
 468         return ERROR_OK;
 469 }
 470
 471 static int etm_get_reg(struct reg *reg)
 472 {
 473         int retval;
 474
 475         retval = etm_read_reg(reg);
 476         if (retval != ERROR_OK) {
 477                 LOG_ERROR("BUG: error scheduling etm register read");
 478                 return retval;
 479         }
 480
 481         retval = jtag_execute_queue();
 482         if (retval != ERROR_OK) {
 483                 LOG_ERROR("register read failed");
 484                 return retval;
 485         }
 486
 487         return ERROR_OK;
 488 }
 489
 490 static int etm_read_reg_w_check(struct reg *reg,
 491         uint8_t *check_value, uint8_t *check_mask)
 492 {
 493         struct etm_reg *etm_reg = reg->arch_info;
 494         const struct etm_reg_info *r = etm_reg->reg_info;
 495         uint8_t reg_addr = r->addr & 0x7f;
 496         struct scan_field fields[3];
 497         int retval;
 498
 499         if (etm_reg->reg_info->mode == WO) {
 500                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 501                 return ERROR_COMMAND_SYNTAX_ERROR;
 502         }
 503
 504         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 505
 506         retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
 507         if (retval != ERROR_OK)
 508                 return retval;
 509         retval = arm_jtag_set_instr(etm_reg->jtag_info,
 510                         etm_reg->jtag_info->intest_instr,
 511                         NULL,
 512                         TAP_IDLE);
 513         if (retval != ERROR_OK)
 514                 return retval;
 515
 516         fields[0].num_bits = 32;
 517         fields[0].out_value = reg->value;
 518         fields[0].in_value = NULL;
 519         fields[0].check_value = NULL;
 520         fields[0].check_mask = NULL;
 521
 522         fields[1].num_bits = 7;
 523         uint8_t temp1;
 524         fields[1].out_value = &temp1;
 525         buf_set_u32(&temp1, 0, 7, reg_addr);
 526         fields[1].in_value = NULL;
 527         fields[1].check_value = NULL;
 528         fields[1].check_mask = NULL;
 529
 530         fields[2].num_bits = 1;
 531         uint8_t temp2;
 532         fields[2].out_value = &temp2;
 533         buf_set_u32(&temp2, 0, 1, 0);
 534         fields[2].in_value = NULL;
 535         fields[2].check_value = NULL;
 536         fields[2].check_mask = NULL;
 537
 538         jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 539
 540         fields[0].in_value = reg->value;
 541         fields[0].check_value = check_value;
 542         fields[0].check_mask = check_mask;
 543
 544         jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 545
 546         return ERROR_OK;
 547 }
 548
 549 static int etm_set_reg(struct reg *reg, uint32_t value)
 550 {
 551         int retval = etm_write_reg(reg, value);
 552         if (retval != ERROR_OK) {
 553                 LOG_ERROR("BUG: error scheduling etm register write");
 554                 return retval;
 555         }
 556
 557         buf_set_u32(reg->value, 0, reg->size, value);
 558         reg->valid = 1;
 559         reg->dirty = 0;
 560
 561         return ERROR_OK;
 562 }
 563
 564 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 565 {
 566         int retval;
 567
 568         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 569
 570         retval = jtag_execute_queue();
 571         if (retval != ERROR_OK) {
 572                 LOG_ERROR("register write failed");
 573                 return retval;
 574         }
 575         return ERROR_OK;
 576 }
 577
 578 static int etm_write_reg(struct reg *reg, uint32_t value)
 579 {
 580         struct etm_reg *etm_reg = reg->arch_info;
 581         const struct etm_reg_info *r = etm_reg->reg_info;
 582         uint8_t reg_addr = r->addr & 0x7f;
 583         struct scan_field fields[3];
 584         int retval;
 585
 586         if (etm_reg->reg_info->mode == RO) {
 587                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 588                 return ERROR_COMMAND_SYNTAX_ERROR;
 589         }
 590
 591         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 592
 593         retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
 594         if (retval != ERROR_OK)
 595                 return retval;
 596         retval = arm_jtag_set_instr(etm_reg->jtag_info,
 597                         etm_reg->jtag_info->intest_instr,
 598                         NULL,
 599                         TAP_IDLE);
 600         if (retval != ERROR_OK)
 601                 return retval;
 602
 603         fields[0].num_bits = 32;
 604         uint8_t tmp1[4];
 605         fields[0].out_value = tmp1;
 606         buf_set_u32(tmp1, 0, 32, value);
 607         fields[0].in_value = NULL;
 608
 609         fields[1].num_bits = 7;
 610         uint8_t tmp2;
 611         fields[1].out_value = &tmp2;
 612         buf_set_u32(&tmp2, 0, 7, reg_addr);
 613         fields[1].in_value = NULL;
 614
 615         fields[2].num_bits = 1;
 616         uint8_t tmp3;
 617         fields[2].out_value = &tmp3;
 618         buf_set_u32(&tmp3, 0, 1, 1);
 619         fields[2].in_value = NULL;
 620
 621         jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 622
 623         return ERROR_OK;
 624 }
 625
 626
 627 /* ETM trace analysis functionality */
 628
 629 static struct etm_capture_driver *etm_capture_drivers[] = {
 630         &etb_capture_driver,
 631         &etm_dummy_capture_driver,
 632 #if BUILD_OOCD_TRACE == 1
 633         &oocd_trace_capture_driver,
 634 #endif
 635         NULL
 636 };
 637
 638 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
 639 {
 640         int i;
 641         int section = -1;
 642         size_t size_read;
 643         uint32_t opcode;
 644         int retval;
 645
 646         if (!ctx->image)
 647                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 648
 649         /* search for the section the current instruction belongs to */
 650         for (i = 0; i < ctx->image->num_sections; i++) {
 651                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 652                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size >
 653                         ctx->current_pc)) {
 654                         section = i;
 655                         break;
 656                 }
 657         }
 658
 659         if (section == -1) {
 660                 /* current instruction couldn't be found in the image */
 661                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 662         }
 663
 664         if (ctx->core_state == ARM_STATE_ARM) {
 665                 uint8_t buf[4];
 666                 retval = image_read_section(ctx->image, section,
 667                                 ctx->current_pc -
 668                                 ctx->image->sections[section].base_address,
 669                                 4, buf, &size_read);
 670                 if (retval != ERROR_OK) {
 671                         LOG_ERROR("error while reading instruction");
 672                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 673                 }
 674                 opcode = target_buffer_get_u32(ctx->target, buf);
 675                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 676         } else if (ctx->core_state == ARM_STATE_THUMB) {
 677                 uint8_t buf[2];
 678                 retval = image_read_section(ctx->image, section,
 679                                 ctx->current_pc -
 680                                 ctx->image->sections[section].base_address,
 681                                 2, buf, &size_read);
 682                 if (retval != ERROR_OK) {
 683                         LOG_ERROR("error while reading instruction");
 684                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 685                 }
 686                 opcode = target_buffer_get_u16(ctx->target, buf);
 687                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 688         } else if (ctx->core_state == ARM_STATE_JAZELLE) {
 689                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 690                 return ERROR_FAIL;
 691         } else {
 692                 LOG_ERROR("BUG: unknown core state encountered");
 693                 return ERROR_FAIL;
 694         }
 695
 696         return ERROR_OK;
 697 }
 698
 699 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
 700 {
 701         while (ctx->data_index < ctx->trace_depth) {
 702                 /* if the caller specified an address packet offset, skip until the
 703                  * we reach the n-th cycle marked with tracesync */
 704                 if (apo > 0) {
 705                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 706                                 apo--;
 707
 708                         if (apo > 0) {
 709                                 ctx->data_index++;
 710                                 ctx->data_half = 0;
 711                         }
 712                         continue;
 713                 }
 714
 715                 /* no tracedata output during a TD cycle
 716                  * or in a trigger cycle */
 717                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 718                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE)) {
 719                         ctx->data_index++;
 720                         ctx->data_half = 0;
 721                         continue;
 722                 }
 723
 724                 /* FIXME there are more port widths than these... */
 725                 if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT) {
 726                         if (ctx->data_half == 0) {
 727                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 728                                 ctx->data_half = 1;
 729                         } else {
 730                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 731                                 ctx->data_half = 0;
 732                                 ctx->data_index++;
 733                         }
 734                 } else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) {
 735                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 736                         ctx->data_index++;
 737                 } else {
 738                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 739                         if (ctx->data_index > (ctx->trace_depth - 2))
 740                                 return -1;
 741
 742                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 743                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 744                         ctx->data_index += 2;
 745                 }
 746
 747                 return 0;
 748         }
 749
 750         return -1;
 751 }
 752
 753 static int etmv1_branch_address(struct etm_context *ctx)
 754 {
 755         int retval;
 756         uint8_t packet;
 757         int shift = 0;
 758         int apo;
 759         uint32_t i;
 760
 761         /* quit analysis if less than two cycles are left in the trace
 762          * because we can't extract the APO */
 763         if (ctx->data_index > (ctx->trace_depth - 2))
 764                 return -1;
 765
 766         /* a BE could be output during an APO cycle, skip the current
 767          * and continue with the new one */
 768         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 769                 return 1;
 770         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 771                 return 2;
 772
 773         /* address packet offset encoded in the next two cycles' pipestat bits */
 774         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 775         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 776
 777         /* count number of tracesync cycles between current pipe_index and data_index
 778          * i.e. the number of tracesyncs that data_index already passed by
 779          * to subtract them from the APO */
 780         for (i = ctx->pipe_index; i < ctx->data_index; i++) {
 781                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 782                         apo--;
 783         }
 784
 785         /* extract up to four 7-bit packets */
 786         do {
 787                 retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0);
 788                 if (retval != 0)
 789                         return -1;
 790                 ctx->last_branch &= ~(0x7f << shift);
 791                 ctx->last_branch |= (packet & 0x7f) << shift;
 792                 shift += 7;
 793         } while ((packet & 0x80) && (shift < 28));
 794
 795         /* one last packet holding 4 bits of the address, plus the branch reason code */
 796         if ((shift == 28) && (packet & 0x80)) {
 797                 retval = etmv1_next_packet(ctx, &packet, 0);
 798                 if (retval != 0)
 799                         return -1;
 800                 ctx->last_branch &= 0x0fffffff;
 801                 ctx->last_branch |= (packet & 0x0f) << 28;
 802                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 803                 shift += 4;
 804         } else
 805                 ctx->last_branch_reason = 0;
 806
 807         if (shift == 32)
 808                 ctx->pc_ok = 1;
 809
 810         /* if a full address was output, we might have branched into Jazelle state */
 811         if ((shift == 32) && (packet & 0x80))
 812                 ctx->core_state = ARM_STATE_JAZELLE;
 813         else {
 814                 /* if we didn't branch into Jazelle state, the current processor state is
 815                  * encoded in bit 0 of the branch target address */
 816                 if (ctx->last_branch & 0x1) {
 817                         ctx->core_state = ARM_STATE_THUMB;
 818                         ctx->last_branch &= ~0x1;
 819                 } else {
 820                         ctx->core_state = ARM_STATE_ARM;
 821                         ctx->last_branch &= ~0x3;
 822                 }
 823         }
 824
 825         return 0;
 826 }
 827
 828 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
 829 {
 830         int j;
 831         uint8_t buf[4];
 832         int retval;
 833
 834         for (j = 0; j < size; j++) {
 835                 retval = etmv1_next_packet(ctx, &buf[j], 0);
 836                 if (retval != 0)
 837                         return -1;
 838         }
 839
 840         if (size == 8) {
 841                 LOG_ERROR("TODO: add support for 64-bit values");
 842                 return -1;
 843         } else if (size == 4)
 844                 *data = target_buffer_get_u32(ctx->target, buf);
 845         else if (size == 2)
 846                 *data = target_buffer_get_u16(ctx->target, buf);
 847         else if (size == 1)
 848                 *data = buf[0];
 849         else
 850                 return -1;
 851
 852         return 0;
 853 }
 854
 855 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
 856 {
 857         int retval;
 858         struct arm_instruction instruction;
 859
 860         /* read the trace data if it wasn't read already */
 861         if (ctx->trace_depth == 0)
 862                 ctx->capture_driver->read_trace(ctx);
 863
 864         if (ctx->trace_depth == 0) {
 865                 command_print(cmd_ctx, "Trace is empty.");
 866                 return ERROR_OK;
 867         }
 868
 869         /* start at the beginning of the captured trace */
 870         ctx->pipe_index = 0;
 871         ctx->data_index = 0;
 872         ctx->data_half = 0;
 873
 874         /* neither the PC nor the data pointer are valid */
 875         ctx->pc_ok = 0;
 876         ctx->ptr_ok = 0;
 877
 878         while (ctx->pipe_index < ctx->trace_depth) {
 879                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 880                 uint32_t next_pc = ctx->current_pc;
 881                 uint32_t old_data_index = ctx->data_index;
 882                 uint32_t old_data_half = ctx->data_half;
 883                 uint32_t old_index = ctx->pipe_index;
 884                 uint32_t last_instruction = ctx->last_instruction;
 885                 uint32_t cycles = 0;
 886                 int current_pc_ok = ctx->pc_ok;
 887
 888                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 889                         command_print(cmd_ctx, "--- trigger ---");
 890
 891                 /* instructions execute in IE/D or BE/D cycles */
 892                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 893                         ctx->last_instruction = ctx->pipe_index;
 894
 895                 /* if we don't have a valid pc skip until we reach an indirect branch */
 896                 if ((!ctx->pc_ok) && (pipestat != STAT_BE)) {
 897                         ctx->pipe_index++;
 898                         continue;
 899                 }
 900
 901                 /* any indirect branch could have interrupted instruction flow
 902                  * - the branch reason code could indicate a trace discontinuity
 903                  * - a branch to the exception vectors indicates an exception
 904                  */
 905                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD)) {
 906                         /* backup current data index, to be able to consume the branch address
 907                          * before examining data address and values
 908                          */
 909                         old_data_index = ctx->data_index;
 910                         old_data_half = ctx->data_half;
 911
 912                         ctx->last_instruction = ctx->pipe_index;
 913
 914                         retval = etmv1_branch_address(ctx);
 915                         if (retval != 0) {
 916                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 917                                  * quit analysing the trace */
 918                                 if (retval < 0)
 919                                         break;
 920
 921                                 /* a positive return values means the current branch was abandoned,
 922                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 923                                  */
 924                                 LOG_WARNING(
 925                                         "abandoned branch encountered, correctnes of analysis uncertain");
 926                                 ctx->pipe_index += retval;
 927                                 continue;
 928                         }
 929
 930                         /* skip over APO cycles */
 931                         ctx->pipe_index += 2;
 932
 933                         switch (ctx->last_branch_reason) {
 934                                 case 0x0:       /* normal PC change */
 935                                         next_pc = ctx->last_branch;
 936                                         break;
 937                                 case 0x1:       /* tracing enabled */
 938                                         command_print(cmd_ctx,
 939                                                 "--- tracing enabled at 0x%8.8" PRIx32 " ---",
 940                                                 ctx->last_branch);
 941                                         ctx->current_pc = ctx->last_branch;
 942                                         ctx->pipe_index++;
 943                                         continue;
 944                                         break;
 945                                 case 0x2:       /* trace restarted after FIFO overflow */
 946                                         command_print(cmd_ctx,
 947                                                 "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---",
 948                                                 ctx->last_branch);
 949                                         ctx->current_pc = ctx->last_branch;
 950                                         ctx->pipe_index++;
 951                                         continue;
 952                                         break;
 953                                 case 0x3:       /* exit from debug state */
 954                                         command_print(cmd_ctx,
 955                                                 "--- exit from debug state at 0x%8.8" PRIx32 " ---",
 956                                                 ctx->last_branch);
 957                                         ctx->current_pc = ctx->last_branch;
 958                                         ctx->pipe_index++;
 959                                         continue;
 960                                         break;
 961                                 case 0x4:       /* periodic synchronization point */
 962                                         next_pc = ctx->last_branch;
 963                                         /* if we had no valid PC prior to this synchronization point,
 964                                          * we have to move on with the next trace cycle
 965                                          */
 966                                         if (!current_pc_ok) {
 967                                                 command_print(cmd_ctx,
 968                                                         "--- periodic synchronization point at 0x%8.8" PRIx32 " ---",
 969                                                         next_pc);
 970                                                 ctx->current_pc = next_pc;
 971                                                 ctx->pipe_index++;
 972                                                 continue;
 973                                         }
 974                                         break;
 975                                 default:        /* reserved */
 976                                         LOG_ERROR(
 977                                                 "BUG: branch reason code 0x%" PRIx32 " is reserved",
 978                                                 ctx->last_branch_reason);
 979                                         return ERROR_FAIL;
 980                         }
 981
 982                         /* if we got here the branch was a normal PC change
 983                          * (or a periodic synchronization point, which means the same for that matter)
 984                          * if we didn't accquire a complete PC continue with the next cycle
 985                          */
 986                         if (!ctx->pc_ok)
 987                                 continue;
 988
 989                         /* indirect branch to the exception vector means an exception occured */
 990                         if ((ctx->last_branch <= 0x20)
 991                                 || ((ctx->last_branch >= 0xffff0000) &&
 992                                 (ctx->last_branch <= 0xffff0020))) {
 993                                 if ((ctx->last_branch & 0xff) == 0x10)
 994                                         command_print(cmd_ctx, "data abort");
 995                                 else {
 996                                         command_print(cmd_ctx,
 997                                                 "exception vector 0x%2.2" PRIx32 "",
 998                                                 ctx->last_branch);
 999                                         ctx->current_pc = ctx->last_branch;
1000                                         ctx->pipe_index++;
1001                                         continue;
1002                                 }
1003                         }
1004                 }
1005
1006                 /* an instruction was executed (or not, depending on the condition flags)
1007                  * retrieve it from the image for displaying */
1008                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1009                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1010                         ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4)))) {
1011                         retval = etm_read_instruction(ctx, &instruction);
1012                         if (retval != ERROR_OK) {
1013                                 /* can't continue tracing with no image available */
1014                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1015                                         return retval;
1016                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE) {
1017                                         /* TODO: handle incomplete images
1018                                          * for now we just quit the analsysis*/
1019                                         return retval;
1020                                 }
1021                         }
1022
1023                         cycles = old_index - last_instruction;
1024                 }
1025
1026                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD)) {
1027                         uint32_t new_data_index = ctx->data_index;
1028                         uint32_t new_data_half = ctx->data_half;
1029
1030                         /* in case of a branch with data, the branch target address was consumed before
1031                          * we temporarily go back to the saved data index */
1032                         if (pipestat == STAT_BD) {
1033                                 ctx->data_index = old_data_index;
1034                                 ctx->data_half = old_data_half;
1035                         }
1036
1037                         if (ctx->control & ETM_CTRL_TRACE_ADDR) {
1038                                 uint8_t packet;
1039                                 int shift = 0;
1040
1041                                 do {
1042                                         retval = etmv1_next_packet(ctx, &packet, 0);
1043                                         if (retval != 0)
1044                                                 return ERROR_ETM_ANALYSIS_FAILED;
1045                                         ctx->last_ptr &= ~(0x7f << shift);
1046                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1047                                         shift += 7;
1048                                 } while ((packet & 0x80) && (shift < 32));
1049
1050                                 if (shift >= 32)
1051                                         ctx->ptr_ok = 1;
1052
1053                                 if (ctx->ptr_ok)
1054                                         command_print(cmd_ctx,
1055                                                 "address: 0x%8.8" PRIx32 "",
1056                                                 ctx->last_ptr);
1057                         }
1058
1059                         if (ctx->control & ETM_CTRL_TRACE_DATA) {
1060                                 if ((instruction.type == ARM_LDM) ||
1061                                         (instruction.type == ARM_STM)) {
1062                                         int i;
1063                                         for (i = 0; i < 16; i++) {
1064                                                 if (instruction.info.load_store_multiple.
1065                                                         register_list & (1 << i)) {
1066                                                         uint32_t data;
1067                                                         if (etmv1_data(ctx, 4, &data) != 0)
1068                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1069                                                         command_print(cmd_ctx,
1070                                                                 "data: 0x%8.8" PRIx32 "",
1071                                                                 data);
1072                                                 }
1073                                         }
1074                                 } else if ((instruction.type >= ARM_LDR) &&
1075                                         (instruction.type <= ARM_STRH)) {
1076                                         uint32_t data;
1077                                         if (etmv1_data(ctx, arm_access_size(&instruction),
1078                                                 &data) != 0)
1079                                                 return ERROR_ETM_ANALYSIS_FAILED;
1080                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1081                                 }
1082                         }
1083
1084                         /* restore data index after consuming BD address and data */
1085                         if (pipestat == STAT_BD) {
1086                                 ctx->data_index = new_data_index;
1087                                 ctx->data_half = new_data_half;
1088                         }
1089                 }
1090
1091                 /* adjust PC */
1092                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID)) {
1093                         if (((instruction.type == ARM_B) ||
1094                                 (instruction.type == ARM_BL) ||
1095                                 (instruction.type == ARM_BLX)) &&
1096                                 (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1097                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1098                         else
1099                                 next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1100                 } else if (pipestat == STAT_IN)
1101                         next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2;
1102
1103                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT)) {
1104                         char cycles_text[32] = "";
1105
1106                         /* if the trace was captured with cycle accurate tracing enabled,
1107                          * output the number of cycles since the last executed instruction
1108                          */
1109                         if (ctx->control & ETM_CTRL_CYCLE_ACCURATE) {
1110                                 snprintf(cycles_text, 32, " (%i %s)",
1111                                         (int)cycles,
1112                                         (cycles == 1) ? "cycle" : "cycles");
1113                         }
1114
1115                         command_print(cmd_ctx, "%s%s%s",
1116                                 instruction.text,
1117                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1118                                 cycles_text);
1119
1120                         ctx->current_pc = next_pc;
1121
1122                         /* packets for an instruction don't start on or before the preceding
1123                          * functional pipestat (i.e. other than WT or TD)
1124                          */
1125                         if (ctx->data_index <= ctx->pipe_index) {
1126                                 ctx->data_index = ctx->pipe_index + 1;
1127                                 ctx->data_half = 0;
1128                         }
1129                 }
1130
1131                 ctx->pipe_index += 1;
1132         }
1133
1134         return ERROR_OK;
1135 }
1136
1137 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1138         uint32_t *mode)
1139 {
1140         uint32_t tracemode;
1141
1142         /* what parts of data access are traced? */
1143         if (strcmp(CMD_ARGV[0], "none") == 0)
1144                 tracemode = 0;
1145         else if (strcmp(CMD_ARGV[0], "data") == 0)
1146                 tracemode = ETM_CTRL_TRACE_DATA;
1147         else if (strcmp(CMD_ARGV[0], "address") == 0)
1148                 tracemode = ETM_CTRL_TRACE_ADDR;
1149         else if (strcmp(CMD_ARGV[0], "all") == 0)
1150                 tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
1151         else {
1152                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1153                 return ERROR_COMMAND_SYNTAX_ERROR;
1154         }
1155
1156         uint8_t context_id;
1157         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1158         switch (context_id) {
1159                 case 0:
1160                         tracemode |= ETM_CTRL_CONTEXTID_NONE;
1161                         break;
1162                 case 8:
1163                         tracemode |= ETM_CTRL_CONTEXTID_8;
1164                         break;
1165                 case 16:
1166                         tracemode |= ETM_CTRL_CONTEXTID_16;
1167                         break;
1168                 case 32:
1169                         tracemode |= ETM_CTRL_CONTEXTID_32;
1170                         break;
1171                 default:
1172                         command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1173                         return ERROR_COMMAND_SYNTAX_ERROR;
1174         }
1175
1176         bool etmv1_cycle_accurate;
1177         COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
1178         if (etmv1_cycle_accurate)
1179                 tracemode |= ETM_CTRL_CYCLE_ACCURATE;
1180
1181         bool etmv1_branch_output;
1182         COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
1183         if (etmv1_branch_output)
1184                 tracemode |= ETM_CTRL_BRANCH_OUTPUT;
1185
1186         /* IGNORED:
1187          *  - CPRT tracing (coprocessor register transfers)
1188          *  - debug request (causes debug entry on trigger)
1189          *  - stall on FIFOFULL (preventing tracedata lossage)
1190          */
1191         *mode = tracemode;
1192
1193         return ERROR_OK;
1194 }
1195
1196 COMMAND_HANDLER(handle_etm_tracemode_command)
1197 {
1198         struct target *target = get_current_target(CMD_CTX);
1199         struct arm *arm = target_to_arm(target);
1200         struct etm_context *etm;
1201
1202         if (!is_arm(arm)) {
1203                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1204                 return ERROR_FAIL;
1205         }
1206
1207         etm = arm->etm;
1208         if (!etm) {
1209                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1210                 return ERROR_FAIL;
1211         }
1212
1213         uint32_t tracemode = etm->control;
1214
1215         switch (CMD_ARGC) {
1216                 case 0:
1217                         break;
1218                 case 4:
1219                         CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update,
1220                                 &tracemode);
1221                         break;
1222                 default:
1223                         return ERROR_COMMAND_SYNTAX_ERROR;
1224         }
1225
1226         /**
1227          * todo: fail if parameters were invalid for this hardware,
1228          * or couldn't be written; display actual hardware state...
1229          */
1230
1231         command_print(CMD_CTX, "current tracemode configuration:");
1232
1233         switch (tracemode & ETM_CTRL_TRACE_MASK) {
1234                 default:
1235                         command_print(CMD_CTX, "data tracing: none");
1236                         break;
1237                 case ETM_CTRL_TRACE_DATA:
1238                         command_print(CMD_CTX, "data tracing: data only");
1239                         break;
1240                 case ETM_CTRL_TRACE_ADDR:
1241                         command_print(CMD_CTX, "data tracing: address only");
1242                         break;
1243                 case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
1244                         command_print(CMD_CTX, "data tracing: address and data");
1245                         break;
1246         }
1247
1248         switch (tracemode & ETM_CTRL_CONTEXTID_MASK) {
1249                 case ETM_CTRL_CONTEXTID_NONE:
1250                         command_print(CMD_CTX, "contextid tracing: none");
1251                         break;
1252                 case ETM_CTRL_CONTEXTID_8:
1253                         command_print(CMD_CTX, "contextid tracing: 8 bit");
1254                         break;
1255                 case ETM_CTRL_CONTEXTID_16:
1256                         command_print(CMD_CTX, "contextid tracing: 16 bit");
1257                         break;
1258                 case ETM_CTRL_CONTEXTID_32:
1259                         command_print(CMD_CTX, "contextid tracing: 32 bit");
1260                         break;
1261         }
1262
1263         if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
1264                 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1265         else
1266                 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1267
1268         if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
1269                 command_print(CMD_CTX, "full branch address output enabled");
1270         else
1271                 command_print(CMD_CTX, "full branch address output disabled");
1272
1273 #define TRACEMODE_MASK ( \
1274                 ETM_CTRL_CONTEXTID_MASK \
1275                 | ETM_CTRL_BRANCH_OUTPUT \
1276                 | ETM_CTRL_CYCLE_ACCURATE \
1277                 | ETM_CTRL_TRACE_MASK \
1278                 )
1279
1280         /* only update ETM_CTRL register if tracemode changed */
1281         if ((etm->control & TRACEMODE_MASK) != tracemode) {
1282                 struct reg *etm_ctrl_reg;
1283
1284                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1285                 if (!etm_ctrl_reg)
1286                         return ERROR_FAIL;
1287
1288                 etm->control &= ~TRACEMODE_MASK;
1289                 etm->control |= tracemode & TRACEMODE_MASK;
1290
1291                 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1292                 etm_store_reg(etm_ctrl_reg);
1293
1294                 /* invalidate old trace data */
1295                 etm->capture_status = TRACE_IDLE;
1296                 if (etm->trace_depth > 0) {
1297                         free(etm->trace_data);
1298                         etm->trace_data = NULL;
1299                 }
1300                 etm->trace_depth = 0;
1301         }
1302
1303 #undef TRACEMODE_MASK
1304
1305         return ERROR_OK;
1306 }
1307
1308 COMMAND_HANDLER(handle_etm_config_command)
1309 {
1310         struct target *target;
1311         struct arm *arm;
1312         uint32_t portmode = 0x0;
1313         struct etm_context *etm_ctx;
1314         int i;
1315
1316         if (CMD_ARGC != 5)
1317                 return ERROR_COMMAND_SYNTAX_ERROR;
1318
1319         target = get_target(CMD_ARGV[0]);
1320         if (!target) {
1321                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1322                 return ERROR_FAIL;
1323         }
1324
1325         arm = target_to_arm(target);
1326         if (!is_arm(arm)) {
1327                 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1328                         target_name(target),
1329                         target_type_name(target));
1330                 return ERROR_FAIL;
1331         }
1332
1333         /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1334          * version we'll be using!! -- so we can't know how to validate
1335          * params yet.  "etm config" should likely be *AFTER* hookup...
1336          *
1337          *  - Many more widths might be supported ... and we can easily
1338          *    check whether our setting "took".
1339          *
1340          *  - The "clock" and "mode" bits are interpreted differently.
1341          *    See ARM IHI 0014O table 2-17 for the old behavior, and
1342          *    table 2-18 for the new.  With ETB it's best to specify
1343          *    "normal full" ...
1344          */
1345         uint8_t port_width;
1346         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1347         switch (port_width) {
1348                 /* before ETMv3.0 */
1349                 case 4:
1350                         portmode |= ETM_PORT_4BIT;
1351                         break;
1352                 case 8:
1353                         portmode |= ETM_PORT_8BIT;
1354                         break;
1355                 case 16:
1356                         portmode |= ETM_PORT_16BIT;
1357                         break;
1358                 /* ETMv3.0 and later*/
1359                 case 24:
1360                         portmode |= ETM_PORT_24BIT;
1361                         break;
1362                 case 32:
1363                         portmode |= ETM_PORT_32BIT;
1364                         break;
1365                 case 48:
1366                         portmode |= ETM_PORT_48BIT;
1367                         break;
1368                 case 64:
1369                         portmode |= ETM_PORT_64BIT;
1370                         break;
1371                 case 1:
1372                         portmode |= ETM_PORT_1BIT;
1373                         break;
1374                 case 2:
1375                         portmode |= ETM_PORT_2BIT;
1376                         break;
1377                 default:
1378                         command_print(CMD_CTX,
1379                                 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1380                         return ERROR_FAIL;
1381         }
1382
1383         if (strcmp("normal", CMD_ARGV[2]) == 0)
1384                 portmode |= ETM_PORT_NORMAL;
1385         else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1386                 portmode |= ETM_PORT_MUXED;
1387         else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1388                 portmode |= ETM_PORT_DEMUXED;
1389         else {
1390                 command_print(CMD_CTX,
1391                         "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'",
1392                         CMD_ARGV[2]);
1393                 return ERROR_FAIL;
1394         }
1395
1396         if (strcmp("half", CMD_ARGV[3]) == 0)
1397                 portmode |= ETM_PORT_HALF_CLOCK;
1398         else if (strcmp("full", CMD_ARGV[3]) == 0)
1399                 portmode |= ETM_PORT_FULL_CLOCK;
1400         else {
1401                 command_print(CMD_CTX,
1402                         "unsupported ETM port clocking '%s', must be 'full' or 'half'",
1403                         CMD_ARGV[3]);
1404                 return ERROR_FAIL;
1405         }
1406
1407         etm_ctx = calloc(1, sizeof(struct etm_context));
1408         if (!etm_ctx) {
1409                 LOG_DEBUG("out of memory");
1410                 return ERROR_FAIL;
1411         }
1412
1413         for (i = 0; etm_capture_drivers[i]; i++) {
1414                 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0) {
1415                         int retval = register_commands(CMD_CTX, NULL,
1416                                         etm_capture_drivers[i]->commands);
1417                         if (ERROR_OK != retval) {
1418                                 free(etm_ctx);
1419                                 return retval;
1420                         }
1421
1422                         etm_ctx->capture_driver = etm_capture_drivers[i];
1423
1424                         break;
1425                 }
1426         }
1427
1428         if (!etm_capture_drivers[i]) {
1429                 /* no supported capture driver found, don't register an ETM */
1430                 free(etm_ctx);
1431                 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1432                 return ERROR_FAIL;
1433         }
1434
1435         etm_ctx->target = target;
1436         etm_ctx->trace_data = NULL;
1437         etm_ctx->control = portmode;
1438         etm_ctx->core_state = ARM_STATE_ARM;
1439
1440         arm->etm = etm_ctx;
1441
1442         return etm_register_user_commands(CMD_CTX);
1443 }
1444
1445 COMMAND_HANDLER(handle_etm_info_command)
1446 {
1447         struct target *target;
1448         struct arm *arm;
1449         struct etm_context *etm;
1450         struct reg *etm_sys_config_reg;
1451         int max_port_size;
1452         uint32_t config;
1453
1454         target = get_current_target(CMD_CTX);
1455         arm = target_to_arm(target);
1456         if (!is_arm(arm)) {
1457                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1458                 return ERROR_FAIL;
1459         }
1460
1461         etm = arm->etm;
1462         if (!etm) {
1463                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1464                 return ERROR_FAIL;
1465         }
1466
1467         command_print(CMD_CTX, "ETM v%d.%d",
1468                 etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1469         command_print(CMD_CTX, "pairs of address comparators: %i",
1470                 (int) (etm->config >> 0) & 0x0f);
1471         command_print(CMD_CTX, "data comparators: %i",
1472                 (int) (etm->config >> 4) & 0x0f);
1473         command_print(CMD_CTX, "memory map decoders: %i",
1474                 (int) (etm->config >> 8) & 0x1f);
1475         command_print(CMD_CTX, "number of counters: %i",
1476                 (int) (etm->config >> 13) & 0x07);
1477         command_print(CMD_CTX, "sequencer %spresent",
1478                 (int) (etm->config & (1 << 16)) ? "" : "not ");
1479         command_print(CMD_CTX, "number of ext. inputs: %i",
1480                 (int) (etm->config >> 17) & 0x07);
1481         command_print(CMD_CTX, "number of ext. outputs: %i",
1482                 (int) (etm->config >> 20) & 0x07);
1483         command_print(CMD_CTX, "FIFO full %spresent",
1484                 (int) (etm->config & (1 << 23)) ? "" : "not ");
1485         if (etm->bcd_vers < 0x20)
1486                 command_print(CMD_CTX, "protocol version: %i",
1487                         (int) (etm->config >> 28) & 0x07);
1488         else {
1489                 command_print(CMD_CTX,
1490                         "coprocessor and memory access %ssupported",
1491                         (etm->config & (1 << 26)) ? "" : "not ");
1492                 command_print(CMD_CTX, "trace start/stop %spresent",
1493                         (etm->config & (1 << 26)) ? "" : "not ");
1494                 command_print(CMD_CTX, "number of context comparators: %i",
1495                         (int) (etm->config >> 24) & 0x03);
1496         }
1497
1498         /* SYS_CONFIG isn't present before ETMv1.2 */
1499         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1500         if (!etm_sys_config_reg)
1501                 return ERROR_OK;
1502
1503         etm_get_reg(etm_sys_config_reg);
1504         config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1505
1506         LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1507
1508         max_port_size = config & 0x7;
1509         if (etm->bcd_vers >= 0x30)
1510                 max_port_size |= (config >> 6) & 0x08;
1511         switch (max_port_size) {
1512                 /* before ETMv3.0 */
1513                 case 0:
1514                         max_port_size = 4;
1515                         break;
1516                 case 1:
1517                         max_port_size = 8;
1518                         break;
1519                 case 2:
1520                         max_port_size = 16;
1521                         break;
1522                 /* ETMv3.0 and later*/
1523                 case 3:
1524                         max_port_size = 24;
1525                         break;
1526                 case 4:
1527                         max_port_size = 32;
1528                         break;
1529                 case 5:
1530                         max_port_size = 48;
1531                         break;
1532                 case 6:
1533                         max_port_size = 64;
1534                         break;
1535                 case 8:
1536                         max_port_size = 1;
1537                         break;
1538                 case 9:
1539                         max_port_size = 2;
1540                         break;
1541                 default:
1542                         LOG_ERROR("Illegal max_port_size");
1543                         return ERROR_FAIL;
1544         }
1545         command_print(CMD_CTX, "max. port size: %i", max_port_size);
1546
1547         if (etm->bcd_vers < 0x30) {
1548                 command_print(CMD_CTX, "half-rate clocking %ssupported",
1549                         (config & (1 << 3)) ? "" : "not ");
1550                 command_print(CMD_CTX, "full-rate clocking %ssupported",
1551                         (config & (1 << 4)) ? "" : "not ");
1552                 command_print(CMD_CTX, "normal trace format %ssupported",
1553                         (config & (1 << 5)) ? "" : "not ");
1554                 command_print(CMD_CTX, "multiplex trace format %ssupported",
1555                         (config & (1 << 6)) ? "" : "not ");
1556                 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1557                         (config & (1 << 7)) ? "" : "not ");
1558         } else {
1559                 /* REVISIT show which size and format are selected ... */
1560                 command_print(CMD_CTX, "current port size %ssupported",
1561                         (config & (1 << 10)) ? "" : "not ");
1562                 command_print(CMD_CTX, "current trace format %ssupported",
1563                         (config & (1 << 11)) ? "" : "not ");
1564         }
1565         if (etm->bcd_vers >= 0x21)
1566                 command_print(CMD_CTX, "fetch comparisons %ssupported",
1567                         (config & (1 << 17)) ? "not " : "");
1568         command_print(CMD_CTX, "FIFO full %ssupported",
1569                 (config & (1 << 8)) ? "" : "not ");
1570
1571         return ERROR_OK;
1572 }
1573
1574 COMMAND_HANDLER(handle_etm_status_command)
1575 {
1576         struct target *target;
1577         struct arm *arm;
1578         struct etm_context *etm;
1579         trace_status_t trace_status;
1580
1581         target = get_current_target(CMD_CTX);
1582         arm = target_to_arm(target);
1583         if (!is_arm(arm)) {
1584                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1585                 return ERROR_FAIL;
1586         }
1587
1588         etm = arm->etm;
1589         if (!etm) {
1590                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1591                 return ERROR_FAIL;
1592         }
1593
1594         /* ETM status */
1595         if (etm->bcd_vers >= 0x11) {
1596                 struct reg *reg;
1597
1598                 reg = etm_reg_lookup(etm, ETM_STATUS);
1599                 if (!reg)
1600                         return ERROR_FAIL;
1601                 if (etm_get_reg(reg) == ERROR_OK) {
1602                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1603
1604                         command_print(CMD_CTX, "etm: %s%s%s%s",
1605                                 /* bit(1) == progbit */
1606                                 (etm->bcd_vers >= 0x12)
1607                                 ? ((s & (1 << 1))
1608                                 ? "disabled" : "enabled")
1609                                 : "?",
1610                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1611                                 ? " triggered" : "",
1612                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1613                                 ? " start/stop" : "",
1614                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1615                                 ? " untraced-overflow" : "");
1616                 }       /* else ignore and try showing trace port status */
1617         }
1618
1619         /* Trace Port Driver status */
1620         trace_status = etm->capture_driver->status(etm);
1621         if (trace_status == TRACE_IDLE)
1622                 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1623         else {
1624                 static char *completed = " completed";
1625                 static char *running = " is running";
1626                 static char *overflowed = ", overflowed";
1627                 static char *triggered = ", triggered";
1628
1629                 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1630                         etm->capture_driver->name,
1631                         (trace_status & TRACE_RUNNING) ? running : completed,
1632                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1633                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1634
1635                 if (etm->trace_depth > 0) {
1636                         command_print(CMD_CTX, "%i frames of trace data read",
1637                                 (int)(etm->trace_depth));
1638                 }
1639         }
1640
1641         return ERROR_OK;
1642 }
1643
1644 COMMAND_HANDLER(handle_etm_image_command)
1645 {
1646         struct target *target;
1647         struct arm *arm;
1648         struct etm_context *etm_ctx;
1649
1650         if (CMD_ARGC < 1)
1651                 return ERROR_COMMAND_SYNTAX_ERROR;
1652
1653         target = get_current_target(CMD_CTX);
1654         arm = target_to_arm(target);
1655         if (!is_arm(arm)) {
1656                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1657                 return ERROR_FAIL;
1658         }
1659
1660         etm_ctx = arm->etm;
1661         if (!etm_ctx) {
1662                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1663                 return ERROR_FAIL;
1664         }
1665
1666         if (etm_ctx->image) {
1667                 image_close(etm_ctx->image);
1668                 free(etm_ctx->image);
1669                 command_print(CMD_CTX, "previously loaded image found and closed");
1670         }
1671
1672         etm_ctx->image = malloc(sizeof(struct image));
1673         etm_ctx->image->base_address_set = 0;
1674         etm_ctx->image->start_address_set = 0;
1675
1676         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1677         if (CMD_ARGC >= 2) {
1678                 etm_ctx->image->base_address_set = 1;
1679                 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address);
1680         } else
1681                 etm_ctx->image->base_address_set = 0;
1682
1683         if (image_open(etm_ctx->image, CMD_ARGV[0],
1684                 (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {
1685                 free(etm_ctx->image);
1686                 etm_ctx->image = NULL;
1687                 return ERROR_FAIL;
1688         }
1689
1690         return ERROR_OK;
1691 }
1692
1693 COMMAND_HANDLER(handle_etm_dump_command)
1694 {
1695         struct fileio file;
1696         struct target *target;
1697         struct arm *arm;
1698         struct etm_context *etm_ctx;
1699         uint32_t i;
1700
1701         if (CMD_ARGC != 1)
1702                 return ERROR_COMMAND_SYNTAX_ERROR;
1703
1704         target = get_current_target(CMD_CTX);
1705         arm = target_to_arm(target);
1706         if (!is_arm(arm)) {
1707                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1708                 return ERROR_FAIL;
1709         }
1710
1711         etm_ctx = arm->etm;
1712         if (!etm_ctx) {
1713                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1714                 return ERROR_FAIL;
1715         }
1716
1717         if (etm_ctx->capture_driver->status == TRACE_IDLE) {
1718                 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1719                 return ERROR_OK;
1720         }
1721
1722         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1723                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1724                 command_print(CMD_CTX, "trace capture not completed");
1725                 return ERROR_FAIL;
1726         }
1727
1728         /* read the trace data if it wasn't read already */
1729         if (etm_ctx->trace_depth == 0)
1730                 etm_ctx->capture_driver->read_trace(etm_ctx);
1731
1732         if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1733                 return ERROR_FAIL;
1734
1735         fileio_write_u32(&file, etm_ctx->capture_status);
1736         fileio_write_u32(&file, etm_ctx->control);
1737         fileio_write_u32(&file, etm_ctx->trace_depth);
1738
1739         for (i = 0; i < etm_ctx->trace_depth; i++) {
1740                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1741                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1742                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1743         }
1744
1745         fileio_close(&file);
1746
1747         return ERROR_OK;
1748 }
1749
1750 COMMAND_HANDLER(handle_etm_load_command)
1751 {
1752         struct fileio file;
1753         struct target *target;
1754         struct arm *arm;
1755         struct etm_context *etm_ctx;
1756         uint32_t i;
1757
1758         if (CMD_ARGC != 1)
1759                 return ERROR_COMMAND_SYNTAX_ERROR;
1760
1761         target = get_current_target(CMD_CTX);
1762         arm = target_to_arm(target);
1763         if (!is_arm(arm)) {
1764                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1765                 return ERROR_FAIL;
1766         }
1767
1768         etm_ctx = arm->etm;
1769         if (!etm_ctx) {
1770                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1771                 return ERROR_FAIL;
1772         }
1773
1774         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
1775                 command_print(CMD_CTX, "trace capture running, stop first");
1776                 return ERROR_FAIL;
1777         }
1778
1779         if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1780                 return ERROR_FAIL;
1781
1782         int filesize;
1783         int retval = fileio_size(&file, &filesize);
1784         if (retval != ERROR_OK) {
1785                 fileio_close(&file);
1786                 return retval;
1787         }
1788
1789         if (filesize % 4) {
1790                 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1791                 fileio_close(&file);
1792                 return ERROR_FAIL;
1793         }
1794
1795         if (etm_ctx->trace_depth > 0) {
1796                 free(etm_ctx->trace_data);
1797                 etm_ctx->trace_data = NULL;
1798         }
1799
1800         {
1801                 uint32_t tmp;
1802                 fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1803                 fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
1804                 fileio_read_u32(&file, &etm_ctx->trace_depth);
1805         }
1806         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1807         if (etm_ctx->trace_data == NULL) {
1808                 command_print(CMD_CTX, "not enough memory to perform operation");
1809                 fileio_close(&file);
1810                 return ERROR_FAIL;
1811         }
1812
1813         for (i = 0; i < etm_ctx->trace_depth; i++) {
1814                 uint32_t pipestat, packet, flags;
1815                 fileio_read_u32(&file, &pipestat);
1816                 fileio_read_u32(&file, &packet);
1817                 fileio_read_u32(&file, &flags);
1818                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1819                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1820                 etm_ctx->trace_data[i].flags = flags;
1821         }
1822
1823         fileio_close(&file);
1824
1825         return ERROR_OK;
1826 }
1827
1828 COMMAND_HANDLER(handle_etm_start_command)
1829 {
1830         struct target *target;
1831         struct arm *arm;
1832         struct etm_context *etm_ctx;
1833         struct reg *etm_ctrl_reg;
1834
1835         target = get_current_target(CMD_CTX);
1836         arm = target_to_arm(target);
1837         if (!is_arm(arm)) {
1838                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1839                 return ERROR_FAIL;
1840         }
1841
1842         etm_ctx = arm->etm;
1843         if (!etm_ctx) {
1844                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1845                 return ERROR_FAIL;
1846         }
1847
1848         /* invalidate old tracing data */
1849         etm_ctx->capture_status = TRACE_IDLE;
1850         if (etm_ctx->trace_depth > 0) {
1851                 free(etm_ctx->trace_data);
1852                 etm_ctx->trace_data = NULL;
1853         }
1854         etm_ctx->trace_depth = 0;
1855
1856         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1857         if (!etm_ctrl_reg)
1858                 return ERROR_FAIL;
1859
1860         etm_get_reg(etm_ctrl_reg);
1861
1862         /* Clear programming bit (10), set port selection bit (11) */
1863         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
1864
1865         etm_store_reg(etm_ctrl_reg);
1866         jtag_execute_queue();
1867
1868         etm_ctx->capture_driver->start_capture(etm_ctx);
1869
1870         return ERROR_OK;
1871 }
1872
1873 COMMAND_HANDLER(handle_etm_stop_command)
1874 {
1875         struct target *target;
1876         struct arm *arm;
1877         struct etm_context *etm_ctx;
1878         struct reg *etm_ctrl_reg;
1879
1880         target = get_current_target(CMD_CTX);
1881         arm = target_to_arm(target);
1882         if (!is_arm(arm)) {
1883                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1884                 return ERROR_FAIL;
1885         }
1886
1887         etm_ctx = arm->etm;
1888         if (!etm_ctx) {
1889                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1890                 return ERROR_FAIL;
1891         }
1892
1893         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
1894         if (!etm_ctrl_reg)
1895                 return ERROR_FAIL;
1896
1897         etm_get_reg(etm_ctrl_reg);
1898
1899         /* Set programming bit (10), clear port selection bit (11) */
1900         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
1901
1902         etm_store_reg(etm_ctrl_reg);
1903         jtag_execute_queue();
1904
1905         etm_ctx->capture_driver->stop_capture(etm_ctx);
1906
1907         return ERROR_OK;
1908 }
1909
1910 COMMAND_HANDLER(handle_etm_trigger_debug_command)
1911 {
1912         struct target *target;
1913         struct arm *arm;
1914         struct etm_context *etm;
1915
1916         target = get_current_target(CMD_CTX);
1917         arm = target_to_arm(target);
1918         if (!is_arm(arm)) {
1919                 command_print(CMD_CTX, "ETM: %s isn't an ARM",
1920                         target_name(target));
1921                 return ERROR_FAIL;
1922         }
1923
1924         etm = arm->etm;
1925         if (!etm) {
1926                 command_print(CMD_CTX, "ETM: no ETM configured for %s",
1927                         target_name(target));
1928                 return ERROR_FAIL;
1929         }
1930
1931         if (CMD_ARGC == 1) {
1932                 struct reg *etm_ctrl_reg;
1933                 bool dbgrq;
1934
1935                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1936                 if (!etm_ctrl_reg)
1937                         return ERROR_FAIL;
1938
1939                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
1940                 if (dbgrq)
1941                         etm->control |= ETM_CTRL_DBGRQ;
1942                 else
1943                         etm->control &= ~ETM_CTRL_DBGRQ;
1944
1945                 /* etm->control will be written to hardware
1946                  * the next time an "etm start" is issued.
1947                  */
1948                 buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
1949         }
1950
1951         command_print(CMD_CTX, "ETM: %s debug halt",
1952                 (etm->control & ETM_CTRL_DBGRQ)
1953                 ? "triggers"
1954                 : "does not trigger");
1955         return ERROR_OK;
1956 }
1957
1958 COMMAND_HANDLER(handle_etm_analyze_command)
1959 {
1960         struct target *target;
1961         struct arm *arm;
1962         struct etm_context *etm_ctx;
1963         int retval;
1964
1965         target = get_current_target(CMD_CTX);
1966         arm = target_to_arm(target);
1967         if (!is_arm(arm)) {
1968                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1969                 return ERROR_FAIL;
1970         }
1971
1972         etm_ctx = arm->etm;
1973         if (!etm_ctx) {
1974                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1975                 return ERROR_FAIL;
1976         }
1977
1978         retval = etmv1_analyze_trace(etm_ctx, CMD_CTX);
1979         if (retval != ERROR_OK) {
1980                 /* FIX! error should be reported inside etmv1_analyze_trace() */
1981                 switch (retval) {
1982                         case ERROR_ETM_ANALYSIS_FAILED:
1983                                 command_print(CMD_CTX,
1984                                         "further analysis failed (corrupted trace data or just end of data");
1985                                 break;
1986                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
1987                                 command_print(CMD_CTX,
1988                                         "no instruction for current address available, analysis aborted");
1989                                 break;
1990                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
1991                                 command_print(CMD_CTX, "no image available for trace analysis");
1992                                 break;
1993                         default:
1994                                 command_print(CMD_CTX, "unknown error");
1995                 }
1996         }
1997
1998         return retval;
1999 }
2000
2001 static const struct command_registration etm_config_command_handlers[] = {
2002         {
2003                 /* NOTE:  with ADIv5, ETMs are accessed by DAP operations,
2004                  * possibly over SWD, not JTAG scanchain 6 of 'target'.
2005                  *
2006                  * Also, these parameters don't match ETM v3+ modules...
2007                  */
2008                 .name = "config",
2009                 .handler = handle_etm_config_command,
2010                 .mode = COMMAND_CONFIG,
2011                 .help = "Set up ETM output port.",
2012                 .usage = "target port_width port_mode clocking capture_driver",
2013         },
2014         COMMAND_REGISTRATION_DONE
2015 };
2016 const struct command_registration etm_command_handlers[] = {
2017         {
2018                 .name = "etm",
2019                 .mode = COMMAND_ANY,
2020                 .help = "Emebdded Trace Macrocell command group",
2021                 .usage = "",
2022                 .chain = etm_config_command_handlers,
2023         },
2024         COMMAND_REGISTRATION_DONE
2025 };
2026
2027 static const struct command_registration etm_exec_command_handlers[] = {
2028         {
2029                 .name = "tracemode",
2030                 .handler = handle_etm_tracemode_command,
2031                 .mode = COMMAND_EXEC,
2032                 .help = "configure/display trace mode",
2033                 .usage = "('none'|'data'|'address'|'all') "
2034                         "context_id_bits "
2035                         "['enable'|'disable'] "
2036                         "['enable'|'disable']",
2037         },
2038         {
2039                 .name = "info",
2040                 .handler = handle_etm_info_command,
2041                 .mode = COMMAND_EXEC,
2042                 .usage = "",
2043                 .help = "display info about the current target's ETM",
2044         },
2045         {
2046                 .name = "status",
2047                 .handler = handle_etm_status_command,
2048                 .mode = COMMAND_EXEC,
2049                 .usage = "",
2050                 .help = "display current target's ETM status",
2051         },
2052         {
2053                 .name = "start",
2054                 .handler = handle_etm_start_command,
2055                 .mode = COMMAND_EXEC,
2056                 .usage = "",
2057                 .help = "start ETM trace collection",
2058         },
2059         {
2060                 .name = "stop",
2061                 .handler = handle_etm_stop_command,
2062                 .mode = COMMAND_EXEC,
2063                 .usage = "",
2064                 .help = "stop ETM trace collection",
2065         },
2066         {
2067                 .name = "trigger_debug",
2068                 .handler = handle_etm_trigger_debug_command,
2069                 .mode = COMMAND_EXEC,
2070                 .help = "enable/disable debug entry on trigger",
2071                 .usage = "['enable'|'disable']",
2072         },
2073         {
2074                 .name = "analyze",
2075                 .handler = handle_etm_analyze_command,
2076                 .mode = COMMAND_EXEC,
2077                 .usage = "",
2078                 .help = "analyze collected ETM trace",
2079         },
2080         {
2081                 .name = "image",
2082                 .handler = handle_etm_image_command,
2083                 .mode = COMMAND_EXEC,
2084                 .help = "load image from file with optional offset",
2085                 .usage = "<file> [base address] [type]",
2086         },
2087         {
2088                 .name = "dump",
2089                 .handler = handle_etm_dump_command,
2090                 .mode = COMMAND_EXEC,
2091                 .help = "dump captured trace data to file",
2092                 .usage = "filename",
2093         },
2094         {
2095                 .name = "load",
2096                 .handler = handle_etm_load_command,
2097                 .mode = COMMAND_EXEC,
2098                 .usage = "",
2099                 .help = "load trace data for analysis <file>",
2100         },
2101         COMMAND_REGISTRATION_DONE
2102 };
2103
2104 static int etm_register_user_commands(struct command_context *cmd_ctx)
2105 {
2106         struct command *etm_cmd = command_find_in_context(cmd_ctx, "etm");
2107         return register_commands(cmd_ctx, etm_cmd, etm_exec_command_handlers);
2108 }