git.gag.com Git - fw/openocd/blob - src/target/etm.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "armv4_5.h"
  25 #include "etm.h"
  26 #include "etb.h"
  27 #include "image.h"
  28 #include "arm_disassembler.h"
  29 #include "register.h"
  30
  31
  32 /*
  33  * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  34  *
  35  * ETM modules collect instruction and/or data trace information, compress
  36  * it, and transfer it to a debugging host through either a (buffered) trace
  37  * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
  38  *
  39  * There are several generations of these modules.  Original versions have
  40  * JTAG access through a dedicated scan chain.  Recent versions have added
  41  * access via coprocessor instructions, memory addressing, and the ARM Debug
  42  * Interface v5 (ADIv5); and phased out direct JTAG access.
  43  *
  44  * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
  45  * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
  46  * implying non-JTAG connectivity options.
  47  *
  48  * Relevant documentation includes:
  49  *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
  50  *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
  51  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  52  */
  53
  54 enum {
  55         RO,                             /* read/only */
  56         WO,                             /* write/only */
  57         RW,                             /* read/write */
  58 };
  59
  60 struct etm_reg_info {
  61         uint8_t         addr;
  62         uint8_t         size;           /* low-N of 32 bits */
  63         uint8_t         mode;           /* RO, WO, RW */
  64         uint8_t         bcd_vers;       /* 1.0, 2.0, etc */
  65         char            *name;
  66 };
  67
  68 /*
  69  * Registers 0..0x7f are JTAG-addressable using scanchain 6.
  70  * (Or on some processors, through coprocessor operations.)
  71  * Newer versions of ETM make some W/O registers R/W, and
  72  * provide definitions for some previously-unused bits.
  73  */
  74
  75 /* core registers used to version/configure the ETM */
  76 static const struct etm_reg_info etm_core[] = {
  77         /* NOTE: we "know" the order here ... */
  78         { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
  79         { ETM_ID, 32, RO, 0x20, "ETM_id", },
  80 };
  81
  82 /* basic registers that are always there given the right ETM version */
  83 static const struct etm_reg_info etm_basic[] = {
  84         /* ETM Trace Registers */
  85         { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
  86         { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
  87         { ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_asic_ctrl", },
  88         { ETM_STATUS,  3, RO, 0x11, "ETM_status", },
  89         { ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_sys_config", },
  90
  91         /* TraceEnable configuration */
  92         { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
  93         { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
  94         { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
  95         { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
  96
  97         /* ViewData configuration (data trace) */
  98         { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
  99         { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
 100         { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
 101         { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
 102
 103         /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
 104
 105         { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
 106         { 0x7a, 22, RO, 0x31, "ETM_config_code_ext", },
 107         { 0x7b, 32, WO, 0x31, "ETM_ext_input_select", },
 108         { 0x7c, 32, WO, 0x34, "ETM_trace_start_stop", },
 109         { 0x7d, 8, WO, 0x34, "ETM_behavior_control", },
 110 };
 111
 112 static const struct etm_reg_info etm_fifofull[] = {
 113         /* FIFOFULL configuration */
 114         { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
 115         { ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_fifofull_level", },
 116 };
 117
 118 static const struct etm_reg_info etm_addr_comp[] = {
 119         /* Address comparator register pairs */
 120 #define ADDR_COMPARATOR(i) \
 121                 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
 122                                 "ETM_addr_" #i "_comparator_value", }, \
 123                 { ETM_ADDR_ACCESS_TYPE + (i) - 1,  7, WO, 0x10, \
 124                                 "ETM_addr_" #i "_access_type", }
 125         ADDR_COMPARATOR(1),
 126         ADDR_COMPARATOR(2),
 127         ADDR_COMPARATOR(3),
 128         ADDR_COMPARATOR(4),
 129         ADDR_COMPARATOR(5),
 130         ADDR_COMPARATOR(6),
 131         ADDR_COMPARATOR(7),
 132         ADDR_COMPARATOR(8),
 133
 134         ADDR_COMPARATOR(9),
 135         ADDR_COMPARATOR(10),
 136         ADDR_COMPARATOR(11),
 137         ADDR_COMPARATOR(12),
 138         ADDR_COMPARATOR(13),
 139         ADDR_COMPARATOR(14),
 140         ADDR_COMPARATOR(15),
 141         ADDR_COMPARATOR(16),
 142 #undef ADDR_COMPARATOR
 143 };
 144
 145 static const struct etm_reg_info etm_data_comp[] = {
 146         /* Data Value Comparators (NOTE: odd addresses are reserved) */
 147 #define DATA_COMPARATOR(i) \
 148                 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
 149                                 "ETM_data_" #i "_comparator_value", }, \
 150                 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
 151                                 "ETM_data_" #i "_comparator_mask", }
 152         DATA_COMPARATOR(1),
 153         DATA_COMPARATOR(2),
 154         DATA_COMPARATOR(3),
 155         DATA_COMPARATOR(4),
 156         DATA_COMPARATOR(5),
 157         DATA_COMPARATOR(6),
 158         DATA_COMPARATOR(7),
 159         DATA_COMPARATOR(8),
 160 #undef DATA_COMPARATOR
 161 };
 162
 163 static const struct etm_reg_info etm_counters[] = {
 164 #define ETM_COUNTER(i) \
 165                 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
 166                                 "ETM_counter_" #i "_reload_value", }, \
 167                 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
 168                                 "ETM_counter_" #i "_enable", }, \
 169                 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
 170                                 "ETM_counter_" #i "_reload_event", }, \
 171                 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
 172                                 "ETM_counter_" #i "_value", }
 173         ETM_COUNTER(1),
 174         ETM_COUNTER(2),
 175         ETM_COUNTER(3),
 176         ETM_COUNTER(4),
 177 #undef ETM_COUNTER
 178 };
 179
 180 static const struct etm_reg_info etm_sequencer[] = {
 181 #define ETM_SEQ(i) \
 182                 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 183                                 "ETM_sequencer_event" #i, }
 184         ETM_SEQ(0),                             /* 1->2 */
 185         ETM_SEQ(1),                             /* 2->1 */
 186         ETM_SEQ(2),                             /* 2->3 */
 187         ETM_SEQ(3),                             /* 3->1 */
 188         ETM_SEQ(4),                             /* 3->2 */
 189         ETM_SEQ(5),                             /* 1->3 */
 190 #undef ETM_SEQ
 191         /* 0x66 reserved */
 192         { ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_sequencer_state", },
 193 };
 194
 195 static const struct etm_reg_info etm_outputs[] = {
 196 #define ETM_OUTPUT(i) \
 197                 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
 198                                 "ETM_external_output" #i, }
 199
 200         ETM_OUTPUT(1),
 201         ETM_OUTPUT(2),
 202         ETM_OUTPUT(3),
 203         ETM_OUTPUT(4),
 204 #undef ETM_OUTPUT
 205 };
 206
 207 #if 0
 208         /* registers from 0x6c..0x7f were added after ETMv1.3 */
 209
 210         /* Context ID Comparators */
 211         { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
 212         { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
 213         { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
 214         { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
 215 #endif
 216
 217 static int etm_get_reg(struct reg *reg);
 218 static int etm_read_reg_w_check(struct reg *reg,
 219                 uint8_t* check_value, uint8_t* check_mask);
 220 static int etm_register_user_commands(struct command_context *cmd_ctx);
 221 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
 222 static int etm_write_reg(struct reg *reg, uint32_t value);
 223
 224 static struct command *etm_cmd;
 225
 226 static const struct reg_arch_type etm_scan6_type = {
 227         .get = etm_get_reg,
 228         .set = etm_set_reg_w_exec,
 229 };
 230
 231 /* Look up register by ID ... most ETM instances only
 232  * support a subset of the possible registers.
 233  */
 234 static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
 235 {
 236         struct reg_cache *cache = etm_ctx->reg_cache;
 237         int i;
 238
 239         for (i = 0; i < cache->num_regs; i++) {
 240                 struct etm_reg *reg = cache->reg_list[i].arch_info;
 241
 242                 if (reg->reg_info->addr == id)
 243                         return &cache->reg_list[i];
 244         }
 245
 246         /* caller asking for nonexistent register is a bug! */
 247         /* REVISIT say which of the N targets was involved */
 248         LOG_ERROR("ETM: register 0x%02x not available", id);
 249         return NULL;
 250 }
 251
 252 static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
 253                 struct reg_cache *cache, struct etm_reg *ereg,
 254                 const struct etm_reg_info *r, unsigned nreg)
 255 {
 256         struct reg *reg = cache->reg_list;
 257
 258         reg += cache->num_regs;
 259         ereg += cache->num_regs;
 260
 261         /* add up to "nreg" registers from "r", if supported by this
 262          * version of the ETM, to the specified cache.
 263          */
 264         for (; nreg--; r++) {
 265
 266                 /* this ETM may be too old to have some registers */
 267                 if (r->bcd_vers > bcd_vers)
 268                         continue;
 269
 270                 reg->name = r->name;
 271                 reg->size = r->size;
 272                 reg->value = &ereg->value;
 273                 reg->arch_info = ereg;
 274                 reg->type = &etm_scan6_type;
 275                 reg++;
 276                 cache->num_regs++;
 277
 278                 ereg->reg_info = r;
 279                 ereg->jtag_info = jtag_info;
 280                 ereg++;
 281         }
 282 }
 283
 284 struct reg_cache *etm_build_reg_cache(struct target *target,
 285                 struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
 286 {
 287         struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 288         struct reg *reg_list = NULL;
 289         struct etm_reg *arch_info = NULL;
 290         unsigned bcd_vers, config;
 291
 292         /* the actual registers are kept in two arrays */
 293         reg_list = calloc(128, sizeof(struct reg));
 294         arch_info = calloc(128, sizeof(struct etm_reg));
 295
 296         /* fill in values for the reg cache */
 297         reg_cache->name = "etm registers";
 298         reg_cache->next = NULL;
 299         reg_cache->reg_list = reg_list;
 300         reg_cache->num_regs = 0;
 301
 302         /* add ETM_CONFIG, then parse its values to see
 303          * which other registers exist in this ETM
 304          */
 305         etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
 306                         etm_core, 1);
 307
 308         etm_get_reg(reg_list);
 309         etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
 310         config = etm_ctx->config;
 311
 312         /* figure ETM version then add base registers */
 313         if (config & (1 << 31)) {
 314                 bcd_vers = 0x20;
 315                 LOG_WARNING("ETMv2+ support is incomplete");
 316
 317                 /* REVISIT more registers may exist; they may now be
 318                  * readable; more register bits have defined meanings;
 319                  * don't presume trace start/stop support is present;
 320                  * and include any context ID comparator registers.
 321                  */
 322                 etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
 323                                 etm_core + 1, 1);
 324                 etm_get_reg(reg_list + 1);
 325                 etm_ctx->id = buf_get_u32(
 326                                 (void *)&arch_info[1].value, 0, 32);
 327                 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
 328                 bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
 329
 330         } else {
 331                 switch (config >> 28) {
 332                 case 7:
 333                 case 5:
 334                 case 3:
 335                         bcd_vers = 0x13;
 336                         break;
 337                 case 4:
 338                 case 2:
 339                         bcd_vers = 0x12;
 340                         break;
 341                 case 1:
 342                         bcd_vers = 0x11;
 343                         break;
 344                 case 0:
 345                         bcd_vers = 0x10;
 346                         break;
 347                 default:
 348                         LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
 349                         goto fail;
 350                 }
 351         }
 352         etm_ctx->bcd_vers = bcd_vers;
 353         LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 354
 355         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 356                         etm_basic, ARRAY_SIZE(etm_basic));
 357
 358         /* address and data comparators; counters; outputs */
 359         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 360                         etm_addr_comp, 4 * (0x0f & (config >> 0)));
 361         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 362                         etm_data_comp, 2 * (0x0f & (config >> 4)));
 363         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 364                         etm_counters, 4 * (0x07 & (config >> 13)));
 365         etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 366                         etm_outputs, (0x07 & (config >> 20)));
 367
 368         /* FIFOFULL presence is optional
 369          * REVISIT for ETMv1.2 and later, don't bother adding this
 370          * unless ETM_SYS_CONFIG says it's also *supported* ...
 371          */
 372         if (config & (1 << 23))
 373                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 374                                 etm_fifofull, ARRAY_SIZE(etm_fifofull));
 375
 376         /* sequencer is optional (for state-dependant triggering) */
 377         if (config & (1 << 16))
 378                 etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
 379                                 etm_sequencer, ARRAY_SIZE(etm_sequencer));
 380
 381         /* REVISIT could realloc and likely save half the memory
 382          * in the two chunks we allocated...
 383          */
 384
 385         /* the ETM might have an ETB connected */
 386         if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 387         {
 388                 struct etb *etb = etm_ctx->capture_driver_priv;
 389
 390                 if (!etb)
 391                 {
 392                         LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 393                         goto fail;
 394                 }
 395
 396                 reg_cache->next = etb_build_reg_cache(etb);
 397
 398                 etb->reg_cache = reg_cache->next;
 399         }
 400
 401         etm_ctx->reg_cache = reg_cache;
 402         return reg_cache;
 403
 404 fail:
 405         free(reg_cache);
 406         free(reg_list);
 407         free(arch_info);
 408         return NULL;
 409 }
 410
 411 static int etm_read_reg(struct reg *reg)
 412 {
 413         return etm_read_reg_w_check(reg, NULL, NULL);
 414 }
 415
 416 static int etm_store_reg(struct reg *reg)
 417 {
 418         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 419 }
 420
 421 int etm_setup(struct target *target)
 422 {
 423         int retval;
 424         uint32_t etm_ctrl_value;
 425         struct arm *arm = target_to_arm(target);
 426         struct etm_context *etm_ctx = arm->etm;
 427         struct reg *etm_ctrl_reg;
 428
 429         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
 430         if (!etm_ctrl_reg)
 431                 return ERROR_OK;
 432
 433         /* initialize some ETM control register settings */
 434         etm_get_reg(etm_ctrl_reg);
 435         etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
 436
 437         /* clear the ETM powerdown bit (0) */
 438         etm_ctrl_value &= ~0x1;
 439
 440         /* configure port width (21,6:4), mode (13,17:16) and
 441          * for older modules clocking (13)
 442          */
 443         etm_ctrl_value = (etm_ctrl_value
 444                         & ~ETM_PORT_WIDTH_MASK
 445                         & ~ETM_PORT_MODE_MASK
 446                         & ~ETM_PORT_CLOCK_MASK)
 447                 | etm_ctx->portmode;
 448
 449         buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
 450         etm_store_reg(etm_ctrl_reg);
 451
 452         if ((retval = jtag_execute_queue()) != ERROR_OK)
 453                 return retval;
 454
 455         /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
 456          * verify that those width and mode settings are OK ...
 457          */
 458
 459         if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK)
 460         {
 461                 LOG_ERROR("ETM capture driver initialization failed");
 462                 return retval;
 463         }
 464         return ERROR_OK;
 465 }
 466
 467 static int etm_get_reg(struct reg *reg)
 468 {
 469         int retval;
 470
 471         if ((retval = etm_read_reg(reg)) != ERROR_OK)
 472         {
 473                 LOG_ERROR("BUG: error scheduling etm register read");
 474                 return retval;
 475         }
 476
 477         if ((retval = jtag_execute_queue()) != ERROR_OK)
 478         {
 479                 LOG_ERROR("register read failed");
 480                 return retval;
 481         }
 482
 483         return ERROR_OK;
 484 }
 485
 486 static int etm_read_reg_w_check(struct reg *reg,
 487                 uint8_t* check_value, uint8_t* check_mask)
 488 {
 489         struct etm_reg *etm_reg = reg->arch_info;
 490         const struct etm_reg_info *r = etm_reg->reg_info;
 491         uint8_t reg_addr = r->addr & 0x7f;
 492         struct scan_field fields[3];
 493
 494         if (etm_reg->reg_info->mode == WO) {
 495                 LOG_ERROR("BUG: can't read write-only register %s", r->name);
 496                 return ERROR_INVALID_ARGUMENTS;
 497         }
 498
 499         LOG_DEBUG("%s (%u)", r->name, reg_addr);
 500
 501         jtag_set_end_state(TAP_IDLE);
 502         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 503         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 504
 505         fields[0].tap = etm_reg->jtag_info->tap;
 506         fields[0].num_bits = 32;
 507         fields[0].out_value = reg->value;
 508         fields[0].in_value = NULL;
 509         fields[0].check_value = NULL;
 510         fields[0].check_mask = NULL;
 511
 512         fields[1].tap = etm_reg->jtag_info->tap;
 513         fields[1].num_bits = 7;
 514         fields[1].out_value = malloc(1);
 515         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 516         fields[1].in_value = NULL;
 517         fields[1].check_value = NULL;
 518         fields[1].check_mask = NULL;
 519
 520         fields[2].tap = etm_reg->jtag_info->tap;
 521         fields[2].num_bits = 1;
 522         fields[2].out_value = malloc(1);
 523         buf_set_u32(fields[2].out_value, 0, 1, 0);
 524         fields[2].in_value = NULL;
 525         fields[2].check_value = NULL;
 526         fields[2].check_mask = NULL;
 527
 528         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 529
 530         fields[0].in_value = reg->value;
 531         fields[0].check_value = check_value;
 532         fields[0].check_mask = check_mask;
 533
 534         jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
 535
 536         free(fields[1].out_value);
 537         free(fields[2].out_value);
 538
 539         return ERROR_OK;
 540 }
 541
 542 static int etm_set_reg(struct reg *reg, uint32_t value)
 543 {
 544         int retval;
 545
 546         if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
 547         {
 548                 LOG_ERROR("BUG: error scheduling etm register write");
 549                 return retval;
 550         }
 551
 552         buf_set_u32(reg->value, 0, reg->size, value);
 553         reg->valid = 1;
 554         reg->dirty = 0;
 555
 556         return ERROR_OK;
 557 }
 558
 559 static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 560 {
 561         int retval;
 562
 563         etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 564
 565         if ((retval = jtag_execute_queue()) != ERROR_OK)
 566         {
 567                 LOG_ERROR("register write failed");
 568                 return retval;
 569         }
 570         return ERROR_OK;
 571 }
 572
 573 static int etm_write_reg(struct reg *reg, uint32_t value)
 574 {
 575         struct etm_reg *etm_reg = reg->arch_info;
 576         const struct etm_reg_info *r = etm_reg->reg_info;
 577         uint8_t reg_addr = r->addr & 0x7f;
 578         struct scan_field fields[3];
 579
 580         if (etm_reg->reg_info->mode == RO) {
 581                 LOG_ERROR("BUG: can't write read--only register %s", r->name);
 582                 return ERROR_INVALID_ARGUMENTS;
 583         }
 584
 585         LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 586
 587         jtag_set_end_state(TAP_IDLE);
 588         arm_jtag_scann(etm_reg->jtag_info, 0x6);
 589         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
 590
 591         fields[0].tap = etm_reg->jtag_info->tap;
 592         fields[0].num_bits = 32;
 593         uint8_t tmp1[4];
 594         fields[0].out_value = tmp1;
 595         buf_set_u32(fields[0].out_value, 0, 32, value);
 596         fields[0].in_value = NULL;
 597
 598         fields[1].tap = etm_reg->jtag_info->tap;
 599         fields[1].num_bits = 7;
 600         uint8_t tmp2;
 601         fields[1].out_value = &tmp2;
 602         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 603         fields[1].in_value = NULL;
 604
 605         fields[2].tap = etm_reg->jtag_info->tap;
 606         fields[2].num_bits = 1;
 607         uint8_t tmp3;
 608         fields[2].out_value = &tmp3;
 609         buf_set_u32(fields[2].out_value, 0, 1, 1);
 610         fields[2].in_value = NULL;
 611
 612         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 613
 614         return ERROR_OK;
 615 }
 616
 617
 618 /* ETM trace analysis functionality
 619  *
 620  */
 621 extern struct etm_capture_driver etm_dummy_capture_driver;
 622 #if BUILD_OOCD_TRACE == 1
 623 extern struct etm_capture_driver oocd_trace_capture_driver;
 624 #endif
 625
 626 static struct etm_capture_driver *etm_capture_drivers[] =
 627 {
 628         &etb_capture_driver,
 629         &etm_dummy_capture_driver,
 630 #if BUILD_OOCD_TRACE == 1
 631         &oocd_trace_capture_driver,
 632 #endif
 633         NULL
 634 };
 635
 636 static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction *instruction)
 637 {
 638         int i;
 639         int section = -1;
 640         size_t size_read;
 641         uint32_t opcode;
 642         int retval;
 643
 644         if (!ctx->image)
 645                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
 646
 647         /* search for the section the current instruction belongs to */
 648         for (i = 0; i < ctx->image->num_sections; i++)
 649         {
 650                 if ((ctx->image->sections[i].base_address <= ctx->current_pc) &&
 651                         (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc))
 652                 {
 653                         section = i;
 654                         break;
 655                 }
 656         }
 657
 658         if (section == -1)
 659         {
 660                 /* current instruction couldn't be found in the image */
 661                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 662         }
 663
 664         if (ctx->core_state == ARMV4_5_STATE_ARM)
 665         {
 666                 uint8_t buf[4];
 667                 if ((retval = image_read_section(ctx->image, section,
 668                         ctx->current_pc - ctx->image->sections[section].base_address,
 669                         4, buf, &size_read)) != ERROR_OK)
 670                 {
 671                         LOG_ERROR("error while reading instruction: %i", retval);
 672                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 673                 }
 674                 opcode = target_buffer_get_u32(ctx->target, buf);
 675                 arm_evaluate_opcode(opcode, ctx->current_pc, instruction);
 676         }
 677         else if (ctx->core_state == ARMV4_5_STATE_THUMB)
 678         {
 679                 uint8_t buf[2];
 680                 if ((retval = image_read_section(ctx->image, section,
 681                         ctx->current_pc - ctx->image->sections[section].base_address,
 682                         2, buf, &size_read)) != ERROR_OK)
 683                 {
 684                         LOG_ERROR("error while reading instruction: %i", retval);
 685                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
 686                 }
 687                 opcode = target_buffer_get_u16(ctx->target, buf);
 688                 thumb_evaluate_opcode(opcode, ctx->current_pc, instruction);
 689         }
 690         else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
 691         {
 692                 LOG_ERROR("BUG: tracing of jazelle code not supported");
 693                 return ERROR_FAIL;
 694         }
 695         else
 696         {
 697                 LOG_ERROR("BUG: unknown core state encountered");
 698                 return ERROR_FAIL;
 699         }
 700
 701         return ERROR_OK;
 702 }
 703
 704 static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
 705 {
 706         while (ctx->data_index < ctx->trace_depth)
 707         {
 708                 /* if the caller specified an address packet offset, skip until the
 709                  * we reach the n-th cycle marked with tracesync */
 710                 if (apo > 0)
 711                 {
 712                         if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE)
 713                                 apo--;
 714
 715                         if (apo > 0)
 716                         {
 717                                 ctx->data_index++;
 718                                 ctx->data_half = 0;
 719                         }
 720                         continue;
 721                 }
 722
 723                 /* no tracedata output during a TD cycle
 724                  * or in a trigger cycle */
 725                 if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD)
 726                         || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE))
 727                 {
 728                         ctx->data_index++;
 729                         ctx->data_half = 0;
 730                         continue;
 731                 }
 732
 733                 if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
 734                 {
 735                         if (ctx->data_half == 0)
 736                         {
 737                                 *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 738                                 ctx->data_half = 1;
 739                         }
 740                         else
 741                         {
 742                                 *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8;
 743                                 ctx->data_half = 0;
 744                                 ctx->data_index++;
 745                         }
 746                 }
 747                 else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 748                 {
 749                         *packet = ctx->trace_data[ctx->data_index].packet & 0xff;
 750                         ctx->data_index++;
 751                 }
 752                 else
 753                 {
 754                         /* on a 4-bit port, a packet will be output during two consecutive cycles */
 755                         if (ctx->data_index > (ctx->trace_depth - 2))
 756                                 return -1;
 757
 758                         *packet = ctx->trace_data[ctx->data_index].packet & 0xf;
 759                         *packet |= (ctx->trace_data[ctx->data_index + 1].packet & 0xf) << 4;
 760                         ctx->data_index += 2;
 761                 }
 762
 763                 return 0;
 764         }
 765
 766         return -1;
 767 }
 768
 769 static int etmv1_branch_address(struct etm_context *ctx)
 770 {
 771         int retval;
 772         uint8_t packet;
 773         int shift = 0;
 774         int apo;
 775         uint32_t i;
 776
 777         /* quit analysis if less than two cycles are left in the trace
 778          * because we can't extract the APO */
 779         if (ctx->data_index > (ctx->trace_depth - 2))
 780                 return -1;
 781
 782         /* a BE could be output during an APO cycle, skip the current
 783          * and continue with the new one */
 784         if (ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x4)
 785                 return 1;
 786         if (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x4)
 787                 return 2;
 788
 789         /* address packet offset encoded in the next two cycles' pipestat bits */
 790         apo = ctx->trace_data[ctx->pipe_index + 1].pipestat & 0x3;
 791         apo |= (ctx->trace_data[ctx->pipe_index + 2].pipestat & 0x3) << 2;
 792
 793         /* count number of tracesync cycles between current pipe_index and data_index
 794          * i.e. the number of tracesyncs that data_index already passed by
 795          * to subtract them from the APO */
 796         for (i = ctx->pipe_index; i < ctx->data_index; i++)
 797         {
 798                 if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE)
 799                         apo--;
 800         }
 801
 802         /* extract up to four 7-bit packets */
 803         do {
 804                 if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0)
 805                         return -1;
 806                 ctx->last_branch &= ~(0x7f << shift);
 807                 ctx->last_branch |= (packet & 0x7f) << shift;
 808                 shift += 7;
 809         } while ((packet & 0x80) && (shift < 28));
 810
 811         /* one last packet holding 4 bits of the address, plus the branch reason code */
 812         if ((shift == 28) && (packet & 0x80))
 813         {
 814                 if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
 815                         return -1;
 816                 ctx->last_branch &= 0x0fffffff;
 817                 ctx->last_branch |= (packet & 0x0f) << 28;
 818                 ctx->last_branch_reason = (packet & 0x70) >> 4;
 819                 shift += 4;
 820         }
 821         else
 822         {
 823                 ctx->last_branch_reason = 0;
 824         }
 825
 826         if (shift == 32)
 827         {
 828                 ctx->pc_ok = 1;
 829         }
 830
 831         /* if a full address was output, we might have branched into Jazelle state */
 832         if ((shift == 32) && (packet & 0x80))
 833         {
 834                 ctx->core_state = ARMV4_5_STATE_JAZELLE;
 835         }
 836         else
 837         {
 838                 /* if we didn't branch into Jazelle state, the current processor state is
 839                  * encoded in bit 0 of the branch target address */
 840                 if (ctx->last_branch & 0x1)
 841                 {
 842                         ctx->core_state = ARMV4_5_STATE_THUMB;
 843                         ctx->last_branch &= ~0x1;
 844                 }
 845                 else
 846                 {
 847                         ctx->core_state = ARMV4_5_STATE_ARM;
 848                         ctx->last_branch &= ~0x3;
 849                 }
 850         }
 851
 852         return 0;
 853 }
 854
 855 static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
 856 {
 857         int j;
 858         uint8_t buf[4];
 859         int retval;
 860
 861         for (j = 0; j < size; j++)
 862         {
 863                 if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0)
 864                         return -1;
 865         }
 866
 867         if (size == 8)
 868         {
 869                 LOG_ERROR("TODO: add support for 64-bit values");
 870                 return -1;
 871         }
 872         else if (size == 4)
 873                 *data = target_buffer_get_u32(ctx->target, buf);
 874         else if (size == 2)
 875                 *data = target_buffer_get_u16(ctx->target, buf);
 876         else if (size == 1)
 877                 *data = buf[0];
 878         else
 879                 return -1;
 880
 881         return 0;
 882 }
 883
 884 static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
 885 {
 886         int retval;
 887         struct arm_instruction instruction;
 888
 889         /* read the trace data if it wasn't read already */
 890         if (ctx->trace_depth == 0)
 891                 ctx->capture_driver->read_trace(ctx);
 892
 893         /* start at the beginning of the captured trace */
 894         ctx->pipe_index = 0;
 895         ctx->data_index = 0;
 896         ctx->data_half = 0;
 897
 898         /* neither the PC nor the data pointer are valid */
 899         ctx->pc_ok = 0;
 900         ctx->ptr_ok = 0;
 901
 902         while (ctx->pipe_index < ctx->trace_depth)
 903         {
 904                 uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat;
 905                 uint32_t next_pc = ctx->current_pc;
 906                 uint32_t old_data_index = ctx->data_index;
 907                 uint32_t old_data_half = ctx->data_half;
 908                 uint32_t old_index = ctx->pipe_index;
 909                 uint32_t last_instruction = ctx->last_instruction;
 910                 uint32_t cycles = 0;
 911                 int current_pc_ok = ctx->pc_ok;
 912
 913                 if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
 914                 {
 915                         command_print(cmd_ctx, "--- trigger ---");
 916                 }
 917
 918                 /* instructions execute in IE/D or BE/D cycles */
 919                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
 920                         ctx->last_instruction = ctx->pipe_index;
 921
 922                 /* if we don't have a valid pc skip until we reach an indirect branch */
 923                 if ((!ctx->pc_ok) && (pipestat != STAT_BE))
 924                 {
 925                         ctx->pipe_index++;
 926                         continue;
 927                 }
 928
 929                 /* any indirect branch could have interrupted instruction flow
 930                  * - the branch reason code could indicate a trace discontinuity
 931                  * - a branch to the exception vectors indicates an exception
 932                  */
 933                 if ((pipestat == STAT_BE) || (pipestat == STAT_BD))
 934                 {
 935                         /* backup current data index, to be able to consume the branch address
 936                          * before examining data address and values
 937                          */
 938                         old_data_index = ctx->data_index;
 939                         old_data_half = ctx->data_half;
 940
 941                         ctx->last_instruction = ctx->pipe_index;
 942
 943                         if ((retval = etmv1_branch_address(ctx)) != 0)
 944                         {
 945                                 /* negative return value from etmv1_branch_address means we ran out of packets,
 946                                  * quit analysing the trace */
 947                                 if (retval < 0)
 948                                         break;
 949
 950                                 /* a positive return values means the current branch was abandoned,
 951                                  * and a new branch was encountered in cycle ctx->pipe_index + retval;
 952                                  */
 953                                 LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
 954                                 ctx->pipe_index += retval;
 955                                 continue;
 956                         }
 957
 958                         /* skip over APO cycles */
 959                         ctx->pipe_index += 2;
 960
 961                         switch (ctx->last_branch_reason)
 962                         {
 963                                 case 0x0:       /* normal PC change */
 964                                         next_pc = ctx->last_branch;
 965                                         break;
 966                                 case 0x1:       /* tracing enabled */
 967                                         command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 968                                         ctx->current_pc = ctx->last_branch;
 969                                         ctx->pipe_index++;
 970                                         continue;
 971                                         break;
 972                                 case 0x2:       /* trace restarted after FIFO overflow */
 973                                         command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 974                                         ctx->current_pc = ctx->last_branch;
 975                                         ctx->pipe_index++;
 976                                         continue;
 977                                         break;
 978                                 case 0x3:       /* exit from debug state */
 979                                         command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 980                                         ctx->current_pc = ctx->last_branch;
 981                                         ctx->pipe_index++;
 982                                         continue;
 983                                         break;
 984                                 case 0x4:       /* periodic synchronization point */
 985                                         next_pc = ctx->last_branch;
 986                                         /* if we had no valid PC prior to this synchronization point,
 987                                          * we have to move on with the next trace cycle
 988                                          */
 989                                         if (!current_pc_ok)
 990                                         {
 991                                                 command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 992                                                 ctx->current_pc = next_pc;
 993                                                 ctx->pipe_index++;
 994                                                 continue;
 995                                         }
 996                                         break;
 997                                 default:        /* reserved */
 998                                         LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
 999                                         return ERROR_FAIL;
1000                         }
1001
1002                         /* if we got here the branch was a normal PC change
1003                          * (or a periodic synchronization point, which means the same for that matter)
1004                          * if we didn't accquire a complete PC continue with the next cycle
1005                          */
1006                         if (!ctx->pc_ok)
1007                                 continue;
1008
1009                         /* indirect branch to the exception vector means an exception occured */
1010                         if ((ctx->last_branch <= 0x20)
1011                                 || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020)))
1012                         {
1013                                 if ((ctx->last_branch & 0xff) == 0x10)
1014                                 {
1015                                         command_print(cmd_ctx, "data abort");
1016                                 }
1017                                 else
1018                                 {
1019                                         command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
1020                                         ctx->current_pc = ctx->last_branch;
1021                                         ctx->pipe_index++;
1022                                         continue;
1023                                 }
1024                         }
1025                 }
1026
1027                 /* an instruction was executed (or not, depending on the condition flags)
1028                  * retrieve it from the image for displaying */
1029                 if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) &&
1030                         !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) &&
1031                                 ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4))))
1032                 {
1033                         if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK)
1034                         {
1035                                 /* can't continue tracing with no image available */
1036                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
1037                                 {
1038                                         return retval;
1039                                 }
1040                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
1041                                 {
1042                                         /* TODO: handle incomplete images
1043                                          * for now we just quit the analsysis*/
1044                                         return retval;
1045                                 }
1046                         }
1047
1048                         cycles = old_index - last_instruction;
1049                 }
1050
1051                 if ((pipestat == STAT_ID) || (pipestat == STAT_BD))
1052                 {
1053                         uint32_t new_data_index = ctx->data_index;
1054                         uint32_t new_data_half = ctx->data_half;
1055
1056                         /* in case of a branch with data, the branch target address was consumed before
1057                          * we temporarily go back to the saved data index */
1058                         if (pipestat == STAT_BD)
1059                         {
1060                                 ctx->data_index = old_data_index;
1061                                 ctx->data_half = old_data_half;
1062                         }
1063
1064                         if (ctx->tracemode & ETMV1_TRACE_ADDR)
1065                         {
1066                                 uint8_t packet;
1067                                 int shift = 0;
1068
1069                                 do {
1070                                         if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0)
1071                                                 return ERROR_ETM_ANALYSIS_FAILED;
1072                                         ctx->last_ptr &= ~(0x7f << shift);
1073                                         ctx->last_ptr |= (packet & 0x7f) << shift;
1074                                         shift += 7;
1075                                 } while ((packet & 0x80) && (shift < 32));
1076
1077                                 if (shift >= 32)
1078                                         ctx->ptr_ok = 1;
1079
1080                                 if (ctx->ptr_ok)
1081                                 {
1082                                         command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
1083                                 }
1084                         }
1085
1086                         if (ctx->tracemode & ETMV1_TRACE_DATA)
1087                         {
1088                                 if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
1089                                 {
1090                                         int i;
1091                                         for (i = 0; i < 16; i++)
1092                                         {
1093                                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
1094                                                 {
1095                                                         uint32_t data;
1096                                                         if (etmv1_data(ctx, 4, &data) != 0)
1097                                                                 return ERROR_ETM_ANALYSIS_FAILED;
1098                                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1099                                                 }
1100                                         }
1101                                 }
1102                                 else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH))
1103                                 {
1104                                         uint32_t data;
1105                                         if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
1106                                                 return ERROR_ETM_ANALYSIS_FAILED;
1107                                         command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
1108                                 }
1109                         }
1110
1111                         /* restore data index after consuming BD address and data */
1112                         if (pipestat == STAT_BD)
1113                         {
1114                                 ctx->data_index = new_data_index;
1115                                 ctx->data_half = new_data_half;
1116                         }
1117                 }
1118
1119                 /* adjust PC */
1120                 if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
1121                 {
1122                         if (((instruction.type == ARM_B) ||
1123                              (instruction.type == ARM_BL) ||
1124                              (instruction.type == ARM_BLX)) &&
1125                             (instruction.info.b_bl_bx_blx.target_address != 0xffffffff))
1126                         {
1127                                 next_pc = instruction.info.b_bl_bx_blx.target_address;
1128                         }
1129                         else
1130                         {
1131                                 next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1132                         }
1133                 }
1134                 else if (pipestat == STAT_IN)
1135                 {
1136                         next_pc += (ctx->core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
1137                 }
1138
1139                 if ((pipestat != STAT_TD) && (pipestat != STAT_WT))
1140                 {
1141                         char cycles_text[32] = "";
1142
1143                         /* if the trace was captured with cycle accurate tracing enabled,
1144                          * output the number of cycles since the last executed instruction
1145                          */
1146                         if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
1147                         {
1148                                 snprintf(cycles_text, 32, " (%i %s)",
1149                                          (int)cycles,
1150                                         (cycles == 1) ? "cycle" : "cycles");
1151                         }
1152
1153                         command_print(cmd_ctx, "%s%s%s",
1154                                 instruction.text,
1155                                 (pipestat == STAT_IN) ? " (not executed)" : "",
1156                                 cycles_text);
1157
1158                         ctx->current_pc = next_pc;
1159
1160                         /* packets for an instruction don't start on or before the preceding
1161                          * functional pipestat (i.e. other than WT or TD)
1162                          */
1163                         if (ctx->data_index <= ctx->pipe_index)
1164                         {
1165                                 ctx->data_index = ctx->pipe_index + 1;
1166                                 ctx->data_half = 0;
1167                         }
1168                 }
1169
1170                 ctx->pipe_index += 1;
1171         }
1172
1173         return ERROR_OK;
1174 }
1175
1176 static COMMAND_HELPER(handle_etm_tracemode_command_update,
1177                 etmv1_tracemode_t *mode)
1178 {
1179         etmv1_tracemode_t tracemode;
1180
1181         /* what parts of data access are traced? */
1182         if (strcmp(CMD_ARGV[0], "none") == 0)
1183                 tracemode = ETMV1_TRACE_NONE;
1184         else if (strcmp(CMD_ARGV[0], "data") == 0)
1185                 tracemode = ETMV1_TRACE_DATA;
1186         else if (strcmp(CMD_ARGV[0], "address") == 0)
1187                 tracemode = ETMV1_TRACE_ADDR;
1188         else if (strcmp(CMD_ARGV[0], "all") == 0)
1189                 tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
1190         else
1191         {
1192                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
1193                 return ERROR_INVALID_ARGUMENTS;
1194         }
1195
1196         uint8_t context_id;
1197         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id);
1198         switch (context_id)
1199         {
1200         case 0:
1201                 tracemode |= ETMV1_CONTEXTID_NONE;
1202                 break;
1203         case 8:
1204                 tracemode |= ETMV1_CONTEXTID_8;
1205                 break;
1206         case 16:
1207                 tracemode |= ETMV1_CONTEXTID_16;
1208                 break;
1209         case 32:
1210                 tracemode |= ETMV1_CONTEXTID_32;
1211                 break;
1212         default:
1213                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
1214                 return ERROR_INVALID_ARGUMENTS;
1215         }
1216
1217         if (strcmp(CMD_ARGV[2], "enable") == 0)
1218                 tracemode |= ETMV1_CYCLE_ACCURATE;
1219         else if (strcmp(CMD_ARGV[2], "disable") == 0)
1220                 tracemode |= 0;
1221         else
1222         {
1223                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[2]);
1224                 return ERROR_INVALID_ARGUMENTS;
1225         }
1226
1227         if (strcmp(CMD_ARGV[3], "enable") == 0)
1228                 tracemode |= ETMV1_BRANCH_OUTPUT;
1229         else if (strcmp(CMD_ARGV[3], "disable") == 0)
1230                 tracemode |= 0;
1231         else
1232         {
1233                 command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[3]);
1234                 return ERROR_INVALID_ARGUMENTS;
1235         }
1236
1237         /* IGNORED:
1238          *  - CPRT tracing (coprocessor register transfers)
1239          *  - debug request (causes debug entry on trigger)
1240          *  - stall on FIFOFULL (preventing tracedata lossage)
1241          */
1242         *mode = tracemode;
1243
1244         return ERROR_OK;
1245 }
1246
1247 COMMAND_HANDLER(handle_etm_tracemode_command)
1248 {
1249         struct target *target = get_current_target(CMD_CTX);
1250         struct arm *arm = target_to_arm(target);
1251         struct etm_context *etm;
1252
1253         if (!is_arm(arm)) {
1254                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1255                 return ERROR_FAIL;
1256         }
1257
1258         etm = arm->etm;
1259         if (!etm) {
1260                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1261                 return ERROR_FAIL;
1262         }
1263
1264         etmv1_tracemode_t tracemode = etm->tracemode;
1265
1266         switch (CMD_ARGC)
1267         {
1268         case 0:
1269                 break;
1270         case 4:
1271                 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode);
1272                 break;
1273         default:
1274                 command_print(CMD_CTX, "usage: configure trace mode "
1275                                 "<none | data | address | all> "
1276                                 "<context id bits> <cycle accurate> <branch output>");
1277                 return ERROR_FAIL;
1278         }
1279
1280         /**
1281          * todo: fail if parameters were invalid for this hardware,
1282          * or couldn't be written; display actual hardware state...
1283          */
1284
1285         command_print(CMD_CTX, "current tracemode configuration:");
1286
1287         switch (tracemode & ETMV1_TRACE_MASK)
1288         {
1289                 case ETMV1_TRACE_NONE:
1290                         command_print(CMD_CTX, "data tracing: none");
1291                         break;
1292                 case ETMV1_TRACE_DATA:
1293                         command_print(CMD_CTX, "data tracing: data only");
1294                         break;
1295                 case ETMV1_TRACE_ADDR:
1296                         command_print(CMD_CTX, "data tracing: address only");
1297                         break;
1298                 case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
1299                         command_print(CMD_CTX, "data tracing: address and data");
1300                         break;
1301         }
1302
1303         switch (tracemode & ETMV1_CONTEXTID_MASK)
1304         {
1305                 case ETMV1_CONTEXTID_NONE:
1306                         command_print(CMD_CTX, "contextid tracing: none");
1307                         break;
1308                 case ETMV1_CONTEXTID_8:
1309                         command_print(CMD_CTX, "contextid tracing: 8 bit");
1310                         break;
1311                 case ETMV1_CONTEXTID_16:
1312                         command_print(CMD_CTX, "contextid tracing: 16 bit");
1313                         break;
1314                 case ETMV1_CONTEXTID_32:
1315                         command_print(CMD_CTX, "contextid tracing: 32 bit");
1316                         break;
1317         }
1318
1319         if (tracemode & ETMV1_CYCLE_ACCURATE)
1320         {
1321                 command_print(CMD_CTX, "cycle-accurate tracing enabled");
1322         }
1323         else
1324         {
1325                 command_print(CMD_CTX, "cycle-accurate tracing disabled");
1326         }
1327
1328         if (tracemode & ETMV1_BRANCH_OUTPUT)
1329         {
1330                 command_print(CMD_CTX, "full branch address output enabled");
1331         }
1332         else
1333         {
1334                 command_print(CMD_CTX, "full branch address output disabled");
1335         }
1336
1337         /* only update ETM_CTRL register if tracemode changed */
1338         if (etm->tracemode != tracemode)
1339         {
1340                 struct reg *etm_ctrl_reg;
1341
1342                 etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
1343                 if (!etm_ctrl_reg)
1344                         return ERROR_FAIL;
1345
1346                 etm_get_reg(etm_ctrl_reg);
1347
1348                 buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
1349                 buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
1350                 buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
1351                 buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
1352                 etm_store_reg(etm_ctrl_reg);
1353
1354                 etm->tracemode = tracemode;
1355
1356                 /* invalidate old trace data */
1357                 etm->capture_status = TRACE_IDLE;
1358                 if (etm->trace_depth > 0)
1359                 {
1360                         free(etm->trace_data);
1361                         etm->trace_data = NULL;
1362                 }
1363                 etm->trace_depth = 0;
1364         }
1365
1366         return ERROR_OK;
1367 }
1368
1369 COMMAND_HANDLER(handle_etm_config_command)
1370 {
1371         struct target *target;
1372         struct arm *arm;
1373         etm_portmode_t portmode = 0x0;
1374         struct etm_context *etm_ctx;
1375         int i;
1376
1377         if (CMD_ARGC != 5)
1378                 return ERROR_COMMAND_SYNTAX_ERROR;
1379
1380         target = get_target(CMD_ARGV[0]);
1381         if (!target)
1382         {
1383                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
1384                 return ERROR_FAIL;
1385         }
1386
1387         arm = target_to_arm(target);
1388         if (!is_arm(arm)) {
1389                 command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
1390                                 target->cmd_name, target_get_name(target));
1391                 return ERROR_FAIL;
1392         }
1393
1394         /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1395          * version we'll be using!! -- so we can't know how to validate
1396          * params yet.  "etm config" should likely be *AFTER* hookup...
1397          *
1398          *  - Many more widths might be supported ... and we can easily
1399          *    check whether our setting "took".
1400          *
1401          *  - The "clock" and "mode" bits are interpreted differently.
1402          *    See ARM IHI 0014O table 2-17 for the old behavior, and
1403          *    table 2-18 for the new.  With ETB it's best to specify
1404          *    "normal full" ...
1405          */
1406         uint8_t port_width;
1407         COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width);
1408         switch (port_width)
1409         {
1410                 /* before ETMv3.0 */
1411                 case 4:
1412                         portmode |= ETM_PORT_4BIT;
1413                         break;
1414                 case 8:
1415                         portmode |= ETM_PORT_8BIT;
1416                         break;
1417                 case 16:
1418                         portmode |= ETM_PORT_16BIT;
1419                         break;
1420                 /* ETMv3.0 and later*/
1421                 case 24:
1422                         portmode |= ETM_PORT_24BIT;
1423                         break;
1424                 case 32:
1425                         portmode |= ETM_PORT_32BIT;
1426                         break;
1427                 case 48:
1428                         portmode |= ETM_PORT_48BIT;
1429                         break;
1430                 case 64:
1431                         portmode |= ETM_PORT_64BIT;
1432                         break;
1433                 case 1:
1434                         portmode |= ETM_PORT_1BIT;
1435                         break;
1436                 case 2:
1437                         portmode |= ETM_PORT_2BIT;
1438                         break;
1439                 default:
1440                         command_print(CMD_CTX,
1441                                 "unsupported ETM port width '%s'", CMD_ARGV[1]);
1442                         return ERROR_FAIL;
1443         }
1444
1445         if (strcmp("normal", CMD_ARGV[2]) == 0)
1446         {
1447                 portmode |= ETM_PORT_NORMAL;
1448         }
1449         else if (strcmp("multiplexed", CMD_ARGV[2]) == 0)
1450         {
1451                 portmode |= ETM_PORT_MUXED;
1452         }
1453         else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
1454         {
1455                 portmode |= ETM_PORT_DEMUXED;
1456         }
1457         else
1458         {
1459                 command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]);
1460                 return ERROR_FAIL;
1461         }
1462
1463         if (strcmp("half", CMD_ARGV[3]) == 0)
1464         {
1465                 portmode |= ETM_PORT_HALF_CLOCK;
1466         }
1467         else if (strcmp("full", CMD_ARGV[3]) == 0)
1468         {
1469                 portmode |= ETM_PORT_FULL_CLOCK;
1470         }
1471         else
1472         {
1473                 command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]);
1474                 return ERROR_FAIL;
1475         }
1476
1477         etm_ctx = calloc(1, sizeof(struct etm_context));
1478         if (!etm_ctx) {
1479                 LOG_DEBUG("out of memory");
1480                 return ERROR_FAIL;
1481         }
1482
1483         for (i = 0; etm_capture_drivers[i]; i++)
1484         {
1485                 if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0)
1486                 {
1487                         int retval;
1488                         if ((retval = etm_capture_drivers[i]->register_commands(CMD_CTX)) != ERROR_OK)
1489                         {
1490                                 free(etm_ctx);
1491                                 return retval;
1492                         }
1493
1494                         etm_ctx->capture_driver = etm_capture_drivers[i];
1495
1496                         break;
1497                 }
1498         }
1499
1500         if (!etm_capture_drivers[i])
1501         {
1502                 /* no supported capture driver found, don't register an ETM */
1503                 free(etm_ctx);
1504                 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]);
1505                 return ERROR_FAIL;
1506         }
1507
1508         etm_ctx->target = target;
1509         etm_ctx->trigger_percent = 50;
1510         etm_ctx->trace_data = NULL;
1511         etm_ctx->portmode = portmode;
1512         etm_ctx->core_state = ARMV4_5_STATE_ARM;
1513
1514         arm->etm = etm_ctx;
1515
1516         return etm_register_user_commands(CMD_CTX);
1517 }
1518
1519 COMMAND_HANDLER(handle_etm_info_command)
1520 {
1521         struct target *target;
1522         struct arm *arm;
1523         struct etm_context *etm;
1524         struct reg *etm_sys_config_reg;
1525         int max_port_size;
1526         uint32_t config;
1527
1528         target = get_current_target(CMD_CTX);
1529         arm = target_to_arm(target);
1530         if (!is_arm(arm))
1531         {
1532                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1533                 return ERROR_FAIL;
1534         }
1535
1536         etm = arm->etm;
1537         if (!etm)
1538         {
1539                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1540                 return ERROR_FAIL;
1541         }
1542
1543         command_print(CMD_CTX, "ETM v%d.%d",
1544                         etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
1545         command_print(CMD_CTX, "pairs of address comparators: %i",
1546                         (int) (etm->config >> 0) & 0x0f);
1547         command_print(CMD_CTX, "data comparators: %i",
1548                         (int) (etm->config >> 4) & 0x0f);
1549         command_print(CMD_CTX, "memory map decoders: %i",
1550                         (int) (etm->config >> 8) & 0x1f);
1551         command_print(CMD_CTX, "number of counters: %i",
1552                         (int) (etm->config >> 13) & 0x07);
1553         command_print(CMD_CTX, "sequencer %spresent",
1554                         (int) (etm->config & (1 << 16)) ? "" : "not ");
1555         command_print(CMD_CTX, "number of ext. inputs: %i",
1556                         (int) (etm->config >> 17) & 0x07);
1557         command_print(CMD_CTX, "number of ext. outputs: %i",
1558                         (int) (etm->config >> 20) & 0x07);
1559         command_print(CMD_CTX, "FIFO full %spresent",
1560                         (int) (etm->config & (1 << 23)) ? "" : "not ");
1561         if (etm->bcd_vers < 0x20)
1562                 command_print(CMD_CTX, "protocol version: %i",
1563                                 (int) (etm->config >> 28) & 0x07);
1564         else {
1565                 command_print(CMD_CTX,
1566                                 "coprocessor and memory access %ssupported",
1567                                 (etm->config & (1 << 26)) ? "" : "not ");
1568                 command_print(CMD_CTX, "trace start/stop %spresent",
1569                                 (etm->config & (1 << 26)) ? "" : "not ");
1570                 command_print(CMD_CTX, "number of context comparators: %i",
1571                                 (int) (etm->config >> 24) & 0x03);
1572         }
1573
1574         /* SYS_CONFIG isn't present before ETMv1.2 */
1575         etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
1576         if (!etm_sys_config_reg)
1577                 return ERROR_OK;
1578
1579         etm_get_reg(etm_sys_config_reg);
1580         config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
1581
1582         LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
1583
1584         max_port_size = config & 0x7;
1585         if (etm->bcd_vers >= 0x30)
1586                 max_port_size |= (config >> 6) & 0x08;
1587         switch (max_port_size)
1588         {
1589                 /* before ETMv3.0 */
1590                 case 0:
1591                         max_port_size = 4;
1592                         break;
1593                 case 1:
1594                         max_port_size = 8;
1595                         break;
1596                 case 2:
1597                         max_port_size = 16;
1598                         break;
1599                 /* ETMv3.0 and later*/
1600                 case 3:
1601                         max_port_size = 24;
1602                         break;
1603                 case 4:
1604                         max_port_size = 32;
1605                         break;
1606                 case 5:
1607                         max_port_size = 48;
1608                         break;
1609                 case 6:
1610                         max_port_size = 64;
1611                         break;
1612                 case 8:
1613                         max_port_size = 1;
1614                         break;
1615                 case 9:
1616                         max_port_size = 2;
1617                         break;
1618                 default:
1619                         LOG_ERROR("Illegal max_port_size");
1620                         return ERROR_FAIL;
1621         }
1622         command_print(CMD_CTX, "max. port size: %i", max_port_size);
1623
1624         if (etm->bcd_vers < 0x30) {
1625                 command_print(CMD_CTX, "half-rate clocking %ssupported",
1626                                 (config & (1 << 3)) ? "" : "not ");
1627                 command_print(CMD_CTX, "full-rate clocking %ssupported",
1628                                 (config & (1 << 4)) ? "" : "not ");
1629                 command_print(CMD_CTX, "normal trace format %ssupported",
1630                                 (config & (1 << 5)) ? "" : "not ");
1631                 command_print(CMD_CTX, "multiplex trace format %ssupported",
1632                                 (config & (1 << 6)) ? "" : "not ");
1633                 command_print(CMD_CTX, "demultiplex trace format %ssupported",
1634                                 (config & (1 << 7)) ? "" : "not ");
1635         } else {
1636                 /* REVISIT show which size and format are selected ... */
1637                 command_print(CMD_CTX, "current port size %ssupported",
1638                                 (config & (1 << 10)) ? "" : "not ");
1639                 command_print(CMD_CTX, "current trace format %ssupported",
1640                                 (config & (1 << 11)) ? "" : "not ");
1641         }
1642         if (etm->bcd_vers >= 0x21)
1643                 command_print(CMD_CTX, "fetch comparisons %ssupported",
1644                                 (config & (1 << 17)) ? "not " : "");
1645         command_print(CMD_CTX, "FIFO full %ssupported",
1646                         (config & (1 << 8)) ? "" : "not ");
1647
1648         return ERROR_OK;
1649 }
1650
1651 COMMAND_HANDLER(handle_etm_status_command)
1652 {
1653         struct target *target;
1654         struct arm *arm;
1655         struct etm_context *etm;
1656         trace_status_t trace_status;
1657
1658         target = get_current_target(CMD_CTX);
1659         arm = target_to_arm(target);
1660         if (!is_arm(arm))
1661         {
1662                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1663                 return ERROR_FAIL;
1664         }
1665
1666         etm = arm->etm;
1667         if (!etm)
1668         {
1669                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1670                 return ERROR_FAIL;
1671         }
1672
1673         /* ETM status */
1674         if (etm->bcd_vers >= 0x11) {
1675                 struct reg *reg;
1676
1677                 reg = etm_reg_lookup(etm, ETM_STATUS);
1678                 if (!reg)
1679                         return ERROR_FAIL;
1680                 if (etm_get_reg(reg) == ERROR_OK) {
1681                         unsigned s = buf_get_u32(reg->value, 0, reg->size);
1682
1683                         command_print(CMD_CTX, "etm: %s%s%s%s",
1684                                 /* bit(1) == progbit */
1685                                 (etm->bcd_vers >= 0x12)
1686                                         ? ((s & (1 << 1))
1687                                                 ? "disabled" : "enabled")
1688                                         : "?",
1689                                 ((s & (1 << 3)) && etm->bcd_vers >= 0x31)
1690                                         ? " triggered" : "",
1691                                 ((s & (1 << 2)) && etm->bcd_vers >= 0x12)
1692                                         ? " start/stop" : "",
1693                                 ((s & (1 << 0)) && etm->bcd_vers >= 0x11)
1694                                         ? " untraced-overflow" : "");
1695                 } /* else ignore and try showing trace port status */
1696         }
1697
1698         /* Trace Port Driver status */
1699         trace_status = etm->capture_driver->status(etm);
1700         if (trace_status == TRACE_IDLE)
1701         {
1702                 command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
1703         }
1704         else
1705         {
1706                 static char *completed = " completed";
1707                 static char *running = " is running";
1708                 static char *overflowed = ", overflowed";
1709                 static char *triggered = ", triggered";
1710
1711                 command_print(CMD_CTX, "%s: trace collection%s%s%s",
1712                         etm->capture_driver->name,
1713                         (trace_status & TRACE_RUNNING) ? running : completed,
1714                         (trace_status & TRACE_OVERFLOWED) ? overflowed : "",
1715                         (trace_status & TRACE_TRIGGERED) ? triggered : "");
1716
1717                 if (etm->trace_depth > 0)
1718                 {
1719                         command_print(CMD_CTX, "%i frames of trace data read",
1720                                         (int)(etm->trace_depth));
1721                 }
1722         }
1723
1724         return ERROR_OK;
1725 }
1726
1727 COMMAND_HANDLER(handle_etm_image_command)
1728 {
1729         struct target *target;
1730         struct arm *arm;
1731         struct etm_context *etm_ctx;
1732
1733         if (CMD_ARGC < 1)
1734         {
1735                 command_print(CMD_CTX, "usage: etm image <file> [base address] [type]");
1736                 return ERROR_FAIL;
1737         }
1738
1739         target = get_current_target(CMD_CTX);
1740         arm = target_to_arm(target);
1741         if (!is_arm(arm))
1742         {
1743                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1744                 return ERROR_FAIL;
1745         }
1746
1747         etm_ctx = arm->etm;
1748         if (!etm_ctx)
1749         {
1750                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1751                 return ERROR_FAIL;
1752         }
1753
1754         if (etm_ctx->image)
1755         {
1756                 image_close(etm_ctx->image);
1757                 free(etm_ctx->image);
1758                 command_print(CMD_CTX, "previously loaded image found and closed");
1759         }
1760
1761         etm_ctx->image = malloc(sizeof(struct image));
1762         etm_ctx->image->base_address_set = 0;
1763         etm_ctx->image->start_address_set = 0;
1764
1765         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1766         if (CMD_ARGC >= 2)
1767         {
1768                 etm_ctx->image->base_address_set = 1;
1769                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], etm_ctx->image->base_address);
1770         }
1771         else
1772         {
1773                 etm_ctx->image->base_address_set = 0;
1774         }
1775
1776         if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK)
1777         {
1778                 free(etm_ctx->image);
1779                 etm_ctx->image = NULL;
1780                 return ERROR_FAIL;
1781         }
1782
1783         return ERROR_OK;
1784 }
1785
1786 COMMAND_HANDLER(handle_etm_dump_command)
1787 {
1788         struct fileio file;
1789         struct target *target;
1790         struct arm *arm;
1791         struct etm_context *etm_ctx;
1792         uint32_t i;
1793
1794         if (CMD_ARGC != 1)
1795         {
1796                 command_print(CMD_CTX, "usage: etm dump <file>");
1797                 return ERROR_FAIL;
1798         }
1799
1800         target = get_current_target(CMD_CTX);
1801         arm = target_to_arm(target);
1802         if (!is_arm(arm))
1803         {
1804                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1805                 return ERROR_FAIL;
1806         }
1807
1808         etm_ctx = arm->etm;
1809         if (!etm_ctx)
1810         {
1811                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1812                 return ERROR_FAIL;
1813         }
1814
1815         if (etm_ctx->capture_driver->status == TRACE_IDLE)
1816         {
1817                 command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
1818                 return ERROR_OK;
1819         }
1820
1821         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1822         {
1823                 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1824                 command_print(CMD_CTX, "trace capture not completed");
1825                 return ERROR_FAIL;
1826         }
1827
1828         /* read the trace data if it wasn't read already */
1829         if (etm_ctx->trace_depth == 0)
1830                 etm_ctx->capture_driver->read_trace(etm_ctx);
1831
1832         if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1833         {
1834                 return ERROR_FAIL;
1835         }
1836
1837         fileio_write_u32(&file, etm_ctx->capture_status);
1838         fileio_write_u32(&file, etm_ctx->portmode);
1839         fileio_write_u32(&file, etm_ctx->tracemode);
1840         fileio_write_u32(&file, etm_ctx->trace_depth);
1841
1842         for (i = 0; i < etm_ctx->trace_depth; i++)
1843         {
1844                 fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat);
1845                 fileio_write_u32(&file, etm_ctx->trace_data[i].packet);
1846                 fileio_write_u32(&file, etm_ctx->trace_data[i].flags);
1847         }
1848
1849         fileio_close(&file);
1850
1851         return ERROR_OK;
1852 }
1853
1854 COMMAND_HANDLER(handle_etm_load_command)
1855 {
1856         struct fileio file;
1857         struct target *target;
1858         struct arm *arm;
1859         struct etm_context *etm_ctx;
1860         uint32_t i;
1861
1862         if (CMD_ARGC != 1)
1863         {
1864                 command_print(CMD_CTX, "usage: etm load <file>");
1865                 return ERROR_FAIL;
1866         }
1867
1868         target = get_current_target(CMD_CTX);
1869         arm = target_to_arm(target);
1870         if (!is_arm(arm))
1871         {
1872                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1873                 return ERROR_FAIL;
1874         }
1875
1876         etm_ctx = arm->etm;
1877         if (!etm_ctx)
1878         {
1879                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1880                 return ERROR_FAIL;
1881         }
1882
1883         if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING)
1884         {
1885                 command_print(CMD_CTX, "trace capture running, stop first");
1886                 return ERROR_FAIL;
1887         }
1888
1889         if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1890         {
1891                 return ERROR_FAIL;
1892         }
1893
1894         if (file.size % 4)
1895         {
1896                 command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
1897                 fileio_close(&file);
1898                 return ERROR_FAIL;
1899         }
1900
1901         if (etm_ctx->trace_depth > 0)
1902         {
1903                 free(etm_ctx->trace_data);
1904                 etm_ctx->trace_data = NULL;
1905         }
1906
1907         {
1908           uint32_t tmp;
1909           fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
1910           fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
1911           fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
1912           fileio_read_u32(&file, &etm_ctx->trace_depth);
1913         }
1914         etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
1915         if (etm_ctx->trace_data == NULL)
1916         {
1917                 command_print(CMD_CTX, "not enough memory to perform operation");
1918                 fileio_close(&file);
1919                 return ERROR_FAIL;
1920         }
1921
1922         for (i = 0; i < etm_ctx->trace_depth; i++)
1923         {
1924                 uint32_t pipestat, packet, flags;
1925                 fileio_read_u32(&file, &pipestat);
1926                 fileio_read_u32(&file, &packet);
1927                 fileio_read_u32(&file, &flags);
1928                 etm_ctx->trace_data[i].pipestat = pipestat & 0xff;
1929                 etm_ctx->trace_data[i].packet = packet & 0xffff;
1930                 etm_ctx->trace_data[i].flags = flags;
1931         }
1932
1933         fileio_close(&file);
1934
1935         return ERROR_OK;
1936 }
1937
1938 COMMAND_HANDLER(handle_etm_trigger_percent_command)
1939 {
1940         struct target *target;
1941         struct arm *arm;
1942         struct etm_context *etm_ctx;
1943
1944         target = get_current_target(CMD_CTX);
1945         arm = target_to_arm(target);
1946         if (!is_arm(arm))
1947         {
1948                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1949                 return ERROR_FAIL;
1950         }
1951
1952         etm_ctx = arm->etm;
1953         if (!etm_ctx)
1954         {
1955                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1956                 return ERROR_FAIL;
1957         }
1958
1959         if (CMD_ARGC > 0)
1960         {
1961                 uint32_t new_value;
1962                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
1963
1964                 if ((new_value < 2) || (new_value > 100))
1965                 {
1966                         command_print(CMD_CTX, "valid settings are 2%% to 100%%");
1967                 }
1968                 else
1969                 {
1970                         etm_ctx->trigger_percent = new_value;
1971                 }
1972         }
1973
1974         command_print(CMD_CTX, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
1975
1976         return ERROR_OK;
1977 }
1978
1979 COMMAND_HANDLER(handle_etm_start_command)
1980 {
1981         struct target *target;
1982         struct arm *arm;
1983         struct etm_context *etm_ctx;
1984         struct reg *etm_ctrl_reg;
1985
1986         target = get_current_target(CMD_CTX);
1987         arm = target_to_arm(target);
1988         if (!is_arm(arm))
1989         {
1990                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
1991                 return ERROR_FAIL;
1992         }
1993
1994         etm_ctx = arm->etm;
1995         if (!etm_ctx)
1996         {
1997                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
1998                 return ERROR_FAIL;
1999         }
2000
2001         /* invalidate old tracing data */
2002         etm_ctx->capture_status = TRACE_IDLE;
2003         if (etm_ctx->trace_depth > 0)
2004         {
2005                 free(etm_ctx->trace_data);
2006                 etm_ctx->trace_data = NULL;
2007         }
2008         etm_ctx->trace_depth = 0;
2009
2010         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2011         if (!etm_ctrl_reg)
2012                 return ERROR_FAIL;
2013
2014         etm_get_reg(etm_ctrl_reg);
2015
2016         /* Clear programming bit (10), set port selection bit (11) */
2017         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x2);
2018
2019         etm_store_reg(etm_ctrl_reg);
2020         jtag_execute_queue();
2021
2022         etm_ctx->capture_driver->start_capture(etm_ctx);
2023
2024         return ERROR_OK;
2025 }
2026
2027 COMMAND_HANDLER(handle_etm_stop_command)
2028 {
2029         struct target *target;
2030         struct arm *arm;
2031         struct etm_context *etm_ctx;
2032         struct reg *etm_ctrl_reg;
2033
2034         target = get_current_target(CMD_CTX);
2035         arm = target_to_arm(target);
2036         if (!is_arm(arm))
2037         {
2038                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2039                 return ERROR_FAIL;
2040         }
2041
2042         etm_ctx = arm->etm;
2043         if (!etm_ctx)
2044         {
2045                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2046                 return ERROR_FAIL;
2047         }
2048
2049         etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
2050         if (!etm_ctrl_reg)
2051                 return ERROR_FAIL;
2052
2053         etm_get_reg(etm_ctrl_reg);
2054
2055         /* Set programming bit (10), clear port selection bit (11) */
2056         buf_set_u32(etm_ctrl_reg->value, 10, 2, 0x1);
2057
2058         etm_store_reg(etm_ctrl_reg);
2059         jtag_execute_queue();
2060
2061         etm_ctx->capture_driver->stop_capture(etm_ctx);
2062
2063         return ERROR_OK;
2064 }
2065
2066 COMMAND_HANDLER(handle_etm_analyze_command)
2067 {
2068         struct target *target;
2069         struct arm *arm;
2070         struct etm_context *etm_ctx;
2071         int retval;
2072
2073         target = get_current_target(CMD_CTX);
2074         arm = target_to_arm(target);
2075         if (!is_arm(arm))
2076         {
2077                 command_print(CMD_CTX, "ETM: current target isn't an ARM");
2078                 return ERROR_FAIL;
2079         }
2080
2081         etm_ctx = arm->etm;
2082         if (!etm_ctx)
2083         {
2084                 command_print(CMD_CTX, "current target doesn't have an ETM configured");
2085                 return ERROR_FAIL;
2086         }
2087
2088         if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK)
2089         {
2090                 switch (retval)
2091                 {
2092                         case ERROR_ETM_ANALYSIS_FAILED:
2093                                 command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data");
2094                                 break;
2095                         case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
2096                                 command_print(CMD_CTX, "no instruction for current address available, analysis aborted");
2097                                 break;
2098                         case ERROR_TRACE_IMAGE_UNAVAILABLE:
2099                                 command_print(CMD_CTX, "no image available for trace analysis");
2100                                 break;
2101                         default:
2102                                 command_print(CMD_CTX, "unknown error: %i", retval);
2103                 }
2104         }
2105
2106         return retval;
2107 }
2108
2109 int etm_register_commands(struct command_context *cmd_ctx)
2110 {
2111         etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell");
2112
2113         register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command,
2114                 COMMAND_CONFIG, "etm config <target> <port_width> <port_mode> <clocking> <capture_driver>");
2115
2116         return ERROR_OK;
2117 }
2118
2119 static int etm_register_user_commands(struct command_context *cmd_ctx)
2120 {
2121         register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
2122                 COMMAND_EXEC, "configure/display trace mode: "
2123                         "<none | data | address | all> "
2124                         "<context_id_bits> <cycle_accurate> <branch_output>");
2125
2126         register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,
2127                 COMMAND_EXEC, "display info about the current target's ETM");
2128
2129         register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command,
2130                 COMMAND_EXEC, "amount (<percent>) of trace buffer to be filled after the trigger occured");
2131         register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command,
2132                 COMMAND_EXEC, "display current target's ETM status");
2133         register_command(cmd_ctx, etm_cmd, "start", handle_etm_start_command,
2134                 COMMAND_EXEC, "start ETM trace collection");
2135         register_command(cmd_ctx, etm_cmd, "stop", handle_etm_stop_command,
2136                 COMMAND_EXEC, "stop ETM trace collection");
2137
2138         register_command(cmd_ctx, etm_cmd, "analyze", handle_etm_analyze_command,
2139                 COMMAND_EXEC, "anaylze collected ETM trace");
2140
2141         register_command(cmd_ctx, etm_cmd, "image", handle_etm_image_command,
2142                 COMMAND_EXEC, "load image from <file> [base address]");
2143
2144         register_command(cmd_ctx, etm_cmd, "dump", handle_etm_dump_command,
2145                 COMMAND_EXEC, "dump captured trace data <file>");
2146         register_command(cmd_ctx, etm_cmd, "load", handle_etm_load_command,
2147                 COMMAND_EXEC, "load trace data for analysis <file>");
2148
2149         return ERROR_OK;
2150 }