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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include <string.h>
  25
  26 #include "arm7_9_common.h"
  27 #include "etb.h"
  28 #include "etm.h"
  29
  30 #include "log.h"
  31 #include "types.h"
  32 #include "binarybuffer.h"
  33 #include "target.h"
  34 #include "register.h"
  35 #include "jtag.h"
  36
  37 #include <stdlib.h>
  38
  39 static char* etb_reg_list[] =
  40 {
  41         "ETB_identification",
  42         "ETB_ram_depth",
  43         "ETB_ram_width",
  44         "ETB_status",
  45         "ETB_ram_data",
  46         "ETB_ram_read_pointer",
  47         "ETB_ram_write_pointer",
  48         "ETB_trigger_counter",
  49         "ETB_control",
  50 };
  51
  52 static int etb_reg_arch_type = -1;
  53
  54 static int etb_get_reg(reg_t *reg);
  55
  56 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  57
  58 static int etb_set_instr(etb_t *etb, u32 new_instr)
  59 {
  60         jtag_tap_t *tap;
  61         tap = etb->tap;
  62         if (tap==NULL)
  63                 return ERROR_FAIL;
  64
  65         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
  66         {
  67                 scan_field_t field;
  68
  69                 field.tap = tap;
  70                 field.num_bits = tap->ir_length;
  71                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  72                 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
  73
  74                 field.in_value = NULL;
  75
  76
  77                 field.in_handler = NULL;
  78
  79
  80                 jtag_add_ir_scan(1, &field, TAP_INVALID);
  81
  82                 free(field.out_value);
  83         }
  84
  85         return ERROR_OK;
  86 }
  87
  88 static int etb_scann(etb_t *etb, u32 new_scan_chain)
  89 {
  90         if(etb->cur_scan_chain != new_scan_chain)
  91         {
  92                 scan_field_t field;
  93
  94                 field.tap = etb->tap;
  95                 field.num_bits = 5;
  96                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);
  97                 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
  98
  99                 field.in_value = NULL;
 100
 101
 102                 field.in_handler = NULL;
 103
 104
 105                 /* select INTEST instruction */
 106                 etb_set_instr(etb, 0x2);
 107                 jtag_add_dr_scan(1, &field, TAP_INVALID);
 108
 109                 etb->cur_scan_chain = new_scan_chain;
 110
 111                 free(field.out_value);
 112         }
 113
 114         return ERROR_OK;
 115 }
 116
 117 reg_cache_t* etb_build_reg_cache(etb_t *etb)
 118 {
 119         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 120         reg_t *reg_list = NULL;
 121         etb_reg_t *arch_info = NULL;
 122         int num_regs = 9;
 123         int i;
 124
 125         /* register a register arch-type for etm registers only once */
 126         if (etb_reg_arch_type == -1)
 127                 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
 128
 129         /* the actual registers are kept in two arrays */
 130         reg_list = calloc(num_regs, sizeof(reg_t));
 131         arch_info = calloc(num_regs, sizeof(etb_reg_t));
 132
 133         /* fill in values for the reg cache */
 134         reg_cache->name = "etb registers";
 135         reg_cache->next = NULL;
 136         reg_cache->reg_list = reg_list;
 137         reg_cache->num_regs = num_regs;
 138
 139         /* set up registers */
 140         for (i = 0; i < num_regs; i++)
 141         {
 142                 reg_list[i].name = etb_reg_list[i];
 143                 reg_list[i].size = 32;
 144                 reg_list[i].dirty = 0;
 145                 reg_list[i].valid = 0;
 146                 reg_list[i].bitfield_desc = NULL;
 147                 reg_list[i].num_bitfields = 0;
 148                 reg_list[i].value = calloc(1, 4);
 149                 reg_list[i].arch_info = &arch_info[i];
 150                 reg_list[i].arch_type = etb_reg_arch_type;
 151                 reg_list[i].size = 32;
 152                 arch_info[i].addr = i;
 153                 arch_info[i].etb = etb;
 154         }
 155
 156         return reg_cache;
 157 }
 158
 159 static int etb_get_reg(reg_t *reg)
 160 {
 161         int retval;
 162         if ((retval = etb_read_reg(reg)) != ERROR_OK)
 163         {
 164                 LOG_ERROR("BUG: error scheduling etm register read");
 165                 return retval;
 166         }
 167
 168         if ((retval = jtag_execute_queue()) != ERROR_OK)
 169         {
 170                 LOG_ERROR("register read failed");
 171                 return retval;
 172         }
 173
 174         return ERROR_OK;
 175 }
 176
 177 static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
 178 {
 179         scan_field_t fields[3];
 180         int i;
 181
 182         jtag_add_end_state(TAP_IDLE);
 183         etb_scann(etb, 0x0);
 184         etb_set_instr(etb, 0xc);
 185
 186         fields[0].tap = etb->tap;
 187         fields[0].num_bits = 32;
 188         fields[0].out_value = NULL;
 189
 190         fields[0].in_value = NULL;
 191
 192
 193         fields[0].in_handler = NULL;
 194
 195
 196         fields[1].tap = etb->tap;
 197         fields[1].num_bits = 7;
 198         fields[1].out_value = malloc(1);
 199         buf_set_u32(fields[1].out_value, 0, 7, 4);
 200
 201         fields[1].in_value = NULL;
 202
 203
 204         fields[1].in_handler = NULL;
 205
 206
 207         fields[2].tap = etb->tap;
 208         fields[2].num_bits = 1;
 209         fields[2].out_value = malloc(1);
 210         buf_set_u32(fields[2].out_value, 0, 1, 0);
 211
 212         fields[2].in_value = NULL;
 213
 214
 215         fields[2].in_handler = NULL;
 216
 217
 218         jtag_add_dr_scan(3, fields, TAP_INVALID);
 219
 220         fields[0].in_handler = buf_to_u32_handler; /* deprecated! invoke this from user code! */
 221
 222         for (i = 0; i < num_frames; i++)
 223         {
 224                 /* ensure nR/W reamins set to read */
 225                 buf_set_u32(fields[2].out_value, 0, 1, 0);
 226
 227                 /* address remains set to 0x4 (RAM data) until we read the last frame */
 228                 if (i < num_frames - 1)
 229                         buf_set_u32(fields[1].out_value, 0, 7, 4);
 230                 else
 231                         buf_set_u32(fields[1].out_value, 0, 7, 0);
 232
 233                 fields[0].in_handler_priv = &data[i];
 234                 jtag_add_dr_scan(3, fields, TAP_INVALID);
 235         }
 236
 237         jtag_execute_queue();
 238
 239         free(fields[1].out_value);
 240         free(fields[2].out_value);
 241
 242         return ERROR_OK;
 243 }
 244
 245 int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 246 {
 247         etb_reg_t *etb_reg = reg->arch_info;
 248         u8 reg_addr = etb_reg->addr & 0x7f;
 249         scan_field_t fields[3];
 250
 251         LOG_DEBUG("%i", etb_reg->addr);
 252
 253         jtag_add_end_state(TAP_IDLE);
 254         etb_scann(etb_reg->etb, 0x0);
 255         etb_set_instr(etb_reg->etb, 0xc);
 256
 257         fields[0].tap = etb_reg->etb->tap;
 258         fields[0].num_bits = 32;
 259         fields[0].out_value = reg->value;
 260
 261         fields[0].in_value = NULL;
 262
 263
 264         fields[0].in_handler = NULL;
 265
 266
 267         fields[1].tap = etb_reg->etb->tap;
 268         fields[1].num_bits = 7;
 269         fields[1].out_value = malloc(1);
 270         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 271
 272         fields[1].in_value = NULL;
 273
 274
 275         fields[1].in_handler = NULL;
 276
 277
 278         fields[2].tap = etb_reg->etb->tap;
 279         fields[2].num_bits = 1;
 280         fields[2].out_value = malloc(1);
 281         buf_set_u32(fields[2].out_value, 0, 1, 0);
 282
 283         fields[2].in_value = NULL;
 284
 285
 286         fields[2].in_handler = NULL;
 287
 288
 289         jtag_add_dr_scan(3, fields, TAP_INVALID);
 290
 291         /* read the identification register in the second run, to make sure we
 292          * don't read the ETB data register twice, skipping every second entry
 293          */
 294         buf_set_u32(fields[1].out_value, 0, 7, 0x0);
 295         fields[0].in_value = reg->value;
 296
 297         jtag_set_check_value(fields+0, check_value, check_mask, NULL);
 298
 299         jtag_add_dr_scan(3, fields, TAP_INVALID);
 300
 301         free(fields[1].out_value);
 302         free(fields[2].out_value);
 303
 304         return ERROR_OK;
 305 }
 306
 307 int etb_read_reg(reg_t *reg)
 308 {
 309         return etb_read_reg_w_check(reg, NULL, NULL);
 310 }
 311
 312 int etb_set_reg(reg_t *reg, u32 value)
 313 {
 314         int retval;
 315         if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 316         {
 317                 LOG_ERROR("BUG: error scheduling etm register write");
 318                 return retval;
 319         }
 320
 321         buf_set_u32(reg->value, 0, reg->size, value);
 322         reg->valid = 1;
 323         reg->dirty = 0;
 324
 325         return ERROR_OK;
 326 }
 327
 328 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
 329 {
 330         int retval;
 331         etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 332
 333         if ((retval = jtag_execute_queue()) != ERROR_OK)
 334         {
 335                 LOG_ERROR("register write failed");
 336                 return retval;
 337         }
 338         return ERROR_OK;
 339 }
 340
 341 int etb_write_reg(reg_t *reg, u32 value)
 342 {
 343         etb_reg_t *etb_reg = reg->arch_info;
 344         u8 reg_addr = etb_reg->addr & 0x7f;
 345         scan_field_t fields[3];
 346
 347         LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
 348
 349         jtag_add_end_state(TAP_IDLE);
 350         etb_scann(etb_reg->etb, 0x0);
 351         etb_set_instr(etb_reg->etb, 0xc);
 352
 353         fields[0].tap = etb_reg->etb->tap;
 354         fields[0].num_bits = 32;
 355         fields[0].out_value = malloc(4);
 356         buf_set_u32(fields[0].out_value, 0, 32, value);
 357
 358         fields[0].in_value = NULL;
 359
 360
 361         fields[0].in_handler = NULL;
 362
 363
 364         fields[1].tap = etb_reg->etb->tap;
 365         fields[1].num_bits = 7;
 366         fields[1].out_value = malloc(1);
 367         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
 368
 369         fields[1].in_value = NULL;
 370
 371
 372         fields[1].in_handler = NULL;
 373
 374
 375         fields[2].tap = etb_reg->etb->tap;
 376         fields[2].num_bits = 1;
 377         fields[2].out_value = malloc(1);
 378         buf_set_u32(fields[2].out_value, 0, 1, 1);
 379
 380         fields[2].in_value = NULL;
 381
 382
 383         fields[2].in_handler = NULL;
 384
 385
 386         jtag_add_dr_scan(3, fields, TAP_INVALID);
 387
 388         free(fields[0].out_value);
 389         free(fields[1].out_value);
 390         free(fields[2].out_value);
 391
 392         return ERROR_OK;
 393 }
 394
 395 int etb_store_reg(reg_t *reg)
 396 {
 397         return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 398 }
 399
 400 static int etb_register_commands(struct command_context_s *cmd_ctx)
 401 {
 402         command_t *etb_cmd;
 403
 404         etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
 405
 406         register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
 407
 408         return ERROR_OK;
 409 }
 410
 411 static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 412 {
 413         target_t *target;
 414         jtag_tap_t *tap;
 415         armv4_5_common_t *armv4_5;
 416         arm7_9_common_t *arm7_9;
 417
 418         if (argc != 2)
 419         {
 420                 return ERROR_COMMAND_SYNTAX_ERROR;
 421         }
 422
 423         target = get_target_by_num(strtoul(args[0], NULL, 0));
 424
 425         if (!target)
 426         {
 427                 LOG_ERROR("target number '%s' not defined", args[0]);
 428                 return ERROR_FAIL;
 429         }
 430
 431         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 432         {
 433                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
 434                 return ERROR_FAIL;
 435         }
 436
 437         tap = jtag_TapByString( args[1] );
 438         if( tap == NULL ){
 439                 command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
 440                 return ERROR_FAIL;
 441         }
 442
 443
 444         if (arm7_9->etm_ctx)
 445         {
 446                 etb_t *etb = malloc(sizeof(etb_t));
 447
 448                 arm7_9->etm_ctx->capture_driver_priv = etb;
 449
 450                 etb->tap  = tap;
 451                 etb->cur_scan_chain = 0xffffffff;
 452                 etb->reg_cache = NULL;
 453                 etb->ram_width = 0;
 454                 etb->ram_depth = 0;
 455         }
 456         else
 457         {
 458                 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
 459                 return ERROR_FAIL;
 460         }
 461
 462         return ERROR_OK;
 463 }
 464
 465 static int etb_init(etm_context_t *etm_ctx)
 466 {
 467         etb_t *etb = etm_ctx->capture_driver_priv;
 468
 469         etb->etm_ctx = etm_ctx;
 470
 471         /* identify ETB RAM depth and width */
 472         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
 473         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
 474         jtag_execute_queue();
 475
 476         etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
 477         etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
 478
 479         return ERROR_OK;
 480 }
 481
 482 static trace_status_t etb_status(etm_context_t *etm_ctx)
 483 {
 484         etb_t *etb = etm_ctx->capture_driver_priv;
 485
 486         etb->etm_ctx = etm_ctx;
 487
 488         /* if tracing is currently idle, return this information */
 489         if (etm_ctx->capture_status == TRACE_IDLE)
 490         {
 491                 return etm_ctx->capture_status;
 492         }
 493         else if (etm_ctx->capture_status & TRACE_RUNNING)
 494         {
 495                 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
 496                 int etb_timeout = 100;
 497
 498                 /* trace is running, check the ETB status flags */
 499                 etb_get_reg(etb_status_reg);
 500
 501                 /* check Full bit to identify an overflow */
 502                 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
 503                         etm_ctx->capture_status |= TRACE_OVERFLOWED;
 504
 505                 /* check Triggered bit to identify trigger condition */
 506                 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
 507                         etm_ctx->capture_status |= TRACE_TRIGGERED;
 508
 509                 /* check AcqComp to identify trace completion */
 510                 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
 511                 {
 512                         while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
 513                         {
 514                                 /* wait for data formatter idle */
 515                                 etb_get_reg(etb_status_reg);
 516                         }
 517
 518                         if (etb_timeout == 0)
 519                         {
 520                                 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
 521                                         buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
 522                         }
 523
 524                         if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
 525                         {
 526                                 LOG_ERROR("trace completed, but no trigger condition detected");
 527                         }
 528
 529                         etm_ctx->capture_status &= ~TRACE_RUNNING;
 530                         etm_ctx->capture_status |= TRACE_COMPLETED;
 531                 }
 532         }
 533
 534         return etm_ctx->capture_status;
 535 }
 536
 537 static int etb_read_trace(etm_context_t *etm_ctx)
 538 {
 539         etb_t *etb = etm_ctx->capture_driver_priv;
 540         int first_frame = 0;
 541         int num_frames = etb->ram_depth;
 542         u32 *trace_data = NULL;
 543         int i, j;
 544
 545         etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
 546         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
 547         jtag_execute_queue();
 548
 549         /* check if we overflowed, and adjust first frame of the trace accordingly
 550          * if we didn't overflow, read only up to the frame that would be written next,
 551          * i.e. don't read invalid entries
 552          */
 553         if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
 554         {
 555                 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 556         }
 557         else
 558         {
 559                 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
 560         }
 561
 562         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
 563
 564         /* read data into temporary array for unpacking */
 565         trace_data = malloc(sizeof(u32) * num_frames);
 566         etb_read_ram(etb, trace_data, num_frames);
 567
 568         if (etm_ctx->trace_depth > 0)
 569         {
 570                 free(etm_ctx->trace_data);
 571         }
 572
 573         if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 574                 etm_ctx->trace_depth = num_frames * 3;
 575         else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 576                 etm_ctx->trace_depth = num_frames * 2;
 577         else
 578                 etm_ctx->trace_depth = num_frames;
 579
 580         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
 581
 582         for (i = 0, j = 0; i < num_frames; i++)
 583         {
 584                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
 585                 {
 586                         /* trace word j */
 587                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 588                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
 589                         etm_ctx->trace_data[j].flags = 0;
 590                         if ((trace_data[i] & 0x80) >> 7)
 591                         {
 592                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 593                         }
 594                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 595                         {
 596                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 597                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 598                         }
 599
 600                         /* trace word j+1 */
 601                         etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
 602                         etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
 603                         etm_ctx->trace_data[j+1].flags = 0;
 604                         if ((trace_data[i] & 0x8000) >> 15)
 605                         {
 606                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
 607                         }
 608                         if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
 609                         {
 610                                 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
 611                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
 612                         }
 613
 614                         /* trace word j+2 */
 615                         etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
 616                         etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
 617                         etm_ctx->trace_data[j+2].flags = 0;
 618                         if ((trace_data[i] & 0x800000) >> 23)
 619                         {
 620                                 etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
 621                         }
 622                         if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
 623                         {
 624                                 etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
 625                                 etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
 626                         }
 627
 628                         j += 3;
 629                 }
 630                 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
 631                 {
 632                         /* trace word j */
 633                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 634                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
 635                         etm_ctx->trace_data[j].flags = 0;
 636                         if ((trace_data[i] & 0x800) >> 11)
 637                         {
 638                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 639                         }
 640                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 641                         {
 642                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 643                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 644                         }
 645
 646                         /* trace word j+1 */
 647                         etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
 648                         etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
 649                         etm_ctx->trace_data[j+1].flags = 0;
 650                         if ((trace_data[i] & 0x800000) >> 23)
 651                         {
 652                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
 653                         }
 654                         if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
 655                         {
 656                                 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
 657                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
 658                         }
 659
 660                         j += 2;
 661                 }
 662                 else
 663                 {
 664                         /* trace word j */
 665                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
 666                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
 667                         etm_ctx->trace_data[j].flags = 0;
 668                         if ((trace_data[i] & 0x80000) >> 19)
 669                         {
 670                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
 671                         }
 672                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)
 673                         {
 674                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
 675                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
 676                         }
 677
 678                         j += 1;
 679                 }
 680         }
 681
 682         free(trace_data);
 683
 684         return ERROR_OK;
 685 }
 686
 687 static int etb_start_capture(etm_context_t *etm_ctx)
 688 {
 689         etb_t *etb = etm_ctx->capture_driver_priv;
 690         u32 etb_ctrl_value = 0x1;
 691         u32 trigger_count;
 692
 693         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
 694         {
 695                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
 696                 {
 697                         LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
 698                         return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 699                 }
 700                 etb_ctrl_value |= 0x2;
 701         }
 702
 703         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
 704                 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
 705
 706         trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
 707
 708         etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
 709         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
 710         etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
 711         jtag_execute_queue();
 712
 713         /* we're starting a new trace, initialize capture status */
 714         etm_ctx->capture_status = TRACE_RUNNING;
 715
 716         return ERROR_OK;
 717 }
 718
 719 static int etb_stop_capture(etm_context_t *etm_ctx)
 720 {
 721         etb_t *etb = etm_ctx->capture_driver_priv;
 722         reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
 723
 724         etb_write_reg(etb_ctrl_reg, 0x0);
 725         jtag_execute_queue();
 726
 727         /* trace stopped, just clear running flag, but preserve others */
 728         etm_ctx->capture_status &= ~TRACE_RUNNING;
 729
 730         return ERROR_OK;
 731 }
 732
 733 etm_capture_driver_t etb_capture_driver =
 734 {
 735         .name = "etb",
 736         .register_commands = etb_register_commands,
 737         .init = etb_init,
 738         .status = etb_status,
 739         .start_capture = etb_start_capture,
 740         .stop_capture = etb_stop_capture,
 741         .read_trace = etb_read_trace,
 742 };