git.gag.com Git - fw/openocd/blob - src/target/etb.c

   1 /***************************************************************************\r
   2  *   Copyright (C) 2007 by Dominic Rath                                    *\r
   3  *   Dominic.Rath@gmx.de                                                   *\r
   4  *                                                                         *\r
   5  *   This program is free software; you can redistribute it and/or modify  *\r
   6  *   it under the terms of the GNU General Public License as published by  *\r
   7  *   the Free Software Foundation; either version 2 of the License, or     *\r
   8  *   (at your option) any later version.                                   *\r
   9  *                                                                         *\r
  10  *   This program is distributed in the hope that it will be useful,       *\r
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
  13  *   GNU General Public License for more details.                          *\r
  14  *                                                                         *\r
  15  *   You should have received a copy of the GNU General Public License     *\r
  16  *   along with this program; if not, write to the                         *\r
  17  *   Free Software Foundation, Inc.,                                       *\r
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
  19  ***************************************************************************/\r
  20 #ifdef HAVE_CONFIG_H\r
  21 #include "config.h"\r
  22 #endif\r
  23 \r
  24 #include <string.h>\r
  25 \r
  26 #include "arm7_9_common.h"\r
  27 #include "etb.h"\r
  28 #include "etm.h"\r
  29 \r
  30 #include "log.h"\r
  31 #include "types.h"\r
  32 #include "binarybuffer.h"\r
  33 #include "target.h"\r
  34 #include "register.h"\r
  35 #include "jtag.h"\r
  36 \r
  37 #include <stdlib.h>\r
  38 \r
  39 char* etb_reg_list[] =\r
  40 {\r
  41         "ETB_identification",\r
  42         "ETB_ram_depth",\r
  43         "ETB_ram_width",\r
  44         "ETB_status",\r
  45         "ETB_ram_data",\r
  46         "ETB_ram_read_pointer",\r
  47         "ETB_ram_write_pointer",\r
  48         "ETB_trigger_counter",\r
  49         "ETB_control",\r
  50 };\r
  51 \r
  52 int etb_reg_arch_type = -1;\r
  53 \r
  54 int etb_get_reg(reg_t *reg);\r
  55 int etb_set_reg(reg_t *reg, u32 value);\r
  56 int etb_set_reg_w_exec(reg_t *reg, u8 *buf);\r
  57 \r
  58 int etb_write_reg(reg_t *reg, u32 value);\r
  59 int etb_read_reg(reg_t *reg);\r
  60 \r
  61 int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  62 \r
  63 int etb_set_instr(etb_t *etb, u32 new_instr)\r
  64 {\r
  65         jtag_device_t *device = jtag_get_device(etb->chain_pos);\r
  66         \r
  67         if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)\r
  68         {\r
  69                 scan_field_t field;\r
  70         \r
  71                 field.device = etb->chain_pos;\r
  72                 field.num_bits = device->ir_length;\r
  73                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);\r
  74                 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);\r
  75                 field.out_mask = NULL;\r
  76                 field.in_value = NULL;\r
  77                 field.in_check_value = NULL;\r
  78                 field.in_check_mask = NULL;\r
  79                 field.in_handler = NULL;\r
  80                 field.in_handler_priv = NULL;\r
  81                                 \r
  82                 jtag_add_ir_scan(1, &field, -1);\r
  83                 \r
  84                 free(field.out_value);\r
  85         }\r
  86         \r
  87         return ERROR_OK;\r
  88 }\r
  89 \r
  90 int etb_scann(etb_t *etb, u32 new_scan_chain)\r
  91 {\r
  92         if(etb->cur_scan_chain != new_scan_chain)\r
  93         {\r
  94                 scan_field_t field;\r
  95                 \r
  96                 field.device = etb->chain_pos;\r
  97                 field.num_bits = 5;\r
  98                 field.out_value = calloc(CEIL(field.num_bits, 8), 1);\r
  99                 buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);\r
 100                 field.out_mask = NULL;\r
 101                 field.in_value = NULL;\r
 102                 field.in_check_value = NULL;\r
 103                 field.in_check_mask = NULL;\r
 104                 field.in_handler = NULL;\r
 105                 field.in_handler_priv = NULL;\r
 106                 \r
 107                 /* select INTEST instruction */\r
 108                 etb_set_instr(etb, 0x2);\r
 109                 jtag_add_dr_scan(1, &field, -1);\r
 110                 \r
 111                 etb->cur_scan_chain = new_scan_chain;\r
 112                 \r
 113                 free(field.out_value);\r
 114         }\r
 115 \r
 116         return ERROR_OK;\r
 117 }\r
 118 \r
 119 reg_cache_t* etb_build_reg_cache(etb_t *etb)\r
 120 {\r
 121         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));\r
 122         reg_t *reg_list = NULL;\r
 123         etb_reg_t *arch_info = NULL;\r
 124         int num_regs = 9;\r
 125         int i;\r
 126         \r
 127         /* register a register arch-type for etm registers only once */\r
 128         if (etb_reg_arch_type == -1)\r
 129                 etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);\r
 130         \r
 131         /* the actual registers are kept in two arrays */\r
 132         reg_list = calloc(num_regs, sizeof(reg_t));\r
 133         arch_info = calloc(num_regs, sizeof(etb_reg_t));\r
 134         \r
 135         /* fill in values for the reg cache */\r
 136         reg_cache->name = "etb registers";\r
 137         reg_cache->next = NULL;\r
 138         reg_cache->reg_list = reg_list;\r
 139         reg_cache->num_regs = num_regs;\r
 140         \r
 141         /* set up registers */\r
 142         for (i = 0; i < num_regs; i++)\r
 143         {\r
 144                 reg_list[i].name = etb_reg_list[i];\r
 145                 reg_list[i].size = 32;\r
 146                 reg_list[i].dirty = 0;\r
 147                 reg_list[i].valid = 0;\r
 148                 reg_list[i].bitfield_desc = NULL;\r
 149                 reg_list[i].num_bitfields = 0;\r
 150                 reg_list[i].value = calloc(1, 4);\r
 151                 reg_list[i].arch_info = &arch_info[i];\r
 152                 reg_list[i].arch_type = etb_reg_arch_type;\r
 153                 reg_list[i].size = 32;\r
 154                 arch_info[i].addr = i;\r
 155                 arch_info[i].etb = etb;\r
 156         }\r
 157         \r
 158         return reg_cache;\r
 159 }\r
 160 \r
 161 int etb_get_reg(reg_t *reg)\r
 162 {\r
 163         if (etb_read_reg(reg) != ERROR_OK)\r
 164         {\r
 165                 ERROR("BUG: error scheduling etm register read");\r
 166                 exit(-1);\r
 167         }\r
 168         \r
 169         if (jtag_execute_queue() != ERROR_OK)\r
 170         {\r
 171                 ERROR("register read failed");\r
 172         }\r
 173         \r
 174         return ERROR_OK;\r
 175 }\r
 176 \r
 177 int etb_read_ram(etb_t *etb, u32 *data, int num_frames)\r
 178 {\r
 179         scan_field_t fields[3];\r
 180         int i;\r
 181         \r
 182         jtag_add_end_state(TAP_RTI);\r
 183         etb_scann(etb, 0x0);\r
 184         etb_set_instr(etb, 0xc);\r
 185         \r
 186         fields[0].device = etb->chain_pos;\r
 187         fields[0].num_bits = 32;\r
 188         fields[0].out_value = NULL;\r
 189         fields[0].out_mask = NULL;\r
 190         fields[0].in_value = NULL;\r
 191         fields[0].in_check_value = NULL;\r
 192         fields[0].in_check_mask = NULL;\r
 193         fields[0].in_handler = NULL;\r
 194         fields[0].in_handler_priv = NULL;\r
 195         \r
 196         fields[1].device = etb->chain_pos;\r
 197         fields[1].num_bits = 7;\r
 198         fields[1].out_value = malloc(1);\r
 199         buf_set_u32(fields[1].out_value, 0, 7, 4);\r
 200         fields[1].out_mask = NULL;\r
 201         fields[1].in_value = NULL;\r
 202         fields[1].in_check_value = NULL;\r
 203         fields[1].in_check_mask = NULL;\r
 204         fields[1].in_handler = NULL;\r
 205         fields[1].in_handler_priv = NULL;\r
 206 \r
 207         fields[2].device = etb->chain_pos;\r
 208         fields[2].num_bits = 1;\r
 209         fields[2].out_value = malloc(1);\r
 210         buf_set_u32(fields[2].out_value, 0, 1, 0);\r
 211         fields[2].out_mask = NULL;\r
 212         fields[2].in_value = NULL;\r
 213         fields[2].in_check_value = NULL;\r
 214         fields[2].in_check_mask = NULL;\r
 215         fields[2].in_handler = NULL;\r
 216         fields[2].in_handler_priv = NULL;\r
 217         \r
 218         jtag_add_dr_scan(3, fields, -1);\r
 219 \r
 220         fields[0].in_handler = buf_to_u32_handler;\r
 221         \r
 222         for (i = 0; i < num_frames; i++)\r
 223         {\r
 224                 /* ensure nR/W reamins set to read */\r
 225                 buf_set_u32(fields[2].out_value, 0, 1, 0);\r
 226                 \r
 227                 /* address remains set to 0x4 (RAM data) until we read the last frame */\r
 228                 if (i < num_frames - 1)\r
 229                         buf_set_u32(fields[1].out_value, 0, 7, 4);\r
 230                 else\r
 231                         buf_set_u32(fields[1].out_value, 0, 7, 0);\r
 232                 \r
 233                 fields[0].in_handler_priv = &data[i];\r
 234                 jtag_add_dr_scan(3, fields, -1);\r
 235         }\r
 236         \r
 237         jtag_execute_queue();\r
 238         \r
 239         free(fields[1].out_value);\r
 240         free(fields[2].out_value);\r
 241         \r
 242         return ERROR_OK;\r
 243 }\r
 244 \r
 245 int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)\r
 246 {\r
 247         etb_reg_t *etb_reg = reg->arch_info;\r
 248         u8 reg_addr = etb_reg->addr & 0x7f;\r
 249         scan_field_t fields[3];\r
 250         \r
 251         DEBUG("%i", etb_reg->addr);\r
 252 \r
 253         jtag_add_end_state(TAP_RTI);\r
 254         etb_scann(etb_reg->etb, 0x0);\r
 255         etb_set_instr(etb_reg->etb, 0xc);\r
 256         \r
 257         fields[0].device = etb_reg->etb->chain_pos;\r
 258         fields[0].num_bits = 32;\r
 259         fields[0].out_value = reg->value;\r
 260         fields[0].out_mask = NULL;\r
 261         fields[0].in_value = NULL;\r
 262         fields[0].in_check_value = NULL;\r
 263         fields[0].in_check_mask = NULL;\r
 264         fields[0].in_handler = NULL;\r
 265         fields[0].in_handler_priv = NULL;\r
 266         \r
 267         fields[1].device = etb_reg->etb->chain_pos;\r
 268         fields[1].num_bits = 7;\r
 269         fields[1].out_value = malloc(1);\r
 270         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);\r
 271         fields[1].out_mask = NULL;\r
 272         fields[1].in_value = NULL;\r
 273         fields[1].in_check_value = NULL;\r
 274         fields[1].in_check_mask = NULL;\r
 275         fields[1].in_handler = NULL;\r
 276         fields[1].in_handler_priv = NULL;\r
 277 \r
 278         fields[2].device = etb_reg->etb->chain_pos;\r
 279         fields[2].num_bits = 1;\r
 280         fields[2].out_value = malloc(1);\r
 281         buf_set_u32(fields[2].out_value, 0, 1, 0);\r
 282         fields[2].out_mask = NULL;\r
 283         fields[2].in_value = NULL;\r
 284         fields[2].in_check_value = NULL;\r
 285         fields[2].in_check_mask = NULL;\r
 286         fields[2].in_handler = NULL;\r
 287         fields[2].in_handler_priv = NULL;\r
 288         \r
 289         jtag_add_dr_scan(3, fields, -1);\r
 290         \r
 291         /* read the identification register in the second run, to make sure we\r
 292          * don't read the ETB data register twice, skipping every second entry\r
 293          */\r
 294         buf_set_u32(fields[1].out_value, 0, 7, 0x0);\r
 295         fields[0].in_value = reg->value;\r
 296         \r
 297         jtag_set_check_value(fields+0, check_value, check_mask, NULL);\r
 298         \r
 299         jtag_add_dr_scan(3, fields, -1);\r
 300 \r
 301         free(fields[1].out_value);\r
 302         free(fields[2].out_value);\r
 303         \r
 304         return ERROR_OK;\r
 305 }\r
 306 \r
 307 int etb_read_reg(reg_t *reg)\r
 308 {\r
 309         return etb_read_reg_w_check(reg, NULL, NULL);   \r
 310 }\r
 311 \r
 312 int etb_set_reg(reg_t *reg, u32 value)\r
 313 {\r
 314         if (etb_write_reg(reg, value) != ERROR_OK)\r
 315         {\r
 316                 ERROR("BUG: error scheduling etm register write");\r
 317                 exit(-1);\r
 318         }\r
 319         \r
 320         buf_set_u32(reg->value, 0, reg->size, value);\r
 321         reg->valid = 1;\r
 322         reg->dirty = 0;\r
 323         \r
 324         return ERROR_OK;\r
 325 }\r
 326 \r
 327 int etb_set_reg_w_exec(reg_t *reg, u8 *buf)\r
 328 {\r
 329         etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));\r
 330         \r
 331         if (jtag_execute_queue() != ERROR_OK)\r
 332         {\r
 333                 ERROR("register write failed");\r
 334                 exit(-1);\r
 335         }\r
 336         return ERROR_OK;\r
 337 }\r
 338 \r
 339 int etb_write_reg(reg_t *reg, u32 value)\r
 340 {\r
 341         etb_reg_t *etb_reg = reg->arch_info;\r
 342         u8 reg_addr = etb_reg->addr & 0x7f;\r
 343         scan_field_t fields[3];\r
 344         \r
 345         DEBUG("%i: 0x%8.8x", etb_reg->addr, value);\r
 346         \r
 347         jtag_add_end_state(TAP_RTI);\r
 348         etb_scann(etb_reg->etb, 0x0);\r
 349         etb_set_instr(etb_reg->etb, 0xc);\r
 350         \r
 351         fields[0].device = etb_reg->etb->chain_pos;\r
 352         fields[0].num_bits = 32;\r
 353         fields[0].out_value = malloc(4);\r
 354         buf_set_u32(fields[0].out_value, 0, 32, value);\r
 355         fields[0].out_mask = NULL;\r
 356         fields[0].in_value = NULL;\r
 357         fields[0].in_check_value = NULL;\r
 358         fields[0].in_check_mask = NULL;\r
 359         fields[0].in_handler = NULL;\r
 360         fields[0].in_handler_priv = NULL;\r
 361         \r
 362         fields[1].device = etb_reg->etb->chain_pos;\r
 363         fields[1].num_bits = 7;\r
 364         fields[1].out_value = malloc(1);\r
 365         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);\r
 366         fields[1].out_mask = NULL;\r
 367         fields[1].in_value = NULL;\r
 368         fields[1].in_check_value = NULL;\r
 369         fields[1].in_check_mask = NULL;\r
 370         fields[1].in_handler = NULL;\r
 371         fields[1].in_handler_priv = NULL;\r
 372 \r
 373         fields[2].device = etb_reg->etb->chain_pos;\r
 374         fields[2].num_bits = 1;\r
 375         fields[2].out_value = malloc(1);\r
 376         buf_set_u32(fields[2].out_value, 0, 1, 1);\r
 377         fields[2].out_mask = NULL;\r
 378         fields[2].in_value = NULL;\r
 379         fields[2].in_check_value = NULL;\r
 380         fields[2].in_check_mask = NULL;\r
 381         fields[2].in_handler = NULL;\r
 382         fields[2].in_handler_priv = NULL;\r
 383         \r
 384         jtag_add_dr_scan(3, fields, -1);\r
 385         \r
 386         free(fields[0].out_value);\r
 387         free(fields[1].out_value);\r
 388         free(fields[2].out_value);\r
 389         \r
 390         return ERROR_OK;\r
 391 }\r
 392 \r
 393 int etb_store_reg(reg_t *reg)\r
 394 {\r
 395         return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));\r
 396 }\r
 397 \r
 398 int etb_register_commands(struct command_context_s *cmd_ctx)\r
 399 {\r
 400         command_t *etb_cmd;\r
 401         \r
 402         etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");\r
 403         \r
 404         register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);\r
 405 \r
 406         return ERROR_OK;\r
 407 }\r
 408 \r
 409 int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 410 {\r
 411         target_t *target;\r
 412         jtag_device_t *jtag_device;\r
 413         armv4_5_common_t *armv4_5;\r
 414         arm7_9_common_t *arm7_9;\r
 415         \r
 416         if (argc != 2)\r
 417         {\r
 418                 ERROR("incomplete 'etb config <target> <chain_pos>' command");\r
 419                 exit(-1);\r
 420         }\r
 421         \r
 422         target = get_target_by_num(strtoul(args[0], NULL, 0));\r
 423         \r
 424         if (!target)\r
 425         {\r
 426                 ERROR("target number '%s' not defined", args[0]);\r
 427                 exit(-1);\r
 428         }\r
 429         \r
 430         if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)\r
 431         {\r
 432                 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");\r
 433                 return ERROR_OK;\r
 434         }\r
 435         \r
 436         jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));\r
 437         \r
 438         if (!jtag_device)\r
 439         {\r
 440                 ERROR("jtag device number '%s' not defined", args[1]);\r
 441                 exit(-1);\r
 442         }\r
 443         \r
 444         if (arm7_9->etm_ctx)\r
 445         {\r
 446                 etb_t *etb = malloc(sizeof(etb_t));\r
 447                 \r
 448                 arm7_9->etm_ctx->capture_driver_priv = etb;\r
 449                 \r
 450                 etb->chain_pos = strtoul(args[1], NULL, 0);\r
 451                 etb->cur_scan_chain = -1;\r
 452                 etb->reg_cache = NULL;\r
 453                 etb->ram_width = 0;\r
 454                 etb->ram_depth = 0;\r
 455         }\r
 456         else\r
 457         {\r
 458                 ERROR("target has no ETM defined, ETB left unconfigured");\r
 459         }\r
 460 \r
 461         return ERROR_OK;\r
 462 }\r
 463 \r
 464 int etb_init(etm_context_t *etm_ctx)\r
 465 {\r
 466         etb_t *etb = etm_ctx->capture_driver_priv;\r
 467         \r
 468         etb->etm_ctx = etm_ctx;\r
 469         \r
 470         /* identify ETB RAM depth and width */\r
 471         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);\r
 472         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);\r
 473         jtag_execute_queue();\r
 474 \r
 475         etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);\r
 476         etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);\r
 477         \r
 478         return ERROR_OK;\r
 479 }\r
 480 \r
 481 trace_status_t etb_status(etm_context_t *etm_ctx)\r
 482 {\r
 483         etb_t *etb = etm_ctx->capture_driver_priv;\r
 484         \r
 485         etb->etm_ctx = etm_ctx;\r
 486         \r
 487         /* if tracing is currently idle, return this information */\r
 488         if (etm_ctx->capture_status == TRACE_IDLE)\r
 489         {\r
 490                 return etm_ctx->capture_status;\r
 491         }\r
 492         else if (etm_ctx->capture_status & TRACE_RUNNING)\r
 493         {\r
 494                 reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];\r
 495                 int etb_timeout = 100;\r
 496                 \r
 497                 /* trace is running, check the ETB status flags */\r
 498                 etb_get_reg(etb_status_reg);\r
 499         \r
 500                 /* check Full bit to identify an overflow */\r
 501                 if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)\r
 502                         etm_ctx->capture_status |= TRACE_OVERFLOWED;\r
 503 \r
 504                 /* check Triggered bit to identify trigger condition */\r
 505                 if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)\r
 506                         etm_ctx->capture_status |= TRACE_TRIGGERED;\r
 507 \r
 508                 /* check AcqComp to identify trace completion */\r
 509                 if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)\r
 510                 {\r
 511                         while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))\r
 512                         {\r
 513                                 /* wait for data formatter idle */\r
 514                                 etb_get_reg(etb_status_reg);\r
 515                         }\r
 516                         \r
 517                         if (etb_timeout == 0)\r
 518                         {\r
 519                                 ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",\r
 520                                         buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));\r
 521                         }\r
 522                         \r
 523                         if (!(etm_ctx->capture_status && TRACE_TRIGGERED))\r
 524                         {\r
 525                                 ERROR("trace completed, but no trigger condition detected");\r
 526                         }\r
 527                         \r
 528                         etm_ctx->capture_status &= ~TRACE_RUNNING;\r
 529                         etm_ctx->capture_status |= TRACE_COMPLETED;\r
 530                 }\r
 531         }\r
 532         \r
 533         return etm_ctx->capture_status;\r
 534 }\r
 535 \r
 536 int etb_read_trace(etm_context_t *etm_ctx)\r
 537 {\r
 538         etb_t *etb = etm_ctx->capture_driver_priv;\r
 539         int first_frame = 0;\r
 540         int num_frames = etb->ram_depth;\r
 541         u32 *trace_data = NULL;\r
 542         int i, j;\r
 543         \r
 544         etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);\r
 545         etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);\r
 546         jtag_execute_queue();\r
 547         \r
 548         /* check if we overflowed, and adjust first frame of the trace accordingly\r
 549          * if we didn't overflow, read only up to the frame that would be written next,\r
 550          * i.e. don't read invalid entries\r
 551          */\r
 552         if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))\r
 553         {\r
 554                 first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);\r
 555         }\r
 556         else\r
 557         {\r
 558                 num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);\r
 559         }\r
 560         \r
 561         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);\r
 562 \r
 563         /* read data into temporary array for unpacking */      \r
 564         trace_data = malloc(sizeof(u32) * num_frames);\r
 565         etb_read_ram(etb, trace_data, num_frames);\r
 566 \r
 567         if (etm_ctx->trace_depth > 0)\r
 568         {\r
 569                 free(etm_ctx->trace_data);\r
 570         }\r
 571         \r
 572         if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)\r
 573                 etm_ctx->trace_depth = num_frames * 3;\r
 574         else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)\r
 575                 etm_ctx->trace_depth = num_frames * 2;\r
 576         else\r
 577                 etm_ctx->trace_depth = num_frames;\r
 578 \r
 579         etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);\r
 580         \r
 581         for (i = 0, j = 0; i < num_frames; i++)\r
 582         {\r
 583                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)\r
 584                 {\r
 585                         /* trace word j */\r
 586                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;\r
 587                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;\r
 588                         etm_ctx->trace_data[j].flags = 0;\r
 589                         if ((trace_data[i] & 0x80) >> 7)\r
 590                         {\r
 591                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;\r
 592                         }\r
 593                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)\r
 594                         {\r
 595                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;\r
 596                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;\r
 597                         }\r
 598                         \r
 599                         /* trace word j+1 */\r
 600                         etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;\r
 601                         etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;\r
 602                         etm_ctx->trace_data[j+1].flags = 0;\r
 603                         if ((trace_data[i] & 0x8000) >> 15)\r
 604                         {\r
 605                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;\r
 606                         }\r
 607                         if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)\r
 608                         {\r
 609                                 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;\r
 610                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;\r
 611                         }\r
 612                         \r
 613                         /* trace word j+2 */\r
 614                         etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;\r
 615                         etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;\r
 616                         etm_ctx->trace_data[j+2].flags = 0;\r
 617                         if ((trace_data[i] & 0x800000) >> 23)\r
 618                         {\r
 619                                 etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;\r
 620                         }\r
 621                         if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)\r
 622                         {\r
 623                                 etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;\r
 624                                 etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;\r
 625                         }\r
 626                         \r
 627                         j += 3;\r
 628                 }\r
 629                 else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)\r
 630                 {\r
 631                         /* trace word j */\r
 632                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;\r
 633                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;\r
 634                         etm_ctx->trace_data[j].flags = 0;\r
 635                         if ((trace_data[i] & 0x800) >> 11)\r
 636                         {\r
 637                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;\r
 638                         }\r
 639                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)\r
 640                         {\r
 641                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;\r
 642                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;\r
 643                         }\r
 644 \r
 645                         /* trace word j+1 */\r
 646                         etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;\r
 647                         etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;\r
 648                         etm_ctx->trace_data[j+1].flags = 0;\r
 649                         if ((trace_data[i] & 0x800000) >> 23)\r
 650                         {\r
 651                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;\r
 652                         }\r
 653                         if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)\r
 654                         {\r
 655                                 etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;\r
 656                                 etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;\r
 657                         }\r
 658                         \r
 659                         j += 2;\r
 660                 }\r
 661                 else\r
 662                 {\r
 663                         /* trace word j */\r
 664                         etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;\r
 665                         etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;\r
 666                         etm_ctx->trace_data[j].flags = 0;\r
 667                         if ((trace_data[i] & 0x80000) >> 19)\r
 668                         {\r
 669                                 etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;\r
 670                         }\r
 671                         if (etm_ctx->trace_data[j].pipestat == STAT_TR)\r
 672                         {\r
 673                                 etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;\r
 674                                 etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;\r
 675                         }\r
 676                         \r
 677                         j += 1;\r
 678                 }\r
 679         }\r
 680         \r
 681         free(trace_data);\r
 682         \r
 683         return ERROR_OK;\r
 684 }\r
 685 \r
 686 int etb_start_capture(etm_context_t *etm_ctx)\r
 687 {\r
 688         etb_t *etb = etm_ctx->capture_driver_priv;\r
 689         u32 etb_ctrl_value = 0x1;\r
 690         u32 trigger_count;\r
 691 \r
 692         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)\r
 693         {\r
 694                 if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)\r
 695                 {\r
 696                         ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");\r
 697                         return ERROR_ETM_PORTMODE_NOT_SUPPORTED;\r
 698                 }\r
 699                 etb_ctrl_value |= 0x2;\r
 700         }\r
 701         \r
 702         if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)\r
 703                 return ERROR_ETM_PORTMODE_NOT_SUPPORTED;\r
 704         \r
 705         trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;\r
 706         \r
 707         etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);\r
 708         etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);\r
 709         etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);\r
 710         jtag_execute_queue();\r
 711         \r
 712         /* we're starting a new trace, initialize capture status */\r
 713         etm_ctx->capture_status = TRACE_RUNNING;\r
 714         \r
 715         return ERROR_OK; \r
 716 }\r
 717 \r
 718 int etb_stop_capture(etm_context_t *etm_ctx)\r
 719 {\r
 720         etb_t *etb = etm_ctx->capture_driver_priv;\r
 721         reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];\r
 722 \r
 723         etb_write_reg(etb_ctrl_reg, 0x0);\r
 724         jtag_execute_queue();\r
 725         \r
 726         /* trace stopped, just clear running flag, but preserve others */ \r
 727         etm_ctx->capture_status &= ~TRACE_RUNNING;\r
 728         \r
 729         return ERROR_OK;\r
 730 }\r
 731 \r
 732 etm_capture_driver_t etb_capture_driver =\r
 733 {\r
 734         .name = "etb",\r
 735         .register_commands = etb_register_commands,\r
 736         .init = etb_init,\r
 737         .status = etb_status,\r
 738         .start_capture = etb_start_capture,\r
 739         .stop_capture = etb_stop_capture,\r
 740         .read_trace = etb_read_trace,\r
 741 };\r